FPGA upgrade system and FPGA upgrade method

Abstract

The present application provides an FPGA upgrade system and an FPGA upgrade method. The system includes at least an FPGA chip, a configuration chip storing an FPGA configuration program, and a trigger control module; the trigger control module generates a reset clear signal in response to an external trigger signal, and transmits the reset clear signal to the FPGA chip through a second interface. After receiving the reset clear signal, the FPGA chip controls the clearing of its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip through a first interface to complete the upgrade of the FPGA. By controlling the width of the reset clear signal output by the trigger control module, the FPGA can be ensured to stably and reliably clear the current configuration program and load the updated configuration program under non-power-off conditions, thereby improving the stability and reliability of the FPGA upgrade.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and in particular to an FPGA upgrade system and an FPGA upgrade method. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a semiconductor device. The basic working principle of FPGA is to change the content of the configuration memory inside the FPGA by loading a configuration file, thereby changing the configuration of various logic resources inside the FPGA to achieve different circuit functions. The configuration file can be loaded multiple times, so that the FPGA can achieve different functions by loading different configuration data, which has good flexibility. In practice, it can also be flexibly programmed according to user needs to achieve user functions, such as assisting the central processing unit (CPU) to complete the management and control of the internal units of the system, managing the startup of the central processing unit, and monitoring the operating status of the central processing unit. Due to its rich logic resources and I / O resources, short development cycle, low design cost, and easy product replacement, it has been widely used in the field of communication products.

[0003] For scenarios with simple master / slave interfaces, such as PCIE (peripheral component interconnect express), PXIE (PCI extensions for instrumentation), and MTCA (Micro Telecommunications Computing Architecture) standard interface peripheral modules, FPGA external firmware (such as Nor-FLASH, PROM) is usually passively loaded. Therefore, when upgrading the FPGA, you only need to add new upgrade firmware.

[0004] When the FPGA is upgraded, new upgrade firmware is sent to the FPGA via PCle, and the FPGA burns the upgrade firmware into the non-volatile random access memory. After the burning is completed, the power supply must be cut off and then turned on again. Cutting off the power supply can cause the host computer and the PCle device to lose power. This action of cutting off the power supply and then turning it on again after powering off will trigger the FPGA to re-read the configuration file of the upgrade firmware from the non-volatile random access memory, thereby completing the circuit update inside the FPGA chip, which is not conducive to product maintenance and upgrades.

[0005] Based on the above problems, a method for upgrading FPGA online without power failure is also proposed. The FPGA drives the logic unit of the configuration chip interface of the firmware through the AXI interface (Advanced extensible Interface) of the PCIE IP module, accesses the configuration chip with the firmware stored externally for upgrading, that is, by triggering the hot start mechanism inside the FPGA, the FPGA configuration is updated. However, this method heavily relies on the configuration chip to provide the corresponding hot start solution support, which depends on the FPGA. The FPGA response time after the output signal of the logic configuration clear pin is enabled, and its reliability is not high. Summary of the invention

[0006] The present application provides an FPGA upgrade system and an FPGA upgrade method, which can solve the technical problem that in the process of upgrading the FPGA in the prior art, a power-off upgrade method is used, which will cause the progress of other devices on the FPGA mainboard to be lost or the operation of other PCle devices to be interrupted; and a non-power-off online upgrade method has a low reliability.

[0007] In a first aspect, an embodiment of the present application provides an FPGA upgrade system, including an FPGA chip, a configuration chip, and a trigger control module;

[0008] The FPGA chip has at least a first interface and a second interface; the first interface is used to connect the configuration chip; the second interface is used to connect the trigger control module;

[0009] The configuration chip is used to store the configuration program of the FPGA;

[0010] The trigger control module is used to generate a reset clear signal in response to an external input trigger signal, and input the reset clear signal to the FPGA chip through the second interface of the FPGA chip; wherein the widening width of the reset clear signal is controllable;

[0011] After receiving the reset clear signal, the FPGA chip controls to clear its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip through the first interface.

[0012] In some embodiments, the FPGA chip includes a PCIe interface, a third interface, a user control module, and a self-loading module;

[0013] The PCIe interface is used to connect the FPGA chip with a host computer for issuing upgrade instructions and configuration programs to be upgraded; the third interface is used to connect the trigger control module and the self-loading module;

[0014] The self-loading module is connected between the first interface and the third interface, and the self-loading module drives the first interface to be connected in response to the effective level of the reset clear signal output by the trigger control module;

[0015] The user control module is used to respond to the upgrade instruction sent by the host computer, output a trigger signal to the trigger control module, and send an erase instruction, a read-write instruction and the configuration program to be upgraded to the configuration chip;

[0016] The configuration chip is also used to erase the stored current configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction.

[0017] In some embodiments, the trigger control module includes at least a reset logic circuit;

[0018] The reset logic circuit is used to obtain the trigger signal, and generate a reset clear signal according to a comparison result between the trigger signal and a reference level, and the stretch width of the effective level of the reset clear signal is greater than or equal to a preset threshold.

[0019] In some embodiments, the reset logic circuit includes at least one charging capacitor; and the stretching width of the effective level of the reset clear signal is positively correlated with the charging time of the charging capacitor.

[0020] In some embodiments, the reset logic circuit is further configured to output a reload signal when the voltage of the external input power supply is lower than the reference level;

[0021] The self-loading module drives the first interface to connect in response to the reloading signal, so that the control module reloads the configuration program of the FPGA through the first interface.

[0022] In some embodiments, when the effective level of the reset clear signal is a low level, the trigger control module includes a first resistor and a second resistor; a first end of the first resistor is connected to an external input power supply, and a second end of the first resistor is connected to an input end of the trigger control module; a first end of the second resistor is connected to the external input power supply, and a second end of the second resistor is connected to an output end of the trigger control module;

[0023] The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a second switch tube, a sixth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor and a logic AND gate;

[0024] The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the control end of the second switch tube is connected to the second end of the fifth resistor, and the second end of the second switch tube is connected to the preset voltage end; the first end of the sixth resistor is connected to the first end of the second switch tube; the first end of the seventh resistor is connected to the external input power supply; the non-inverting input end of the first comparator is connected to the second end of the sixth resistor, and the inverting input end of the first comparator is connected to the second end of the sixth resistor. The input terminal is connected to the second end of the seventh resistor; the first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the preset voltage terminal; the first end of the ninth resistor is connected to the external input terminal, and the second end of the ninth resistor is connected to the second end of the sixth resistor; the first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the preset voltage terminal; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input terminal of the logic AND gate is connected to the output terminal of the first comparator, the second input terminal of the logic AND gate is connected to the reference level, and the output terminal of the logic AND gate is connected to the second end of the second resistor.

[0025] In some embodiments, when the effective level of the reset clear signal is a high level, the trigger control module includes a first resistor and a second resistor; a first end of the first resistor is connected to an external input power supply, and a second end of the first resistor is connected to an input end of the trigger control module; a first end of the second resistor is connected to an output end of the trigger control module, and a second end of the second resistor is connected to a preset voltage end;

[0026] The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a second switch tube, a sixth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor, a logic AND gate and an inverter;

[0027] The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the control end of the second switch tube is connected to the second end of the fifth resistor, and the second end of the second switch tube is connected to the preset voltage end; the first end of the sixth resistor is connected to the first end of the second switch tube; the first end of the seventh resistor is connected to the external input power supply; the non-inverting input end of the first comparator is connected to the second end of the sixth resistor, and the inverting input end of the first comparator is connected to the inverting input end of the seventh resistor The first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the preset voltage terminal; the first end of the ninth resistor is connected to the external input terminal, and the second end of the ninth resistor is connected to the second end of the sixth resistor; the first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the preset voltage terminal; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input terminal of the logic AND gate is connected to the output terminal of the first comparator, and the second input terminal of the logic AND gate is connected to the reference level; the first end of the inverter is connected to the output terminal of the logic AND gate, and the second end of the inverter is connected to the second end of the second resistor.

[0028] In some embodiments, the reset logic circuit further includes a drop voltage detection circuit;

[0029] The drop voltage detection circuit includes an eleventh resistor, a second comparator and a twelfth resistor;

[0030] The first end of the eleventh resistor is connected to the external input power supply; the non-inverting input end of the second comparator is connected to the second end of the eleventh resistor, the inverting input end of the second comparator is connected to the reference level, and the output end of the second comparator is connected to the second input end of the logic AND gate; the first end of the twelfth resistor is connected to the second end of the eleventh resistor, and the second end of the twelfth resistor is connected to the preset voltage end.

[0031] In some embodiments, when the effective level of the reset clear signal is a high level, the trigger control module includes a first resistor and a second resistor; a first end of the first resistor is connected to an external input power supply, and a second end of the first resistor is connected to an input end of the trigger control module; a first end of the second resistor is connected to an output end of the trigger control module, and a second end of the second resistor is connected to a preset voltage end;

[0032] The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor and a logic OR gate;

[0033] The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the non-inverting input end of the first comparator is connected to the second end of the fifth resistor, and the inverting input end of the first comparator is connected to the second end of the seventh resistor; the first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the The first end of the ninth resistor is connected to the external input terminal, and the second end of the ninth resistor is connected to the non-inverting input terminal of the first comparator; the first end of the tenth resistor is connected to the second end of the ninth resistor, and the second end of the tenth resistor is connected to the preset voltage terminal; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input end of the logic OR gate is connected to the output end of the first comparator, the second input end of the logic OR gate is connected to the reference level, for obtaining the reference level, and the output end of the logic OR gate is connected to the first end of the second resistor;

[0034] And, the reset logic circuit also includes a drop voltage detection circuit;

[0035] The drop voltage detection circuit includes an eleventh resistor, a second comparator and a twelfth resistor;

[0036] The first end of the eleventh resistor is connected to the external input power supply; the non-inverting input end of the second comparator is connected to the reference level, the inverting input end of the second comparator is connected to, and the output end of the second comparator is connected to the second input end of the logic OR gate; the first end of the twelfth resistor is connected to the second end of the eleventh resistor, and the second end of the twelfth resistor is connected to the preset voltage end.

[0037] In some embodiments, the reset logic circuit is any one of the control chips of ADI MAX 70 series, TITPS3820 series or STM32 series single chip microcomputers.

[0038] In a second aspect, an embodiment of the present application provides an FPGA upgrade method, which is applied to the FPGA upgrade system as described in any embodiment of the first aspect; the method includes:

[0039] Obtain the upgrade instructions and configuration program to be upgraded issued by the host computer;

[0040] In response to the upgrade instruction sent by the host computer, output a trigger signal to the trigger control module, and send an erase instruction, a read / write instruction and the configuration program to be upgraded to the configuration chip;

[0041] Control the configuration chip to erase the current configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction;

[0042] Controlling the self-loading module to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module;

[0043] Load the configuration program to be upgraded and upgrade the FPGA.

[0044] In some embodiments, the FPGA upgrade method further includes:

[0045] Get the single erase command issued by the host computer;

[0046] In response to the single erase instruction, the self-loading module is controlled to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module.

[0047] The FPGA upgrade system and the FPGA upgrade method applied to the system provided by the embodiment of the present application, the system at least includes an FPGA chip, a configuration chip storing the configuration program of the FPGA, and a trigger control module; the trigger control module responds to the trigger signal input from the outside to generate a reset clear signal, and transmits the reset clear signal to the FPGA chip through the second interface. After receiving the reset clear signal, the FPGA chip controls the clearing of its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip through the first interface to complete the upgrade of the FPGA. By controlling the widening width of the reset clear signal output by the trigger control module, the FPGA can be ensured to stably and reliably clear the current configuration program and load the updated configuration program under non-power-off conditions. Compared with the prior art, it no longer depends on the response time after the FPGA is enabled and the timing of its output trigger signal, and the reset clear signal widening width is controlled at a low cost, which improves the stability and reliability of the FPGA upgrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0049] Figure 1 A schematic diagram of the structure of an FPGA upgrade system provided in one embodiment of the present application.

[0050] Figure 2 A schematic diagram of the structure of an FPGA upgrade system provided in another embodiment of the present application.

[0051] Figure 3 A schematic diagram of the structure of a trigger control module provided in one embodiment of the present application.

[0052] Figure 4 A circuit diagram of a trigger control module provided in one embodiment of the present application.

[0053] Figure 5 A circuit diagram of a trigger control module provided in another embodiment of the present application.

[0054] Figure 6 A comparison chart of charging times calculated according to an embodiment of the present application.

[0055] Figure 7 A circuit diagram of a trigger control module provided in yet another embodiment of the present application.

[0056] Figure 8 A circuit diagram of a trigger control module provided in yet another embodiment of the present application.

[0057] Fig. 9A flowchart of an FPGA upgrade method provided in one embodiment of the present application.

[0058] Fig.10 A flowchart of an FPGA upgrade method provided in another embodiment of the present application.

[0059] Fig.11 A flowchart of an FPGA upgrade method provided in yet another embodiment of the present application.

[0060] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0061] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0062] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0063] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are usually a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated before and after are in an "or" relationship. The "connection" and "connection" mentioned in this application, unless otherwise specified, include direct and indirect connections (connections).

[0064] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0065] Figure 1 This is a schematic diagram of the structure of an FPGA upgrade system provided by an embodiment of the present application. Figure 1 As shown, the FPGA upgrade system provided in this embodiment at least includes an FPGA chip 110 , a configuration chip 120 and a trigger control module 130 .

[0066] In this embodiment, the FPGA chip 110 has at least a first interface 1101 and a second interface 1102 , wherein the first interface 1101 is used to connect the FPGA chip 110 and the configuration chip 120 , and the second interface 1102 is used to connect the FPGA chip 110 and the trigger control module 130 .

[0067] Configuration chip 120 is a chip that stores and provides FPGA configuration programs. These configuration programs define the logical functions and connection relationships within the FPGA. The main function of configuration chip 120 is to store the configuration program of the FPGA and load these data into the FPGA when the FPGA is powered on or reset. Common configuration chips include Flash memory, EPROM (erasable programmable read-only memory), PROM (programmable read-only memory), and SRAM (static random access memory). Each type of configuration chip has different advantages. According to different application scenarios, selecting and using different types of configuration chips can ensure the stable operation and performance of the FPGA.

[0068] It is understandable that the configuration chip supports multiple configuration modes to adapt to different application requirements. Common configuration modes include active configuration mode, passive configuration mode and JTAG configuration mode. Active configuration mode is that the FPGA reads configuration data from an external memory (such as Flash) and configures itself. Passive configuration mode is that the FPGA is controlled by an external device (such as a microprocessor), reads configuration data from an external memory and configures it. JTAG configuration mode is to download configuration data to the FPGA through the JTAG interface. This configuration mode is usually used in the debugging and programming stages.

[0069] This embodiment is mainly used to solve the problem that the FPGA in the passive configuration mode depends on the response time and timing of the trigger signal sent by the FPGA to the configuration chip 120, which has certain limitations. In this embodiment, the trigger control module 130 is used to respond to an external input trigger signal, generate a reset clear signal, and input the reset clear signal to the FPGA chip 110 through the second interface 1102 of the FPGA chip 110. After receiving the reset clear signal, the FPGA chip 110 controls the clearing of its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip 120 through the first interface 1101.

[0070] In some prior art, for example: CN113360198, a method for updating FPGA configuration online using only FPGA itself, specifically, the host computer is connected to the host computer interface of the FPGA program; the host computer driver transmits the erase command, read-write command and configuration file to the host computer interface; the host computer interface transmits the erase command, read-write command and configuration file to the FLASH controller; the FLASH controller executes the erase command to erase FLASH and burns the configuration file to FLASH according to the read-write command; when receiving the online update command from the host computer, the FPGA controls the IO pin to output a pull-down pulse signal, the program_b signal is pulled low, and the FPGA starts FLASH loading. The present invention can realize online update without power failure; under the condition of scene restrictions, it can also realize online update, which makes up for the deficiency of using JTAG download equipment for burning, which needs to be opened and restricted by the scene without adding extra cost.

[0071] The FPGA's own online update method can achieve FPGA online update without power failure, but this method relies on the rising edge timing of the trigger path to complete, as well as the FPGA response time after PROGRAM_B is enabled, and the reliability is not high.

[0072] To solve the above problems, the width of the reset clear signal in this embodiment is controllable, and this feature can bring multiple significant advantages. When the reset signal is widened, it can remain valid for a longer time, thereby reducing the risk of reset failure due to signal jitter or instability. The widened reset signal can more reliably trigger the reset operation of the configuration chip 120, ensuring that the FPGA can correctly reload the configuration data. Secondly, by controlling the width of the reset signal, a short-term unstable state that occurs during the power-on or reset process of the FPGA can be avoided. This helps to reduce the failure rate of the system due to configuration errors or instability, thereby improving the overall stability of the system. In some prior art, a method for updating FPGA configuration online using only FPGA itself, specifically, a host computer is connected to the host computer interface of the FPGA program; the host computer driver transmits the erase command, read-write command and configuration file to the host computer interface; the host computer interface transmits the erase command, read-write command and configuration file to the FLASH controller; the FLASH controller executes the erase command to erase FLASH and burns the configuration file to FLASH according to the read-write command; when receiving the online update command of the host computer, the FPGA controls the IO pin to output a pull-down pulse signal, the program_b signal is pulled low, and the FPGA starts FLASH loading. The present invention can realize online update without power failure; under the condition of scene restrictions, it can also realize online update, which makes up for the deficiency of using JTAG download device for burning and needs to be opened and restricted by the scene without adding extra cost. And, for some FPGA designs, accurate timing control is crucial. By controlling the widening width of the reset signal, these timing requirements can be more easily met, which helps to simplify the timing design process and reduce the design difficulty and cost. At the same time, the controllable reset signal width makes the reset operation more flexible. For example, when a quick reset is required, the reset signal width can be shortened; when the reset operation needs to be stable, the reset signal width can be increased. This flexibility helps to adapt to different application scenarios and needs.

[0073] Controlling the width of the reset clear signal of the trigger configuration chip 120 brings many significant advantages in the FPGA upgrade process, including ensuring the reliability of the reset signal, enhancing the stability of the system, simplifying the timing design, improving the flexibility of the reset operation, and supporting remote update and debugging, etc. These advantages help reduce the complexity and cost of FPGA design and application, and improve the overall performance and reliability of the system.

[0074] In summary, the FPGA upgrade system provided in this embodiment generates a reset clear signal in response to an external input trigger signal through the trigger control module 130, and transmits the reset clear signal to the FPGA chip 110 through the second interface 1102. After receiving the reset clear signal, the FPGA chip 110 controls the clearing of its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip 120 through the first interface 1101, thereby completing the upgrade of the FPGA. Based on the reset clear signal with controllable width, the FPGA can be ensured to stably and reliably clear the current configuration program and load the updated configuration program under non-power-off conditions.

[0075] Figure 2 This is a schematic diagram of the structure of an FPGA upgrade system provided by another embodiment of the present application. Figure 2 As shown, the FPGA upgrade system provided in this embodiment is based on any of the above embodiments, and the FPGA chip 110 also includes a PCIe interface 1103, an AXI Lite control module 1104, a user control module 1105, a self-loading module 1106 and a third interface 1107.

[0076] In this embodiment, the PCIe interface 1103 is used to connect the FPGA chip 110 with a host computer for sending upgrade instructions and configuration programs to be upgraded, that is, the FPGA chip 110 establishes communication with the external host computer through the PCIe interface 1103. When the FPGA chip 110 needs to be upgraded, the host will send the upgrade instructions and the configuration program to be upgraded to the FPGA chip 110 through the PCIe interface 1103.

[0077] In some embodiments, the host computer can interact with the user through an upgrade software (such as GUI or command line based software) and complete the loading of new configuration data, wherein the upgrade software can be a separate software, and the software can provide a call interface to other software so that other software can call the software to complete the FPGA upgrade. In addition, the upgrade software can also be a software or multiple software modules in other software, which is not limited in this embodiment.

[0078] In some embodiments, the host can send an upgrade instruction to the FPGA through the PCIe interface 1103 through the installed upgrade program, and the upgrade instruction is used to notify the FPGA to upgrade. It should be noted that in order to enable the FPGA to be upgraded, it is necessary to store the upgrade data for the FPGA upgrade in the FPGA configuration memory in advance, and the upgrade data can specifically be the new configuration data of the FPGA. Specifically, the new configuration data can be transmitted to the FPGA through the PCIe interface 1103 by the host, and then transmitted to the FPGA configuration memory by the FPGA through an interface (such as an SPI interface or other custom interface). Transmission in this way can realize remote online loading, that is, the host can be controlled through the network to load the new configuration data into the FPGA configuration memory, and the loading of the new configuration data can be completed without manual operation on site.

[0079] In this embodiment, the self-loading module 1106 is connected between the first interface 1101 and the third interface 1107, that is, the third interface 1107 is used to connect the trigger control module 130 and the self-loading module 1106, and the self-loading module 1106 drives the first interface 1101 to be connected in response to the effective level of the reset clear signal output by the trigger control module 130.

[0080] In some embodiments, the third interface 1107 is a clear configuration pin of the FPGA.

[0081] The user control module 1105 is used to respond to the upgrade instruction sent by the host computer, output a trigger signal to the trigger control module 130, and send an erase instruction, a read / write instruction and a configuration program to be upgraded to the configuration chip 120.

[0082] The AXI Lite control module 1104 is connected between the PCIe interface 1103 and the user control module 1105. AXI Lite (AXI4-Lite) is a simplified version of the AXI (Advanced eXtensible Interface) protocol launched by ARM, which is mainly used to control register access and low-throughput data transmission. AXI Lite is often used by the processor to read and write configuration registers of peripherals. The AXI Lite control module 1104 includes at least an AXI Lite interface, an AXI write channel, an AXI read channel, and an IRQ (interrupt request) unit, which can realize simple and reliable communication between PCIe interfaces 1103.

[0083] The configuration chip 120 is also used to erase the currently stored configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction.

[0084] It should be noted that the main improvement of the embodiment of the present application is that during the FPGA upgrade process, the reset clear signal with controllable widening width output by the trigger control module 130 can ensure that the FPGA stably and reliably clears the current configuration program and loads the updated configuration program. Therefore, the trigger control module 130 in the present application can be applied to any FPGA upgrade system, all of which have the technical effects of the above-mentioned trigger control module 130, and does not limit the specific structure of the FPGA upgrade system. Other structures of the FPGA upgrade system provided in the present application are not described in detail here.

[0085] The following describes how the trigger control module 130 outputs a reset clearing signal with controllable widening width according to the trigger signal.

[0086] Figure 3 This is a schematic diagram of the structure of a trigger control module provided by an embodiment of the present application. Figure 3 As shown, the trigger control module 130 in this embodiment at least includes a first resistor R1, a second resistor R2 and a reset logic circuit.

[0087] In this embodiment, the first end of the first resistor R1 is connected to an external input power supply, and the second end of the first resistor R1 is connected to the input end of the trigger control module 130, that is, connected to the second interface 1102 of the FPGA chip 110, for obtaining the trigger signal output by the FPGA chip 110; the first end of the second resistor R2 is connected to the external input power supply, and the second end of the second resistor R2 is connected to the output end of the trigger control module 130, that is, connected to the third interface 1107 of the FPGA chip 110, and outputs a reset clear signal to the self-loading module 1106. The first end of the reset logic circuit is connected to the second end of the first resistor R1, and the second end of the reset logic circuit is connected to the second end of the second resistor R2.

[0088] The reset logic circuit is used to obtain a trigger signal, and generates a reset clear signal according to the comparison result between the trigger signal and a reference level, and the width of the effective level of the reset clear signal is greater than or equal to a preset threshold. It can be understood that the first resistor R1 is a pull-up resistor connected to the output end of the second interface 1102 of the FPGA chip 110. When the trigger signal output by the FPGA chip 110 is detected to be at an effective level, the reset logic circuit will be triggered to generate an effective pulse, that is, a reset clear signal, and output it to the self-loading module 1106 to ensure the startup action of the self-loading module 1106.

[0089] If the effective level of the reset clear signal is a low level, then when the trigger signal output by the FPGA chip 110 is detected to be a low level, the reset logic circuit will be triggered to generate a low effective pulse with a width greater than or equal to a preset threshold, so as to ensure that the reset clear signal received by the third pin (clear configuration pin) of the FPGA chip 110 can reliably trigger the startup action of the loading module from the falling edge to the rising edge.

[0090] Similarly, if the effective level of the reset clear signal is a high level, when the trigger signal output by the FPGA chip 110 is detected to be a low level, the reset logic circuit will be triggered to generate a high effective pulse with a width greater than or equal to a preset threshold, so as to ensure that the reset clear signal received by the third pin (clear configuration pin) of the FPGA chip 110 can reliably trigger the startup action of the loading module from the rising edge to the falling edge.

[0091] In some embodiments, the reset logic circuit includes at least one charging capacitor, and the width of the effective level of the reset clear signal is positively correlated with the charging time of the charging capacitor.

[0092] In some embodiments, the reset logic circuit is further configured to output a reload signal when the voltage of the external input power supply is lower than a reference level. The self-loading module 1106 drives the first interface 1101 to connect in response to the reload signal, so that the control module reloads the configuration program of the FPGA through the first interface 1101.

[0093] Figure 4 A circuit diagram of a trigger control module provided in one embodiment of the present application. Figure 4 As shown, assuming that the reset clear signal output by the trigger control module 130 is low level effective, the trigger control module 130 provided in this embodiment includes a first resistor R1, a second resistor R2 and a reset logic circuit.

[0094] In this embodiment, the reset logic circuit includes a third resistor R3, a fourth resistor R4, a first switch tube Q1, a fifth resistor R5, a second switch tube Q2, a sixth resistor R6, a seventh resistor R7, a first comparator Z1, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a charging capacitor C1 and a logic AND gate Z3.

[0095] Specifically, the first end of the third resistor R3 is connected to the input end of the reset logic circuit, that is, the second end of the first resistor R1; the first end of the fourth resistor R4 is connected to the external input power supply; the control end of the first switch tube Q1 is connected to the second end of the first resistor R1, the first end of the first switch tube Q1 is connected to the second end of the fourth resistor R4, and the second end of the first switch tube Q1 is connected to the preset voltage end; the first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4; the control end of the second switch tube Q2 is connected to the second end of the fifth resistor R5, and the second end of the second switch tube Q2 is connected to the preset voltage end; the first end of the sixth resistor R6 is connected to the first end of the second switch tube Q2; the first end of the seventh resistor R7 is connected to the external input power supply; the in-phase input end of the first comparator Z1 is connected to the second end of the sixth resistor R6, and the inverting input end of the first comparator Z1 is connected to the second end of the sixth resistor R6. The input terminal is connected to the second end of the seventh resistor R7; the first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 is connected to the preset voltage terminal; the first end of the ninth resistor R9 is connected to the external input terminal, and the second end of the ninth resistor R9 is connected to the second end of the sixth resistor R6; the first end of the tenth resistor R10 is connected to the second end of the sixth resistor R6, and the second end of the tenth resistor R10 is connected to the preset voltage terminal; the first end of the charging capacitor C1 is connected to the first end of the tenth resistor R10, and the second end of the charging capacitor C1 is connected to the second end of the tenth resistor R10; the first input terminal of the logic AND gate Z3 is connected to the output terminal of the first comparator Z1, the second input terminal of the logic AND gate Z3 is connected to the reference level, and the output terminal of the logic AND gate Z3 is connected to the output terminal of the reset logic circuit, that is, connected to the second end of the second resistor R2.

[0096] like Figure 4 As shown, when the trigger signal output by the second interface 1102 (trigger start IO pin) of the FPGA chip is high, the input end of the reset logic circuit obtains a high-level signal, the first switch tube Q1 is in a saturated state, its emitter and collector are turned on, the second switch tube Q2 is in a cut-off state, and the level of the in-phase input end of the first comparator Z1 is determined by the voltage divider of the ninth resistor R9 and the tenth resistor R10; when the trigger signal output by the second interface 1102 of the FPGA chip 110 is low, the input end of the reset logic circuit obtains a low-level signal, the first switch tube Q1 is in a cut-off state, the second switch tube Q2 is in a saturated state, its emitter and collector are turned on, the sixth resistor R6 is a low resistance, and the level of the in-phase input end of the first comparator Z1 is close to being short-circuited with the ground.

[0097] The first comparator Z1, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the charging capacitor C1 form a pulse stretching circuit. The seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10 can all be regarded as voltage divider resistors. In some embodiments, the default voltage divider ratio of the voltage divider resistors satisfies: the voltage at the in-phase input terminal of the first comparator Z1 is Greater than its inverting input voltage ,Right now .

[0098]

[0099]

[0100] based on , we can get:

[0101]

[0102] As mentioned above, a low-level signal is obtained at the input end of the reset logic circuit, the second switch tube Q2 is in a saturated state, its emitter and collector are turned on, the sixth resistor R6 is low resistance, and the level of the in-phase input end of the first comparator Z1 is close to being short-circuited to the ground. The voltage of the in-phase input end of the first comparator Z1 will be quickly discharged to a low level. If the voltage of the inverting input end of the first comparator Z1 Remain unchanged, at this time , the output end of the first comparator Z1 outputs a low level.

[0103] A high level signal is obtained at the input end of the reset logic circuit, the second switch tube Q2 is in the cut-off state, and the external input power supply VCC charges the charging capacitor C1 through the ninth resistor R9 and the tenth resistor R10 (R9 / / R10) connected in parallel. When the charging capacitor C1 is charged to Greater than When , the output terminal of the first comparator Z1 will output a high level.

[0104] It can be seen that the width of the low level pulse of the output signal of the first comparator Z1 is determined by the charging time t of the charging capacitor C1.

[0105] The charging time t of the charging capacitor C1 satisfies:

[0106]

[0107] Where C1 is the charging capacitor value, is the equivalent resistance value of the ninth resistor R9 and the tenth resistor R10 in parallel, V0 is the initial voltage of the charging capacitor C1, V1 is the full voltage of the charging capacitor C1, and Vt is the comparator state flip value charged to the charging capacitor C1. In an ideal state, the initial voltage V0 is approximately equal to 0V when it is quickly discharged, and Vt is approximately equal to (In actual application, add the comparator response hysteresis coefficient σ), V1 is equal to , from which we can get,

[0108]

[0109]

[0110]

[0111] Thereby, the charging time t of the charging capacitor C1 , ie, the extension width of the low level pulse of the output signal of the first comparator Z1 , can be further determined.

[0112] The first input terminal of the logic AND gate Z3 is connected to the output terminal of the first comparator Z1, and the second input terminal of the logic AND gate Z3 is connected to the reference level. According to the operation rule of the logic AND gate Z3, when at least one of the output terminal of the first comparator Z1 and the reference level outputs a low level, the output terminal of the logic AND gate Z3 will output a low level, that is, the reset clear signal output by the reset logic circuit is a low level; when both the first comparator Z1 and the second comparator Z2 output a high level, the output terminal of the logic AND gate Z3 will output a high level, that is, the reset clear signal output by the reset logic circuit is a high level.

[0113] It can be known that the logic AND gate Z3 is only a logic operation and will not change the width of the signal, that is, when determining the width of the low level pulse of the output signal of the first comparator Z1, the width of the reset clear signal output by the reset logic circuit is also determined.

[0114] Figure 5 This is a circuit diagram of a trigger control module provided in another embodiment of the present application. Figure 5 As shown, the trigger control module 130 provided in this embodiment is based on the above embodiment, and the reset logic circuit further includes a drop voltage detection circuit. The drop voltage detection circuit includes an eleventh resistor R11, a second comparator Z2 and a twelfth resistor.

[0115] Specifically, the first end of the eleventh resistor R11 is connected to the external input power supply; the non-inverting input terminal of the second comparator Z2 is connected to the second end of the eleventh resistor R11, the inverting input terminal of the second comparator Z2 is connected to the reference level, and the output terminal of the second comparator Z2 is connected to the second input terminal of the logic AND gate Z3; the first end of the twelfth resistor is connected to the second end of the eleventh resistor R11, and the second end of the twelfth resistor is connected to the preset voltage terminal.

[0116] The reset logic circuit is also used to output a reloading signal to the self-loading module 1106 when the voltage of the external input power supply is lower than the reference level. The self-loading module 1106 responds to the reloading signal to drive the first interface 1101 to be connected, so that the control module reloads the configuration program of the FPGA through the first interface 1101.

[0117] like Figure 5 As shown, the voltage at the non-inverting input terminal of the second comparator Z2 is satisfy:

[0118]

[0119] When the voltage at the non-inverting input terminal of the second comparator Z2 Less than reference level When , the output terminal of the second comparator Z2 will output a low level; when the voltage at the non-inverting input terminal of the second comparator Z2 Greater than reference level When , the output terminal of the second comparator Z2 will output a high level.

[0120] The first input terminal of the logic AND gate Z3 is connected to the output terminal of the first comparator Z1, and the second input terminal of the logic AND gate Z3 is connected to the output terminal of the second comparator Z2. According to the operation rule of the logic AND gate Z3, only if at least one of the first comparator Z1 and the second comparator Z2 outputs a low level, the output terminal of the logic AND gate Z3 will output a low level, that is, the reset clear signal output by the reset logic circuit is a low level; when both the first comparator Z1 and the second comparator Z2 output a high level, the output terminal of the logic AND gate Z3 will output a high level, that is, the reset clear signal output by the reset logic circuit is a high level.

[0121] In one possible embodiment, Figure 5 The parameters of the various components in the circuit of the trigger control module 130 shown in Table 1 can be referred to.

[0122] Table 1 Parameters of each component

[0123]

[0124] According to the above formula, the charging time of the charging capacitor C1 in the reset logic circuit can be calculated. The calculation results are shown in Table 2.

[0125] Table 2 Calculation of charging time for charging capacitor

[0126]

[0127] Figure 6 This is a comparison chart of the charging time calculated according to an embodiment of the present application. Figure 6 As shown, the charging capacitor C1 is assigned values ​​of 1.8uF, 2.2uF, and 3.3uF respectively, and the charging times (output low-level pulse widths) t1, t2, and t3 are obtained. It can be directly seen that the widening width of the effective level of the reset clear signal is positively correlated with the charging time of the charging capacitor C1.

[0128] Figure 7 A circuit diagram of a trigger control module provided in yet another embodiment of the present application. Figure 7 As shown, the trigger control module 130 provided in this embodiment includes a first resistor R1, a second resistor R2 and a reset logic circuit, wherein the effective level of the reset clear signal output by the trigger control module 130 is a high level. Figure 5 In the embodiment shown, in this embodiment, the second resistor R2 is changed from a pull-up resistor to a weak pull-down resistor, that is, the first end of the second resistor R2 is connected to the output end of the trigger control module for outputting a reset clear signal, and the second end of the second resistor R2 is connected to the preset voltage end. At the same time, the reset logic circuit adds an inverter Z4 at the output end of the logic AND gate Z3 to achieve the level flipping, so as to achieve the purpose of the effective level of the reset clear signal being a high level.

[0129] like Figure 7 As shown, the reset logic circuit in this embodiment includes a third resistor R3, a fourth resistor R4, a first switch tube Q1, a fifth resistor R5, a second switch tube Q2, a sixth resistor R6, a seventh resistor R7, a first comparator Z1, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a charging capacitor C1, a logic AND gate Z3 and an inverter Z4.

[0130] Specifically, a first end of the third resistor R3 is connected to an input end of the reset logic circuit; a first end of the fourth resistor R4 is connected to an external input power supply; a control end of the first switch tube Q1 is connected to a second end of the first resistor R1, a first end of the first switch tube Q1 is connected to a second end of the fourth resistor R4, and a second end of the first switch tube Q1 is connected to a preset voltage end; a first end of the fifth resistor R5 is connected to a second end of the fourth resistor R4; a control end of the second switch tube Q2 is connected to a second end of the fifth resistor R5, and a second end of the second switch tube Q2 is connected to a preset voltage end; a first end of the sixth resistor R6 is connected to a first end of the second switch tube Q2; a first end of the seventh resistor R7 is connected to an external input power supply; a non-inverting input end of the first comparator Z1 is connected to a second end of the sixth resistor R6, and an inverting input end of the first comparator Z1 is connected to a The first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 is connected to the preset voltage end; the first end of the ninth resistor R9 is connected to the external input end, and the second end of the ninth resistor R9 is connected to the second end of the sixth resistor R6; the first end of the tenth resistor R10 is connected to the second end of the sixth resistor R6, and the second end of the tenth resistor R10 is connected to the preset voltage end; the first end of the charging capacitor C1 is connected to the first end of the tenth resistor R10, and the second end of the charging capacitor C1 is connected to the second end of the tenth resistor R10; the first input end of the logic AND gate Z3 is connected to the output end of the first comparator Z1, and the second input end of the logic AND gate Z3 is connected to the reference level; the first end of the inverter Z4 is connected to the output end of the logic AND gate Z3, and the second end of the inverter Z4 is connected to the second end of the second resistor R2.

[0131] Likewise, the reset logic circuit also includes a drop voltage detection circuit.

[0132] The working principle of the reset logic circuit provided in this embodiment is the same as that of the above embodiment, and the technical effect achieved is also the same. To avoid repetition, it will not be described again here.

[0133] Figure 8 The circuit diagram of the trigger control module provided in another embodiment of the present application. The reset clear signal output by the trigger control module 130 can also be high level effective, such as Figure 8 As shown, the trigger control module 130 provided in this embodiment includes a first resistor R1, a second resistor R2 and a reset logic circuit.

[0134] The trigger control module 130 provided in this embodiment includes a first resistor R1, a second resistor R2 and a reset logic circuit. Figure 7In the embodiment shown, in this embodiment, the second resistor R2 is changed from a pull-up resistor to a weak pull-down resistor, that is, the first end of the second resistor R2 is connected to the output end of the trigger control module for outputting a reset clear signal, and the second end of the second resistor R2 is connected to the preset voltage end. At the same time, the reset logic circuit reduces the second switch tube Q2, which can achieve that the level of the signal obtained by the in-phase input end of the first comparator Z1 is opposite to the level of the trigger signal obtained by the output end of the reset logic circuit. After passing through the subsequent circuit, the level of the reset clear signal output by the reset logic circuit is also opposite to the level of the trigger signal, so that when the trigger signal is low, the reset clear signal is high; when the trigger signal is high, the reset clear signal is low, so that the reset clear signal output by the trigger control module can also be high-level effective. Technical effect.

[0135] like Figure 8 As shown, the reset logic circuit provided in this embodiment includes a third resistor R3, a fourth resistor R4, a first switch tube Q1, a fifth resistor R5, a seventh resistor R7, a first comparator Z1, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a charging capacitor C1 and a logic OR gate Z3.

[0136] Specifically, a first end of the third resistor R3 is connected to an input end of the reset logic circuit; a first end of the fourth resistor R4 is connected to an external input power supply; a control end of the first switch tube Q1 is connected to a second end of the first resistor R1, a first end of the first switch tube Q1 is connected to a second end of the fourth resistor R4, and a second end of the first switch tube Q1 is connected to a preset voltage end; a first end of the fifth resistor R5 is connected to a second end of the fourth resistor R4; a non-inverting input end of the first comparator Z1 is connected to a second end of the fifth resistor R5, and an inverting input end of the first comparator Z1 is connected to a second end of the seventh resistor R7; a first end of the eighth resistor R8 is connected to a second end of the seventh resistor R7, and a second end of the eighth resistor R8 is connected to a second end of the seventh resistor R7; connected to the preset voltage terminal; the first end of the ninth resistor R9 is connected to the external input terminal, and the second end of the ninth resistor R9 is connected to the in-phase input terminal of the first comparator Z1; the first end of the tenth resistor R10 is connected to the second end of the ninth resistor R9, and the second end of the tenth resistor R10 is connected to the preset voltage terminal; the first end of the charging capacitor C1 is connected to the first end of the tenth resistor R10, and the second end of the charging capacitor C1 is connected to the second end of the tenth resistor R10; the first input terminal of the logic OR gate Z3 is connected to the output terminal of the first comparator Z1, the second input terminal of the logic OR gate Z3 is connected to the reference level, for obtaining the reference level, and the output terminal of the logic OR gate Z3 is connected to the first end of the second resistor R2.

[0137] Similarly, the reset logic circuit also includes a drop voltage detection circuit. Figure 7In the embodiment shown, in order to ensure the undervoltage triggering function, the non-inverting input terminal of the second comparator Z2 of the drop voltage detection circuit should be connected to the reference level. Figure 8 As shown, the drop voltage detection circuit includes an eleventh resistor R11, a second comparator Z2 and a twelfth resistor R12.

[0138] Specifically, the first end of the eleventh resistor R11 is connected to the external input power supply; the non-inverting input terminal of the second comparator Z2 is connected to the reference level, the inverting input terminal of the second comparator Z2 is connected to the output terminal of the second comparator Z2 is connected to the second input terminal of the logic OR gate Z3; the first end of the twelfth resistor R12 is connected to the second end of the eleventh resistor R11, and the second end of the twelfth resistor R12 is connected to the preset voltage terminal.

[0139] The working principle of the reset logic circuit provided in this embodiment is the same as that of the above embodiment, and the technical effect achieved is also the same. To avoid repetition, it will not be described again here.

[0140] The effective level of the trigger signal can be a low level or a high level. In the process of building the circuit, it can be determined according to actual needs, and then cleared according to the effective level of the defined reset clear signal, and finally the circuit is adjusted to meet the needs. Compared with other possible implementation examples, the principle is the same as any of the above embodiments, and to avoid repetition, it will not be repeated here.

[0141] Based on the reset logic circuit described in any of the above embodiments, in some embodiments, the reset logic circuit can also be implemented by a control chip or a single-chip microcomputer having the above logic function. For example: ADI MAX 705 / MAX706 / MAX707 / MAX708 series chips, TI's TPS3820 / TPS3823 / TPS3824 / TPS3825 / TPS3828 series chips. Another example: STMicroelectronics STM32 series single-chip microcomputer, through the detection of IO pins by the CPU / ARM counter, realizes the reset clear pulse detection, and outputs the function through another IO pin after delay and widening, and at the same time, the ADC integrated in the single-chip microcomputer performs undervoltage detection function to realize abnormal loading function.

[0142] Fig. 9 This is a flowchart of an FPGA upgrade method provided by an embodiment of the present application. The FPGA upgrade method of this embodiment is applied to the FPGA upgrade system described in any of the above embodiments, and the FPGA upgrade method is introduced based on the application scenario where the FPGA chip is connected to the host computer through a PCIe slot. Fig. 9 As shown, each step in the FPGA upgrade method provided in this embodiment is executed by the FPGA chip, and specifically includes the following steps:

[0143] Step S901: Obtain the upgrade instruction and the configuration program to be upgraded issued by the host computer.

[0144] Step S902: In response to the upgrade instruction sent by the host computer, a trigger signal is output to the trigger control module, and an erase instruction, a read / write instruction and a configuration program to be upgraded are sent to the configuration chip.

[0145] Step S903: Control the configuration chip to erase the current configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction.

[0146] Step S904: Control the self-loading module to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module.

[0147] Step S905: load the configuration program to be upgraded and upgrade the FPGA.

[0148] The width of the reset clear signal is controllable, which can ensure that the FPGA can stably and reliably clear the current configuration program and load the updated configuration program without power failure.

[0149] In some embodiments, such as Fig.10 As shown, step S903, controlling the configuration chip to erase the current configuration program according to the erase instruction, and writing the configuration program to be upgraded according to the read-write instruction, specifically includes:

[0150] Step S9031, controlling the configuration chip to erase the current configuration program according to the erase instruction;

[0151] Step S9032, determining whether erasing the current configuration program is successful;

[0152] Step S9033: after determining that the erasure is successful, write the configuration program to be upgraded according to the read-write instruction;

[0153] Step S9034, determining whether the configuration program to be upgraded is written successfully;

[0154] Step S9035: After determining that the writing is successful, read in the configuration program to be upgraded for verification.

[0155] Fig.11 This is a flowchart of an FPGA upgrade method provided by another embodiment of the present application. Fig.11 As shown, in some embodiments, the FPGA upgrade method further includes:

[0156] Step S1101, obtaining a single erase instruction issued by a host computer;

[0157] Step S1102 , in response to the single erase instruction, the self-loading module is controlled to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module.

[0158] It should be noted that when there are multiple FPGA chips in the PCIE board, the first FPGA chip is used as the main FPGA chip, and the above method can also be used to complete the configuration. The other FPGA chips are used as slave FPGA chips. The host writes the configuration address and configuration program into the main FPGA chip through PCIE. The main FPGA chip will write the data into the configuration chip of the corresponding slave FPGA according to the address. After completion, a verification judgment is performed. After all the configuration data is written to the configuration chip of the corresponding FPGA, the self-loading module of the response FPGA is triggered to start according to the different trigger signals output by the main FPGA chip, and the upgrade and update of the FPGA is completed.

[0159] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the inspiration of the present application, ordinary technicians in the field can make several simple deductions, deformations or substitutions based on the ideas of the present application without departing from the scope of protection of the purpose of the present application and the claims. All of these are within the protection of the present application.

Claims

1. An FPGA upgrade system, characterized in that: Including FPGA chip, configuration chip and trigger control module; The FPGA chip has at least a first interface and a second interface; the first interface is used to connect the configuration chip; the second interface is used to connect the trigger control module; The configuration chip is used to store the configuration program of the FPGA; The trigger control module at least includes a reset logic circuit; The reset logic circuit is used to respond to an externally input trigger signal, generate a reset clear signal according to a comparison result between the trigger signal and a reference level, and input the reset clear signal to the FPGA chip through the second interface of the FPGA chip; wherein the reset logic circuit includes at least one charging capacitor, and the width of the effective level of the reset clear signal is controllable; After receiving the reset clear signal, the FPGA chip controls to clear its current configuration program, and obtains and loads the configuration program to be upgraded from the configuration chip through the first interface; In the case where the effective level of the reset clear signal is set to a high level, the trigger control module includes a first resistor and a second resistor; a first end of the first resistor is connected to an external input power supply, and a second end of the first resistor is connected to an input end of the trigger control module; a first end of the second resistor is connected to an output end of the trigger control module, and a second end of the second resistor is connected to a preset voltage end; The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a second switch tube, a sixth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor, a logic AND gate and an inverter; The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the control end of the second switch tube is connected to the second end of the fifth resistor, and the second end of the second switch tube is connected to the preset voltage end; the first end of the sixth resistor is connected to the first end of the second switch tube; the first end of the seventh resistor is connected to the external input power supply; the non-inverting input end of the first comparator is connected to the second end of the sixth resistor, and the inverting input end of the first comparator is connected to the inverting input end of the seventh resistor The first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the preset voltage end; the first end of the ninth resistor is connected to the external input power supply, and the second end of the ninth resistor is connected to the second end of the sixth resistor; the first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the preset voltage end; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input end of the logic AND gate is connected to the output end of the first comparator, and the second input end of the logic AND gate is connected to the reference level; the first end of the inverter is connected to the output end of the logic AND gate, and the second end of the inverter is connected to the second end of the second resistor.

2. The FPGA upgrade system according to claim 1, characterized in that: The FPGA chip includes a PCIe interface, a third interface, a user control module and a self-loading module; The PCIe interface is used to connect the FPGA chip with a host computer for issuing upgrade instructions and configuration programs to be upgraded; the third interface is used to connect the trigger control module and the self-loading module; The self-loading module is connected between the first interface and the third interface, and the self-loading module drives the first interface to be connected in response to the effective level of the reset clear signal output by the trigger control module; The user control module is used to respond to the upgrade instruction sent by the host computer, output a trigger signal to the trigger control module, and send an erase instruction, a read-write instruction and the configuration program to be upgraded to the configuration chip; The configuration chip is also used to erase the stored current configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction.

3. The FPGA upgrade system according to claim 2, characterized in that: The stretch width of the effective level of the reset clear signal is greater than or equal to a preset threshold.

4. The FPGA upgrade system according to claim 3, characterized in that: The width of the effective level of the reset clear signal is positively correlated with the charging time of the charging capacitor.

5. The FPGA upgrade system according to claim 3, characterized in that: The reset logic circuit is also used to output a reload signal when the voltage of the external input power supply is lower than the reference level; The self-loading module drives the first interface to connect in response to the reloading signal, so that the trigger control module reloads the configuration program of the FPGA through the first interface.

6. The FPGA upgrade system according to claim 1, characterized in that: In the case where the effective level of the reset clear signal is set to a low level, the trigger module is implemented as follows: the trigger control module includes a first resistor and a second resistor; the first end of the first resistor is connected to an external input power supply, and the second end of the first resistor is connected to the input end of the trigger control module; the first end of the second resistor is connected to the external input power supply, and the second end of the second resistor is connected to the output end of the trigger control module; The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a second switch tube, a sixth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor and a logic AND gate; The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the control end of the second switch tube is connected to the second end of the fifth resistor, and the second end of the second switch tube is connected to the preset voltage end; the first end of the sixth resistor is connected to the first end of the second switch tube; the first end of the seventh resistor is connected to the external input power supply; the non-inverting input end of the first comparator is connected to the second end of the sixth resistor, and the inverting input end of the first comparator is connected to the second end of the sixth resistor. The input end is connected to the second end of the seventh resistor; the first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the preset voltage end; the first end of the ninth resistor is connected to the external input power supply, and the second end of the ninth resistor is connected to the second end of the sixth resistor; the first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the preset voltage end; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input end of the logic AND gate is connected to the output end of the first comparator, the second input end of the logic AND gate is connected to the reference level, and the output end of the logic AND gate is connected to the second end of the second resistor.

7. The FPGA upgrade system according to any one of claims 1 to 6, characterized in that: The reset logic circuit also includes a drop voltage detection circuit; The drop voltage detection circuit includes an eleventh resistor, a second comparator and a twelfth resistor; The first end of the eleventh resistor is connected to the external input power supply; the non-inverting input end of the second comparator is connected to the second end of the eleventh resistor, the inverting input end of the second comparator is connected to the reference level, and the output end of the second comparator is connected to the second input end of the logic AND gate; the first end of the twelfth resistor is connected to the second end of the eleventh resistor, and the second end of the twelfth resistor is connected to the preset voltage end.

8. The FPGA upgrade system according to claim 1, characterized in that: In the case where the effective level of the reset clear signal is set to a high level, another implementation of the trigger module is: the trigger control module includes a first resistor and a second resistor; the first end of the first resistor is connected to an external input power supply, and the second end of the first resistor is connected to the input end of the trigger control module; the first end of the second resistor is connected to the output end of the trigger control module, and the second end of the second resistor is connected to the preset voltage end; The reset logic circuit includes a third resistor, a fourth resistor, a first switch tube, a fifth resistor, a seventh resistor, a first comparator, an eighth resistor, a ninth resistor, a tenth resistor, a charging capacitor and a logic OR gate; The first end of the third resistor is connected to the input end of the reset logic circuit; the first end of the fourth resistor is connected to the external input power supply; the control end of the first switch tube is connected to the second end of the first resistor, the first end of the first switch tube is connected to the second end of the fourth resistor, and the second end of the first switch tube is connected to the preset voltage end; the first end of the fifth resistor is connected to the second end of the fourth resistor; the non-inverting input end of the first comparator is connected to the second end of the fifth resistor, and the inverting input end of the first comparator is connected to the second end of the seventh resistor; the first end of the eighth resistor is connected to the second end of the seventh resistor, and the second end of the eighth resistor is connected to the The first end of the ninth resistor is connected to the external input power supply, and the second end of the ninth resistor is connected to the non-inverting input end of the first comparator; the first end of the tenth resistor is connected to the second end of the ninth resistor, and the second end of the tenth resistor is connected to the preset voltage end; the first end of the charging capacitor is connected to the first end of the tenth resistor, and the second end of the charging capacitor is connected to the second end of the tenth resistor; the first input end of the logic OR gate is connected to the output end of the first comparator, the second input end of the logic OR gate is connected to the reference level, for obtaining the reference level, and the output end of the logic OR gate is connected to the first end of the second resistor; And, the reset logic circuit also includes a drop voltage detection circuit; The drop voltage detection circuit includes an eleventh resistor, a second comparator and a twelfth resistor; The first end of the eleventh resistor is connected to the external input power supply; the non-inverting input end of the second comparator is connected to the reference level, the inverting input end of the second comparator is connected to, and the output end of the second comparator is connected to the second input end of the logic OR gate; the first end of the twelfth resistor is connected to the second end of the eleventh resistor, and the second end of the twelfth resistor is connected to the preset voltage end.

9. The FPGA upgrade system according to claim 3, characterized in that: The reset logic circuit is any one of the control chips of ADIMAX 70 series, TI TPS3820 series or STM32 series single chip microcomputers.

10. An FPGA upgrade method, applied to the FPGA upgrade system according to any one of claims 1 to 9; characterized in that: The method comprises: Obtain the upgrade instructions and configuration program to be upgraded issued by the host computer; In response to the upgrade instruction sent by the host computer, output a trigger signal to the trigger control module, and send an erase instruction, a read / write instruction and the configuration program to be upgraded to the configuration chip; Control the configuration chip to erase the current configuration program according to the erase instruction, and write the configuration program to be upgraded according to the read-write instruction; Controlling the self-loading module to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module; Load the configuration program to be upgraded and upgrade the FPGA.

11. The FPGA upgrade method according to claim 10, characterized in that: Also includes: Get the single erase command issued by the host computer; In response to the single erase instruction, the self-loading module is controlled to perform a logic reset on the FPGA according to the reset clear signal output by the trigger control module.

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