Task scheduling method and device, equipment, chip and storage medium

Abstract

The invention discloses a task scheduling method and device, equipment, a chip and a storage medium, and the method comprises the steps: determining a prediction performance index of a to-be-scheduled task when the to-be-scheduled task runs in one or more cores according to a first performance feature and a first performance demand of one or more cores, and a second performance feature and a second performance demand of the to-be-scheduled task; and determining a target core for running the to-be-scheduled task based on the predicted performance index when the to-be-scheduled task runs in one or more cores. Therefore, the working load characteristics of each core are represented through the performance characteristics and the performance requirements of each core, the performance expression of the task on each core is predicted by combining the performance characteristics and the performance requirements of the task, and the target core most suitable for the task is selected based on load perception, so that the energy efficiency ratio of the core is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a task scheduling method, device, equipment, chip and storage medium. Background Art

[0002] At present, the core strategies of Android / Linux kernel to solve the energy efficiency scheduling of heterogeneous multi-core architecture are based on utilization (util) (Energy Aware Scheduler, EAS) scheduling and Completely Fair Scheduler (Completely Fair Scheduler, CFS) scheduling, which calculate the computing power requirements of tasks and cores at runtime, predict the core frequency corresponding to the requirements of each cluster, and finally place tasks based on energy optimization. However, the energy efficiency scheduling and frequency adjustment strategies based on util do not take into account the performance differences of tasks between CPU clusters.

[0003] like Figure 1 As shown in the figure, the CPI speedup ratio (CPI_big / CPI_small) of the same benchmark in the two clusters varies greatly, for example, the difference is as high as 5 times for susuan; and due to the existence of load memory access and IO characteristics, the performance and frequency of different loads on the same core are not completely linearly mapped. Figure 2 As shown, the normalized performance (Normalized_Performance) and frequency (Frequency) of the memory access type benchmark show an obvious nonlinear relationship, which conforms to the formula 1 / time = freq / (x1*Freq*Stall_Time+x2*Base_cycles), where Stall_Time represents the stagnation time affected by memory access, Base_cycles represents the number of basic cycles that must be consumed by the instruction execution central processing unit (CPU), and x1 and x2 are determined by the instruction characteristic value of the load and the core architecture. Therefore, the scheduling strategy of the CFS+EAS solution currently used in mobile devices ignores the influence of the instruction characteristic value of the load, cannot make an accurate judgment on the CPU affinity of the task, and cannot accurately select the best energy-efficient core. Summary of the invention

[0004] The embodiments of the present application are intended to provide a task scheduling method, apparatus, device, chip and storage medium.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, a task scheduling method is provided, comprising:

[0007] Obtaining a first performance characteristic and a first performance requirement of one or more cores;

[0008] Obtaining a second performance characteristic and a second performance requirement of the task to be scheduled when running on the first core, where the task to be scheduled includes one or more tasks;

[0009] Determine, based on the first performance characteristic and the first performance requirement of the one or more cores and the second performance characteristic and the second performance requirement of the task to be scheduled, a predicted performance indicator when the task to be scheduled runs on the one or more cores;

[0010] Based on the predicted performance indicators of the task to be scheduled when it runs on one or more cores, a target core for running the task to be scheduled is determined.

[0011] In a second aspect, a task scheduling device is provided, comprising:

[0012] An acquisition unit, configured to acquire a first performance characteristic and a first performance requirement of one or more cores;

[0013] The acquisition unit is further used to acquire a second performance characteristic and a second performance requirement of the task to be scheduled when the task to be scheduled runs on the first core, wherein the task to be scheduled includes one or more tasks;

[0014] A prediction unit, configured to determine, based on the first performance characteristics and the first performance requirement of the one or more cores and the second performance requirement of the task to be scheduled, a predicted performance indicator of the one or more cores when the task to be scheduled runs on the one or more cores;

[0015] The determination unit is used to determine a target core for the task to be scheduled based on the predicted performance indicators of one or more cores.

[0016] According to a third aspect, an electronic device is provided, comprising: a processor and a memory configured to store a computer program that can be run on the processor,

[0017] Wherein, when the processor is configured to run a computer program, the steps of the aforementioned method are executed.

[0018] In a fourth aspect, a chip is provided, comprising: a processor configured to call and run a computer program from a memory to execute the steps of the aforementioned method.

[0019] In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program implements the steps of the aforementioned method when executed by a processor.

[0020] In an embodiment of the present application, a task scheduling method, device, equipment, chip and storage medium are provided, the method comprising: determining the predicted performance index of the task to be scheduled when it runs on one or more cores according to the first performance characteristics and first performance requirements of one or more cores, and the second performance characteristics and second performance requirements of the task to be scheduled; determining the target core for running the task to be scheduled based on the predicted performance index of the task to be scheduled when it runs on one or more cores. In this way, the characteristics of the workload of each core are characterized by the performance characteristics and performance requirements of each core, the performance of the task on each core is predicted in combination with the performance characteristics and performance requirements of the task, and the target core that best suits the task is selected based on load perception, thereby improving the energy efficiency ratio of the core. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of CPI speedup ratio when different benchmarks are executed on large cores and small core clusters;

[0022] Figure 2 A schematic diagram of the nonlinear relationship between performance and frequency for different loads on the same core;

[0023] Figure 3 This is a schematic diagram of the first process of the task scheduling method in an embodiment of the present application;

[0024] Figure 4 Schematic diagram of the frequency prediction method in the embodiment of the present application;

[0025] Figure 5 Schematic diagram of the performance indicator prediction method in the embodiment of the present application;

[0026] Figure 6 A second flow chart of the task scheduling method in an embodiment of the present application;

[0027] Figure 7 This is a schematic diagram of the overall framework of the task scheduling method implemented in the embodiment of the present application;

[0028] Figure 8 A third flow chart of the task scheduling method according to an embodiment of the present application;

[0029] Fig. 9 This is a schematic diagram showing the frame loss rate performance of four application programs in the embodiment of the present application when running;

[0030] Fig.10 A schematic diagram showing the energy consumption of four application programs in the embodiment of the present application when they are running;

[0031] Fig.11 This is a schematic diagram of the composition structure of the task scheduling device in the embodiment of the present application;

[0032] Fig.12 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0033] Fig.13 Schematic diagram of the chip structure in the embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0035] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are applicable to the following interpretations:

[0036] The average number of cycles per instruction (Cycle Per Instruction, CPI) indicates the number of clock cycles required for the CPU to execute each instruction. It is an important indicator to measure the performance of a computer processor. The lower the CPI value, the more efficient the CPU is in executing instructions, that is, the CPU can execute more instructions in the same clock cycle. CPI is closely related to computer performance. When the main frequency (CPU clock frequency) is the same, the lower the CPI, the faster the CPU operates, because the CPU can complete more instructions in fewer clock cycles. On the contrary, the higher the CPI, the slower the CPU operates.

[0037] The CPI composition can be expressed as:

[0038] CPI = Base_CPI + Stall_SPI×cpufreq (1)

[0039] Among them, Stall_SPI indicates the time that each CPU instruction is stalled due to memory access, while Base_CPI indicates the number of cycles (cpu_cycle) that the CPU must spend to execute each instruction under a specific load, and cpufreq indicates the CPU frequency, specifically the CPU's main frequency, indicating the number of cycles that the CPU can complete per second. It is worth noting that Base_CPI depends entirely on the instruction characteristics and CPU microarchitecture characteristics, and does not change with the CPU frequency.

[0040] The average number of instructions executed per second (IPS) indicates the number of instructions that a processor can execute per second. It reflects the processor's computing speed within a certain period of time and is one of the key indicators for evaluating processor performance. The higher the IPS value, the faster the processor's computing speed per unit time and the better the performance.

[0041] Since the relationship between IPS and CPI is: IPS = cpufreq / CPI, IPS is defined as:

[0042] IPS = cpufreq / ( base_CPI + stall_SPI×cpufreq) (2)

[0043] Performance per Watt (PPW), PPW is the ratio of core performance to power consumption, which is used to measure the performance that the core can provide when consuming a unit of energy. The higher the value, the better the performance that the hardware can provide at the same power consumption, and the higher the efficiency. Performance can be measured by various benchmarks or performance indicators in actual applications, such as the average number of instructions executed per second IPS. Power consumption can be obtained by measuring the actual power consumption of the hardware during operation.

[0044] The present application provides a task scheduling method, which specifically includes a load sensing method and a load sensing frequency modulation method. The method characterizes the characteristics of the workload of each core through the performance characteristics and performance requirements of each core, combines the performance characteristics and performance requirements of the task, predicts the performance of the task on each core, and selects the target core that best suits the task based on load sensing, thereby improving the energy efficiency ratio of the core.

[0045] Figure 3 FIG. 1 is a first flow chart of the task scheduling method in the embodiment of the present application. Figure 3 As shown, the method may specifically include:

[0046] Step 301: Obtain a first performance characteristic and a first performance requirement of one or more cores;

[0047] The first performance characteristic is used to characterize the load characteristics and micro-architecture characteristics of each core, and the first performance characteristic specifically characterizes the instruction-level performance characteristics of each core.

[0048] For example, the first performance characteristic may include an instruction characteristic value of the load and a memory access characteristic value of the load. For another example, the first performance characteristic may also include an average number of cycles (CPI) spent on each instruction executed by each core.

[0049] The instruction characteristic value of a load is the number of cycles spent on the core side for each instruction executed by a specific load. The instruction characteristic value of a load is not affected by memory access. The smaller the instruction characteristic value of a load, the higher the execution efficiency of the core, and vice versa. The instruction characteristic value of a load can be called the basic CPI (Basic Cycle Per Instruction, base_CPI).

[0050] The memory access characteristic value of the load is the stall time (Stall Second PerInstruction, stall_SPI) of each instruction affected by memory access. The smaller the memory access characteristic value of the load, the shorter the stall time of the instruction affected by memory access, and the higher the execution efficiency of the core. Otherwise, the execution efficiency is lower.

[0051] The first performance requirement is used to characterize the load requirements of each core. The first performance requirement specifically characterizes how many instructions need to be executed in the load. For example, it can be represented by how many instructions need to be executed per second on average in the load. The first performance requirement is expressed as the core's IPS demand value (CPU_demand_IPS), which monitors how many instructions need to be executed per second on average in the previous cycle. CPU_demand_IPS = X / period, where period is the duration of the previous cycle and X is the number of instructions that need to be executed in the previous cycle. The larger the IPS demand value, the higher the core's computing speed requirement, and vice versa.

[0052] In some embodiments, operating information of one or more cores is obtained; and based on the operating information of the one or more cores, a first performance characteristic and a first performance requirement of the one or more cores are determined.

[0053] The core operation information is one or more event statistics related to the core collected by the performance detection unit during the operation of the core, which is used to characterize the actual performance and operation status of the core.

[0054] In some embodiments, the core operation information includes at least one of the following: LLC data cache refill times (LLCC Cache Refill), L2 data cache refill times (L2d Cache Refill), L2 data Tlb cache refill times (L2d Tlb Refill), number of instruction retirements (inst_retired), number of instruction cycles (cycles), number of instructions (instructions), frequency (f), voltage (V) and temperature (T), etc.

[0055] Exemplarily, the memory access characteristic value of the load is determined based on the number of LLC data cache refills, the number of L2 data cache refills, the number of L2 data Tlb cache refills, and the number of instruction retirements of the core. In some embodiments, the first function is called based on the number of LLC data cache refills, the number of L2 data cache refills, the number of L2 data Tlb cache refills, and the number of instruction retirements of the core to calculate the memory access characteristic value of the load. For example, the first function can be expressed as: stall_SPI = a1*LLCC_Cache_Refill / inst_retired+a2*L2d_Cache_Refil / inst_retired+a3*L2d_Tlb_Refill / inst_retire d, where a1, a2, and a3 are fitting coefficients obtained by offline fitting.

[0056] Exemplarily, the instruction characteristic value of the load is determined based on the memory access characteristic value of the load, the frequency of the core, and the running speed of each instruction. In some embodiments, the second function is called to calculate the instruction characteristic value of the load based on the memory access characteristic value of the load, the frequency of the core, and the running speed of each instruction. For example, the second function can be expressed as: Base-CPI=(SPI i -Stall-SPI)*cpufreq i .

[0057] It should be noted that the memory access characteristic value of the load and / or the instruction characteristic value of the load can also be directly obtained by monitoring the CPU pipeline.

[0058] Step 302: Obtain a second performance characteristic and a second performance requirement of the task to be scheduled when it runs on the first core, where the task to be scheduled includes one or more tasks;

[0059] The second performance characteristic is used to characterize the load characteristic of the task to be scheduled, and the second performance characteristic specifically characterizes the instruction-level load characteristic of the task to be scheduled. For example, the second performance characteristic includes the average number of cycles CPI per instruction spent when the task to be scheduled runs on the first core.

[0060] The second performance requirement is used to characterize the load demand of the task to be scheduled. The second performance requirement specifically characterizes how many instructions need to be executed in the task, which can be expressed by how many instructions need to be executed per second on average. The second performance requirement is expressed as the IPS demand value of the task (Task_demand_IPS), which monitors how many instructions need to be executed per second on average in the previous cycle (or the most recent running cycle). Task_demand_IPS = Y / period, where period is the duration of the previous cycle, and Y is the number of instructions that need to be executed in the task in the previous cycle. The larger the IPS demand value of the task, the higher the demand for the core's computing speed, and vice versa.

[0061] In some embodiments, the running information of the task to be scheduled when it runs on the first core is obtained; based on the running information of the task to be scheduled when it runs on the first core, the second performance characteristic and the second performance requirement of the task to be scheduled are determined.

[0062] The running information of the task to be scheduled is one or more event statistics related to the task collected by the performance detection unit when the task runs on the first core, which is used to characterize the actual performance and running status of the task when it runs on the first core. The first core may include one or more cores on which the task runs at a historical moment, for example, the first core includes the core on which the task runs at a recent historical moment.

[0063] The running information of the task to be scheduled includes at least one of the following: the number of L2 data cache refills, the number of L1 data Tlb cache refills (L1d Tlb Refill), the number of instruction retirements, the number of instruction cycles, the number of instructions, frequency, voltage and temperature.

[0064] The performance detection unit may be a performance monitoring unit (PMU) or an activity monitoring unit (AMU).

[0065] It should be noted that the load characteristics and / or load requirements of the task can also be directly obtained by monitoring the CPU pipeline.

[0066] Step 303: Determine a predicted performance indicator of the task to be scheduled when it runs on the one or more cores based on the first performance characteristics and the first performance requirement of the one or more cores and the second performance characteristics and the second performance requirement of the task to be scheduled;

[0067] The embodiments of the present application characterize the characteristics of the workload of each core through the performance characteristics and performance requirements of each core, predict the performance of the task on each core in combination with the performance characteristics and performance requirements of the task, and select the target core that best suits the task based on load perception, thereby improving the energy efficiency ratio of the core.

[0068] In some embodiments, the method may include: determining the predicted frequency of the task to be scheduled when it runs on the second core based on the first performance characteristics and the first performance requirement of the second core to be predicted, and the second performance requirement of the task to be scheduled, where the second core is any core of one or more cores; determining the predicted performance indicator of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core, the second performance characteristics and the second performance requirement of the task to be scheduled.

[0069] In some embodiments, the first core and the second core are cores of different architecture types, which may also be referred to as heterogeneous cores. For example, the first core is a large core and the second core is a small core, the first core is a large core and the second core is a super large core, or the first core is a small core and the second core is a super large core.

[0070] In some embodiments, Figure 4 As shown, the frequency prediction method may specifically include:

[0071] Step 401: determining a predicted performance requirement of the second core when the task to be scheduled runs on the second core based on the first performance requirement of the second core and the second performance requirement of the task to be scheduled;

[0072] In some embodiments, the first performance requirement includes how many instructions need to be executed per second on the second core in the previous cycle, and the second performance requirement includes how many instructions need to be executed per second on the task to be scheduled in the previous cycle (most recent running cycle). The predicted performance requirement may include how many instructions need to be executed per second on the task after the task is placed on the second core. The predicted performance requirement may be expressed as demand_IPS.

[0073] Exemplarily, the Task_demand_IPS of the task to be scheduled and the CPU_demand_IPS of each core in the previous sampling period are obtained, and the Task_demand_IPS of the task to be scheduled is added to the CPU_demand_IPS of each core to obtain the IPS demand value (demand_IPS) of each core when the task to be scheduled runs on each core.

[0074] Step 402: Determine a predicted frequency of the second core when the task to be scheduled runs on the second core based on the predicted performance requirement of the second core and the first performance characteristic of the second core;

[0075] Exemplarily, the first performance characteristic includes the instruction characteristic value of the load, the memory access characteristic value and frequency of the load, and combined with the predicted IPS demand value of each core, the predicted frequency of the core that needs to be set to meet the predicted IPS demand value of each core is calculated. The predicted frequency can be understood as the operating frequency of the second core in the next cycle.

[0076] In a heterogeneous multi-core system, a cluster refers to a processing unit formed by combining multiple cores. This combination can improve the computer's parallel processing capabilities, thereby speeding up program execution. In a cluster, each core communicates and collaborates through a high-speed bus or shared cache.

[0077] One or more cores belong to one or more clusters, for example, homogeneous cores belong to the same cluster, heterogeneous cores belong to different clusters, more specifically, multiple small cores belong to one cluster, multiple large cores belong to one cluster, and multiple super large cores belong to one cluster. Accordingly, the method further includes: taking the maximum predicted frequency of the cores included in the first cluster as the final predicted frequency of the second core, and the second core belongs to the first cluster. That is, the frequency of each core of the cluster is the maximum value of the frequencies of all cores.

[0078] In some embodiments, Figure 5 As shown, the prediction performance index takes the prediction of running time as an example, and the performance index prediction method may specifically include:

[0079] Step 501: Determine a predicted CPI of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core and the second performance characteristic of the task to be scheduled;

[0080] Exemplarily, the method also includes: based on a multivariate linear regression algorithm, pre-building one or more CPI prediction models, the CPI prediction model is used to predict performance characteristics between heterogeneous cores; based on the first core and the second core, determining a target CPI prediction model, the target CPI prediction model is used to determine the predicted CPI of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core and the second performance characteristic of the task to be scheduled.

[0081] The second performance characteristic includes the average number of cycles per instruction (CPI) spent by the scheduled task when it runs on the first core and the frequency of the first core. In other words, the CPI prediction model is used to determine the predicted CPI of the task when it runs on the second core based on the frequency and CPI of the task in the historical running core, as well as the predicted frequency of the second core, and other information, so as to perceive the load characteristics of the task on different cores, thereby improving the energy efficiency ratio of the core.

[0082] Exemplarily, the CPI of a task to be scheduled refers to the average number of cycles CPI spent by each instruction of the task during its operation. The CPI of a task is related to the load and core type of the task to be scheduled. The CPI values ​​of the same task running on cores of different architecture types are significantly different. The embodiment of the present application uses a CPI prediction model to perform cross-core CPI prediction based on the CPI characteristics of the task when it runs on the first core (historical running core), the frequency of the first core, and the predicted frequency of the second core, and determines the CPI characteristics when the task runs on other heterogeneous cores, that is, predicting the performance of the task on other heterogeneous cores through the performance of the task on the historical running core, and using the variability of the load as the basis for core selection, thereby improving the energy efficiency ratio of the core.

[0083] Step 502: determining a predicted running speed of the task to be scheduled when it runs on the second core based on the predicted CPI of the task to be scheduled when it runs on the second core and the predicted frequency of the second core;

[0084] Exemplarily, the running speed may be the average number of instructions per second (IPS) executed when the task to be scheduled runs on the second core. The quotient of the predicted frequency of the second core and the predicted CPI of the second core is calculated to obtain the predicted IPS of the second core.

[0085] Step 503: Based on the running speed of the second core and the second performance requirement of the task to be scheduled, determine the predicted running time of the task to be scheduled when running on the second core.

[0086] Exemplarily, the running speed of the second core is the predicted IPS, the second performance requirement includes how many instructions need to be executed per second for the scheduled task on average, and the quotient of the average number of instructions need to be executed per second for the scheduled task and the predicted IPS is calculated to obtain the predicted running time of the second core.

[0087] Step 304: Determine a target core for running the task to be scheduled based on the predicted performance index when the task to be scheduled is run on one or more cores.

[0088] In some embodiments, the method specifically includes: determining one or more alternative cores that meet performance constraints based on predicted performance indicators of the task to be scheduled when it runs on one or more cores; determining energy efficiency characteristics of the task to be scheduled when it runs on one or more alternative cores based on operating information of the one or more alternative cores; and determining the alternative core with the best energy efficiency characteristics as the target core based on the energy efficiency characteristics of the task to be scheduled when it runs on one or more alternative cores.

[0089] In some embodiments, based on the predicted performance index of the task to be scheduled when running on one or more cores, an alternative core that does not meet the performance constraint condition is determined; and the first core is determined as the target core.

[0090] In some embodiments, when the predicted performance indicator includes predicted running time, the performance constraint condition includes that the predicted running time is less than or equal to a preset running time corresponding to the task to be scheduled.

[0091] In some embodiments, when the predicted performance indicator includes a predicted running speed, the performance constraint condition includes that the predicted running speed is greater than or equal to a preset running speed corresponding to the task to be scheduled.

[0092] Energy efficiency characteristics include, but are not limited to, performance per watt (PPW). PPW is a ratio of core performance to power consumption, and is used to measure the performance that a core can provide when consuming a unit of energy.

[0093] In some embodiments, a method for determining the energy efficiency characteristics of an alternative core may include: the operating information of each alternative core is input into a power consumption model to obtain the power consumption characteristics of each alternative core, the power consumption characteristics including static power consumption characteristics; based on the power consumption characteristics and predicted operating speed of each alternative core, the energy efficiency characteristics of the alternative core are determined.

[0094] The mainstream EAS mechanism does not take into account the composition of static power consumption. However, experiments have shown that the static power consumption characteristics are an important part of the overall core power consumption and temperature changes will also have a certain impact on static power consumption. The embodiment of the present application takes into account the static power consumption characteristics when predicting power consumption to improve the prediction accuracy, thereby improving the prediction accuracy of energy efficiency characteristics and the core selection accuracy.

[0095] In some embodiments, the operating information of the alternative core includes: the frequency, voltage and temperature of the alternative core; the power consumption model is configured as: based on the temperature and voltage of the alternative core, calculating the static power consumption characteristics of the alternative core; based on the frequency, voltage and static power consumption characteristics of the alternative core, calculating the power consumption characteristics of the alternative core.

[0096] In some embodiments, the frequency of the target core is adjusted to the predicted frequency of the target core. That is, after determining the target core, the frequency adjustment operation is performed according to the predicted frequency of the target core so that the target core meets the performance requirements of the task. The predicted frequency of the target core is determined based on the first performance characteristic and the first performance requirement of the target core and the second performance requirement of the task to be scheduled. The specific determination method refers to the determination method of the predicted frequency of the second core, which will not be repeated here.

[0097] By adopting the above technical solution, the characteristics of the workload of each core are characterized by the performance characteristics and performance requirements of each core. The performance of the task on each core is predicted based on the performance characteristics and performance requirements of the task. The target core that best suits the task is selected based on load perception, thereby improving the energy efficiency ratio of the core.

[0098] In order to better reflect the purpose of this application, further examples are given based on the above embodiments of this application. Figure 6 As shown, the method specifically includes:

[0099] Step 601: Obtaining the operation information of one or more cores and the operation information of the tasks to be scheduled;

[0100] In some embodiments, the operating information of the core includes at least one of the following: the core's LLC data cache refill times (LLCC Cache Refill), L2 data cache refill times (L2d Cache Refill), L2 data Tlb cache refill times (L2d Tlb Refill), the number of instruction retirements (inst_retired), the number of instruction cycles (cycles), the number of instructions (instructions), frequency (f), voltage (V) and temperature (T), etc.

[0101] In some embodiments, the running information of the task to be scheduled includes at least one of the following: LLC data cache refill times (LLCC Cache Refill), L2 data cache refill times (L2d Cache Refill), L2 data Tlb cache refill times (L2d Tlb Refill), number of instruction retirements (inst_retired), number of instruction cycles (cycles), number of instructions (instructions), frequency (f), voltage (V) and temperature (T), etc.

[0102] Step 602: Determine a first performance characteristic and a first performance requirement of one or more cores based on the operation information of the one or more cores;

[0103] Step 603: determining a second performance characteristic and a second performance requirement of the task to be scheduled based on the running information of the task to be scheduled, where the task to be scheduled includes one or more tasks;

[0104] Step 604: Determine a predicted frequency of the task to be scheduled when it runs on the second core based on the first performance characteristic and the first performance requirement of the second core to be predicted and the second performance requirement of the task to be scheduled;

[0105] Step 605: Determine a predicted performance index of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core, the second performance characteristic and the second performance requirement of the task to be scheduled;

[0106] Step 606: Determine one or more candidate cores that meet the performance constraint based on the predicted performance index of the task to be scheduled when running on one or more cores;

[0107] Step 607: Based on the operation information of the one or more candidate cores, predict the energy efficiency characteristics of the task to be scheduled when it runs on the one or more candidate cores;

[0108] Step 608: Based on the energy efficiency characteristics of the task to be scheduled when running on one or more candidate cores, determine the candidate core with the best energy efficiency characteristics as the target core;

[0109] Step 609: Adjust the frequency of the target core to the predicted frequency of the target core to run the task to be scheduled.

[0110] The EAS and CFS scheduling strategies based on util cannot reflect the performance differences of tasks when they are executed on cores of different architectures, and cannot make accurate judgments on the performance limits of tasks. For example, some tasks with deadlines (such as UI Thread, RenderThread, etc.) cannot accurately select the best core. However, the CPI prediction model constructed by this application can perceive the performance differences of tasks on heterogeneous cores when selecting cores, and use the power consumption model that considers static power consumption characteristics to calculate energy efficiency more accurately; based on the performance characteristic values ​​at the instruction level (such as CPI, IPS, base_CPI, PPW, etc.), it can perceive the characteristic changes of different workloads, make more accurate core selection interventions, improve the energy efficiency ratio of the core, and perform more accurate frequency modulation operations.

[0111] Figure 7 FIG. 1 is a schematic diagram of the overall framework of the method for implementing task scheduling in an embodiment of the present application. Figure 7As shown in the figure, firstly, the data collection modules such as AMU / PMU are used to collect data within the statistical period, and the running information of each task (per_task) and each core (per_core) are collected. The running information of each core is input into the IPS-Freq mapping model to predict the performance demand demand_IPS (CPU_demand_IPS+Task_demand_IPS) of each core, as well as the instruction characteristic value base_CPI and the memory access characteristic value stall_SPI of the load of each core. The IPS-Freq mapping module is used to further predict the performance demand demand_IPS (CPU_demand_IPS+Task_demand_IPS) of each core. Each core then predicts the frequency Predict_cpufreqj that meets the demand_IPS requirement. The running information of each task is input into the cross-cluster CPI prediction model to predict the predicted CPI of the task on the heterogeneous core. The cross-cluster prediction module further determines the performance index (such as execution time exec_time) level of the task when it is running on other cores (not the current core) based on the predicted frequency and predicted CPI, and selects the core that meets the performance constraints (such as time constraints) as the candidate core; finally, the power consumption model is used to calculate the energy efficiency PPW of each candidate core, and the core with the best energy efficiency is selected from the candidate cores according to the candidate core PPW to place the task. While ensuring the core performance, the best energy efficiency core is allocated to the task.

[0112] Figure 8 This is a third flow chart of the task scheduling method of the embodiment of the present application. The task scheduling method for each monitoring cycle is as follows:

[0113] Step 801: data collection;

[0114] The data acquisition module (PMU / AMU) collects the running information of the tasks during the period (period_time) and the running information of each core of the CPU during the running period. The data acquisition module provides input for the IPS-freq mapping module, the cross-cluster prediction module, and the energy efficiency calculation module.

[0115] Step 802: IPS-freq mapping module;

[0116] The IPS-freq mapping module obtains the operation information of each core collected by the data collection module. The core operation information includes: LLCC Cache Refill, L2d Cache Refill, L2d Tlb Refill, number of instruction retirements, number of instruction cycles, number of instructions, frequency, voltage, temperature, etc.

[0117] In a specific implementation example, the memory access characteristic value stall_SPI of the load in formula (2) is fitted by the first function, that is, formula (3):

[0118] stall_SPI =∑parai×PMUi_PI (3)

[0119] Among them, PMUi_PI represents the characteristics of each instruction of the core, PMUi_PI=PMU / inst_retired, PMU represents some event statistics of the CPU pipeline (such as LLCC Cache Refill, L2d Cache Refill and L2d TlbRefill), inst_retired represents the number of retired instructions, and parai represents the fitting coefficient obtained by linear regression.

[0120] The data acquisition module can obtain the IPS and frequency of the current core in real time when the CPU is running. Therefore, when the fitted Stall_SPI is known, the second function, that is, formula (4), can be used to calculate the instruction characteristic value base_CPI of the load of each core. Then, the IPS performance at different frequency points freq can be predicted.

[0121] Base-CPI=(SPI i -Stall-SPI)*freq i (4)

[0122] Among them, SPI i Indicates the running time of each instruction of core i, freq i Indicates the frequency of core i.

[0123] When making decisions, the data acquisition module obtains the Task_demand_IPS (instruction / period_time, task instruction demand per cycle) of the current task to be scheduled, the CPU_demand_IPS (instruction / period_time, CPU instruction demand per cycle) of each CPU in the previous cycle, and the PMU / AMU event data of the performance monitoring unit. At the same time, the stall_SPI characteristics and base_CPI characteristics of each CPU are calculated through Formula 3 and Formula 4; after accumulating the Task_demand_IPS of the current task to be scheduled and adding it to the CPU_demand_IPS of each core, through Formula 5 and Formula 6, we can calculate the CPU frequency that can be set when the IPS demand value of each core is met, and finally take the maximum frequency in the cluster as the output; the final output of this module is: the possible CPU frequency of each cluster after assuming that the task is placed on each core.

[0124]

[0125] Step 803: cross-cluster prediction module;

[0126] The cross-cluster prediction module obtains the running information of each task collected by the data collection module. The running information of the task includes: LLCC Cache Refill, L2d Cache Refill, L1d Tlb Refill, number of instruction retirements, number of instruction cycles, and number of instructions.

[0127] In order to allocate resources in a heterogeneous multi-core system to meet the performance requirements of application-related tasks, it is necessary to understand how applications are executed on cores of different architecture types. Methods based on historical data have problems such as poor timeliness and low accuracy. Here, the solution estimates the performance of applications on different types of cores by running data on only one core type.

[0128] Here, the solution is based on the multivariate linear regression algorithm to build cross-cluster CPI prediction models between large cores and small cores, large cores and super-large cores, and small cores and super-large cores offline. The model uses the Pearson coefficient to find the most relevant events between the PMU events collected by the current cluster and the predicted cluster CPI. Then, based on the regression principle of maximizing R square, all PMUs are traversed, and the PMU combination with the best fitting degree is found according to the greedy algorithm. The fitting target formula is as follows:

[0129]

[0130] Among them, CoreType1 represents the core on which the task is currently running (or most recently running), that is, the first core in the embodiment of the present application, and CPI CoreType2 Indicates the CPI characteristics of the task in the current running core. CoreType2 indicates other architecture cores for which CPI performance prediction is required, i.e., the second core in the embodiment of the present application. CoreType1 Indicates the CPI characteristics of the task in other architecture cores. In other words, through the CPI characteristics of the task in the current running core, PMU information, the ratio of the running frequencies of two heterogeneous cores, and other information, the CPI characteristics of the task in other architecture cores are predicted, the load characteristics of the task in different cores are perceived, and more accurate core selection intervention is made.

[0131] When making decisions, the data acquisition module obtains the PMU information of the task that needs to be scheduled, as well as the CPI, frequency and PMU information of the task that needs to be scheduled in the previous cycle. The CPI prediction model can be used to calculate the CPI characteristics of the current task in other architecture cores, and then the IPS-Freq mapping module is used to determine the predicted frequency that meets the performance requirements. Formula 8 can be used to determine the running speed (such as IPS) of the target task in the target core.

[0132] IPS CoreTypei =CPUfreq CoreTypei / CPI CoreTypei(8)

[0133] In the embodiment of the present application, the execution time is used as the prediction performance indicator, and the execution time of the task on each core can be estimated by the following formula 9, where IPS CoreTypei Calculated by Formula 8, Task_demand_IPS represents the number of demand instructions when the task was executed in the last cycle;

[0134] exec_time CoreTypei =Task_demand_IPS / IPS CoreTypei (9)

[0135] The currently scheduled task should meet the performance constraint (performance_limitation):

[0136] exec_time CoreTypei ≤performance_limitation (10)

[0137] For example, the time constraint, in a specific example, the UI Thread and the Render Thread should be executed within one vsync cycle (16.66ms or 8.33ms). The performance constraint here can also be a custom input or a direct performance constraint on the target core's operating speed IPS.

[0138] The scheme uses the cores that meet the performance constraints (Formula 10) as candidate cores for task scheduling.

[0139] It should be noted that load perception in the embodiment of the present application mainly refers to sensing the calculation or memory access characteristic values ​​of the load, and calculating the load characteristics base_CPI and stall_SPI through the core's operating information. The values ​​of these two parameters are closely related to the load type and can characterize the memory access and computing intensity of the load; in addition, in the cross-cluster prediction module, through the PMU-based CPI cross-cluster prediction model, the performance of the load on other types of cores is sensed through the PMU characteristics of the load on a certain core, thereby realizing load perception between heterogeneous cores.

[0140] Step 804: Energy efficiency calculation module;

[0141] The embodiment of the present application also constructs a power consumption model taking into account static power consumption offline, and the fitting formula 11 of the power consumption model is as follows:

[0142] Power=C×V 2 ×f+Static(T,V) (11)

[0143] The fitting formula 12 of the static power consumption model is as follows:

[0144] Static(T,V)=para1×T×V+para2×T 2 ×V+para3 (12)

[0145] Among them, C, para1, para2 and para3 are obtained by offline linear fitting, T is temperature, V is voltage, and f is frequency.

[0146] When making decisions, the power consumption model calculates the power consumption information of each core online based on the operating information of each core in the previous cycle transmitted by the data acquisition module, including frequency, voltage, temperature and other information, and calculates the energy efficiency characteristics (such as PPW) after placing the task on each candidate core.

[0147] PPW CoreTypei =IPS CoreTypei / Power CoreTypei (13)

[0148] Step 805: Select the best core.

[0149] After calculating the core with the best energy efficiency, the task is placed on the corresponding core.

[0150] Furthermore, the operating frequency of the next cycle may be set according to the predicted frequency of the best core obtained by the IPS-freq mapping module.

[0151] In summary, the embodiments of the present application obtain and predict the performance characteristic values ​​of instruction granularity (such as CPI, IPS, base_CPI, PPW, etc.) through a model, and perform core selection intervention on tasks in a fine-grained periodic manner to guide the tasks to select the best energy-efficient core that meets the performance constraints; since the performance characteristic values ​​of the instruction level of each task are counted, the method can perceive the characteristic changes of different workloads. Compared with the default Linux core selection method, more accurate core selection intervention can be made to improve the energy efficiency ratio of the core.

[0152] The embodiment of the present application constructs a cross-cluster prediction model on Xiaolong 8gen2. The specific example shown in Table 1 below is the fitting result of the cross-cluster prediction model of ARM Cortex-A715 architecture predicting ARM Cortex-X3:

[0153] Table 1

[0154]

[0155] The model R2 exceeds 0.994, indicating that the model's regression analysis explains more than 99.4% of CPI changes. The prediction errors of different benchmarks are as follows: Figure 8As shown, the average prediction error on the validation set is 8.6%, and the F-statistic and the p-value corresponding to the fitting parameters are much smaller than the predetermined significance level (0.05), indicating that the model has high reliability and validity.

[0156] This application example tests four applications, application 1-4 are shopping application, news application, social application and video application. The energy consumption and frame loss rate performance of the method provided by this application example are compared with those under the Android default strategy. In terms of performance, Fig. 9 As shown in Figure 2, the frame loss optimization of the four applications is 24%, 49%, 21%, and 32% respectively compared with the default strategy. Fig.10 As shown, the CPU energy consumption is reduced by 3.6%, 1.6%, 0%, and 1.8% respectively.

[0157] In summary, (1) the embodiments of the present application introduce performance and power consumption and prediction models to calculate the impact of executing each task on different heterogeneous cores on performance and power consumption, expose the variability of CPU workload (performance, power consumption) to the operating system, and dynamically map tasks to the heterogeneous processor core that best suits their execution characteristics to maximize overall task performance and energy efficiency.

[0158] (2) The embodiment of the present application uses a unified demand_IPS as the performance requirement and counts the performance characteristic values ​​of each task instruction level. Compared with the original util-based EAS mechanism and CFS scheduler, it can perceive the characteristic changes of the load in a fine-grained manner, thereby making more accurate core selection intervention and providing accurate CPU frequency modulation;

[0159] (3) The embodiments of the present application are simple and universal. The IPS-Freq mapping model, cross-cluster CPI prediction model, and power consumption model built based on PMU / AMU in the method all use as few and reusable performance counters as possible. The model is simple and effective and can be directly deployed in mobile devices with a limited number of PMUs. As long as the chip supports the required performance counters, the method provided by the embodiments of the present application can theoretically be used.

[0160] To implement the method of the embodiment of the present application, based on the same inventive concept, the embodiment of the present application also provides a task scheduling device, such as Fig.11 As shown, the task scheduling device 110 includes:

[0161] An acquisition unit 1101 is configured to acquire a first performance characteristic and a first performance requirement of one or more cores;

[0162] The acquisition unit 1101 is further used to acquire a second performance characteristic and a second performance requirement of the task to be scheduled when the task to be scheduled runs on the first core, where the task to be scheduled includes one or more tasks;

[0163] A prediction unit 1102, configured to determine predicted performance indicators of the one or more cores when the task to be scheduled runs on the one or more cores based on the first performance characteristics and the first performance requirement of the one or more cores and the second performance requirement of the task to be scheduled;

[0164] The determination unit 1103 is used to determine the target core of the task to be scheduled based on the predicted performance indicators of one or more cores.

[0165] In some embodiments, the prediction unit 1102 is specifically used to determine the predicted frequency of the task to be scheduled when it runs on the second core based on the first performance characteristics and the first performance requirement of the second core to be predicted, and the second performance requirement of the task to be scheduled, where the second core is any core of one or more cores; based on the predicted frequency of the second core, the second performance characteristics and the second performance requirement of the task to be scheduled, determine the predicted performance indicator of the task to be scheduled when it runs on the second core.

[0166] In some embodiments, the prediction unit 1102 is specifically used to determine the predicted performance requirement of the second core when the task to be scheduled runs on the second core based on the first performance requirement of the second core and the second performance requirement of the task to be scheduled; and to determine the predicted frequency of the second core when the task to be scheduled runs on the second core based on the predicted performance requirement of the second core and the first performance characteristic of the second core.

[0167] In some embodiments, one or more cores belong to one or more clusters, each cluster contains homogeneous cores, and the prediction unit 1102 is further configured to use the maximum predicted frequency of the cores contained in the first cluster as the final predicted frequency of the second core, which belongs to the first cluster.

[0168] In some embodiments, the predicted performance metric includes predicted run time;

[0169] In some embodiments, the prediction unit 1102 is specifically used to determine the predicted CPI of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core and the second performance characteristics of the task to be scheduled; determine the predicted running speed of the task to be scheduled when it runs on the second core based on the predicted CPI of the task to be scheduled when it runs on the second core and the predicted frequency of the second core; determine the predicted running time of the task to be scheduled when it runs on the second core based on the running speed of the second core and the second performance requirement of the task to be scheduled.

[0170] In some embodiments, the prediction unit 1102 is specifically used to pre-build one or more CPI prediction models based on a multivariate linear regression algorithm, and the CPI prediction model is used to predict performance characteristics between heterogeneous cores; based on the first core and the second core, a target CPI prediction model is determined, and the target CPI prediction model is used to determine the predicted CPI of the task to be scheduled when it runs on the second core based on the predicted frequency of the second core and the second performance characteristic of the task to be scheduled.

[0171] In some embodiments, the second performance characteristic includes the average number of cycles CPI per instruction taken by the scheduled task when it runs on the first core and the frequency of the first core; the second performance requirement includes the average number of instructions actually executed per second by the scheduled task.

[0172] In some embodiments, the determination unit 1103 is specifically used to determine one or more alternative cores that meet the performance constraint conditions based on the predicted performance indicators of the task to be scheduled when it runs on one or more cores; determine the energy efficiency characteristics of the task to be scheduled when it runs on one or more alternative cores based on the operating information of the one or more alternative cores; and determine the alternative core with the best energy efficiency characteristics as the target core based on the energy efficiency characteristics of the task to be scheduled when it runs on one or more alternative cores.

[0173] In some embodiments, when the predicted performance indicator includes predicted running time, the performance constraint condition includes that the predicted running time is less than or equal to a preset running time corresponding to the task to be scheduled.

[0174] In some embodiments, the determination unit 1103 is specifically used to input the operating information of each candidate core into the power consumption model to obtain the power consumption characteristics of each candidate core, the power consumption characteristics including static power consumption characteristics; based on the power consumption characteristics and predicted operating speed of each candidate core, the energy efficiency characteristics of the candidate core are determined.

[0175] In some embodiments, the operating information of the candidate core includes: the frequency, voltage, and temperature of the candidate core;

[0176] The power consumption model is configured as follows: based on the temperature and voltage of the candidate core, the static power consumption characteristics of the candidate core are calculated; based on the frequency, voltage and static power consumption characteristics of the candidate core, the power consumption characteristics of the candidate core are calculated.

[0177] In some embodiments, the determination unit 1103 is further configured to adjust the frequency of the target core to the predicted frequency of the target core to run the task to be scheduled.

[0178] In some embodiments, the first performance characteristic includes the instruction characteristic value of the load and the memory access characteristic value of the load. The instruction characteristic value of the load is the number of cycles spent on the core side for each instruction executed by the specific load. The instruction characteristic value of the load is not affected by memory access. The memory access characteristic value of the load is the stall time of each instruction affected by memory access. The first performance requirement includes the average number of instructions actually executed by the core per second.

[0179] In some embodiments, the operation information of the core includes at least one of the following: the number of LLC data cache refills, the number of L2 data cache refills, the number of L2 data Tlb cache refills, the number of instruction retirements, the number of instruction cycles, the number of instructions, the frequency, the voltage, and the temperature of the core;

[0180] The instruction characteristic value of the load is determined based on the LLC data cache refill times, the L2 data cache refill times, the L2 data Tlb cache refill times and the number of instruction retirements of the core. In some embodiments, the first function is called to calculate the memory access characteristic value of the load based on the LLC data cache refill times, the L2 data cache refill times, the L2 data Tlb cache refill times and the number of instruction retirements of the core;

[0181] The memory access characteristic value of the load is determined based on the memory access characteristic value of the load, the frequency of the core, and the running speed of each instruction.

[0182] It should be noted that the memory access characteristic value of the load and / or the instruction characteristic value of the load can also be directly obtained by monitoring the CPU pipeline.

[0183] In practical applications, the above device can be an electronic device for implementing the task scheduling method, or a chip applied to an electronic device. In the present application, the device can implement the functions of multiple units by software, hardware, or a combination of software and hardware, so that the device can execute the task scheduling method provided in any of the above embodiments. The technical effects of each technical solution of the device can refer to the technical effects of the corresponding technical solution in the task scheduling method, and the present application will not repeat them one by one.

[0184] Based on the hardware implementation of each unit in the above task scheduling device, the embodiment of the present application also provides an electronic device, such as Fig.12 As shown, the electronic device 120 includes: a processor 1201 and a memory 1202 configured to store a computer program that can be run on the processor;

[0185] The processor 1201 is configured to execute the method steps in the aforementioned embodiment when running a computer program.

[0186] Of course, in practical applications, Fig.12As shown, the various components in the electronic device 120 are coupled together through a bus system 1203. It can be understood that the bus system 1203 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1203 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, various buses are marked as bus system 1203 in the figure.

[0187] In practical applications, the processor may be at least one of an application-specific integrated circuit (ASIC), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a controller, a microcontroller, and a microprocessor. It is understandable that for different devices, the electronic device used to implement the functions of the processor may also be other, and the embodiments of the present application do not specifically limit this.

[0188] The above-mentioned memory can be a volatile memory (volatile memory), such as a random access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD); or a combination of the above-mentioned types of memory, and provide instructions and data to the processor.

[0189] The electronic devices described in this application may include, for example, mobile phones, tablet computers, laptop computers, PDAs, portable media players (PMPs), navigation devices, wearable devices, etc.

[0190] The embodiment of the present application also provides a chip, Fig.13 It is a schematic structural diagram of the chip of an embodiment of the present application. Fig.13 The chip 1300 shown includes a processor 1310, which can call and run a computer program from a memory to implement the method in the embodiment of the present application.

[0191] Alternatively, if Fig.13 As shown, the chip 1300 may further include a memory 1320. The processor 1310 may call and run a computer program from the memory 1320 to implement the method in the embodiment of the present application.

[0192] The memory 1320 may be a separate device independent of the processor 1310 , or may be integrated into the processor 1310 .

[0193] Optionally, the chip 1300 may further include an input interface 1330. The processor 1310 may control the input interface 1330 to communicate with other devices or chips, and specifically, may obtain information or data sent by other devices or chips.

[0194] Optionally, the chip 1300 may further include an output interface 1340. The processor 1310 may control the output interface 1340 to communicate with other devices or chips, and specifically, may output information or data to other devices or chips.

[0195] Optionally, the chip can be applied to the electronic device in the embodiments of the present application, and the chip can implement the corresponding processes implemented by the electronic device in each method of the embodiments of the present application, which will not be described in detail here for the sake of brevity.

[0196] In an exemplary embodiment, the embodiment of the present application further provides a computer-readable storage medium, such as a memory including a computer program, and the computer program can be executed by a processor of an electronic device to complete the steps of the aforementioned method.

[0197] An embodiment of the present application further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any one of the methods described in the embodiments of the present application are implemented.

[0198] Optionally, the computer program product can be applied to the electronic device in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the electronic device in the various methods of the embodiments of the present application. For the sake of brevity, they are not repeated here.

[0199] The embodiment of the present application also provides a computer program.

[0200] Optionally, the computer program can be applied to the electronic device in the embodiments of the present application. When the computer program runs on a computer, the computer executes the corresponding processes implemented by the electronic device in the various methods of the embodiments of the present application. For the sake of brevity, they are not described here.

[0201] It should be understood that in the embodiments of the present application, related data such as user information is involved. When the embodiments of the present application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0202] It should be understood that the terms used in the present application are only for the purpose of describing specific embodiments, but are not intended to limit the present application. The singular forms of "a", "said" and "the" used in the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items. The expressions "having", "may have", "include" and "include", or "may include" and "may include" in this application can be used to indicate the presence of corresponding features (e.g., elements such as numerical values, functions, operations or components), but the presence of additional features is not excluded.

[0203] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other and are not necessarily used to describe a specific order or sequence. For example, without departing from the scope of the present invention, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0204] The technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0205] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and equipment can be implemented in other ways. The embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0206] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0207] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0208] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A task scheduling method, characterized in that: The method comprises: Obtaining a first performance characteristic and a first performance requirement of one or more cores; Obtaining a second performance characteristic and a second performance requirement of a task to be scheduled when the task to be scheduled runs on the first core, wherein the task to be scheduled includes one or more tasks; Determine, based on the first performance characteristic and the first performance requirement of the one or more cores, and the second performance characteristic and the second performance requirement of the task to be scheduled, a predicted performance indicator when the task to be scheduled runs on the one or more cores; Based on the predicted performance index of the task to be scheduled when it is run on the one or more cores, a target core for running the task to be scheduled is determined.

2. The method according to claim 1, characterized in that The determining, based on the first performance characteristic and the first performance requirement of the one or more cores, and the second performance characteristic and the second performance requirement of the task to be scheduled, a predicted performance indicator when the task to be scheduled runs on the one or more cores, includes: Determine, based on a first performance characteristic and a first performance requirement of a second core to be predicted and a second performance requirement of the task to be scheduled, a predicted frequency when the task to be scheduled runs on the second core, where the second core is any core of the one or more cores; Based on the predicted frequency of the second core, the second performance characteristic of the task to be scheduled, and the second performance requirement, a predicted performance indicator of the task to be scheduled when running on the second core is determined.

3. The method according to claim 2, characterized in that The step of determining the predicted frequency of the task to be scheduled when running on the second core based on the first performance characteristic and the first performance requirement of the second core to be predicted and the second performance requirement of the task to be scheduled includes: Determine, based on the first performance requirement of the second core and the second performance requirement of the task to be scheduled, a predicted performance requirement of the second core when the task to be scheduled runs on the second core; Based on the predicted performance requirement of the second core and the first performance characteristic of the second core, a predicted frequency of the second core when the task to be scheduled runs on the second core is determined.

4. The method according to claim 3, characterized in that The one or more cores belong to one or more clusters, each cluster containing homogeneous cores, and the method further comprises: The maximum predicted frequency of the cores included in the first cluster is used as the final predicted frequency of the second core, and the second core belongs to the first cluster.

5. The method according to claim 2, characterized in that: The prediction performance indicators include prediction run time; The step of determining, based on the predicted frequency of the second core, the second performance characteristic of the task to be scheduled, and the second performance requirement, a predicted performance indicator when the task to be scheduled runs on the second core includes: Determine, based on the predicted frequency of the second core and the second performance characteristic of the task to be scheduled, a predicted average number of cycles per instruction CPI when the task to be scheduled runs on the second core; Determining a predicted running speed of the task to be scheduled when it runs on the second core based on a predicted CPI when the task to be scheduled runs on the second core and a predicted frequency of the second core; Based on the running speed of the second core and the second performance requirement of the task to be scheduled, a predicted running time of the task to be scheduled when running on the second core is determined.

6. The method according to claim 5, characterized in that The method further comprises: Based on a multivariate linear regression algorithm, one or more CPI prediction models are pre-built, and the CPI prediction models are used to predict performance characteristics between heterogeneous cores; Based on the first core and the second core, a target CPI prediction model is determined, and the target CPI prediction model is used to determine the predicted average number of cycles CPI per instruction taken when the task to be scheduled runs on the second core based on the predicted frequency of the second core and the second performance characteristics of the task to be scheduled.

7. The method according to any one of claims 1 to 6, characterized in that: The second performance characteristic includes an average number of cycles CPI per instruction taken when the task to be scheduled runs on the first core and a frequency of the first core; The second performance requirement includes how many instructions the to-be-scheduled task needs to execute per second on average.

8. The method according to claim 1, characterized in that The determining, based on the predicted performance index of the task to be scheduled when it is run on the one or more cores, a target core for running the task to be scheduled includes: Determine one or more candidate cores that meet performance constraints based on the predicted performance indicators of the task to be scheduled when it runs on the one or more cores; Based on the operation information of the one or more candidate cores, determining the energy efficiency characteristics of the task to be scheduled when running on the one or more candidate cores; Based on the energy efficiency characteristics of the task to be scheduled when running on the one or more candidate cores, determine the candidate core with the best energy efficiency characteristics as the target core.

9. The method according to claim 8, characterized in that When the predicted performance indicator includes the predicted running time, the performance constraint condition includes that the predicted running time is less than or equal to the preset running time corresponding to the task to be scheduled.

10. The method according to claim 8, characterized in that The determining, based on the operation information of the one or more candidate cores, the energy efficiency characteristics of the to-be-scheduled task when it runs on the one or more candidate cores includes: The operation information of each candidate core is input into the power consumption model to obtain the power consumption characteristics of each candidate core, wherein the power consumption characteristics include static power consumption characteristics; Based on the power consumption characteristics and predicted operating speeds of the candidate cores, energy efficiency characteristics of the candidate cores are determined.

11. The method according to claim 10, characterized in that The operation information of the candidate core includes: the frequency, voltage and temperature of the candidate core; The power consumption model is configured as follows: Calculating a static power consumption characteristic of the candidate core based on the temperature and voltage of the candidate core; The power consumption characteristics of the candidate core are calculated based on the frequency, voltage and static power consumption characteristics of the candidate core.

12. The method according to claim 8, characterized in that The method further comprises: The frequency of the target core is adjusted to the predicted frequency of the target core to run the task to be scheduled.

13. The method according to claim 1, characterized in that The first performance characteristic comprises an instruction characteristic value of the load and a memory access characteristic value of the load, wherein the instruction characteristic value of the load is the number of cycles spent on the core side by each instruction executed by a specific load, the instruction characteristic value of the load is not affected by memory access, and the memory access characteristic value of the load is the stall time of each instruction affected by memory access; The first performance requirement includes how many instructions need to be executed per second on average.

14. A task scheduling device, characterized in that: The device comprises: An acquisition unit, configured to acquire a first performance characteristic and a first performance requirement of one or more cores; The acquisition unit is further used to acquire a second performance characteristic and a second performance requirement of the task to be scheduled when the task to be scheduled runs on the first core, wherein the task to be scheduled includes one or more tasks; a prediction unit, configured to determine, based on the first performance characteristics and the first performance requirement of the one or more cores and the second performance requirement of the task to be scheduled, a predicted performance indicator of the one or more cores when the task to be scheduled runs on the one or more cores; A determination unit is used to determine a target core for the task to be scheduled based on the predicted performance indicators of the one or more cores.

15. An electronic device, characterized in that: The electronic device comprises: a processor and a memory configured to store a computer program capable of running on the processor, Wherein, the processor is configured to execute the steps of the method according to any one of claims 1 to 13 when running the computer program.

16. A chip, comprising: A processor configured to call and run a computer program from a memory to perform the steps of the method according to any one of claims 1 to 13.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 13 are implemented.

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