Electronic device

Abstract

The invention provides an electronic device including a panel. The panel of the electronic device includes a substrate on which a plurality of signal lines and a test circuit are disposed. The test circuit includes a first switching element and a second switching element electrically connected to the same switching signal line. The test circuit further comprises a first conductive connection part and a second conductive connection part, the first conductive connection part is electrically connected between the first switch element and one signal line, and the second conductive connection part is electrically connected between the second switch element and the other signal line. And at least partially overlaps one of the switching elements.

Description

Technical Field

[0001] The present invention relates to an electronic device, in particular to an electronic device comprising a panel. Background Art

[0002] Display panels are widely used in a variety of consumer electronic products, such as computer monitors, mobile phones, televisions, etc. In order to improve the yield of display panels and ensure the quality of shipment, a test circuit is usually set in the non-display area of ​​the panel, such as the peripheral area, to perform array testing on the display panel and detect the electrical characteristics of the pixel array. However, the peripheral area of ​​the current high pixel density (pixel per inch, PPI) products with narrow bezel design often cannot provide enough layout area to set up a complete test circuit, and cannot detect all the pixels in the display area, resulting in a decrease in yield. Therefore, the art still needs a novel test circuit design to meet the needs of narrow bezel products. Summary of the invention

[0003] The main purpose of the present invention is to provide an electronic device including a panel.

[0004] The present invention provides an electronic device including a panel, wherein the panel includes a substrate, a plurality of signal lines and a test circuit are arranged on the substrate. The test circuit includes a first switch element and a second switch element, which are electrically connected to the same switch signal line. The test circuit also includes a first conductive connection portion and a second conductive connection portion, wherein the first conductive connection portion is electrically connected between the first switch element and one of the signal lines, and the second conductive connection portion is electrically connected between the second switch element and another of the signal lines, and at least partially overlaps one of the switch elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a plan view of a panel of an electronic device according to an embodiment of the present invention, showing the layout of a test circuit unit.

[0006] Figure 2 Schematic diagrams of some cross-sections of a panel of an electronic device according to an embodiment of the present invention.

[0007] Figure 3 FIG. 4 is an equivalent circuit diagram of a test circuit unit according to an embodiment of the present invention.

[0008] Figure 4 FIG. 1 is a partial plan view of a panel of an electronic device according to an embodiment of the present invention.

[0009] Figure 5 FIG. 4 is a schematic diagram of a circuit block configuration of a first gate driving circuit according to an embodiment of the present invention.

[0010] Figure 6 FIG. 4 is a schematic diagram of a circuit block configuration of a second gate driving circuit according to an embodiment of the present invention.

[0011] Figure 7 FIG. 4 is a plan view of a panel of an electronic device according to an embodiment of the present invention.

[0012] Figure 8 FIG. 4 is a plan view of a panel of an electronic device according to an embodiment of the present invention.

[0013] Fig. 9 FIG. 4 is a plan view of a panel of an electronic device according to an embodiment of the present invention.

[0014] Fig.10 FIG. 4 is a plan view of a panel of an electronic device according to an embodiment of the present invention.

[0015] Explanation of reference numerals: 10-panel; 30-circuit layer; 100-substrate; 102-test circuit; 104-static protection circuit; 112-first conductive connection; 114-second conductive connection; 122-third conductive connection; 124-fourth conductive connection; 302-shift register circuit block; 304-output circuit block; 306-charge release circuit block; 308-buffer circuit block; 100a-cutting edge; 102a-test circuit unit; AA-display area; AA'-cut line; ACT1-semiconductor layer; ACT2-semiconductor layer; ACT3-semiconductor layer; BB'-cut line; BDL-common source line; BF-insulating layer; CT-control element; CT1-first control element; CT2-second control element; CT3-third control element; D1-drain; D2-drain; D3-drain; DL-data signal line; GE-gate; GI-gate insulating layer; GL-scan signal line; GOP-1-first gate drive circuit; GOP-2-second gate drive circuit; ILD-insulating layer; ITO-conductive layer; ITO1-conductive layer; ITO2-conductive layer; L1-length; L2-length; M0-conductive layer; M1-conductive layer; M2-conductive layer; M3-conductive layer; M4-conductive layer; PLN-insulating layer; PR-peripheral region; PV1-insulating layer; PV2-insulating layer; PV3-insulating layer; S1-source; S2-source S3-source; SB-switching signal line; SML-semiconductor layer; ST-switching element; ST1-first switching element; ST2-second switching element; ST3-third switching element; SW-control signal line; V1-contact portion; V2-contact portion; V2-1-contact portion; V3-contact portion; V4-contact portion; W1-width; W2-width; Wa-width; Wb-width; X-direction; Y-direction; Z-direction; M-direction; N-direction. DETAILED DESCRIPTION

[0016] The present invention may be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the reader's understanding and the simplicity of the drawings, the various drawings in the present invention only depict a portion of the panel, and certain elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are for illustration only and are not intended to limit the scope of the present invention.

[0017] Certain words are used throughout the specification and claims of the present invention to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. The present invention is not intended to distinguish between components that have the same function but different names. In the specification and claims of the present invention, the words "including", "comprising" and "having" are open-ended words and should therefore be interpreted as "including but not limited to...".

[0018] It should be understood that when an element or film layer is referred to as being "on another element or film layer" or "connected to another element or film layer", it may be directly on another element or film layer, or directly connected to another element or film layer, or there may be other elements or film layers between the two without direct contact or connection. Conversely, when an element is referred to as being "directly on another element or film layer", or "directly connected to another element or film layer", there are no intervening elements or film layers between the two.

[0019] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the present invention to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is turned over, the element described as being "below" or "below" the other elements will be oriented as being "above" the other elements. Therefore, the exemplary terms "above" or "below" can include both above and below orientations.

[0020] It should be understood that when a component or a film layer is referred to as being "connected" to another component or a film layer, it can be directly connected to the other component or film layer, or there can be an intervening component or film layer between the two. When a component is referred to as being "directly connected" to another component or a film layer, there can be no intervening component or film layer between the two. In addition, when a component is referred to as being "coupled to another component (or a variation thereof)" or "electrically connected to another component (or a variation thereof)", it can be directly connected to the other component, indirectly connected (e.g., electrically connected) to the other component through one or more components.

[0021] Although terms such as "first", "second", "third", etc. may be used to describe or name different components, these components are not limited to these terms. These terms are only used to distinguish one component from other components in the specification and have nothing to do with the order in which these components are manufactured. The same terms may not be used in the claims, and may be replaced by "first", "second", "third", etc. according to the order in which the elements are declared in the claims. Accordingly, in the following description, the first component may be the second component in the claims.

[0022] In the present invention, the terms "about", "approximately", "substantially", and "roughly" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific descriptions of "about", "approximately", "substantially", and "roughly", the meanings of "about", "approximately", "substantially", and "roughly" can still be implied.

[0023] The electronic device of the present invention may include a display device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. Among them, the display device may include a common display device form, or a splicing display device, a bendable or flexible display device and other special display devices, but is not limited thereto. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may have peripheral systems, such as but not limited to a drive system, a control system, a light source system, etc., to support a display device, an antenna device, a wearable device (such as including augmented reality or virtual reality), a vehicle-mounted device (such as including a car windshield) or a splicing device. The following description will take a panel-type device as an electronic device to illustrate the content of the present invention, but the present invention is not limited thereto.

[0024] The panel of the electronic device of the present invention may be a display panel for manufacturing a display device. The electronic device may, for example, include liquid crystal, light emitting diode, fluorescence, phosphor, other suitable display media, or a combination of the foregoing. For example, the electronic device may be a non-self-luminous liquid crystal display (LCD) or a self-luminous organic light emitting diode display (OLED Display), an inorganic light emitting diode display (LED Display), a sub-millimeter inorganic light emitting diode display (Mini-LED Display), a micro-inorganic light emitting diode (Micro-LED Display), a quantum dot diode display (QLED Display), or an electrophoretic display (EPD) and other displays that can present images and pictures, but are not limited thereto.

[0025] In the present invention, the "flat edge" of the cutting edge of the display area or substrate is defined as the edge parallel to the extension direction of the data signal line or scanning signal line of the display area, and the "bevel edge" is defined as any edge that is not parallel to the "flat edge".

[0026] It should be noted that the following embodiments may replace, reorganize, or mix features of several different embodiments to implement other embodiments without departing from the spirit of the present invention.

[0027] Please refer to Figure 4 . Figure 4 FIG. 1 is a partial plan view of a panel 10 according to an embodiment of the present invention. The surface of the panel 10 is along a plane defined by the X direction and the Y direction in the figure, wherein the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to the surface of the panel 10. The M direction and the N direction are parallel to the surface of the panel 10 and are different from the X direction and the Y direction. In some embodiments, the M direction and the N direction are perpendicular to each other.

[0028] like Figure 4As shown, the panel 10 includes a display area AA and a peripheral area PR disposed adjacent to at least one side of the display area AA. The display area AA includes a pixel array for displaying a picture or pattern. A plurality of signal lines extend through the display area AA along the X direction and the Y direction and are electrically connected to each pixel unit to control the operation of each pixel unit. To simplify the illustration, Figure 4 Only data signal lines DL and scanning signal lines GL are schematically shown, wherein the data signal lines DL extend along the Y direction and are arranged in parallel along the X direction, and the scanning signal lines GL extend along the X direction and are arranged in parallel along the Y direction. The area between adjacent data signal lines DL and adjacent scanning signal lines GL is a pixel unit.

[0029] The peripheral area PR includes peripheral circuits or electronic components for controlling the screen display of the display area AA or for detecting the yield of the display area AA, such as gate drive circuits, chip bonding circuits, fan-out circuits, demultiplexers, backplane lines, FPC bonding circuits, test circuits, reset circuits, compensation control circuits, initialization circuits, power lines, ground potential lines, clock signal lines, capacitors, inductors, or combinations thereof, but not limited thereto. Among them, the gate drive circuit (called Gate on Array, GOA or Gate on Panel, GOP) is used to generate gate drive signals for pixels of the display area AA. The chip bonding circuit is used for bonding the driver chip (IC). The fan-out circuit is used to realize the wiring connection between the driver chip and the data line of the display area AA. The demultiplexer is used to split the output terminal drawn from the driver chip to realize the driving of multiple data lines. The backplane line is used for connecting the wiring around the panel. The FPC bonding circuit is used to bond the FPC soft board to connect the circuit board. The test circuit is connected to the display area AA through a connecting line to provide a test control signal to detect the electrical characteristics of the pixel array.

[0030] To simplify the diagram, Figure 4 Only part of the gate driving circuit (e.g., the first gate driving circuit GOP-1 and the second gate driving circuit GOP-2) and the test circuit 102 are schematically illustrated. Specifically, the test circuit 102 is disposed along the flat edge of the data signal line DL of the display area AA to facilitate electrical connection with each data signal line DL. In some embodiments, the test circuit 102 may be composed of a plurality of test circuit units 102a (see Figure 1 and Figure 3 ) to shorten the wiring length and improve space utilization. The gate driver circuit (e.g., the first gate driver circuit GOP-1) is arranged along the flat edge of the scanning signal line GL of the display area AA to facilitate electrical connection with each scanning signal line GL. In some embodiments, if the display area AA includes a bevel (e.g. Figure 4When the data signal line DL and the scanning signal line GL are led out from the oblique side of the display area AA, the test circuit 102 and the gate driving circuit can be arranged along the oblique side of the display area AA, and the test circuit 102 can be arranged between the display area AA and the gate driving circuit. It should be understood that in other embodiments, the driving circuit (such as the second gate driving circuit GOP-2) can be arranged between the display area AA and the test circuit 102 according to design requirements.

[0031] Please refer to Figure 3 , is an equivalent circuit diagram of a test circuit unit 102a according to an embodiment of the present invention. The test circuit 102 includes a switch element ST, a control element CT, a switch signal line SB that controls the switch element ST to be turned on or off, a control signal line SW that controls the control element CT to be turned on or off, and a common source line BDL, wherein each data signal line DL is connected to the common source line BDL via a switch element ST and a control element CT. When performing a test, the switch signal line SB and the selected control signal line SW are at a high level, turning on the switch element ST and the selected control element CT to input the test signal provided by the common source line BDL to the selected data signal line DL. After the test is completed, the switch signal line SB is at a low level, turning off the switch element ST to cut off the electrical connection between the test circuit unit 102a and the data signal line DL, so as to reduce the probability that the test circuit unit 102a generates interference noise that affects the display area AA. It should be understood that Figure 3 The switch elements, signal lines, and the number of connected data signal lines DL of the test circuit unit 102a are only examples, and the present invention is not limited thereto. The actual design can be adjusted according to the requirements. The switch elements and control elements of the present invention can be transistors or thin film transistors, for example, but are not limited thereto.

[0032] Please refer to Figure 1 , Figure 1 FIG. 1 is a regional plan view of a panel 10, showing the layout of a test circuit unit 102a according to an embodiment of the present invention, which includes a plurality of switch elements ST, a plurality of control elements CT, a switch signal line SB, a plurality of control signal lines SW, a common source line BDL, a plurality of data signal lines DL, a plurality of conductive connecting portions, a local interconnection structure, and an interlayer contact to achieve electrical connection between circuit components, such as Figure 3Circuit shown. The aforementioned circuit components are composed of at least one patterned semiconductor layer SML and a plurality of patterned conductive layers M0, M1, M2, M3, and ITO2 of the circuit layer 30 of the panel 10. In some embodiments, the semiconductor layers of the switch element ST and the control element CT (e.g., semiconductor layer ACT1, semiconductor layer ACT2, and semiconductor layer ACT3) are composed of the semiconductor layer SML, the gate GE is composed of the conductive layer M1, the common source line BDL and the data signal line DL are composed of the conductive layer M2, and the switch signal line SB and the control signal line SW are composed of the conductive layer M1. The detailed stacked structure of the circuit layer 30 can be referred to Figure 2 The semiconductor layer SML and the conductive layers M0, M1, M2, M3 and ITO2 are respectively located at different heights on the substrate 100, that is, the minimum distances from the substrate 100 are different from each other.

[0033] like Figure 1 As shown, the test circuit unit 102a is divided into a left half and a right half with the common source line BDL as the central axis. The switch element ST, the control element CT, the control signal line SW, and the data signal line DL are divided into two groups, which are arranged on the left and right sides of the common source line BDL in a mirror-symmetrical manner. The switch signal line SB bypasses the common source line BDL from the outside of the left half to the outside of the right half, and has a roughly U-shaped shape. The test circuit unit 102a has a symmetrical structure as a whole.

[0034] In detail, the left half of the test circuit unit 102a includes a first switch element ST1, a second switch element ST2, and a third switch element ST3, which are aligned along the Y direction. The first control element CT1, the second control element CT2, and the third control element CT3 are also aligned along the Y direction, and are respectively located between the first switch element ST1, the second switch element ST2, and the third switch element ST3 and the common source line BDL in the X direction. This embodiment only illustrates three switch elements and three control elements, and in other embodiments, the number of switch elements and control elements can be increased or decreased according to actual needs.

[0035] The first switch element ST1, the second switch element ST2, the third switch element ST3, the first control element CT1, the second control element CT2 and the third control element CT3 are, for example, top gate thin film transistors, wherein the first switch element ST1 and the first control element CT1 are formed on the same semiconductor layer ACT1. The gate GE of the first switch element ST1, i.e., the portion where the switch signal line SB overlaps the semiconductor layer ACT1. The drain D1 of the first switch element ST1 is electrically connected to one of the data signal lines DL through the first conductive connection portion 112. The source S1 of the first control element CT1 is electrically connected to the common source line BDL. The gate GE of the first control element CT1 is electrically connected to one of the control signal lines SW. According to some embodiments of the present invention, the first conductive connection portion 112 is formed of a conductive layer ITO2, which crosses over the second switch element ST2 and at least partially overlaps the second switch element ST2. The gate GE, the switch signal line SB and the control signal line SW are formed of a conductive layer M1. The drain D1 of the first switching element ST1 and the source S1 of the first control element CT1 are formed of the conductive layer M2 .

[0036] Similarly, the second switch element ST2 and the second control element CT2 share the same semiconductor layer ACT2. The gate GE of the second switch element ST2, that is, the portion of the switch signal line SB overlapping the semiconductor layer ACT2. The drain D2 of the second switch element ST2 is electrically connected to another of the data signal lines DL through the second conductive connection portion 114. The source S2 of the second control element CT2 is electrically connected to the common source line BDL. The gate GE of the second control element CT2 is electrically connected to another of the control signal lines SW through the fourth conductive connection portion 124. According to some embodiments of the present invention, the second conductive connection portion 114 and the fourth conductive connection portion 124 are both formed by a conductive layer M3, wherein the second conductive connection portion 114 crosses over the third switch element ST3 and at least partially overlaps the third switch element ST3, and the fourth conductive connection portion 124 crosses over the first control element CT1 and at least partially overlaps the first control element CT1. The drain D2 of the second switch element ST2 and the source S2 of the second control element CT2 are formed by a conductive layer M2.

[0037] The third switch element ST3 and the third control element CT3 share the same semiconductor layer ACT3. The gate GE of the third switch element ST3, i.e., the portion of the switch signal line SB overlapping the semiconductor layer ACT3. The drain D3 of the third switch element ST3 is electrically connected to another data signal line DL. The source S3 of the third control element CT3 is electrically connected to the common source line BDL. The gate GE of the third control element CT3 is electrically connected to another control signal line SW through the third conductive connection portion 122. According to some embodiments of the present invention, the third conductive connection portion 122 is formed by a conductive layer M0, which passes under the second control element CT2 and at least partially overlaps with the second control element CT2. The drain D3 of the third switch element ST3 and the source S3 of the third control element CT3 are formed by a conductive layer M2.

[0038] In some embodiments, the electrical connection between different conductive layers in the vertical direction (Z direction) can be achieved through interlayer contacts. Figure 1 As shown, the conductive layer M1 and the conductive layer M0 can be electrically connected through the contact portion V1, the conductive layer M2 and the conductive layer M1 can be electrically connected through the contact portion V2, the conductive layer M2 and the semiconductor layer SML can be electrically connected through the contact portion V2-1, the conductive layer M3 and the conductive layer M2 can be electrically connected through the contact portion V3, and the conductive layer ITO2 and the conductive layer M3 can be electrically connected through the contact portion V4.

[0039] In some embodiments, the test circuit unit 102a further includes a local interconnection structure to realize the layer-hopping electrical connection of the conductive connection portion. Figure 1 As shown, two ends of the first conductive connection portion 112 are electrically connected to the drain electrode D1 of the first switch element ST1 and the data signal line DL through the regional interconnection structure composed of the conductive layer M3 and the contact portion V3. Two ends of the fourth conductive connection portion 124 are smoothly electrically connected to the gate electrode GE of the second control element CT2 and the control signal line SW through the regional interconnection structure composed of the conductive layer M2 and the contact portion V2. The interconnection structure can be set in any conductive layer according to the layout design requirements.

[0040] It should be understood that the right side portion of the test circuit unit 102a is mirror-symmetrical to the left side portion, so the layout design of the right side portion can refer to the description of the left side portion, which will not be repeated here.

[0041] Please refer to Figure 2 , which shows some cross-sectional schematic diagrams of the panel 10, wherein the left part is along Figure 1The tangent line AA' shown cuts through the cross section of the third switch element ST3 and the third control element CT3, and the middle part is along Figure 1 The tangent line BB' shown cuts through the cross section of the first switch element ST1 and the first control element CT1. The right part is a cross-sectional schematic diagram of other parts, illustrating other conductive layers and the connection structure between the conductive layers (such as the contact part) to help understand Figure 1 The layout design of the test circuit unit 102a is shown.

[0042] like Figure 2 As shown, the panel 10 includes a substrate 100 and a circuit layer 30 disposed on the substrate 100. The substrate 100 may include a hard substrate or a flexible substrate, and the material of the substrate 100 may include glass, ceramic, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethyleneterephthalate (PET), or a combination of the foregoing materials, but is not limited thereto. The circuit layer 30 includes a stacked structure, for example, from bottom to top, it may include a conductive layer M0, an insulating layer BF, a semiconductor layer SML, a gate insulating layer GI, a conductive layer M1, an insulating layer ILD, a conductive layer M2, an insulating layer PV1, a conductive layer M3, an insulating layer PV3, a conductive layer ITO1, an insulating layer PLN, a conductive layer ITO2, and an insulating layer PV2. In other embodiments, the circuit layer 30 may include other suitable stacked structures. In some embodiments, other conductive layers, such as a conductive layer M4 and a conductive layer ITO, may be disposed on the circuit layer 30 for wiring or electrically connecting electronic components (such as light-emitting components) on the circuit layer 30 .

[0043] The circuit layer 30 also includes interlayer contacts that pass through the insulating layer to electrically connect different conductive layers in the vertical direction (Z direction), such as a contact portion V1 that passes through the gate insulating layer GI and the insulating layer BF to electrically connect the conductive layer M1 and the conductive layer M0, a contact portion V2 that passes through the insulating layer ILD to electrically connect the conductive layer M2 and the conductive layer M1, a contact portion V2-1 that passes through the insulating layer ILD and the gate insulating layer GI to electrically connect the conductive layer M2 and the semiconductor layer SML, a contact portion V3 that passes through the insulating layer PV1 to electrically connect the conductive layer M3 and the conductive layer M2, and a contact portion V4 that passes through the insulating layer PLN and the insulating layer PV3 to electrically connect the conductive layer ITO2 and the conductive layer M3. Figure 2 The designs of the conductive layer and the contact portion shown are merely examples, and the present invention is not limited thereto. The actual design may be adjusted according to requirements.

[0044] The insulating layer BF, the gate insulating layer GI, the insulating layer ILD, the insulating layer PV1, the insulating layer PV3, the insulating layer PLN and the insulating layer PV2 may be single-layer or multi-layer structures, respectively, and the materials may include inorganic dielectric materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or organic dielectric materials such as acrylic resin or other suitable materials, or a combination of the foregoing, but not limited thereto.

[0045] The semiconductor layer SML may include amorphous silicon, low temperature polycrystalline silicon (LTPS), low temperature polycrystalline oxide (LTPO), or a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc oxide (IGTZO), but is not limited thereto.

[0046] Conductive layer M0, conductive layer M1, conductive layer M2, conductive layer M3, conductive layer M4, conductive layer ITO1, conductive layer ITO2 and conductive layer ITO may respectively include metal conductive materials, transparent conductive materials or other suitable types of conductive materials, wherein the applicable metal conductive materials may include metals such as aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), titanium (Ti), molybdenum (Mo), nickel (Ni), molybdenum (Mc) or other suitable metal materials, or a combination of the above materials, or an alloy of the above metal materials, but not limited thereto. Applicable transparent conductive materials may include, for example, indium tin oxide (ITO), indium zinc oxide (IGZO) or aluminum zinc oxide (AZO), but not limited thereto.

[0047] In summary, the test circuit (or test circuit unit) proposed by the present invention utilizes different layers of conductive layers to jumper the wiring of the test circuit, which can improve the layout density. The present invention can set a test circuit that is sufficient to match the pixel array of the display area in a limited area to achieve the purpose of full testing.

[0048] In some embodiments of the present invention, for example Figure 4 The bevel area of ​​the display area AA shown in the figure can selectively adjust the configuration of the circuit block of the second gate drive circuit GOP-2 at the bevel to shorten the length L2 of the second gate drive circuit GOP-2, so that even when the test circuit 102 and the second gate drive circuit GOP-2 are provided at the same time, the width Wb of the surrounding area PR at the bevel can be substantially equal to the width Wa of the side area, thereby achieving the purpose of making the border width more consistent.

[0049] For example, see Figure 5 and Figure 6 , are schematic diagrams of circuit block configurations of the first gate drive circuit GOP-1 and the second gate drive circuit GOP-2 according to an embodiment of the present invention, wherein the first gate drive circuit GOP-1 is arranged along the Y direction at the side of the display area AA (the side where the scanning signal line GL is led out), and the second gate drive circuit GOP-2 is arranged along the M direction at the oblique side of the display area AA, wherein the oblique side is substantially parallel to the M direction. The first gate drive circuit GOP-1 and the second gate drive circuit GOP-2 respectively include a plurality of circuit blocks, such as but not limited to a shift register circuit block 302, an output circuit block 304, a charge release circuit block 306, and a buffer circuit block 308. Among them, as Figure 5 As shown, the shift register circuit block 302, the output circuit block 304, the charge release circuit block 306 and the buffer circuit block 308 of the first gate driving circuit GOP-1 are arranged in sequence along the X direction, so that the overall layout area of ​​the first gate driving circuit GOP-1 has a length L1 and a width W1. Figure 6 As shown, the output circuit block 304 and the charge release circuit block 306 of the second gate drive circuit GOP-2 are arranged between the shift register circuit block 302 and the buffer circuit block 308, and the output circuit block 304 and the charge release circuit block 306 are arranged along the M direction, and the shift register circuit block 302 and the buffer circuit block 308 are arranged along the N direction, so that the overall layout area of ​​the second gate drive circuit GOP-2 roughly has a length L2 and a width W2, wherein the length L2 is less than the length L1, and the width W2 is greater than the width W1.

[0050] In still other embodiments of the present invention, the test circuit 102 may be disposed in the cut-out area of ​​the substrate 100, and after the test is completed, the test circuit 102 is cut out together with the cut-out area of ​​the substrate 100. In this way, the test circuit 102 will not occupy the space of the peripheral area PR of the product, which helps to reduce the width of the peripheral area PR of the product and meet the narrow frame design specification.

[0051] For example, see Figures 7 to 10 , which shows some implementations of the test circuit 102 being disposed in the cut-away area of ​​the substrate 100. In the figure, the cut-away area is the area divided by the cutting edge 100a and does not include the display area AA. Figure 7 As shown, when the cutting edge 100a has a flat edge and a beveled edge along the shape of the display area AA, the test circuit 102 can be continuously arranged along the flat edge and the beveled edge of the cutting edge 100a, and the data signal line DL led out from the beveled edge of the display area AA can be bent and arranged in parallel along the extending direction of the beveled edge to smoothly electrically connect with the test circuit 102. Figure 8As shown, the test circuit 102 is disposed in the cut-out area in a direction parallel to the flat side of the cutting edge 100a, and extends to a sufficient length to smoothly electrically connect to each data signal line DL extending from the oblique side and the flat side of the display area AA, wherein the data signal lines DL are parallel to each other. Fig. 9 As shown, the test circuit 102-1 is arranged in the cut-out area in a direction parallel to the flat side of the cutting edge 100a, and is electrically connected to the data signal line DL led from the flat side of the display area AA. The test circuit 102-2 is arranged in parallel on the side of the test circuit 102-1 relative to the display area AA, and is electrically connected to the data signal line DL led from the oblique side of the display area AA, wherein the data signal line DL led from the oblique side of the display area AA may include a bend in the cut-out area, so as to smoothly electrically connect to the test circuit 102-2. Fig.10 As shown, the test circuit 102-1 and the test circuit 102-2 are respectively arranged in the cut-away area in parallel to different oblique edges, and are respectively electrically connected to the data signal lines DL led from the corresponding oblique edges and part of the data signal lines DL led from the flat edges, wherein the data signal lines DL led from the flat edges may include bends in the cut-away area to smoothly electrically connect with the test circuit 102-1 and the test circuit 102-2. In some embodiments, as Figure 7 As shown, an electrostatic protection circuit 104 may be provided at the portion where the data signal line DL passes through the peripheral region PR to reduce the probability of damage caused by static electricity entering from the end of the data signal line DL exposed from the cutting edge 100a. In some embodiments, an insulating material may be applied to the cutting edge 100a to electrically isolate the exposed end of the data signal line DL from the outside.

[0052] In summary, the panel of the electronic device proposed by the present invention uses different layers of conductive layers to jumper the wiring of the test circuit, which can improve the layout density of the test circuit, help to set up a test circuit that is sufficient to match the pixel array of the display area in a limited area, and achieve the purpose of full testing. In addition, in the embodiment where the test circuit and the scan drive circuit are simultaneously set at the bevel of the peripheral area, the space utilization rate can be optimized by changing the block configuration of the scan drive circuit, and the width of the bevel of the peripheral area can be reduced to meet the narrow frame design specifications.

[0053] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic device comprising a panel, characterized in that: The panel includes; substrate; A plurality of signal lines are arranged on the substrate; as well as A test circuit is arranged on the substrate, wherein the test circuit comprises: The first switch element and the second switch element are electrically connected to the same switch signal line; A first conductive connection portion, electrically connected between the first switch element and one of the signal lines; as well as The second conductive connection portion is electrically connected between the second switch element and another of the signal lines, wherein the first conductive connection portion at least partially overlaps with the second switch element.

2. The electronic device according to claim 1, characterized in that: A minimum distance from the first conductive connection portion to the substrate is different from a minimum distance from the second conductive connection portion to the substrate.

3. The electronic device according to claim 1, characterized in that: The test circuit further comprises: The third switch element is electrically connected to the same switch signal line as the first switch element and the second switch element, and the third switch element is electrically connected to another one of the signal lines.

4. The electronic device according to claim 3, characterized in that: An arrangement direction of the first switch element, the second switch element, and the third switch element is parallel to an extension direction of the signal line.

5. The electronic device according to claim 3, characterized in that: The test circuit further comprises: A first control element, a second control element and a third control element are electrically connected to the first switch element, the second switch element and the third switch element respectively; and A plurality of control signal lines are electrically connected to the first control element, the second control element and the third control element respectively.

6. The electronic device according to claim 5, characterized in that: The test circuit also includes a third conductive connection portion and a fourth conductive connection portion, the third conductive connection portion is electrically connected between one of the control signal lines and the third control element, and the fourth conductive connection portion is electrically connected between another one of the control signal lines and the second control element, wherein the third conductive connection portion at least partially overlaps with the second control element.

7. The electronic device according to claim 6, characterized in that: A minimum distance from the third conductive connection portion to the substrate is different from a minimum distance from the fourth conductive connection portion to the substrate.

8. The electronic device according to claim 1, characterized in that: Also includes: A plurality of first gate driving circuits are arranged along the first direction and disposed on the substrate; as well as A plurality of second gate driving circuits are arranged along a second direction and are disposed on the substrate, wherein the first direction is different from the second direction.

9. The electronic device according to claim 8, characterized in that: The first gate driving circuit includes a shift register circuit block, an output circuit block, a charge release circuit block, and a buffer circuit block which are sequentially arranged along a third direction.

10. The electronic device according to claim 8, characterized in that: The second gate drive circuit includes a shift register circuit block, an output circuit block, a charge release circuit block, and a buffer circuit block, wherein the output circuit block and the charge release circuit block are arranged between the shift register circuit block and the buffer circuit block, and the output circuit block and the charge release circuit block are arranged along the second direction, and the shift register circuit block and the buffer circuit block are arranged along a fourth direction, and the second direction is different from the fourth direction.

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