Test panel

Abstract

A test panel is provided. The test panel includes a pixel, a first test element connected to the pixel, the first test element including a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the pixel, a test pad spaced apart from the first test element, a first connection line connected to the first electrode, and a first resistive layer connected to the second electrode. The first connection line is connected to the first test element and the test pad, and the first resistive layer is located on the same layer as the semiconductor layer and connects the first electrode and the first connection line spaced apart from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0108972 filed in the Korean Intellectual Property Office on August 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure described herein relate to a test panel and a display device. Background Art

[0004] Generally, a display device includes a display panel for displaying an image and a driver connected to the display panel. The display panel includes a plurality of pixels for displaying an image. The pixels are driven by a driving signal and generate light for displaying an image.

[0005] After manufacturing the display panel, it is possible to test whether the pixels are operating normally. The display panel may include a plurality of test elements connected to the pixels to test the pixels. A test signal may be applied to the pixels through the test elements, and it may be possible to check whether the pixels are operating normally by determining whether the pixels are turned on.

[0006] After the pixels are fully tested, the test element may be removed from the display panel. For example, the test element may be positioned in a cutout region of the display panel, and the cutout region may be cut and removed after the pixels are fully tested.

[0007] When external static electricity is applied to the test element, the test element may be damaged, and thus a normal test operation may not be performed.

[0008] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0009] Aspects of some embodiments of the present disclosure relate to systems and methods for protecting a test element from static electricity.

[0010] Aspects of some embodiments of the present disclosure include a test panel for protecting a first test element from static electricity and a display device including the test panel from which the test element is removable.

[0011] According to some embodiments, the test panel includes a pixel; a first test element connected to the pixel and including a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the pixel; a test pad spaced apart from the first test element; a first connecting line connected to the first test element and the test pad; and a first resistance layer that is located at the same layer as the semiconductor layer and connects the first electrode and the first connecting line spaced apart from each other.

[0012] According to some embodiments, the test panel includes a pixel; a first test element connected to the pixel and including a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the pixel; a test pad spaced apart from the first test element; a first connection line between the first test element and the test pad; a first resistance layer connecting the first electrode and the first connection line; and a second resistance layer connecting the first connection line and the test pad. According to some embodiments, the first resistance layer and the second resistance layer are located at the same layer as the semiconductor layer.

[0013] According to some embodiments, a display device includes a pixel including a transistor and a light-emitting element connected to the transistor, a test element, a connection line connected to the pixel and the test element, a connection pad spaced from the test element and defined at one end of the connection line, and a resistance layer connected to the connection pad. According to some embodiments, the resistance layer is formed of the same material as a semiconductor layer of the transistor, and the resistance layer is located at the same layer as the semiconductor layer of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The patent or application file contains at least one drawing executed in color.

[0015] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings.

[0016] Figure 1 is a plan view of a test panel according to some embodiments of the present disclosure.

[0017] Figure 2 It is shown in the removal Figure 1 The second section is shown in the view of the data driver that is connected to the test panel.

[0018] Figure 3 According to some embodiments Figure 2 A cross-sectional view of a display panel shown in FIG.

[0019] Figure 4 According to some embodiments Figure 1 A cross-sectional view of one of the pixels shown in FIG.

[0020] Figure 5is a diagram showing that according to some embodiments Figure 1 A view of the circuit configuration of the first test unit and the second test unit shown in FIG.

[0021] Figure 6 yes Figure 1 An enlarged view of the first area AA1 shown in FIG. Figure 6 According to some embodiments, Figure 5 The planar configuration of the first test element is shown in FIG.

[0022] Figure 7 yes Figure 1 An enlarged view of the second area AA2 shown in FIG. Figure 7 According to some embodiments, Figure 5 Planar configuration of the test pads shown in .

[0023] Figure 8 According to some embodiments, Figure 6 A cross-sectional view taken along line II' shown in FIG.

[0024] Fig. 9 According to some embodiments, Figure 7 A cross-sectional view taken along line II-II' shown in FIG.

[0025] Fig.10 yes Figure 1 FIG. 1 is an enlarged view of the third area AA3 shown in FIG. 1 , wherein Fig.10 According to some embodiments, Figure 5 The planar configuration of the connection pads shown in FIG.

[0026] Fig.11 According to some embodiments, Fig.10 A cross-sectional view taken along line III-III' shown in FIG.

[0027] Fig.12 and Fig.13 is a view showing a configuration of a first resistance layer according to some embodiments of the present disclosure.

[0028] Fig.14 and Fig.15 is a view showing a configuration of a second resistance layer according to some embodiments of the present disclosure.

[0029] Fig.16 According to some embodiments, when static electricity is applied to a Figure 6 , Figure 7 , Fig.12 and Fig.15 The test pads in the test panel of the resistance layer shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0030] Fig.17 is a view showing an anti-static circuit connected to a first connection line according to some embodiments of the present disclosure.

[0031] Fig.18 According to some embodiments Fig.17 An enlarged view of the antistatic circuit shown in .

[0032] Fig.19 is a view showing an anti-static circuit connected to a first connection line according to some embodiments of the present disclosure.

[0033] Fig. 20 According to some embodiments, when static electricity is applied to a Fig.17 and Fig.19 The test pads in the test panel of the antistatic circuit shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0034] Fig.21 is a diagram showing a method according to some embodiments wherein Figure 6 and Figure 7 The first resistor and the second resistor formed by the first resistor layer and the second resistor layer shown in Fig.17 A view of a structure for use with an antistatic circuit is shown in FIG.

[0035] Fig. 22 According to some embodiments, when static electricity is applied to a Fig.21 The antistatic circuit shown in FIG. 1 and the test pads in the test panel of the first resistor and the second resistor are test results of the electric field formed on the semiconductor layer of the first test element.

[0036] Fig.23 is a view showing a configuration of a third resistance layer according to some embodiments of the present disclosure.

[0037] Fig.24 According to some embodiments, Fig.23 A cross-sectional view taken along line IV-IV' shown in FIG.

[0038] Fig.25 is a view showing a configuration of a fourth resistance layer according to some embodiments of the present disclosure.

[0039] Fig.26 is along Fig.25 A cross-sectional view taken along line V-V' shown in FIG.

[0040] Fig. 27 is a view showing a configuration of connection lines according to some embodiments of the present disclosure.

[0041] Fig.28According to some embodiments, Fig. 27 A cross-sectional view taken along line VI-VI' shown in FIG.

[0042] Fig.29 According to some embodiments, Fig. 27 A cross-sectional view taken along line VII-VII' shown in FIG.

[0043] Fig.30 and Fig.31 is a diagram showing a method for performing a Fig.28 and Fig.29 The configuration of the third connecting line shown in FIG. 5 is a view of a third connecting line with different configurations.

[0044] Fig.32 According to some embodiments, when static electricity is applied to a Fig.28 and Fig.29 The connection pads in the test panel of the third connection line shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0045] Fig.33 is a diagram showing the removal of Figure 1 A view of the display panel in the second section.

[0046] Fig.34 is a diagram showing a method according to some embodiments including Fig.33 FIG. 1 is a view of a cross-sectional configuration of a display device showing a display panel. DETAILED DESCRIPTION

[0047] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on," "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may be present between them.

[0048] The same reference numerals indicate the same components. In addition, in the drawings, the thickness, ratio, and size of components are exaggerated for efficient description.

[0049] As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0050] Terms such as first, second, etc. can be used to describe various components, but components should not be limited by the terms. These terms can only be used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise specified, terms in the singular may include plural forms.

[0051] In addition, terms such as "below", "below", "above", and "on" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0052] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Such terms as those defined in commonly used dictionaries will be interpreted as having the same meaning as the contextual meaning in the relevant technical field, and will not be interpreted as having an idealized or overly rigid meaning unless explicitly defined as having such a meaning in this application.

[0053] It should be understood that terms such as “includes,” “comprising,” and “having,” when used in this document, specify the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0054] Hereinafter, aspects of some embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.

[0055] Figure 1 is a plan view of a test panel according to some embodiments of the present disclosure.

[0056] Reference Figure 1 , the test panel TPN may include a scan driver SDV, a light emission driver EDV, a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emission lines EL1 to ELm, a first test unit TSP1, a second test unit TSP2, a plurality of connection lines CNL, a plurality of first connection lines CNL1, a plurality of second connection lines CNL2, a plurality of test pads TPD, and a plurality of connection pads CPD. Here, "m" and "n" are natural numbers greater than 0.

[0057] The test panel TPN may have a rectangular shape including long sides extending in the first direction DR1 and short sides extending in the second direction DR2 crossing the first direction DR1. However, the shape of the test panel TPN is not limited thereto.

[0058] Hereinafter, a direction perpendicular (or orthogonal or substantially perpendicular) to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. As used herein, the expression "when viewed from above a plane" or "in a plan view" may mean viewing it from the third direction DR3.

[0059] The test panel TPN may include a first portion PT1 and a second portion PT2 extending from the first portion PT1 in a direction opposite to the first direction DR1. A cutting line CL may be defined at a boundary between the first portion PT1 and the second portion PT2. In a plan view, the first portion PT1 may include a display area DA and a non-display area NDA surrounding the display area DA (e.g., outside the periphery of the display area DA or the cover area of ​​the display area DA).

[0060] The pixel PX may be positioned in the display area DA. The scan driver SDV and the light emission driver EDV may be positioned in the non-display area NDA adjacent to edges of the first portion PT1 extending parallel to each other in the first direction DR1.

[0061] The scan lines SL1 to SLm may extend in the second direction DR2 and may be connected to the pixel PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 in the display area DA and may be connected to the pixel PX. The light emission lines EL1 to ELm may extend in a direction opposite to the second direction DR2 and may be connected to the pixel PX and the light emission driver EDV.

[0062] The first test unit TSP1 and the test pad TPD may be positioned on the second portion PT2. The first test unit TSP1 and the test pad TPD may be spaced apart from each other in the first direction DR1. The test pad TPD may be arranged along the second direction DR2.

[0063] The first connection line CNL1 may be positioned between the first test unit TSP1 and the test pad TPD, and may be connected to the first test unit TSP1 and the test pad TPD. The first connection line CNL1 may be connected to the test pads TPD, respectively.

[0064] The first connection line CNL1 may extend from the test pad TPD toward the first test unit TSP1 and may be arranged in the second direction DR2. The first connection line CNL1 may be connected to the first test element of the first test unit TSP1. This configuration will be described in more detail below.

[0065] The first connection line CNL1 may extend from the test pad TPD in the first direction DR1 and then may extend obliquely to form a certain oblique angle with respect to the first direction DR1. Thereafter, the first connection line CNL1 may extend in the first direction DR1 and may be connected to the first test unit TSP1.

[0066] The second test unit TSP2 and the connection pad CPD may be positioned on the first portion PT1. The second test unit TSP2 and the connection pad CPD may be spaced apart from each other in the first direction DR1. The second test unit TSP2 and the connection pad CPD may be positioned in the non-display area NDA adjacent to a boundary between the first portion PT1 and the second portion PT2.

[0067] The connection pad CPD may be closer to a boundary between the first portion PT1 and the second portion PT2 than the second test cell TSP2. The second test cell TSP2 may be positioned between the connection pad CPD and the display area DA. The connection pad CPD may be arranged in the second direction DR2.

[0068] The second connection lines CNL2 may be positioned between the first test unit TSP1 and the connection pads CPD, and may be connected to the first test unit TSP1 and the connection pads CPD. The second connection lines CNL2 may be connected to the connection pads CPD, respectively.

[0069] The second connection line CNL2 may extend from the first test unit TSP1 toward the connection pad CPD and may be arranged in the second direction DR2. The second connection line CNL2 may be connected to the first test element of the first test unit TSP1. This configuration will be described in detail below.

[0070] The second connection line CNL2 may be connected to the first test unit TSP1 on the second portion PT2, may extend toward the first portion PT1, and may be connected to the connection pad CPD on the first portion PT1. The second connection line CNL2 may extend from the first test unit TSP1 in the first direction DR1, and then may extend obliquely to form a certain inclination angle with respect to the first direction DR1. Thereafter, the second connection line CNL2 may extend in the first direction DR1, and may be connected to the connection pad CPD.

[0071] The connection lines CNL may be connected to the connection pads CPD, respectively, and may extend from the connection pads CPD to the second test unit TSP2. The connection lines CNL may extend toward the display area DA via the second test unit TSP2.

[0072] For example, a portion of the connection line CNL passing through the second test unit TSP2 is shown by a dotted line. The connection line CNL may be connected to the second test element of the second test unit TSP2. This configuration will be described in detail below.

[0073] The connection lines CNL may extend toward the display area DA and may be connected to the data lines DL1 to DLn, respectively. Therefore, the connection lines CNL may be connected to the pixels PX through the data lines DL1 to DLn. The connection pads CPD may be connected to the pixels PX through the connection lines CNL and the data lines DL1 to DLn.

[0074] The connection line CNL may be connected to the data lines DL1 to DLn through a contact hole CTH defined in an insulating layer between the connection line CNL and the data lines DL1 to DLn.

[0075] The data driver D-IC may be positioned adjacent to the test panel TPN. The data driver D-IC may be mounted on a flexible circuit board FPCB. Figure 2 A structure in which a data driver D-IC is connected to a test panel TPN is described.

[0076] According to some embodiments, power lines for supplying operating power to the pixels PX and control lines for applying control signals to the scan driver SDV and the light emission driver EDV may be additionally located in the test panel TPN.

[0077] A test signal may be applied to the pixel PX through the first test unit TSP1 to check a driving state of the pixel PX. Furthermore, a test signal may be applied to the pixel PX through the second test unit TSP2 to additionally check a driving state of the pixel PX.

[0078] According to some embodiments, a mother panel may be manufactured in a manufacturing process of a display device. The mother panel may include a plurality of test panels TPN. Each of the test panels TPN of the mother panel may include the first test unit TSP1 and the second test unit TSP2 as described above.

[0079] In the mother panel, the driving state of the pixel PX may be checked by the first test unit TSP1. After the mother panel is manufactured, the test panel TPN may be cut from the mother panel and separated from each other. As a result, Figure 1 The second test unit TSP2 may be used to check a driving state of a pixel PX in each of the test panels TPN that are separated from each other.

[0080] Figure 2 It is shown in the removal Figure 1 The second section is shown in the view of the data driver that is connected to the test panel.

[0081] Reference Figure 1 and Figure 2 , after checking the driving state of the pixel PX, the test panel TPN may be cut along the cutting line CL, and the second portion PT2 may be removed. The test panel TPN from which the second portion PT2 is removed may be defined as a display panel DP. Hereinafter, the test panel TPN from which the second portion PT2 is removed is referred to as a display panel DP.

[0082] The display panel DP according to some embodiments of the present disclosure may be an emissive display panel, but is not limited thereto according to embodiments of the present disclosure. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, the display panel DP will be described in the context of an organic light-emitting display panel, but is not limited thereto according to embodiments of the present disclosure.

[0083] The flexible circuit board FPCB may be connected to the connection pad CPD. The connection pad CPD is positioned below the flexible circuit board FPCB. Figure 2 , the connection pads CPD are shown as being visible through the flexible circuit board FPCB.

[0084] The data driver D-IC may be connected to the connection pad CPD through the flexible circuit board FPCB and may be connected to the display panel DP accordingly. According to some embodiments, the flexible circuit board FPCB may include a line connected to the data driver D-IC and a pad connecting the line to the connection pad CPD. The data driver D-IC may be connected to the pixel PX through the connection pad CPD, the connection line CNL, and the data lines DL1 to DLn.

[0085] When an image is displayed on the display panel DP, the scan driver SDV, the data driver D-IC, and the pixels PX may be driven as follows.

[0086] The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver D-IC may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emission driver EDV may generate a plurality of light emission signals, and the light emission signals may be applied to the pixels PX through the light emission lines EL1 to ELm.

[0087] The pixel PX may receive a data voltage in response to the scan signal, and may display an image by emitting light having brightness corresponding to the data voltage in response to the light emission signal.

[0088] The second test unit TSP2 may remain in the display panel DP after the cutting process. However, when the display panel DP displays an image, the second test unit TSP2 may be turned off. The second test unit TSP2 may remain in a turned-off state and thus may not affect the image display operation of the display panel DP.

[0089] Figure 3 yes Figure 2 A cross-sectional view of a display panel shown in FIG.

[0090] exist Figure 3, a cross section of the display panel DP viewed in the first direction DR1 is shown.

[0091] Reference Figure 3 , the display panel DP may include a substrate SUB, a circuit element layer DP-CL positioned on the substrate SUB, a display element layer DP-OLED positioned on the circuit element layer DP-CL, and a thin film encapsulation layer TFE positioned on the display element layer DP-OLED.

[0092] The substrate SUB may include a display area DA and a non-display area NDA located around the display area DA. The substrate SUB may include a flexible plastic material such as polyimide (PI) or glass. The display element layer DP-OLED may be positioned in the display area DA.

[0093] A plurality of pixels PX may be positioned in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels PX may include a transistor positioned in the circuit element layer DP-CL and a light emitting element positioned in the display element layer DP-OLED and connected to the transistor.

[0094] The thin film encapsulation layer TFE may be positioned on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixel PX from moisture, oxygen, and external foreign matter.

[0095] Figure 4 yes Figure 1 A cross-sectional view of one of the pixels shown in FIG.

[0096] Reference Figure 4 , the pixel PX may include transistors DT and ET and a light emitting element OLED disposed above the transistors DT and ET. The transistors DT and ET may be located in the circuit element layer DP-CL, and the light emitting element OLED may be located in the display element layer DP-OLED.

[0097] The transistors DT and ET may include a driving transistor DT and a light emitting transistor ET. Although two transistors DT and ET are shown as an example, the pixel PX may include more transistors.

[0098] The driving transistor DT and the light emitting transistor ET may be positioned on the substrate SUB. The display area DA may include an emission area LEA corresponding to the pixel PX and a non-emission area NLEA adjacent to the emission area LEA. The light emitting element OLED may be positioned in the emission area LEA.

[0099] A buffer layer BFL may be positioned on the substrate SUB. The buffer layer BFL may be an inorganic layer. Semiconductor layers S1, A1, and D1 of the driving transistor DT and semiconductor layers S2, A2, and D2 of the light emitting transistor ET may be positioned on the buffer layer BFL. The semiconductor layers S1, A1, D1, S2, A2, and D2 may include polycrystalline silicon. However, not limited thereto, the semiconductor layers S1, A1, D1, S2, A2, and D2 may include amorphous silicon.

[0100] The semiconductor layers S1, A1, D1, S2, A2, and D2 may be doped with an N-type dopant or a P-type dopant. Each of the semiconductor layers S1, A1, D1, S2, A2, and D2 may include a heavily doped region and a lightly doped region. The heavily doped region (e.g., a source region and a drain region) may have a higher conductivity than the lightly doped region and may substantially serve as a source electrode and a drain electrode of the driving transistor DT and the light emitting transistor ET. The lightly doped region may correspond to (or substantially correspond to) a channel region (or channel) of the driving transistor DT and the light emitting transistor ET.

[0101] The first source region S1, the first channel region A1, and the first drain region D1 of the driving transistor DT may be formed by semiconductor layers S1, A1, and D1. The second source region S2, the second channel region A2, and the second drain region D2 of the light emitting transistor ET may be formed by semiconductor layers S2, A2, and D2. The first channel region A1 may be positioned between the first source region S1 and the first drain region D1. The second channel region A2 may be positioned between the second source region S2 and the second drain region D2.

[0102] A first insulating layer INS1 may be positioned on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S2, A2 and D2. A first gate electrode G1 (or control electrode) of the driving transistor DT and a second gate electrode G2 (or control electrode) of the light emission transistor ET may be positioned on the first insulating layer INS1.

[0103] A second insulating layer INS2 may be positioned on the first insulating layer INS1 to cover the first gate electrode G1 and the second gate electrode G2. A dummy electrode DME may be positioned on the second insulating layer INS2. The dummy electrode DME may be disposed above the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from above a plane. The dummy electrode DME may form a capacitor together with the first gate electrode G1.

[0104] A third insulating layer INS3 may be positioned on the second insulating layer INS2 to cover the dummy electrode DME. The buffer layer BFL and the first to third insulating layers INS1 to INS3 may include an inorganic layer.

[0105] A connection electrode CNE may be positioned between the light emitting transistor ET and the light emitting element OLED. The connection electrode CNE may electrically connect the light emitting transistor ET and the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 positioned on the first connection electrode CNE1.

[0106] The first connection electrode CNE1 may be positioned on the third insulating layer INS3 and may be connected to the second drain region D2 through a first contact hole CH1 defined in the first to third insulating layers INS1 to INS3. A fourth insulating layer INS4 may be positioned on the third insulating layer INS3 to cover the first connection electrode CNE1.

[0107] The second connection electrode CNE2 may be positioned on the fourth insulating layer INS4. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4. A fifth insulating layer INS5 may be positioned on the fourth insulating layer INS4 to cover the second connection electrode CNE2. The fourth insulating layer INS4 and the fifth insulating layer INS5 may include an inorganic layer or an organic layer.

[0108] The light emitting element OLED may be positioned on the fifth insulating layer INS5. The light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emission layer EML. The first electrode AE ​​may be an anode, and the second electrode CE may be a cathode.

[0109] The first electrode AE ​​may be positioned on the fifth insulating layer INS5. The first electrode AE ​​may be electrically connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the fifth insulating layer INS5.

[0110] A pixel defining layer PDL exposing a portion (eg, a set or predetermined portion) of the first electrode AE ​​may be positioned on the first electrode AE ​​and the fifth insulating layer INS5. An opening PX_OP for exposing a portion (eg, a set or predetermined portion) of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0111] The hole control layer HCL may be positioned on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0112] The emission layer EML may be positioned on the hole control layer HCL. The emission layer EML may be positioned in a region corresponding to the opening PX_OP. The emission layer EML may include an organic material and / or an inorganic material. The emission layer EML may generate one of red light, green light, and blue light.

[0113] The electron control layer ECL may be positioned on the emission layer EML and the hole control layer HCL. The electron control layer ECL may be commonly positioned in the emission area LEA and the non-emission area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0114] The second electrode CE may be positioned on the electronic control layer ECL. The second electrode CE may be positioned in common in a plurality of pixels PX. That is, the second electrode CE may be arranged in common throughout the emission layer EML of the pixels PX. The thin film encapsulation layer TFE may be positioned on the light emitting element OLED.

[0115] The layers from the buffer layer BFL to the fifth insulating layer INS5 may be defined as a circuit element layer DP-CL. The layer in which the light emitting element OLED is positioned may be defined as a display element layer DP-OLED.

[0116] A first voltage may be applied to the first electrode AE, and a second voltage having a voltage level lower than that of the first voltage may be applied to the second electrode CE. Holes and electrons injected into the emission layer EML may be combined to form excitons, and the light emitting element OLED may emit light as the excitons transition to a ground state. As the light emitting element OLED emits light, an image may be displayed.

[0117] Figure 5 It is shown Figure 1 A view of the circuit configuration of the first test unit and the second test unit shown in FIG.

[0118] exist Figure 5 , the first and second connection lines CNL1 and CNL2 are shown to extend in the first direction DR1.

[0119] Reference Figure 1 and Figure 5 , the first test unit TSP1 may include a plurality of first test elements TS1. The first test element TS1 may include a PMOS transistor. However, not limited thereto, the first test element TS1 may include an NMOS transistor.

[0120] The test pad TPD may be spaced apart from the first test element TS1. The test pad TPD and the first test element TS1 may be connected through a first connection line CNL1.

[0121] Each of the first test elements TS1 may include a source electrode, a drain electrode, and a gate electrode. Figure 5 In the present invention, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0122] The first test element TS1 may include a plurality of 1-1st test elements TS1-1, a plurality of 1-2nd test elements TS1-2, and a plurality of 1-3rd test elements TS1-3. The 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may be repeatedly arranged in the second direction DR2 in the order of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3.

[0123] The control electrodes of the 1-1th test element TS1-1 may be commonly connected to the 1-1th control line C1-1. The control electrodes of the 1-2nd test element TS1-2 may be commonly connected to the 1-2nd control line C1-2. The control electrodes of the 1-3rd test element TS1-3 may be commonly connected to the 1-3rd control line C1-3.

[0124] The 1-1st, 1-2nd, and 1-3rd control lines C1-1, C1-2, and C1-3 may be connected to the test pad TPD-1, respectively. According to some embodiments, the test panel TPN may include the 1-1st, 1-2nd, and 1-3rd control lines C1-3 and the test pad TPD-1.

[0125] The first electrodes of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3, which are sequentially adjacent to each other, may be connected to the corresponding first connection line CNL1 among the first connection lines CNL1. That is, the first electrodes of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3, which are sequentially adjacent to each other, may be commonly connected to the corresponding first connection line CNL1.

[0126] The test panel TPN may include a plurality of first resistors R1 connected to the first test unit TSP1 and the first connection line CNL1 and a plurality of second resistors R2 connected to the first connection line CNL1 and the test pad TPD. The first resistors R1 and the second resistors R2 may be connected to opposite ends of the first connection line CNL1 facing each other in the first direction DR1.

[0127] The first resistor R1 may be located adjacent to the first test unit TSP1 and may be connected to the first end of the first connection line CNL1. The first electrodes of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3, which are adjacent to each other in sequence, may be commonly connected to the corresponding first resistor R1 among the first resistors R1. The configuration of the first resistor R1 will be described in detail below.

[0128] The second resistor R2 may be positioned adjacent to the test pad TPD and may be connected to the second end of the first connection line CNL1. A configuration of the second resistor R2 will be described in detail below.

[0129] The second electrodes of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may be connected to the second connection line CNL2, respectively. The second electrodes of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may be connected to the connection pads CPD through the second connection lines CNL2, respectively. The connection pads CPD may be connected to the connection lines CNL, respectively.

[0130] As described above, the connection lines CNL may be connected to the data lines DL1 to DLn, respectively. Therefore, the first test element TS1 may be connected to the pixel PX through the second connection line CNL2, the connection pad CPD, the connection line CNL, and the data lines DL1 to DLn.

[0131] The control signal may be applied to the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 through the test pad TPD-1 and the 1-1st control line C1-1, the 1-2nd control line C1-2, and the 1-3rd control line C1-3. The control signal may be applied to the 1-1st control line C1-1, the 1-2nd control line C1-2, and the 1-3rd control line C1-3 in sequence. Therefore, the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may be turned on in sequence.

[0132] The test signal may be applied to the 1-1th test element TS1-1, the 1-2th test element TS1-2, and the 1-3rd test element TS1-3 through the test pad TPD and the first connection line CNL1. The test signal may be provided to the second connection line CNL2 through the turned-on 1-1th test element TS1-1, the turned-on 1-2th test element TS1-2, and the turned-on 1-3rd test element TS1-3.

[0133] The test signal may be applied to the pixel PX through the second connection line CNL2, the connection pad CPD, the connection line CNL, and the data lines DL1 to DLn. The pixel PX may be turned on in response to the test signal. The pixel PX may be turned on in response to the test signal, and a pixel PX that is not turned on or does not generate normal brightness may be determined as a defective pixel.

[0134] The first test element TS1 may be easily affected by external static electricity and may be damaged by the external static electricity. The external static electricity may flow into the first test element TS1 through the test pad TPD. Static electricity may be defined as a rapid flow of current.

[0135] According to some embodiments of the present disclosure, the first resistor R1 and the second resistor R2 may be positioned between the first test element TS1 and the test pad TPD. When static electricity flows into the first test element TS1 through the test pad TPD, the first resistor R1 and the second resistor R2 may prevent or reduce static electricity by hindering the rapid flow of current. Since the first resistor R1 and the second resistor R2 prevent or reduce static electricity, damage to the first test element TS1 may be prevented or reduced.

[0136] The second test unit TSP2 may include a plurality of second test elements TS2. The connection pad CPD may be spaced apart from the second test elements TS2 in the first direction DR1. The second test element TS2 may include a PMOS transistor. However, not limited thereto, the second test element TS2 may include an NMOS transistor.

[0137] The second test element TS2 may include a plurality of 2-1st test elements TS2-1, a plurality of 2-2nd test elements TS2-2, and a plurality of 2-3rd test elements TS2-3. The 2-1st test element TS2-1, the 2-2nd test element TS2-2, and the 2-3rd test element TS2-3 may be repeatedly arranged in the second direction DR2 in the order of the 2-1st test element TS2-1, the 2-2nd test element TS2-2, and the 2-3rd test element TS2-3.

[0138] The 2-1st test element TS2-1, the 2-2nd test element TS2-2, and the 2-3rd test element TS2-3 may be commonly connected to the second control line C2. The first electrode of the 2-1st test element TS2-1 may be commonly connected to the first test line TL1. The first electrode of the 2-2nd test element TS2-2 may be commonly connected to the second test line TL2. The first electrode of the 2-3rd test element TS2-3 may be commonly connected to the third test line TL3.

[0139] The second control line C2 and the first, second, and third test lines TL1, TL2, and TL3 may be connected to the test pad TPD-2, respectively. According to some embodiments, the test panel TPN may include the second control line C2, the first, second, and third test lines TL1, TL2, and TL3, and the test pad TPD-2.

[0140] The second electrode of the 2-1st test element TS2-1 may be connected to the connection line CNL connected to the 1-1st test element TS1-1. The second electrode of the 2-2nd test element TS2-2 may be connected to the connection line CNL connected to the 1-2nd test element TS1-2. The second electrode of the 2-3rd test element TS2-3 may be connected to the connection line CNL connected to the 1-3rd test element TS1-3. Therefore, the second test element TS2 may be connected to the pixel PX through the connection line CNL and the data lines DL1 to DLn.

[0141] According to some embodiments, the pixel PX may include a red pixel, a green pixel, and a blue pixel. The 1-1st test element TS1-1 and the 2-1st test element TS2-1 may be connected to the red pixel. The 1-2nd test element TS1-2 and the 2-2nd test element TS2-2 may be connected to the green pixel. The 1-3rd test element TS1-3 and the 2-3rd test element TS2-3 may be connected to the blue pixel.

[0142] The 2-1st test element TS2-1, the 2-2nd test element TS2-2, and the 2-3rd test element TS2-3 may be turned on by a control signal applied through the second control line C2. The 2-1st test element TS2-1, the 2-2nd test element TS2-2, and the 2-3rd test element TS2-3 may receive a test signal through the first test line TL1, the second test line TL2, and the third test line TL3.

[0143] The test signal applied to the 2-1st test element TS2-1 through the first test line TL1 can be applied to the above-mentioned red pixel through the 2-1st test element TS2-1. The test signal applied to the 2-2nd test element TS2-2 through the second test line TL2 can be applied to the above-mentioned green pixel through the 2-2nd test element TS2-2. The test signal applied to the 2-3rd test element TS2-3 through the third test line TL3 can be applied to the above-mentioned blue pixel through the 2-3rd test element TS2-3. Therefore, it can be checked whether the pixel PX is driven normally.

[0144] Figure 6 yes Figure 1 An enlarged view of the first area AA1 shown in FIG. Figure 6 Shows Figure 5 The planar configuration of the first test element is shown in FIG. Figure 7 yes Figure 1 An enlarged view of the second area AA2 shown in FIG. Figure 7 Shows Figure 5 Planar configuration of the test pads shown in .

[0145] Figure 6 and Figure 7A layout diagram that can be defined as the first test element TS1 and the test pad TPD.

[0146] Reference Figure 6 , each of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may include a gate electrode GE, a semiconductor layer AT, a first electrode E1, and a second electrode E2. The 1-1st control line C1-1, the 1-2nd control line C1-2, and the 1-3rd control line C1-3 may extend to cross the semiconductor layer AT of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3.

[0147] Since the first test element TS1 has substantially the same configuration, the configuration of the 1-1 test element TS1-1 will be mainly described below. In addition, since the 1-1 control line C1-1, the 1-2 control line C1-2 and the 1-3 control line C1-3 have substantially the same configuration, the configuration of the 1-1 control line C1-1 will be described below.

[0148] The semiconductor layer AT of the 1-1th test element TS1-1 may extend in the first direction DR1. The 1-1th control line C1-1 may include a plurality of gate patterns GPT extending and arranged in the second direction DR2 and connection electrodes CE and CE' connecting the gate patterns GPT. The connection electrodes CE and CE' may be connected to the gate pattern GPT through the first contact hole H1.

[0149] The connection electrode CE' connected to the leftmost gate pattern GPT may extend adjacent to the test pad TPD and may define the test pad TPD-1. Hereinafter, the gate pattern GPT crossing the semiconductor layer AT of the 1-1th test element TS1-1 will be described.

[0150] The gate pattern GPT may extend in the second direction DR2 to cross the semiconductor layer AT. A portion of the gate pattern GPT overlapping the semiconductor layer AT may form the gate electrode GE of the 1-1th test device TS1-1.

[0151] The first electrode E1 and the second electrode E2 of the 1-1th test element TS1-1 may be spaced apart from each other in the first direction DR1 via the gate electrode GE of the 1-1th test element TS1-1. The first electrode E1 and the second electrode E2 may be connected to the semiconductor layer AT through the second contact hole H2.

[0152] The first electrodes E1 of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3, which are adjacent to each other in sequence, may be integrally formed. The integrally formed first electrodes E1 may be connected to the corresponding first resistance layers RL1 among the first resistance layers RL1. The first resistance layers RL1 may be formed Figure 5 The first resistor R1 is shown in FIG.

[0153] The second electrodes E2 of the 1-1st test element TS1-1, the 1-2nd test element TS1-2, and the 1-3rd test element TS1-3 may be connected to the second connection lines CNL2, respectively. The second electrodes E2 may be connected to the second connection lines CNL2 through the third contact holes H3, respectively. Since the second connection lines CNL2 are connected to the data lines DL1 to DLn as described above, the second electrodes E2 may be connected to the pixels PX, respectively.

[0154] Reference Figure 6 and Figure 7 , the test pads TPD may be connected to the second resistance layer RL2 respectively. The second resistance layer RL2 may be formed Figure 5 The second resistor R2 is shown in FIG.

[0155] Since the first resistance layer RL1 has the same configuration and the second resistance layer RL2 has the same configuration, the configuration of one first resistance layer RL1 and one second resistance layer RL2 connected to the 1-1 test element TS1-1 will be mainly described below. In addition, since the first connection line CNL1 has the same configuration and the test pad TPD has the same configuration, the configuration of one first connection line CNL1 and one test pad TPD connected to the 1-1 test element TS1-1 will be mainly described below.

[0156] The first connection line CNL1 may be connected to the 1-1th test element TS1-1 and the test pad TPD spaced apart from each other through the first resistance layer RL1 and the second resistance layer RL2. The first connection line CNL1 may be positioned between the 1-1th test element TS1-1 and the test pad TPD. The first connection line CNL1 may be spaced apart from the first electrode E1 of the 1-1th test element TS1-1. The first connection line CNL1 may be spaced apart from the test pad TPD.

[0157] The first resistance layer RL1 may connect the first electrode E1 and the first connection line CNL1 of the 1-1th test element TS1-1 spaced apart from each other. The first resistance layer RL1 may be connected to the first electrode E1 and the first connection line CNL1 of the 1-1th test element TS1-1 through the fourth contact hole H4.

[0158] One side of the first electrode E1 and one side of the first connection line CNL1 may face each other. The first resistance layer RL1 may be connected to a portion of the first electrode E1 adjacent to one side of the first electrode E1 and a portion of the first connection line CNL1 adjacent to one side of the first connection line CNL1.

[0159] The second resistance layer RL2 may connect the first connection line CNL1 and the test pad TPD which are spaced apart from each other. The second resistance layer RL2 may be connected to the first connection line CNL1 and the test pad TPD through the fifth contact hole H5.

[0160] The opposite side of the first connection line CNL1 facing away from the first connection line CNL1 and the side of the test pad TPD may face each other. The second resistance layer RL2 may be connected to a portion of the first connection line CNL1 adjacent to the opposite side of the first connection line CNL1 and a portion of the test pad TPD adjacent to the side of the test pad TPD.

[0161] The first resistance layer RL1, the second resistance layer RL2, and the test pad TPD may extend in the first direction DR1. The test pad TPD may have a first length LT1 in the first direction DR1. The first resistance layer RL1 may have a second length LT2 in the first direction DR1, and the second resistance layer RL2 may have a third length LT3 in the first direction DR1.

[0162] The second length LT2 and the third length LT3 may be equal to each other. However, not limited thereto, the second length LT2 and the third length LT3 may be different from each other. Each of the second length LT2 and the third length LT3 may be set to 1 / 4 to 1 / 3 of the first length LT1. For example, the first length LT1 may be 100 micrometers (μm), and each of the second length LT2 and the third length LT3 may be 32.5 micrometers (μm).

[0163] Figure 8 is along Figure 6 A cross-sectional view taken along line II' shown in FIG. Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II' shown in FIG.

[0164] Reference Figure 8 The 1-1 test element TS1-1 may include a gate electrode GE, a semiconductor layer AT, a first electrode E1, and a second electrode E2 positioned on a substrate SUB. The gate electrode GE and the semiconductor layer AT may be connected to Figure 4 The first gate electrode G1 and the semiconductor layers S1, A1, and D1 shown in FIG. 1 have substantially the same configuration and may be positioned at the same layer. The first electrode E1 and the second electrode E2 may be Figure 4 The first connection electrode CNE1 shown in FIG. 1 has substantially the same configuration and may be positioned at the same layer.

[0165] A buffer layer BFL may be positioned, and the semiconductor layer AT and the first resistance layer RL1 may be positioned on the buffer layer BFL. The first resistance layer RL1 may be positioned at the same layer as the semiconductor layer AT. The first resistance layer RL1 may include the same material as that of the semiconductor layer AT. The first resistance layer RL1 may be a semiconductor doped with impurities, and may be defined as a conductor having a high resistance.

[0166] The first insulating layer INS1 may be positioned on the buffer layer BFL to cover the semiconductor layer AT and the first resistance layer RL1. The gate electrode GE, the gate pattern GPT, and the second connection line CNL2 may be positioned on the first insulating layer INS1. The gate electrode GE, the gate pattern GPT, and the second connection line CNL2 may be positioned at the same layer. The semiconductor layer AT and the first resistance layer RL1 may be positioned at a layer located below the gate electrode GE, the gate pattern GPT, and the second connection line CNL2.

[0167] The second insulating layer INS2 may be positioned on the first insulating layer INS1 to cover the gate electrode GE, the gate pattern GPT, and the second connection line CNL2. The third insulating layer INS3 may be positioned on the second insulating layer INS2.

[0168] The first electrode E1, the second electrode E2, and the first connection line CNL1 may be positioned on the third insulating layer INS3. The first electrode E1, the second electrode E2, and the first connection line CNL1 may be positioned at the same layer. The first electrode E1, the second electrode E2, and the first connection line CNL1 may be positioned at a layer located above the gate electrode GE.

[0169] The first electrode E1 and the second electrode E2 may be connected to the semiconductor layer AT through a second contact hole H2 defined in the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The second electrode E2 may be connected to the second connection line CNL2 through a third contact hole H3 defined in the second insulating layer INS2 and the third insulating layer INS3. The first electrode E1 and the first connection line CNL1 may be connected to the first resistance layer RL1 through a fourth contact hole H4 defined in the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0170] According to some embodiments, Figure 6 The connection electrode CE shown in FIG. 1 may be positioned at the same layer as the first electrode E1 and the second electrode E2. Therefore, the first contact hole H1 may be defined in the second insulating layer INS2 and the third insulating layer INS3.

[0171] The fourth insulating layer INS4 may be positioned on the third insulating layer INS3 to cover the first electrode E1, the second electrode E2, and the first connection line CNL1.

[0172] Reference Figure 8 and Fig. 9 , the second resistance layer RL2 may be positioned on the buffer layer BFL. The second resistance layer RL2 may be positioned at the same layer as the semiconductor layer AT and may include the same material as the semiconductor layer AT. The second resistance layer RL2 may be positioned at a layer located below the gate electrode GE. The second resistance layer RL2 may be a semiconductor doped with impurities and may be defined as a conductor having a high resistance.

[0173] The first connection line CNL1 and the test pad TPD may be positioned on the third insulating layer INS3. The first connection line CNL1 and the test pad TPD may be positioned on the same layer. The first connection line CNL1 and the test pad TPD may be connected to the second resistance layer RL2 through a fifth contact hole H5 defined in the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0174] The fourth insulating layer INS4 may be positioned on the first connection line CNL1. The fourth insulating layer INS4 may not be positioned on the test pad TPD. The test pad TPD may be exposed to the outside.

[0175] Reference Figures 6 to 9 The first resistance layer RL1 and the second resistance layer RL2 may have high resistance, and thus static electricity flowing into the first test element TS1 through the test pad TPD may be prevented or reduced. Therefore, damage to the first test element TS1 may be prevented or reduced by the first resistance layer RL1 and the second resistance layer RL2.

[0176] Fig.10 yes Figure 1 FIG. 1 is an enlarged view of the third area AA3 shown in FIG. 1 , wherein Fig.10 Shows Figure 5 The planar configuration of the connection pads shown in FIG. Fig.11 is along Fig.10 A cross-sectional view taken along line III-III' shown in FIG.

[0177] Reference Figure 6 and Fig.10 , the connection pad CPD may be spaced apart from the second electrode E2. The second connection line CNL2 may be connected to the connection pad CPD and the second electrode E2. The second connection line CNL2 and the connection pad CPD may be connected through the connection electrode CE-1. The connection lines CNL may extend from the connection pads CPD in the first direction DR1, respectively.

[0178] Hereinafter, the configuration of one second connection line CNL2 and one connection pad CPD connected to one connection electrode CE- 1 will be mainly described.

[0179] The connection electrode CE-1 may be connected to the second connection line CNL2 through the sixth contact hole H6. The connection pad CPD may be connected to the connection electrode CE-1 through the seventh contact hole H7.

[0180] Reference Fig.10 and Fig.11 , the second connection line CNL2 may be positioned on the first insulating layer INS1. The connection electrode CE-1 may be positioned on the third insulating layer INS3. The connection pad CPD and the connection line CNL extending from the connection pad CPD may be positioned on the fourth insulating layer INS4. The connection pad CPD may be positioned at a layer located above the second electrode E2 and the connection electrode CE-1.

[0181] The connection electrode CE-1 may be connected to the second connection line CNL2 through a sixth contact hole H6 defined in the second insulating layer INS2 and the third insulating layer INS3. The connection pad CPD may be connected to the connection electrode CE-1 through a seventh contact hole H7 defined in the fourth insulating layer INS4. The connection pad CPD may be exposed to the outside and may be connected to the above-mentioned flexible circuit board FPCB.

[0182] Fig.12 and Fig.13 is a view showing a configuration of a first resistance layer according to some embodiments of the present disclosure.

[0183] Fig.12 and Fig.13 is with Figure 6 and Figure 7 The following description will focus on Figure 6 and Figure 7 The parts shown in Fig.12 and Fig.13 Hereinafter, for the convenience of description, the configuration of one first resistance layer RL1 - 1 will be mainly described.

[0184] Reference Fig.12 and Fig.13 The first resistance layer RL1-1 may connect the 1-1th test element TS1-1 and the first connection line CNL1. The first resistor R1 may be formed by the first resistance layer RL1-1. Figure 7 Unlike the configuration shown in , the second resistance layer RL2 for connecting the test pad TPD and the first connection line CNL1 may not be used.

[0185] The first resistance layer RL1-1 may have a fourth length LT4 in the first direction DR1. The fourth length LT4 may be set to 1 / 3 to 2 / 3 of the first length LT1. For example, the fourth length LT4 may be 65 micrometers (μm).

[0186] Although not used Figure 7The second resistance layer RL2 shown in FIG. 1 is a first resistance layer RL1-1 connected to the first test element TS1 and a second resistance layer RL2 connected to the test pad TPD may be used together. In this case, the second resistance layer RL2 may be shorter than the first resistance layer RL1-1.

[0187] Fig.14 and Fig.15 is a view showing a configuration of a second resistance layer according to some embodiments of the present disclosure.

[0188] Fig.14 and Fig.15 is with Figure 6 and Figure 7 The following description will focus on Figure 6 and Figure 7 The parts shown in Fig.14 and Fig.15 Hereinafter, for the convenience of description, the configuration of one second resistance layer RL2 - 1 will be mainly described.

[0189] Reference Fig.14 and Fig.15 The second resistor layer RL2-1 may connect the test pad TPD and the first connection line CNL1. The second resistor R2 may be formed by the second resistor layer RL2-1. Figure 6 Unlike the configuration shown in , the first resistance layer RL1 for connecting the 1-1th test device TS1 - 1 and the first connection line CNL1 may not be used.

[0190] The second resistance layer RL2-1 may have a fifth length LT5 in the first direction DR1. The fifth length LT5 may be set to 1 / 3 to 2 / 3 of the first length LT1. For example, the fifth length LT5 may be 65 micrometers (μm).

[0191] Although not used Figure 6 The first resistance layer RL1 shown in FIG. 1 is a first resistance layer RL2-1, but the embodiments of the present disclosure are not limited thereto. For example, the second resistance layer RL2-1 connected to the test pad TPD and the first resistance layer RL1 connected to the first test element TS1 may be used together. In this case, the first resistance layer RL1 may be shorter than the second resistance layer RL2-1.

[0192] When the lengths of the first resistance layer RL1, the second resistance layer RL2, the first resistance layer RL1-1, and the second resistance layer RL2-1 are too long, the resistance value may be too large, and thus it may be difficult to transmit a signal. According to some embodiments of the present disclosure, the lengths of the first resistance layer RL1, the second resistance layer RL2, the first resistance layer RL1-1, and the second resistance layer RL2-1 may be set to 2 / 3 or less of the first length LT1. In this case, the test signal may be transmitted normally, and static electricity may be prevented or reduced.

[0193] Fig.16 shows that when static electricity is applied to Figure 6 , Figure 7 , Fig.12 and Fig.15 The test pads in the test panel of the resistance layer shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0194] For example, the test is performed by applying static electricity to three first test elements TS1 connected to one test pad TPD. The three first test elements TS1 connected to one test pad TPD may include a 1-1th test element TS1-1, a 1-2th test element TS1-2, and a 1-3th test element TS1-3. Fig.16 The reference numerals of the first test elements TS1 (TS1-1, TS1-2, and TS1-3) are omitted.

[0195] Reference Fig.16 , the electric field (E-Field) profile in the attached figure is a picture showing the profile of the intensity of the electric field in color. In the table, the intensity of the electric field may increase as it approaches red, and the intensity of the electric field may decrease as it approaches blue.

[0196] The R, G and B of the electric field in the accompanying drawings represent the values ​​of the intensity of the electric field measured in the 1-1th test element TS1-1 connected to the red pixel R, the 1-2nd test element TS1-2 connected to the green pixel G, and the 1-3rd test element TS1-3 connected to the blue pixel B.

[0197] The comparison resistance layer RL may refer to a resistance layer connected to the test pad TPD and the first connection line CNL1, and the length of the comparison resistance layer RL may be 12 micrometers (μm). That is, the comparison resistance layer RL and the second resistance layer RL2 may be connected to the test pad TPD, but the comparison resistance layer RL may be shorter than the second resistance layer RL2.

[0198] When static electricity is applied through the test pad TPD, according to the comparison resistance layer RL, Fig.15 The second resistance layer RL2-1 shown in Fig.12 The first resistance layer RL1-1 shown in FIG. Figure 6 and Figure 7 The strength of the electric field formed by the first resistance layer RL1 plus the second resistance layer RL2 in the first test element TS1 is as shown in FIG. Fig.16 as shown in .

[0199] When the second resistance layer RL2-1 is used, the intensity of the electric field can be further reduced compared to when the comparison resistance layer RL is used. When the first resistance layer RL1-1 is used, the intensity of the electric field can be further reduced compared to when the second resistance layer RL2-1 is used. When the first resistance layer RL1 plus the second resistance layer RL2 is used, the intensity of the electric field can be further reduced compared to when the first resistance layer RL1-1 is used. Therefore, when the first resistance layer RL1 plus the second resistance layer RL2, the first resistance layer RL1-1 and the second resistance layer RL2-1 are used, static electricity can be effectively prevented or reduced.

[0200] Fig.17 is a view showing an anti-static circuit connected to a first connection line according to some embodiments of the present disclosure. Fig.18 yes Fig.17 An enlarged view of the antistatic circuit shown in .

[0201] Reference Fig.17 and Fig.18 , the test panel TPN may further include an antistatic circuit STP. The antistatic circuits STP may be connected to the first connection lines CNL1, respectively. One end of each of the antistatic circuits STP may be connected to the first line L1, and the opposite end of the antistatic circuit STP may be connected to the second line L2. The first line L1 and the second line L2 may be connected to the ground pad GPD. The antistatic circuits STP may be positioned adjacent to the test pads TPD, respectively.

[0202] Hereinafter, configuration of one first connection line CNL1 and one anti-static circuit STP connected to the one first connection line CNL1 will be mainly described. The anti-static circuit STP may include a plurality of diodes DO1 and DO2 connected to a corresponding first connection line CNL1 among the first connection lines CNL1.

[0203] The diodes DO1 and DO2 of the antistatic circuit STP may include a first diode DO1 and a second diode DO2. The first diode DO1 may be connected to the first line L1 and the first connection line CNL1. The second diode DO2 may be connected to the second line L2 and the first connection line CNL1.

[0204] The first diode DO1 may be connected to the first line L1 and the node ND. The first diode DO1 may be arranged in a forward direction from the first line L1 toward the node ND and may be connected in series.

[0205] The second diode DO2 may be connected to the second line L2 and the node ND. The second diode DO2 may be arranged in a forward direction from the node ND toward the second line L2 and may be connected in series.

[0206] The node ND may be connected to the first connection line CNL1. The first diode DO1 may be connected to the first connection line CNL1 through the node ND. The second diode DO2 may be connected to the first connection line CNL1 through the node ND.

[0207] The first connection line CNL1 may include a first extension portion EXP1 extending from the test pad TPD in a first direction DR1 and a second extension portion EXP2 extending to form an obtuse angle with the first extension portion EXP1. The second extension portion EXP2 may extend toward the first test element TS1. The antistatic circuit STP may be connected to the first extension portion EXP1 and may be positioned adjacent to a corresponding one of the test pads TPD.

[0208] Static electricity applied through the test pad TPD may be distributed to the anti-static circuit STP, and may be discharged through the ground pad GPD. Therefore, damage to the first test element TS1 due to static electricity may be prevented or reduced.

[0209] Fig.19 is a view showing an anti-static circuit connected to a first connection line according to some embodiments of the present disclosure.

[0210] The following description will focus on Fig.17 The components shown in the figure are different components.

[0211] Reference Fig.19 , the antistatic circuit STP can have Fig.17 The anti-static circuit STP shown in FIG. 1 may be connected to the first connection line CNL1 , respectively. Fig.17 Unlike what is shown in FIG. 2 , each of the anti-static circuits STP may be positioned adjacent to the second extension portion EXP2 of the corresponding first connection line CNL1 .

[0212] Reference Fig.17 and Fig.19 According to some embodiments, the first resistance layer RL1 and the second resistance layer RL2 may be used together with the antistatic circuit STP. Alternatively, the first resistance layer RL1-1 or the second resistance layer RL2-1 may be used together with the antistatic circuit STP. In another case, referring to Fig.16 The described comparison resistance layer RL can also be used together with the antistatic circuit STP.

[0213] Fig. 20 shows that when static electricity is applied to Fig.17 and Fig.19 The test pads in the test panel of the antistatic circuit shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0214] Fig. 20 The items marked as STP in the Fig.16 The comparison resistance layer RL shown in Fig.17 or Fig.19 The strength of the electric field when used with the antistatic circuit STP is shown in FIG.

[0215] Reference Fig. 20 , when additionally used Fig.19 When the antistatic circuit STP is used, the strength of the electric field can be reduced compared to when the comparison resistance layer RL is used. Fig.17 When the antistatic circuit STP is used, the intensity of the electric field can be further reduced compared to when the comparison resistance layer RL is used.

[0216] Fig.21 It is shown that Figure 6 and Figure 7 The first resistor and the second resistor formed by the first resistor layer and the second resistor layer shown in Fig.17 A view of a structure for use with an antistatic circuit is shown in FIG.

[0217] exist Fig.21 , a first test element TS1, a first resistor R1, a second resistor R2, and an antistatic circuit STP are shown as a circuit structure.

[0218] Reference Fig.21 , the antistatic circuits STP may be respectively adjacent to the test pads TPD and may be respectively connected to the first connection lines CNL1. The antistatic circuits STP may be respectively positioned adjacent to the second resistance layer RL2. To further prevent or reduce static electricity, the antistatic circuits STP may be used together with the first resistor R1 and the second resistor R2 formed by the first resistance layer RL1 and the second resistance layer RL2.

[0219] Fig. 22 shows that when static electricity is applied to Fig.21 The antistatic circuit shown in FIG. 1 and the test pads in the test panel of the first resistor and the second resistor are test results of the electric field formed on the semiconductor layer of the first test element.

[0220] Reference Fig. 22 , when using Fig.21 When the first resistance layer RL1 and the second resistance layer RL2 and the antistatic circuit STP are used, the intensity of the electric field can be further reduced compared to when the comparative resistance layer RL is used.

[0221] Fig.23 is a view showing a configuration of a third resistance layer according to some embodiments of the present disclosure. Fig.24 is along Fig.23 A cross-sectional view taken along line IV-IV' shown in FIG.

[0222] Fig.23 is with Figure 6 The following description will focus on Figure 6 The components shown in the figure are different components.

[0223] Reference Fig.23 , the test panel TPN may further include a plurality of third resistance layers RL3. The second connection line CNL2 may be spaced apart from the second electrode E2 of the first test element TS1. The third resistance layer RL3 may connect the second electrode E2 and the second connection line CNL2 spaced apart from each other. The third resistance layer RL3 may be connected to the second connection line CNL2 and the second electrode E2 through the eighth contact hole H8 and the ninth contact hole H9.

[0224] Reference Fig.24 The third resistance layer RL3 may be positioned on the buffer layer BFL, the second connection line CNL2 may be positioned on the first insulating layer INS1, and the second electrode E2 may be positioned on the third insulating layer INS3. The third resistance layer RL3 may include the same material as that of the semiconductor layer AT described above, and may be positioned on the same layer as the semiconductor layer AT.

[0225] The second connection line CNL2 may be connected to the third resistance layer RL3 through an eighth contact hole H8 defined in the first insulating layer INS1. The second electrode E2 may be connected to the third resistance layer RL3 through a ninth contact hole H9 defined in the first, second and third insulating layers INS1, INS2 and INS3.

[0226] Reference Fig.10 and Fig.23 , static electricity may be applied to the connection pad CPD. When static electricity flows into the first test element TS1 through the connection pad CPD, the third resistance layer RL3 may prevent or reduce static electricity. Therefore, damage to the first test element TS1 may be prevented or reduced.

[0227] Reference Fig.23 , the third resistance layer RL3 may be used together with the first resistance layer RL1 and the second resistance layer RL2. However, not limited thereto, the third resistance layer RL3 may be used together with the first resistance layer RL1-1 or the second resistance layer RL2-1.

[0228] Fig.25 is a view showing a configuration of a fourth resistance layer according to some embodiments of the present disclosure. Fig.26 is along Fig.25A cross-sectional view taken along line V-V' shown in FIG.

[0229] Fig.25 is with Fig.10 The following description will focus on Fig.10 The components shown in the figure are different components.

[0230] Reference Fig.25 , the test panel TPN may further include a plurality of fourth resistance layers RL4. The second connection lines CNL2 may be spaced apart from the connection pads CPD, respectively. The fourth resistance layer RL4 may connect the connection pads CPD and the second connection lines CNL2 spaced apart from each other.

[0231] The fourth resistance layer RL4 may be connected to the connection pad CPD and the second connection line CNL2 through the connection electrode CE-1. The fourth resistance layer RL4 may be connected to the second connection line CNL2 and the connection electrode CE-1 through the tenth contact hole H10 and the eleventh contact hole H11.

[0232] The connection lines CNL may extend from the connection pads CPD. Ends of the connection lines CNL may define the connection pads CPD, respectively.

[0233] Reference Fig.26 , the fourth resistance layer RL4 may be positioned on the buffer layer BFL, and the second connection line CNL2 may be positioned on the first insulating layer INS1. The fourth resistance layer RL4 may include the same material as that of the semiconductor layer AT described above, and may be positioned on the same layer as the semiconductor layer AT. The connection electrode CE-1 may be positioned on the third insulating layer INS3, and the connection pad CPD and the connection line CNL may be positioned on the fourth insulating layer INS4.

[0234] The second connection line CNL2 may be connected to the fourth resistance layer RL4 through a tenth contact hole H10 defined in the first insulating layer INS1. The connection electrode CE-1 may be connected to the fourth resistance layer RL4 through an eleventh contact hole H11 defined in the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The connection pad CPD may be connected to the connection electrode CE-1 through a seventh contact hole H7 defined in the fourth insulating layer INS4.

[0235] When static electricity flows into the first test element TS1 through the connection pad CPD, the fourth resistance layer RL4 may prevent or reduce static electricity, and thus, may prevent or reduce damage to the first test element TS1.

[0236] The fourth resistance layer RL4 may be used together with the first resistance layer RL1 and the second resistance layer RL2. However, not limited thereto, the fourth resistance layer RL4 may be used together with the third resistance layer RL3 and the first resistance layer RL1 and the second resistance layer RL2. Alternatively, the fourth resistance layer RL4 may be used together with the first resistance layer RL1-1 or the second resistance layer RL2-1.

[0237] Fig. 27 is a view showing a configuration of connection lines according to some embodiments of the present disclosure. Fig.28 is along Fig. 27 A cross-sectional view taken along line VI-VI' shown in FIG. Fig.29 is along Fig. 27 A cross-sectional view taken along line VII-VII' shown in FIG.

[0238] Fig. 27 The connection line CNL shown in Figure 1 The connection line CNL shown in FIG.

[0239] Reference Fig. 27 Among the connection lines CNL, each of the odd-numbered connection lines CNL-1 may include a third connection line CNL3-1 and a fourth connection line CNL4. Among the connection lines CNL, each of the even-numbered connection lines CNL-2 may include a third connection line CNL3-2 and a fourth connection line CNL4.

[0240] The third connection lines CNL3 - 1 and CNL3 - 2 may extend toward the display area DA, and may be connected to the pixels PX through the data lines DL1 to DLn. The fourth connection lines CNL4 may extend from the connection pads CPD, respectively.

[0241] The fourth connection line CNL4 may be connected to the third connection lines CNL3-1 and CNL3-2, respectively. For example, the fourth connection line CNL4 may be connected to the third connection lines CNL3-1 and CNL3-2 through the connection electrode CE-2. The connection electrode CE-2 may be connected to the third connection lines CNL3-1 and CNL3-2 through the twelfth contact hole H12 and the thirteenth contact hole H13. The connection electrode CE-2 may be connected to the fourth connection line CNL4 through the fourteenth contact hole H14.

[0242] Hereinafter, for convenience of description, the configuration of one odd-numbered connection line CNL- 1 and one even-numbered connection line CNL- 2 will be mainly described.

[0243] The third connection line CNL3-1 of the odd-numbered connection lines CNL-1 may extend toward the corresponding connection pad CPD and may be connected to the corresponding second connection line CNL2. Substantially, the third connection line CNL3-1 may be integrally formed with the corresponding second connection line CNL2.

[0244] The third connection line CNL3-2 of the even-numbered connection lines CNL-2 may extend toward the corresponding connection pad CPD and may be connected to the corresponding second connection line CNL2. The third connection line CNL3-2 may be connected to the corresponding second connection line CNL2 through the fifteenth contact hole H15 and may be connected to the corresponding connection electrode CE-1 through the sixteenth contact hole H16.

[0245] Reference Fig.28 , the third connection line CNL3-1 may be positioned on the first insulating layer INS1. The third connection line CNL3-1 may be positioned at the same layer as the gate electrode GE described above. Therefore, the third connection line CNL3-1 may also be positioned at the same layer as the second connection line CNL2. The third connection line CNL3-1 may extend under the fourth connection line CNL4 and may be connected to the second connection line CNL2. For example, on the first insulating layer INS1, the third connection line CNL3-1 may be formed integrally with the second connection line CNL2.

[0246] The connection electrodes CE-1 and CE-2 may be positioned on the third insulating layer INS3, and the connection pad CPD and the fourth connection line CNL4 may be positioned on the fourth insulating layer INS4. The connection electrode CE-2 may be connected to the third connection line CNL3-1 through a twelfth contact hole H12 defined in the second insulating layer INS2 and the third insulating layer INS3. The fourth connection line CNL4 may be connected to the connection electrode CE-2 through a fourteenth contact hole H14 defined in the fourth insulating layer INS4.

[0247] Reference Fig.29 , the third connection line CNL3-2 may be positioned on the second insulating layer INS2. The third connection line CNL3-2 may include Figure 4 The dummy electrode DME shown in FIG. 1 may be made of the same material and may be positioned at the same layer as the dummy electrode DME. Therefore, the third connection line CNL3 - 2 may be positioned at a layer between the gate electrode GE and the second electrode E2 .

[0248] The third connection line CNL3-2 may extend under the fourth connection line CNL4 and may be connected to the second connection line CNL2. For example, the third connection line CNL3-2 may be connected to the second connection line CNL2 through a fifteenth contact hole H15 defined in the second insulating layer INS2.

[0249] The connection electrodes CE-1 and CE-2 may be positioned on the third insulating layer INS3, and the connection pad CPD and the fourth connection line CNL4 may be positioned on the fourth insulating layer INS4. The connection electrode CE-2 may be connected to the third connection line CNL3-2 through a thirteenth contact hole H13 defined in the third insulating layer INS3. The connection electrode CE-1 may be connected to the third connection line CNL3-2 through a sixteenth contact hole H16 defined in the third insulating layer INS3.

[0250] The third connection lines CNL3 - 1 and CNL3 - 2 may be used together with the first resistance layer RL1 , the second resistance layer RL2 , the first resistance layer RL1 - 1 , the second resistance layer RL2 - 1 , the third resistance layer RL3 , or the fourth resistance layer RL4 described above.

[0251] Fig.30 and Fig.31 is shown with Fig.28 and Fig.29 The configuration of the third connecting line shown in FIG. 5 is a view of a third connecting line with different configurations.

[0252] Fig.30 and Fig.31 is with Fig.28 and Fig.29 The corresponding cross-section diagram.

[0253] Reference Fig.30 and Fig.31 , the third connection lines CNL3-1' and CNL3-2' may be separated from the second connection line CNL2 and may not be connected to the second connection line CNL2. The third connection lines CNL3-1' and CNL3-2' may not extend under the fourth connection line CNL4.

[0254] Reference Fig.28 and Fig.29 When static electricity is applied to the connection pad CPD, the static electricity may be distributed to both the third connection lines CNL3-1 and CNL3-2 and the second connection line CNL2 relative to the connection pad CPD. Therefore, the strength of the static electricity applied to the first test element TS1 may be weakened, and thus damage to the first test element TS1 may be prevented or reduced.

[0255] Fig.32 shows that when static electricity is applied to Fig.28 and Fig.29 The connection pads in the test panel of the third connection line shown in FIG. 1 are test results of the electric field formed on the semiconductor layer of the first test element.

[0256] Reference Fig.32 , when using the third connection lines CNL3-1 and CNL3-2, Fig.30 and Fig.31Compared with the third connection lines CNL3 - 1 ′ and CNL3 - 2 ′ shown in FIG. 8 , the intensity of the electric field may be reduced.

[0257] Fig.33 It shows that the Figure 1 A view of the display panel in the second section.

[0258] Reference Fig.25 and Fig.33 When the first resistance layer RL1, the second resistance layer RL2, the first resistance layer RL1-1, the second resistance layer RL2-1, the third resistance layer RL3 or the fourth resistance layer RL4 is positioned in the test panel TPN, the second portion PT2 may be removed, and in this case, the fourth resistance layer RL4 may remain in the first portion PT1. Therefore, the display panel DP may include the fourth resistance layer RL4.

[0259] A connection pad CPD defined at one end of the connection line CNL may be spaced apart from the second test unit TSP2. The fourth resistance layer RL4 may be connected to the connection pad CPD.

[0260] Fig.34 It is shown that Fig.33 FIG. 1 is a view of a cross-sectional configuration of a display device including a display panel shown in FIG.

[0261] exist Fig.34 , a cross section of the display device DD viewed in the first direction DR1 is shown.

[0262] Reference Fig.34 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2. The display device DD may include the fourth resistance layer RL4 described above.

[0263] The input sensing unit ISP may be positioned on the display panel DP. The input sensing unit ISP may include a plurality of sensing units of a capacitive type for sensing external input. When manufacturing the display device DD, the input sensing unit ISP may be directly manufactured on the display panel DP. However, not limited thereto, the input sensing unit ISP may be manufactured as a panel separated from the display panel DP and may be attached to the display panel DP through an adhesive layer.

[0264] The anti-reflection layer RPL may be positioned on the input sensing unit ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP. However, not limited thereto, the anti-reflection layer RPL may be manufactured as a separate panel and may be attached to the input sensing unit ISP through an adhesive layer.

[0265] The anti-reflection layer RPL may be defined as a film for preventing or reducing reflection of external light. The anti-reflection layer RPL may reduce reflectivity of external light incident from above the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be visible to the user.

[0266] When external light traveling toward the display panel DP is reflected from the display panel DP and provided back to the user, the user can visually recognize the external light as in a mirror. To prevent or reduce this phenomenon, the anti-reflection layer RPL may include a plurality of color filters displaying the same color as the color of the pixels of the display panel DP.

[0267] The color filter may filter the external light into the same color as the color of the pixel. In this case, the external light may not be visible to the user. However, not limited thereto, the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0268] The window WIN may be positioned on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0269] The panel protection film PPF may be positioned under the display panel DP. The panel protection film PPF may protect a lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0270] The first adhesive layer AL1 may be positioned between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be positioned between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0271] According to some embodiments of the present disclosure, a resistance layer formed of a semiconductor layer may be positioned adjacent to the first test element, the test pad, and the connection pad to prevent or reduce static electricity, thereby preventing or reducing damage to the test element.

[0272] Although aspects of some embodiments of the present disclosure have been described with reference to some embodiments of the present disclosure, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the embodiments according to the present disclosure and their equivalents as set forth in the appended claims.

Claims

1. A test panel, comprising: Pixels; a first test element, the first test element being connected to the pixel, the first test element comprising a gate electrode, a semiconductor layer, a first electrode, and a second electrode connected to the pixel; a test pad, the test pad being spaced apart from the first test element; a first connection line connected to the first test element and the test pad; as well as A first resistance layer is located at the same layer as the semiconductor layer, and the first resistance layer connects the first electrode and the first connection line which are spaced apart from each other.

2. The test panel according to claim 1, further comprising: A second resistance layer is located at the same layer as the semiconductor layer and connects the first connection line and the test pad which are spaced apart from each other.

3. The test panel according to claim 2, wherein: The first resistance layer and the second resistance layer include the same material as that of the semiconductor layer.

4. The test panel according to claim 2, wherein: The first resistance layer and the second resistance layer have the same length in respective extending directions of the first resistance layer and the second resistance layer.

5. The test panel according to claim 2, wherein: The first resistance layer and the second resistance layer have different lengths in respective extending directions of the first resistance layer and the second resistance layer.

6. The test panel according to claim 2, wherein: The semiconductor layer and the first and second resistance layers are located at a layer below the gate electrode, the first and second electrodes are located at a layer above the gate electrode, and the first connection line is located at the same layer as each of the first and second electrodes.

7. The test panel according to claim 2, wherein: The first resistance layer is connected to a portion of the first electrode adjacent to one side of the first electrode and a portion of the first connection line adjacent to one side of the first connection line, and the one side of the first electrode and the one side of the first connection line face each other, and wherein the second resistance layer is connected to a portion of the first connection line adjacent to the opposite side of the first connection line and a portion of the test pad adjacent to one side of the test pad, and the opposite side of the first connection line and the one side of the test pad face each other.

8. The test panel according to claim 2, wherein: The test pad, the first resistance layer, and the second resistance layer extend in a first direction, and in the first direction, a length of each of the first resistance layer and the second resistance layer is set to 1 / 4 to 1 / 3 of a length of the test pad.

9. The test panel according to claim 2, wherein: The test pad and the first resistance layer extend in a first direction, and in the first direction, a length of the first resistance layer is set to 1 / 3 to 2 / 3 of a length of the test pad.

10. The test panel according to claim 2, wherein: The test pad and the second resistance layer extend in a first direction, and in the first direction, a length of the second resistance layer is set to 1 / 3 to 2 / 3 of a length of the test pad.

11. The test panel of claim 2, further comprising: An anti-static circuit is connected to the first connection line, and the anti-static circuit includes a plurality of diodes.

12. The test panel according to claim 11, wherein: The anti-static circuit is adjacent to the test pad.

13. The test panel according to claim 11, wherein: The first connecting line comprises: a first extending portion extending from the test pad in a first direction which is an extending direction of the test pad; and a second extension portion extending toward the first test element to form an obtuse angle with the first extension portion, and The antistatic circuit is connected to the first extension portion and is adjacent to the second extension portion.

14. The test panel according to claim 11, wherein: The antistatic circuit is adjacent to the second resistance layer.

15. The test panel of claim 1, further comprising: a connection pad spaced apart from the second electrode and connected to the pixel; a second connection line connected to the second electrode and the connection pad; as well as A third resistance layer is located at the same layer as the semiconductor layer, and the third resistance layer connects the second electrode and the second connection line which are spaced apart from each other.

16. The test panel of claim 15, further comprising: A fourth resistance layer is located at the same layer as the semiconductor layer and connects the connection pad and the second connection line which are spaced apart from each other.

17. The test panel of claim 15, wherein: The second connection line is located at the same layer as the gate electrode, and the connection pad is located at a layer above the second electrode.

18. The test panel of claim 15, further comprising: a second test element; a third connecting line connected to the second test element and the pixel; as well as a fourth connection line extending from the connection pad and connected to the third connection line, The third connection line extends below the fourth connection line and is connected to the second connection line.

19. The test panel according to claim 18, wherein: The third connection line is located at the same layer as the second connection line, and the third connection line is formed integrally with the second connection line.

20. The test panel of claim 18, wherein: The third connection line is located at a layer between the gate electrode and the second electrode, and the third connection line is connected to the second connection line.

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