Display panel and display device

Abstract

The display panel and the display device belong to the technical field of display. The display panel comprises at least one first pixel driving circuit; the first pixel driving circuit comprises a second transistor, a third transistor, a fourth transistor and a storage capacitor; the second electrode of the second transistor is electrically connected with the gate electrode of the third transistor and the first electrode of the storage capacitor; the fourth transistor is used for writing a data voltage to the storage capacitor; the third transistor is used for controlling the size of the output driving current according to the voltage on the gate electrode of the third transistor; the display panel is provided with a first scan signal wire for electrical connection with the gate electrode of the fourth transistor; the gate electrode of the fourth transistor and the first scan signal wire are located in different film layers; the gate electrode of the fourth transistor has a first coupling structure, and the second electrode of the second transistor has a second coupling structure; the first coupling structure and the second coupling structure are arranged in an overlapping manner. The display panel can reduce the risk that the black state voltage exceeds the driving capability of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the application of OLED (Organic Light Emitting Diode) technology in large-screen products such as foldable phones, laptops, and automotive displays, the use of large-size OLED displays is becoming increasingly widespread. The increase in OLED display size leads to longer signal traces, resulting in a greater load on the signal traces and a greater impact on display quality.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device that reduces the risk of black state voltage exceeding the chip driving capability.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising a substrate, a driving layer, and a pixel layer stacked sequentially; the driving layer has a pixel driving circuit for driving sub-pixels;

[0006] The pixel driving circuit includes a second transistor, a third transistor, a fourth transistor, and a storage capacitor; the second electrode of the second transistor is electrically connected to the gate of the third transistor and the first electrode of the storage capacitor; the fourth transistor is used to write data voltage to the storage capacitor; the third transistor is used to control the magnitude of the output driving current according to the voltage on the gate of the third transistor; the display panel is provided with a first scan signal trace for electrical connection with the gate of the fourth transistor; the gate of the fourth transistor and the first scan signal trace are located in different film layers;

[0007] The pixel driving circuit includes at least a first pixel driving circuit; in the first pixel driving circuit, the gate of the fourth transistor has a first coupling structure, and the second electrode of the second transistor has a second coupling structure; the orthographic projection of the first coupling structure on the substrate and the orthographic projection of the second coupling structure on the substrate at least partially overlap.

[0008] According to one embodiment of the present disclosure, in the first pixel driving circuit, the width of the second coupling structure is greater than the width of the channel region of the second transistor; the extension direction of the first coupling structure is parallel to the length direction of the second coupling structure.

[0009] According to one embodiment of the present disclosure, in the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; in the column direction, the orthographic projection of the second coupling structure on the substrate does not exceed the orthographic projection of the first coupling structure on the substrate, or the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

[0010] According to one embodiment of the present disclosure, in the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; along the row direction, both ends of the first coupling structure extend beyond the second coupling structure; along the column direction, the orthogonal projection of the first coupling structure on the substrate does not exceed the orthogonal projection of the second coupling structure on the substrate.

[0011] According to one embodiment of the present disclosure, in the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, and the first coupling structure connected in sequence; the second metal portion is connected to the first scan signal trace through a via.

[0012] The width of the first coupling structure is smaller than the width of the first metal part.

[0013] According to one embodiment of the present disclosure, in the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure and the first connection portion; the first connection portion extends along the column direction, one end of the first connection portion is connected to one end of the second coupling structure away from the channel region of the fourth transistor, and the other end of the first connection portion is electrically connected to the channel region of the second transistor.

[0014] According to one embodiment of the present disclosure, in the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; along the row direction, one end of the first coupling structure does not extend beyond the second coupling structure.

[0015] The gate of the fourth transistor includes a first metal portion, a second metal portion, and a first coupling structure connected in sequence; the second metal portion is connected to the first scan signal trace via a via; the width of the first coupling structure is greater than the width of the first metal portion; the width of the second coupling structure is greater than the width of the channel region of the second transistor.

[0016] According to one embodiment of the present disclosure, in the first pixel driving circuit, the second electrode of the second transistor includes a second coupling structure, a second connection portion, and a first connection portion connected in sequence; the second connection portion extends along the row direction, and the first connection portion extends along the column direction; the width of the second connection portion and the first connection portion is smaller than the width of the second coupling structure.

[0017] According to one embodiment of this disclosure, in the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, a third metal portion and a first coupling structure connected in sequence, the second metal portion being connected to the first scan signal trace via a via; the gate of the fourth transistor extends along the row direction, and the dimension of the first coupling structure in the column direction is larger than the dimension of the third metal portion in the column direction;

[0018] The second electrode of the second transistor includes a second coupling structure, a first connection portion, and a second connection portion connected in sequence; the first connection portion extends along the row direction, and the second connection portion extends along the column direction; the dimension of the second coupling structure in the column direction is larger than the dimension of the second connection portion in the column direction.

[0019] According to one embodiment of this disclosure, the third transistor and the fourth transistor are P-type thin-film transistors.

[0020] According to one embodiment of this disclosure, the pixel layer has a variety of sub-pixels of different colors; the pixel driving circuit for driving the sub-pixel with the highest luminous efficiency is the first pixel driving circuit.

[0021] According to one embodiment of this disclosure, each pixel driving circuit is the first pixel driving circuit.

[0022] According to one embodiment of this disclosure, the pixel layer has a variety of sub-pixels of different colors, the sub-pixels including a first sub-pixel and a second sub-pixel, wherein the luminous efficiency of the first sub-pixel is greater than that of the second sub-pixel;

[0023] The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the first pixel driving circuit.

[0024] In the first pixel driving circuit that drives the first sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is the first area; in the first pixel driving circuit that drives the second sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is the second area; the first area is greater than the second area.

[0025] According to one embodiment of this disclosure, the pixel layer has a variety of sub-pixels of different colors, the sub-pixels including a first sub-pixel and a second sub-pixel, wherein the luminous efficiency of the first sub-pixel is greater than that of the second sub-pixel;

[0026] The pixel driving circuit includes a second pixel driving circuit, wherein the gate of the fourth transistor of the second pixel driving circuit does not overlap with the second electrode of the second transistor;

[0027] The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the second pixel driving circuit.

[0028] According to another aspect of this disclosure, a display device is provided, including the display panel described above, and a drive module including a drive module for driving the display panel.

[0029] According to one embodiment of this disclosure, the driving module is configured to provide a driving power supply voltage to the display panel, the driving power supply voltage being applied to the pixel driving circuit to drive the pixel driving circuit; the voltage of the driving power supply voltage is not less than 4.0V.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0032] Figure 1 This is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0033] Figure 2 This is a schematic diagram of the film layer structure of a display panel in one embodiment of the present disclosure.

[0034] Figure 3 This is a schematic diagram of a portion of the structure of the display panel near the first node, as shown in the first embodiment of this disclosure.

[0035] Figure 4 This is a schematic diagram of the stacked structure between the gate of the fourth transistor and the second electrode of the second transistor in the first embodiment of this disclosure.

[0036] Figure 5This is a schematic diagram of a portion of the structure of the display panel near the first node, as shown in the second embodiment of this disclosure.

[0037] Figure 6 This is a schematic diagram of the stacked structure between the gate of the fourth transistor and the second electrode of the second transistor in a second embodiment of the present disclosure.

[0038] Figure 7 This is a schematic diagram of a portion of the structure of the display panel near the first node, as shown in the third embodiment of this disclosure.

[0039] Figure 8 This is a schematic diagram of the stacked structure between the gate of the fourth transistor and the second electrode of the second transistor in the third embodiment of this disclosure.

[0040] Figure 9 This is a schematic diagram of the gate structure of the fourth transistor in the third embodiment of this disclosure.

[0041] Figure 10 This is a schematic diagram of the active layer of the second transistor in the third embodiment of this disclosure.

[0042] Figure 11 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0043] Figure 12 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0044] Figure 13 This is a partial structural schematic diagram of the first source / drain metal layer in the first layout example of this disclosure.

[0045] Figure 14 This is a partial structural schematic diagram of the first semiconductor layer in a first layout example of this disclosure.

[0046] Figure 15 This is a schematic diagram of a partial structural stacking of the first semiconductor layer and the first source / drain metal layer in the first layout example of this disclosure.

[0047] Figure 16 This is a partial structural schematic diagram of the first gate layer in a first layout example of this disclosure.

[0048] Figure 17 This is a schematic diagram of a partial structural stacking of the first semiconductor layer and the first gate layer in the first layout example of this disclosure.

[0049] Figure 18 This is a schematic diagram of a partial structural stacking of the first gate layer and the first source / drain metal layer in the first layout example of this disclosure.

[0050] Figure 19 This is a partial structural diagram of the second gate layer in a first layout example of this disclosure.

[0051] Figure 20 This is a schematic diagram of a partial structural stacking of the second gate layer and the first source / drain metal layer in the first layout example of this disclosure.

[0052] Figure 21 This is a partial structural diagram of the second semiconductor layer in a first layout example of this disclosure.

[0053] Figure 22 This is a schematic diagram of a partial structural stacking of the second gate layer and the second semiconductor layer in a first layout example of this disclosure.

[0054] Figure 23 This is a schematic diagram of a partial structural stacking of the second semiconductor layer and the first source / drain metal layer in the first layout example of this disclosure.

[0055] Figure 24 This is a partial structural diagram of the third gate layer in the first layout example of this disclosure.

[0056] Figure 25 This is a schematic diagram of a partial structural stacking of the second semiconductor layer and the third gate layer in the first layout example of this disclosure.

[0057] Figure 26 This is a schematic diagram of a partial structural stacking of the third gate layer and the first source / drain metal layer in the first layout example of this disclosure.

[0058] Figure 27 This is a partial structural diagram of the second source / drain metal layer in the first layout example of this disclosure.

[0059] Figure 28 This is a schematic diagram of the partial structural stacking of the first source / drain metal layer and the second source / drain metal layer in the first layout example of this disclosure.

[0060] Figure 29 This is a partial structural diagram of the third source / drain metal layer in the first layout example of this disclosure.

[0061] Figure 30 This is a schematic diagram of the partial structural stacking of the second source / drain metal layer and the third source / drain metal layer in the first layout example of this disclosure.

[0062] Figure 31 This is a partial structural diagram of the first source / drain metal layer in a second layout example of this disclosure.

[0063] Figure 32 This is a partial structural diagram of the second source / drain metal layer in a second layout example of this disclosure.

[0064] Figure 33 This is a schematic diagram of the partial structural stacking of the first source / drain metal layer and the second source / drain metal layer in a second layout example of this disclosure. Detailed Implementation

[0065] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0066] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0067] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0068] In this disclosure, structural layer A is located on the side of structural layer B facing away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B facing away from the substrate. When structural layer B is a patterned structure, a portion of structural layer A may also be located at the same physical height as or below the physical height of structural layer B, wherein the substrate serves as the height reference.

[0069] In this disclosure, when describing the overlapping arrangement of structures C and D, it means that structures C and D are located in different film layers, but the orthographic projections of structures C and D on the substrate at least partially overlap.

[0070] In this disclosure, a transistor refers to a device that includes at least three electrodes: a gate, a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the area through which current primarily flows. In embodiments of this disclosure, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be interchanged. In embodiments of this disclosure, for any given transistor, one of the "source" and "drain" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0071] For large-size display panels, changes in signal load have a significant impact on display performance. Figure 1 Taking the pixel driving circuit example, the first scan signal trace GPL used to load the first scan signal Gate_P can control the data voltage Vdata to be written to the first node N1. However, the first scan signal trace GPL or the gate T4G of the fourth transistor T4 itself will be coupled to the structure of the first node N1 (e.g., the second terminal T2D of the second transistor T2), and this coupling will affect the voltage written to the first node N1. As follows, Figure 1 Taking the example pixel driving circuit, the influence of the coupling between the first scan signal trace GPL or the gate T4G of the fourth transistor T4 and the first node N1 is illustrated. It is understood that this influence is not limited to... Figure 1 The example pixel driving circuit.

[0072] exist Figure 1In the illustrated pixel driving circuit, the pixel driving circuit includes a first transistor T1 (as a gate reset transistor for resetting the gate of the driving transistor), a second transistor T2 (as a threshold compensation transistor for compensating the threshold voltage of the driving transistor), a third transistor T3 (as a driving transistor), a fourth transistor T4 (as a data write transistor for writing data voltage to the pixel driving circuit), a fifth transistor T5 (as a first light-emitting control transistor), a sixth transistor T6 (as a second light-emitting control transistor), a seventh transistor T7 (as an electrode reset transistor for resetting the pixel electrode), and an eighth transistor T8 (as a source reset transistor for resetting the source of the driving transistor). The second transistor T2 is an N-type thin-film transistor, such as a metal-oxide-semiconductor thin-film transistor. The third transistor T3 and the fourth transistor T4 are P-type transistors, such as P-type low-temperature polycrystalline silicon thin-film transistors. Specifically, the second electrode T2D of the second transistor T2, the first electrode CP1 of the storage capacitor, and the gate of the third transistor T3 (which can be reused as the first electrode CP1 of the storage capacitor) are electrically connected to the first node N1; the second electrodes of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the first electrode of the third transistor T3 are electrically connected to the second node N2; the second electrode of the third transistor T3, the first electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the sixth transistor T6 are electrically connected to the third node N3; the second electrodes of the sixth transistor T6 and the seventh transistor T7 are electrically connected to the fourth node N4 and to the light-emitting element; the first electrode of the fifth transistor T5 and the second electrode CP2 of the storage capacitor are electrically connected to the driving power supply voltage terminal (used to load the driving power supply voltage VDD); the first electrode of the fourth transistor T4 is electrically connected to the data voltage terminal (used to load the data voltage Vdata); the first electrode of the eighth transistor T8 is electrically connected to the third initialization terminal... The first transistor T1 is electrically connected to the first initialization voltage terminal (Vinit3) and the first initialization voltage terminal (Vinit1). The first terminal of the seventh transistor T7 is electrically connected to the second initialization voltage terminal (Vinit2). The gate of the first transistor T1 is electrically connected to the first reset signal terminal (Reset_P). The gate of the second transistor T2 is electrically connected to the second scan signal terminal (Gate_N). The gate of the fourth transistor T4 is electrically connected to the first scan signal terminal (Gate_P). The gates of the fifth transistor T5 and the sixth transistor T6 are both electrically connected to the light emission control signal terminal (EM). The gates of the seventh transistor T7 and the eighth transistor T8 are both electrically connected to the second reset signal terminal (Reset_H).

[0073] In this example, during the data writing phase, the first scan signal terminal is loaded with a low level to turn on the fourth transistor T4, and the second scan signal terminal is loaded with a high level to turn on the second transistor T2. This causes the data voltage Vdata on the data voltage terminal to be written to the first node N1. After the data writing phase, the first scan signal terminal goes high to turn off the fourth transistor T4, and the second scan signal terminal is loaded with a low level to turn off the second transistor T2. In related technologies, the driving power supply voltage VDD used in the pixel driving circuit is approximately 2.8V. At this voltage, the black-state voltage required by the pixel driving circuit is also relatively low, within the chip's output capability. Therefore, it is necessary to minimize the coupling between the first scan signal terminal and the first node N1 to prevent the voltage of the first node N1 from being pulled up through coupling when the voltage of the first scan signal terminal rises.

[0074] The inventors discovered that when the pixel driving circuit uses a higher driving power supply voltage VDD, such as 4.6V, the black-state voltage of the pixel driving circuit also increases significantly, potentially exceeding the output capability of the chip (e.g., the source driver chip). The black-state voltage of the pixel driving circuit is the voltage applied to the data voltage terminal to ensure that the third transistor T3 is completely turned off.

[0075] Based on this, embodiments of the present disclosure provide a display device and a display panel PNL of the display device. At least a portion of the pixel driving circuit of the display panel PNL is an improved pixel driving circuit. In this improved pixel driving circuit, the coupling capacitance between the first scan signal terminal and the first node N1 is increased to raise the voltage of the first node N1 by means of the coupling effect between the first scan signal terminal and the first node N1, thereby reducing the black state voltage value required by the pixel driving circuit. The display device also includes a driving module for driving the display panel. The driving module is configured to provide a driving power supply voltage VDD to the display panel PNL, and the driving power supply voltage VDD is used to apply to the pixel driving circuit to drive the pixel driving circuit. Because at least a portion of the pixel driving circuit in the PNL provided by the present disclosure is an improved pixel driving circuit, the risk of the black state voltage exceeding the output capability of the driving chip is less likely to occur even under high driving power supply voltages.

[0076] See Figure 2 The display panel PNL includes a substrate SBT, a driving layer DRL, and a pixel layer PXL stacked sequentially; the driving layer DRL has pixel driving circuitry for driving sub-pixels PX. Figure 2In the example, a light-emitting element LD, serving as a sub-pixel PX, is disposed in the pixel layer PXL, and the output terminal of the pixel driving circuit is electrically connected to the light-emitting element LD. In this embodiment of the disclosure, the pixel driving circuit can be... Figure 1 The pixel driving circuit shown is not limited to this one. Figure 1 Examples.

[0077] See Figure 1 and Figures 3 to 10 The pixel driving circuit includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a storage capacitor CST. The second electrode T2D of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first electrode CP1 of the storage capacitor. The fourth transistor T4 is used to write a data voltage Vdata to the storage capacitor CST. The third transistor T3 is used to control the magnitude of the output driving current based on the voltage on its gate. The display panel PNL is provided with a first scan signal trace GPL for electrical connection to the gate T4G of the fourth transistor T4 (e.g., the gate T4G of the fourth transistor T4 and the first scan signal trace GPL are electrically connected through a via); the gate T4G of the fourth transistor T4 and the first scan signal trace GPL are located on different film layers. The pixel driving circuit includes at least a first pixel driving circuit PDC1 (i.e., an improved pixel driving circuit); in the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 has a first coupling structure CA, and the second terminal T2D of the second transistor T2 has a second coupling structure CB; the orthographic projection of the first coupling structure CA on the substrate SBT and the orthographic projection of the second coupling structure CB on the substrate SBT at least partially coincide.

[0078] In other words, in this embodiment of the present disclosure, a first pixel driving circuit PDC1 is provided on the display panel PNL. The gate T4G of the fourth transistor T4 of the first pixel driving circuit PDC1 overlaps with the second electrode T2D of the second transistor T2, so that the first scan signal terminal and the first node N1 have a large coupling capacitance. This reduces the black state voltage of the first pixel driving circuit PDC1 by utilizing the coupling effect between the first scan signal terminal and the first node N1. Specifically, after applying a low level to the first scan signal terminal to write the data voltage Vdata to the pixel driving circuit, a high level is applied to the first scan signal terminal to turn off the fourth transistor T4. During the level increase at the first scan signal terminal, the voltage of the first node N1 can be raised through the coupling effect. Thus, when writing the black state voltage to the pixel driving circuit, a lower black state voltage can be written. In some embodiments of the present disclosure, all pixel driving circuits are the first pixel driving circuit PDC1, that is, all adopt the design of overlapping the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2. In some other implementations, only a portion of the pixel driving circuit can be the first pixel driving circuit PDC1, meaning that the gate T4G of the fourth transistor T4 of the other portion of the pixel driving circuit does not overlap with the second electrode T2D of the second transistor T2.

[0079] In one embodiment of this disclosure, see Figure 4 , Figure 6 and Figure 10 The active layer of the second transistor T2 includes the first electrode of the second transistor T2, the channel region T2A of the second transistor T2, and the second electrode T2D of the second transistor T2 connected in sequence. The channel region T2A of the second transistor can maintain semiconductor characteristics, while the first electrode and the second electrode T2D of the second transistor T2 can be made conductive. The width of the second coupling structure CB of the second electrode T2D of the second transistor T2 can be greater than the width of the channel region T2A of the second transistor T2. This is beneficial in increasing the coupling capacitance between the second coupling structure CB and the first coupling structure CA, and also in preventing excessive coupling between the second scan signal terminal and the first node N1. It is understood that after the data writing stage, the second scan signal terminal needs to be pulled down to turn off the second transistor T2. If the coupling between the second scan signal terminal and the first node N1 increases, the voltage pull-down of the second scan signal terminal will pull down the voltage of the first node N1, which will cause the black state voltage of the pixel driving circuit to increase, thus exacerbating the risk of the black state voltage exceeding the chip's driving capability.

[0080] In one embodiment of this disclosure, the extension direction of the first coupling structure CA is parallel to the length direction of the second coupling structure CB. For example, the extension direction of the first coupling structure CA and the length direction of the second coupling structure CB are both row directions DH. In this example, the length direction of the second coupling structure CB refers to the extension direction of the active layer of the second transistor T2, which is perpendicular to the width direction of the active layer of the second transistor T2. Figures 3 to 10 In the example, the length direction of the second coupling structure CB is the row direction DH, and the length direction of the channel region T2A of the second transistor is the column direction DV.

[0081] In one embodiment of this disclosure, see Figure 4 and Figure 6 In the first pixel driving circuit PDC1, the extension direction of the first coupling structure CA is parallel to the length direction of the second coupling structure CB. This increases the overlap area between the first coupling structure CA and the second coupling structure CB, thereby improving the coupling capacitance between the first scan signal terminal and the first node N1.

[0082] Optionally, the extension direction of the first coupling structure CA is parallel to the extension direction of the second coupling structure CB, for example, both extending along the row direction DH. Further, the midline of the extension of the first coupling structure CA coincides with the midline of the extension of the second coupling structure CB. In this way, while maximizing the overlap area between the first coupling structure CA and the second coupling structure CB, the second coupling structure CB can be used to shield the first coupling structure CA to minimize the coupling between the first coupling structure CA and other structures, thereby reducing the load on the first scan signal trace GPL.

[0083] In another example, see Figure 4 In the column direction DV, the orthographic projection of the first coupling structure CA onto the substrate SBT does not exceed the orthographic projection of the second coupling structure CB onto the substrate SBT. Specifically, in the column direction DV, the orthographic projection of the first coupling structure CA onto the substrate SBT lies within the orthographic projection of the second coupling structure CB onto the substrate SBT. This ensures the stability of the overlap area between the first coupling structure CA and the second coupling structure CB, avoids changes in the coupling capacitance caused by changes in the relative positions of the first coupling structure CA and the second coupling structure CB, thereby ensuring the stability of the coupling capacitance between the first scan signal terminal and the first node N1, and improving the uniformity of each first pixel driving circuit PDC1.

[0084] In one example, see Figure 6In the column direction DV, the orthographic projection of the second coupling structure CB onto the substrate SBT does not exceed the orthographic projection of the first coupling structure CA onto the substrate SBT. Specifically, in the column direction DV, the orthographic projection of the second coupling structure CB onto the substrate SBT lies within the orthographic projection of the first coupling structure CA onto the substrate SBT. This ensures the stability of the overlap area between the first coupling structure CA and the second coupling structure CB, avoiding changes in the coupling capacitance caused by changes in the relative positions of the first coupling structure CA and the second coupling structure CB. This, in turn, ensures the stability of the coupling capacitance between the first scan signal terminal and the first node N1, improving the uniformity of each first pixel driving circuit PDC1.

[0085] In one embodiment of this disclosure, the display panel PNL is provided with a first conductive structure MA1 corresponding to a pixel driving circuit. The first conductive structure MA1 is electrically connected to the second electrode T2D of the second transistor T2 and the first electrode CP1 of the storage capacitor via vias. The second coupling structure CB of the second electrode T2D of the second transistor T2 may have a via region, which overlaps with the first conductive structure MA1 via the via. In this embodiment, the second coupling structure CB needs to have a large width to ensure a large contact area with the first conductive structure MA1, thereby reducing the contact resistance between the two structures. Thus, without additionally increasing the width of the second coupling structure CB or by minimizing the adjustment to the width of the second electrode T2D of the second transistor T2, a large coupling can be achieved between the first coupling structure CA and the second electrode T2D of the second transistor T2.

[0086] In the first embodiment of this disclosure, see [link to relevant documentation]. Figure 3 and Figure 4 In the first pixel driving circuit PDC1, both the first coupling structure CA and the second coupling structure CB extend along the row direction DH. Along the row direction DH, both ends of the first coupling structure CA extend beyond the second coupling structure CB. Along the column direction DV, the orthogonal projection of the first coupling structure CA onto the substrate SBT does not exceed the orthogonal projection of the second coupling structure CB onto the substrate SBT. In this embodiment, the gate T4G of the fourth transistor T4 extends from its end near the second electrode T2D of the second transistor T2 in a direction toward the second electrode T2D of the second transistor T2 until it extends beyond the range of the second coupling structure CB, for example, extending beyond the channel region T2A of the second transistor in the row direction DH. This can be achieved by making the first coupling structure CA as long as possible to increase the overlap area between the first coupling structure CA and the second coupling structure CB.

[0087] In one example of this embodiment, two adjacent pixel driving circuits in the same row can form a pixel driving circuit group. The two pixel driving circuits in the pixel driving circuit group can be arranged in a mirror symmetrical manner, and the channel region T2A of the second transistor is located close to the center of symmetry. The first coupling structure CA of the gate T4G of the fourth transistor T4 of the two pixel driving circuits in the pixel driving circuit group can extend towards each other and be interconnected. In this way, the gate T4G of the interconnected fourth transistor T4 is arranged in parallel with the first scan signal trace GPL, which can further reduce the impedance of the first scan signal trace GPL and reduce the transmission delay of the first scan signal Gate_P. In another example of this embodiment, the first coupling structures CA of the two first pixel driving circuits PDC1 in the same pixel driving circuit group can extend towards each other, but they do not extend to be interconnected. For example, they only slightly exceed the channel region T2A of the second transistor. This can avoid the first coupling structure CA from coupling with other conductive structures and increasing the load on the first scan signal trace GPL.

[0088] In another example of this embodiment, two adjacent pixel driving circuits in the same row can form a pixel driving circuit group. The two pixel driving circuits in the pixel driving circuit group can be arranged in a mirror symmetrical manner, and the channel region T2A of the second transistor is located away from the center of symmetry. The gates T4G of the fourth transistors T4 of the two pixel driving circuits in the pixel driving circuit group can extend towards each other and be interconnected. In this way, the gates T4G of the interconnected fourth transistors T4 are arranged in parallel with the first scan signal trace GPL, which can further reduce the impedance of the first scan signal trace GPL and reduce the transmission delay of the first scan signal Gate_P.

[0089] In one example of this implementation, see Figure 3 and Figure 4 In the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 includes a first metal portion GA, a second metal portion GB, and a first coupling structure CA connected in sequence; the second metal portion GB is connected to the first scan signal trace GPL through a via; the width of the first coupling structure CA is smaller than the width of the first metal portion GA. Figure 4 In the example, the second metal portion GB has a first bottom via region HA1, and the first scan signal trace GPL has a first top via region HB1. The first bottom via region HA1 and the first top via region HB1 overlap and are connected by vias. The first metal portion GA is located on the side of the second metal portion GB away from the channel region T2A of the second transistor, and overlaps with the channel region T4A of the fourth transistor. The width of the first coupling structure CA is smaller than the width of the first metal portion GA to avoid the coupling capacitance between the first scan signal terminal and the first node N1 being too large due to the excessive width of the first coupling structure CA.

[0090] In one example of this implementation, see Figure 3 and Figure 4 In the first pixel driving circuit PDC1, the second terminal T2D of the second transistor T2 includes the second coupling structure CB and the first connection portion OXA. The first connection portion OXA extends along the column direction DV, one end of the first connection portion OXA is connected to the end of the second coupling structure CB away from the channel region T4A of the fourth transistor, and the other end of the first connection portion OXA is electrically connected to the channel region T2A of the second transistor. This ensures that the second coupling structure CB has a larger length in the row direction DH, thereby ensuring that the overlap area between the first coupling structure CA and the second coupling structure CB is sufficiently large.

[0091] exist Figure 3 and Figure 4 In the example, the first pixel driving circuit PDC1 employs a strategy of making the first coupling structure CA narrow and long to increase the coupling area between the first coupling structure CA and the second coupling structure CB. In other embodiments of this disclosure, a strategy of making at least a portion of the second coupling structure CB narrow and wide may also be adopted, for example, making the width of the second coupling structure CB smaller than the width of the first coupling structure CA.

[0092] In a second embodiment of this disclosure, see [link to relevant documentation]. Figure 5 and Figure 6 In the first pixel driving circuit PDC1, both the first coupling structure CA and the second coupling structure CB extend along the row direction DH. Along the row direction DH, one end of the first coupling structure CA does not extend beyond the second coupling structure CB, meaning that the first coupling structure CA and the second coupling structure CB partially overlap in the row direction DH. The gate T4G of the fourth transistor T4 includes a first metal portion GA, a second metal portion GB, and a first coupling structure CA connected in sequence. The width of the first coupling structure CA is greater than the width of the first metal portion GA; the width of the second coupling structure CB is greater than the width of the channel region T2A of the second transistor. Thus, both the first coupling structure CA and the second coupling structure CB are widened and partially overlap to ensure a large coupling capacitance between them.

[0093] exist Figure 5 and Figure 6In one example, the width of the first coupling structure CA is greater than the width of the second coupling structure CB, such that the orthographic projection of the second coupling structure CB onto the substrate SBT in the column direction DV lies within the orthographic projection of the first coupling structure CA onto the substrate SBT. In other examples of this disclosure, the width of the second coupling structure CB may also be greater than the width of the first coupling structure CA, for example, such that the orthographic projection of the second coupling structure CB onto the substrate SBT in the column direction DV lies within the orthographic projection of the first coupling structure CA onto the substrate SBT.

[0094] exist Figure 5 and Figure 6 In the example, the width of the first coupling structure CA is greater than the width of the first metal portion GA, and the width change of the gate T4G of the fourth transistor T4 occurs at the first metal portion GA. In other embodiments of this disclosure, the width change may also occur at the first metal portion GA or the first coupling structure CA, provided that the width change does not overlap with the second coupling structure CB.

[0095] In one example of this embodiment, in the first pixel driving circuit PDC1, the second terminal T2D of the second transistor T2 includes a second coupling structure CB, a second connection portion OXB, and a first connection portion OXA connected in sequence; the second connection portion OXB extends along the row direction DH, and the first connection portion OXA extends along the column direction DV; the widths of the second connection portion OXB and the first connection portion OXA are smaller than the width of the second coupling structure CB. In other words, the second terminal T2D of the second transistor T2 can be widened only at the second coupling structure CB to ensure the overlap area with the first coupling structure CA. In other examples of this disclosure, at least one of the second connection portion OXB and the first connection portion OXA can also be widened, for example, the width of the second connection portion OXB is the same as the width of the second coupling structure CB.

[0096] In a third embodiment of this disclosure, see [link to relevant documentation]. Figures 7-10In the first pixel driving circuit PDC1, the gate T4G of the fourth transistor T4 includes a first metal portion GA, a second metal portion GB, a third metal portion GC, and a first coupling structure CA connected in sequence. The second metal portion GB is connected to the first scan signal trace GPL through a via. The gate T4G of the fourth transistor T4 extends along the row direction DH, and the size of the first coupling structure CA in the column direction DV is larger than the size of the third metal portion GC in the column direction DV. The second electrode T2D of the second transistor T2 includes a second coupling structure CB, a first connection portion OXA, and a second connection portion OXB connected in sequence. The first connection portion OXA extends along the row direction DH, and the second connection portion OXB extends along the column direction DV. The size of the second coupling structure CB in the column direction DV is larger than the size of the second connection portion OXB in the column direction DV.

[0097] In this embodiment, the gate T4G of the fourth transistor T4 is enlarged at the end near the second transistor T2 and is called the first coupling structure CA. The second electrode T2D of the second transistor T2 is enlarged at the end near the fourth transistor T4 and is called the second coupling structure CB. The first coupling structure CA and the second coupling structure CB are overlapped to give the first scan signal terminal a large coupling capacitance with the first node N1.

[0098] exist Figures 7-10 In the example, the widths of the second connection portion OXB and the first connection portion OXA are not increased. This avoids excessively increasing the second electrode T2D of the second transistor T2, which would cause an excessive increase in the coupling capacitance between the second electrode T2D of the second transistor T2 and other structures. In other examples of this disclosure, the width of at least one of the second connection portion OXB and the first connection portion OXA may also be increased, for example, making the width of the second connection portion OXB smaller than that of the second coupling structure CB and larger than that of the first connection portion OXA.

[0099] exist Figures 7-10 In the example, the width of the third metal part GC is smaller than that of the first coupling structure CA. This avoids the increased load on the first scan signal trace GPL caused by the third metal part GC coupling with other structures. Furthermore, the width of the third metal part GC is smaller than that of the first metal part GA.

[0100] exist Figures 7-10 In the example, the width of the second metal part GB is equal to the width of the first metal part GA. In other examples of this disclosure, the width of the second metal part GB may also be adjusted, for example, by increasing the width of the second metal part GB to be greater than that of the first metal part GA, or by decreasing the width of the second metal part GB (for example, by reducing it to the same width as the third metal part GC).

[0101] In one embodiment of this disclosure, see Figure 2 The driving layer DRL includes a first gate layer GT1, a second semiconductor layer OSCL, and a first source-drain metal layer SD1, which are sequentially stacked on one side of the substrate SBT. The gate T4G of the fourth transistor T4 is disposed on the first gate layer GT1, the first scan signal trace GPL is disposed on the first source-drain metal layer SD1, and the second electrode T2D of the second transistor T2 is located on the second semiconductor layer OSCL. The first scan signal trace GPL is disposed on the first source-drain metal layer SD1, which reduces the resistivity of the first scan signal trace GPL, thereby reducing the rise and fall times of the first scan signal Gate_P and lowering the delay of the first scan signal Gate_P. This facilitates the timely turn-on and turn-off of the fourth transistor T4 and the full writing of the data voltage Vdata. No thick organic insulating layer is disposed between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2. Therefore, the step difference between the first coupling structure CA and the second coupling structure CB is small, which helps to increase the coupling capacitance between the first coupling structure CA and the second coupling structure CB.

[0102] In this embodiment of the disclosure, with the driving power supply voltage VDD at 4.6V, the inventors also evaluated the effects of changes in the capacitance between the first scan signal terminal and the first node N1, and the capacitance between the second scan signal terminal and the first node N1, on the black state voltage of different sub-pixels.

[0103] The results of the first evaluation are shown in Table 1. In this evaluation, the inventors assessed the coupling and black-state voltage of the improved scheme, as well as the coupling and black-state voltage of the original scheme. The local structure of the improved scheme is shown below. Figure 3 and Figure 4 As shown; the local structure of the original scheme is basically the same as... Figure 3 , Figure 4 Similar to the example shown, but the gate T4G of the fourth transistor T4 does not have a first coupling structure CA that overlaps with the second coupling structure CB.

[0104] Table 1. Differences in black-state voltage (VGMP) between the improved and unimproved schemes.

[0105]

[0106]

[0107] As shown in Table 1, compared to the original scheme, the coupling capacitance between the second scan signal terminal and the first node N1 remains basically unchanged in the improved scheme, but the coupling capacitance between the first scan signal terminal and the first node N1 increases. Of course, as the coupling capacitance between the first scan signal terminal and the first node N1 increases, the parasitic capacitance of the first scan signal terminal also increases.

[0108] Because the green sub-pixel has the highest luminous efficiency, it is the most difficult for it to turn black while in an luminous state, resulting in the highest black-state voltage. Therefore, the inventors evaluated the black-state voltage of the green sub-pixel under different maximum luminous brightness levels (the higher the maximum luminous brightness, the more difficult it is for the sub-pixel to completely turn off, and the higher the required black-state voltage). In the original scheme, the black-state voltage of the green sub-pixel was 7.192V at 500 nits and 7.549V at 1200 nits. In the improved scheme, the black-state voltage of the green sub-pixel is 6.669V at 500 nits and 7.032V at 1200 nits. Therefore, this improved scheme can reduce the black-state voltage of the green sub-pixel by approximately 0.5V. Especially under high brightness conditions, this improved scheme, by reducing the black-state voltage, makes it easier to ensure that the black-state voltage does not exceed the chip's output capability, reducing the risk of the black-state voltage exceeding the chip's output capability due to a high drive power supply voltage VDD.

[0109] The inventors also evaluated the black-state voltages corresponding to different sub-pixels in different improved schemes. The main differences between these improved schemes lie in the coupling capacitance between the first scan signal terminal and the first node N1, and the coupling capacitance between the second scan signal terminal and the first node N1. The evaluation results are shown in Table 2.

[0110] Table 2: Differences in black-state voltage (VGMP) among different improvement schemes

[0111]

[0112]

[0113] In Table 2, C N1-Gtp C is the coupling capacitor between the first scan signal terminal and the first node; N1-Gtn This is the coupling capacitor between the second scan signal terminal and the first node. PXR represents the red sub-pixel, PXG represents the green sub-pixel, and PXB represents the blue sub-pixel.

[0114] As shown in Table 2, when the coupling capacitance between the first scan signal terminal and the first node N1 is approximately the same for both improved schemes, the improved scheme with a larger coupling capacitance between the second scan signal terminal and the first node N1 has a larger black-state voltage for its sub-pixels. Conversely, when the coupling capacitance between the second scan signal terminal and the first node N1 is approximately the same for both improved schemes, the improved scheme with a larger coupling capacitance between the first scan signal terminal and the first node N1 has a smaller black-state voltage for its sub-pixels. In the various improved schemes evaluated in Table 2, the black-state voltage of each sub-pixel is not very high, for example, none exceeding 6.8V. This allows these improved schemes to reduce the risk of black-state voltage exceeding the IC's output capability in products with a high driving power supply voltage VDD (e.g., 4.6V), thereby improving the stability and quality of these products. Correspondingly, by adopting the improved schemes provided in this disclosure, the product can use a higher driving power supply voltage VDD with lower risk, thereby making the output of the IC (e.g., the source driver chip) more efficient.

[0115] In one embodiment of this disclosure, the driving power supply voltage VDD is not less than 4.0V, for example, the driving power supply voltage VDD is 4.6V.

[0116] In some embodiments of this disclosure, sub-pixels PX may include multiple sub-pixels PX of different colors, and the luminous efficiency of sub-pixels PX of different colors may vary. In this case, if no improvements are made to the pixel driving circuit on the display panel PNL, the pixel driving circuit with the highest luminous efficiency is most likely to experience a black-state voltage exceeding the chip's driving capability. Therefore, in these embodiments, the pixel driving circuit used to drive the sub-pixel PX with the highest luminous efficiency can be at least a first pixel driving circuit PDC1, in order to at least reduce the black-state voltage corresponding to the sub-pixel PX with the highest luminous efficiency. For sub-pixels PX with non-highest luminous efficiency, it can be determined whether its corresponding pixel driving circuit should be improved as needed. For example, all other pixel driving circuits can be improved to the first pixel driving circuit PDC1, or some pixel driving circuits can be improved to the first pixel driving circuit PDC1, or none of the other pixel driving circuits can be improved to the first pixel driving circuit PDC1, or the first pixel driving circuit PDC1 can have different black-state voltage reduction capabilities depending on the luminous efficiency of the sub-pixel PX.

[0117] In one implementation, see Figure 11Each pixel driving circuit on the display panel PNL is a first pixel driving circuit PDC1, meaning that each pixel driving circuit employs an improved method that overlaps the gate T4G of the fourth transistor T4 with the second electrode T2D of the second transistor T2. In other words, the pixel driving circuit corresponding to each sub-pixel PX is a first pixel driving circuit PDC1 to reduce the black state voltage required by the pixel driving circuit corresponding to each sub-pixel PX.

[0118] In one example, a sub-pixel PX includes multiple sub-pixels of different colors, whose luminous efficiencies may vary. For example, a sub-pixel PX may include a red sub-pixel PXR, a green sub-pixel PXG, a blue sub-pixel PXB, etc. The first pixel driving circuit PDC1 used by sub-pixels of different colors or with different luminous efficiencies has a basically the same structure. For example, the coupling capacitance between the first scan signal terminal and the first node N1 of each first pixel driving circuit PDC1 is roughly the same, and the coupling capacitance between the second scan signal terminal and the first node N1 of each first pixel driving circuit PDC1 is also roughly the same. Thus, the pixel driving circuits corresponding to each sub-pixel PX do not need to be designed differently, which is beneficial for the design and fabrication of the display panel PNL.

[0119] In another example, the display panel PNL may include multiple different first pixel driving circuits (PDC1). The main difference between the different first pixel driving circuits (PDC1) lies in the different overlap areas of the gate T4G of the fourth transistor T4 and the electrode T2D of the second transistor T2, resulting in different capabilities to reduce black-state voltage. The larger the overlap area between the gate T4G of the fourth transistor T4 and the electrode T2D of the second transistor T2, the stronger the ability of the first pixel driving circuit (PDC1) to reduce black-state voltage. Based on the differences in luminous efficiency of different sub-pixels (PX), the display panel PNL adapts different first pixel driving circuits (PDC1) for different sub-pixels (PX): for sub-pixels (PX) with higher luminous efficiency, a first pixel driving circuit (PDC1) with a stronger ability to reduce black-state voltage is configured.

[0120] For example, see Figure 11Sub-pixels PX include a first sub-pixel PX1 and a second sub-pixel PX2, wherein the luminous efficiency of the first sub-pixel PX1 is greater than that of the second sub-pixel PX2. The pixel driving circuits corresponding to the first sub-pixel PX1 and the second sub-pixel PX2 are both first pixel driving circuits PDC1, meaning that the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 are designed to overlap. However, in the first pixel driving circuit PDC1 driving the first sub-pixel PX1, the overlap area between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 is a first area; in the first pixel driving circuit PDC1 driving the second sub-pixel PX2, the overlap area between the gate T4G of the fourth transistor T4 and the second electrode T2D of the second transistor T2 is a second area; the first area is greater than the second area. Thus, the luminous efficiency of the first sub-pixel PX1 is higher than that of the second sub-pixel PX2, and the first pixel driving circuit PDC1 driving the first sub-pixel PX1 has a stronger ability to reduce black state voltage than the first pixel driving circuit PDC1 driving the second sub-pixel PX2.

[0121] In another implementation, see Figure 12 The pixel layer PXL has multiple sub-pixels PX of different colors. Each sub-pixel PX includes a first sub-pixel PX1 and a second sub-pixel PX2. The luminous efficiency of the first sub-pixel PX1 is greater than that of the second sub-pixel PX2. The pixel driving circuit includes a second pixel driving circuit PDC2. The gate T4G of the fourth transistor T4 of the second pixel driving circuit PDC2 does not overlap with the second electrode T2D of the second transistor T2. The pixel driving circuit corresponding to the first sub-pixel PX1 is the first pixel driving circuit PDC1, and the pixel driving circuit corresponding to the second sub-pixel PX2 is the second pixel driving circuit PDC2. In this embodiment, only the pixel driving circuit driving the first sub-pixel PX1 is the first pixel driving circuit PDC1, which has the capability to reduce black-state voltage. The pixel driving circuit driving the second sub-pixel PX2 does not employ the improved scheme that causes the gate T4G of the fourth transistor T4 to overlap with the second electrode T2D of the second transistor T2.

[0122] As an example, see Figure 12 The sub-pixel PX includes a red sub-pixel PXR, a green sub-pixel PXG, and a blue sub-pixel PXB. The green sub-pixel PXG serves as the first sub-pixel PX1, and the red sub-pixel PXR and blue sub-pixel PXB serve as the second sub-pixel PX2. In this example, the green sub-pixel PXG is driven by a first pixel driving circuit PDC1, while the blue sub-pixel PXB and red sub-pixel PXR are driven by a second pixel driving circuit PDC2.

[0123] As an example, see Figure 2 The driving layer DRL also includes a first semiconductor layer PSCL, which is used to form the active layer of transistors such as the third transistor T3 and the fourth transistor T4. Optionally, in the film layer stacking order, the first gate layer GT1 is located between the first semiconductor layer PSCL and the second semiconductor layer OSCL.

[0124] As an example, see Figure 2 The driving layer DRL also includes a second gate layer GT2, a third gate layer GT3, etc. The second gate layer GT2 and the third gate layer GT3 can form the top gate and bottom gate of the second transistor T2, as well as other required structures.

[0125] As an example, see Figure 2 The driving layer DRL also includes a second source / drain metal layer SD2 and a third source / drain metal layer SD3 located on the side of the first source / drain metal layer SD1 away from the substrate SBT, so as to better transmit signals or make electrical connections.

[0126] As another example, the driver layer DRL can be configured with only two source / drain metal layers instead of three.

[0127] It is understandable that an insulating material film layer can be disposed between adjacent metal layers and semiconductor layers.

[0128] As an example, see Figure 2 The driving layer DRL comprises, in sequence, a first inorganic buffer layer BLA, a first semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BLB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer SD3, and a third planarization layer PLN3, all stacked on one side of the substrate SBT. The active layer of a P-type transistor can be disposed on the first semiconductor layer PSCL, and the active layer of an N-type transistor can be disposed on the second semiconductor layer OSCL. In one example, the first semiconductor layer PSCL can be a low-temperature polysilicon semiconductor layer. The second semiconductor layer OSCL can be a metal-oxide-semiconductor layer.

[0129] Understandable, Figure 2 This is merely one example of the driver layer DRL in this disclosure; other embodiments of the driver layer DRL in this disclosure may be compatible with... Figure 2The differences are as follows: for example, it may include only two gate layers while simultaneously including a first semiconductor layer PSCL and a second semiconductor layer OSCL; or it may include only two source / drain metal layers instead of three source / drain metal layers.

[0130] In one embodiment of this disclosure, see Figure 2 The pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, an emissive light-emitting layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of ​​the display panel. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the emissive light-emitting layer EFL), thereby defining the light-emitting area and light-emitting region of the sub-pixel PX. The common electrode layer COML covers the emissive light-emitting layer EFL as a common electrode. The pixel electrodes and the common electrode layer COML provide electrons, holes, and other charge carriers to the emissive light-emitting layer EFL, causing the emissive light-emitting layer EFL to emit light. The portion of the emissive light-emitting layer EFL located between the pixel electrodes and the common electrode layer COML can serve as the light-emitting functional unit of the sub-pixel PX. A pixel electrode, a common electrode layer (COML), and a light-emitting functional unit form a light-emitting element (LD) that serves as a sub-pixel (PX). One of the pixel electrode and the common electrode layer (COML) serves as the anode of the light-emitting element (LD), and the other serves as the cathode.

[0131] In one example, the display panel PNL is an OLED display substrate. The light-emitting functional layer (EFL) may include an organic light-emitting layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a host material and a guest material, wherein the guest material may be a fluorescent dopant or a phosphorescent dopant, and particularly may be a thermally activated delayed fluorescence material.

[0132] In another example, the display panel PNL is a QLED display substrate. The light-emitting functional layer (EFL) may include a quantum dot layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0133] In one embodiment of this disclosure, see Figure 2The display panel PNL has a thin-film encapsulation layer TFE on the surface of the pixel layer PXL away from the substrate SBT. This TFE may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the thin-film encapsulation layer TFE may also adopt other structures, such as multiple stacked inorganic encapsulation layers. In other embodiments, the display panel may not have a thin-film encapsulation layer, but instead use other methods to encapsulate and protect the pixel layer.

[0134] As follows, Figures 13-30 Taking the first layout example as an example, a first pixel driving circuit PDC1 according to an embodiment of this disclosure will be described exemplarily. In this first layout example, the equivalent circuit of the first pixel driving circuit PDC1 is as follows: Figure 1 As shown. The driving layer DRL includes a first inorganic buffer layer BLA, a first semiconductor layer PSCL, a first gate insulating layer GI1, a first gate layer GT1, a second inorganic buffer layer BLB, a second gate layer GT2, a second gate insulating layer GI2, a second semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, an interlayer dielectric layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer SD3, and a third planarization layer PLN3, which are stacked sequentially.

[0135] Figure 13 This is a partial structural diagram of the first source / drain metal layer SD1 in the first layout example. Figure 14 This is a partial structural diagram of the first semiconductor layer PSCL in the first layout example. Figure 15 This is a schematic diagram of a partial stacking structure of the first semiconductor layer PSCL and the first source / drain metal layer SD1, as shown in the first layout example of this disclosure.

[0136] See Figure 14The first semiconductor layer PSCL has multiple channel regions of thin-film transistors, such as channel region T1A of the first transistor, channel region T3A of the third transistor, channel region T4A of the fourth transistor, channel region T5A of the fifth transistor, channel region T6A of the sixth transistor, channel region T7A of the seventh transistor and channel region T8A of the eighth transistor, and includes conductive portions located on both sides of the channel regions as the first or second electrode of the thin-film transistor.

[0137] See Figures 13-15 The first semiconductor layer PSCL has the second terminals of the fifth transistor T5, the eighth transistor T8, the fourth transistor T4, and the third transistor T3, which are part of the second node N2, located in the first semiconductor layer PSCL. The first terminals of the third transistor T3, the fifth transistor T5, and the fourth transistor T4 are interconnected. The second terminals of the eighth transistor T8 and the fifth transistor T5 are electrically connected through the second conductive structure MA2 located in the first source-drain metal layer SD1. The second terminal of the fifth transistor T5 has a fourth bottom via region HA4, and the second conductive structure MA2 has a fourth top via region HB4; the fourth bottom via region HA4 and the fourth top via region HB4 overlap and are connected by vias. The second terminal of the eighth transistor T8 has a fifth bottom via region HA5, and the second conductive structure MA2 has a fifth top via region HB5; the fifth bottom via region HA5 and the fifth top via region HB5 overlap and are connected by vias.

[0138] The first semiconductor layer PSCL has a second terminal of a first transistor T1, a second terminal of a third transistor T3, and a first terminal of a sixth transistor T6, which are part of the third node N3. The second terminal of the third transistor T3 and the first terminal of the sixth transistor T6 are interconnected, and the second terminals of the first transistor T1 and the third transistor T3 are electrically connected through a third conductive structure MA3 located in the first source-drain metal layer SD1. Specifically, the second terminal of the first transistor T1 has a sixth bottom via region HA6, and the third conductive structure MA3 has a sixth top via region HB6; the sixth bottom via region HA6 and the sixth top via region HB6 overlap and are connected through vias. The second terminal of the third transistor T3 has an eighth bottom via region HA8, and the third conductive structure MA3 has an eighth top via region HB8; the eighth bottom via region HA8 and the eighth top via region HB8 overlap and are connected through vias.

[0139] The first semiconductor layer PSCL has the second terminals of the sixth transistor T6 and the seventh transistor T7, which are part of the fourth node N4. The second terminal of the seventh transistor T7 is interconnected with the second terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is electrically connected to the fourth conductive structure MA4 located in the first source-drain metal layer SD1 through a via. The second terminal of the sixth transistor T6 has a ninth bottom via region HA9, and the fourth conductive structure MA4 has a ninth top via region HB9; the ninth bottom via region HA9 and the ninth top via region HB9 overlap and are connected through vias.

[0140] The first semiconductor layer PSCL has a first terminal of a fifth transistor T5, which is part of the drive power supply voltage node. The first terminal of the fifth transistor T5 is electrically connected to the fifth conductive structure MA5 located in the first source-drain metal layer SD1 through a via. The first terminal of the fifth transistor T5 has a fifteenth bottom via region HA15, and the fifth conductive structure MA5 has a fifteenth top via region HB15. The fifteenth bottom via region HA15 and the fifteenth top via region HB15 overlap each other and are connected through vias.

[0141] The first semiconductor layer PSCL has a first terminal of a fourth transistor T4, which is part of a data voltage node. The first terminal of the fourth transistor T4 is electrically connected to the sixth conductive structure MA6 located in the first source-drain metal layer SD1 through a via. The first terminal of the fourth transistor T4 has a sixteenth bottom via region HA16, and the sixth conductive structure MA6 has a sixteenth top via region HB16. The sixteenth bottom via region HA16 and the sixteenth top via region HB16 overlap and are connected by vias.

[0142] The first semiconductor layer PSCL has a first terminal of a first transistor T1, which is part of a first initialization voltage node. The first terminal of the first transistor T1 is electrically connected to the seventh conductive structure MA7 located in the first source-drain metal layer SD1 through a via. The first terminal of the first transistor T1 has a nineteenth bottom via region HA19, and the seventh conductive structure MA7 has a nineteenth top via region HB19. The nineteenth bottom via region HA19 and the nineteenth top via region HB19 overlap each other and are connected through vias.

[0143] The first semiconductor layer PSCL has a first terminal of a seventh transistor T7, which is part of the second initialization voltage node. The first terminal of the seventh transistor T7 is electrically connected to the eighth conductive structure MA8 located in the first source-drain metal layer SD1 through a via. The first terminal of the seventh transistor T7 has a twenty-first bottom via region HA21, and the eighth conductive structure MA8 has a twenty-first top via region HB21. The twenty-first bottom via region HA21 and the twenty-first top via region HB21 overlap and are connected through a via.

[0144] The first semiconductor layer PSCL has a first terminal of an eighth transistor T8, which is part of the third initialization voltage node. The first terminal of the eighth transistor T8 is electrically connected to the ninth conductive structure MA9 located in the first source-drain metal layer SD1 through a via. The first terminal of the eighth transistor T8 has a twenty-third bottom via region HA23, and the ninth conductive structure MA9 has a twenty-third top via region HB23. The twenty-third bottom via region HA23 and the twenty-third top via region HB23 overlap and are connected by vias.

[0145] Figure 16 This is a partial structural schematic diagram of the first gate layer GT1 in the first layout example of this disclosure. Figure 17 This is a schematic diagram of a partial stacking structure of the first semiconductor layer PSCL and the first gate layer GT1 in the first layout example of this disclosure. Figure 18 This is a partial structural stacking diagram of the first gate layer GT1 and the first source / drain metal layer SD1 in the first layout example of this disclosure.

[0146] See Figures 16-18 The first gate layer GT1 has a first electrode CP1 of a storage capacitor that is part of the first node N1. The first electrode CP1 of the storage capacitor overlaps with the channel region T3A of the third transistor and is multiplexed as the gate of the third transistor T3. The first electrode CP1 of the storage capacitor is electrically connected to the first conductive structure MA1 located in the first source-drain metal layer SD1 through a via. The first electrode CP1 of the storage capacitor has a second bottom via region HA2, and the first conductive structure MA1 has a second top via region HB2. The second bottom via region HA2 and the second top via region HB2 overlap each other and are connected through vias.

[0147] The first gate layer GT1 has a gate T4G of a fourth transistor T4, which is part of a first scan signal node. The gate T4G of the fourth transistor T4 is electrically connected to the first scan signal trace GPL located on the first source-drain metal layer SD1 through a via. The gate T4G of the fourth transistor T4 has a first bottom via region HA1, and the first scan signal trace GPL has a first top via region HB1. The first bottom via region HA1 and the first top via region HB1 overlap and are connected by vias.

[0148] The first gate layer GT1 is provided with a light emission control trace EML, which serves as a light emission control signal terminal. The light emission control trace EML is used to load the light emission control trace EML and extends along the row direction DH; the light emission control trace EML overlaps with the channel region T5A of the fifth transistor and the channel region T6A of the sixth transistor to be reused as the gate of the fifth transistor T5 and the gate of the sixth transistor T6.

[0149] The first gate layer GT1 is provided with a second reset signal trace RHL, which serves as the second reset signal terminal. The second reset signal trace RHL is used to load the second reset signal Reset_H and extends along the row direction DH. The second reset signal trace RHL overlaps with the channel region T7A of the seventh transistor and the channel region T8A of the eighth transistor, respectively, and is multiplexed as the gate of the seventh transistor T7 and the gate of the eighth transistor T8.

[0150] The first gate layer GT1 is provided with a first reset signal trace RPL, which serves as a first reset signal terminal. The first reset signal trace RPL is used to load the first reset signal Reset_P and extends along the row direction DH; the first reset signal trace RPL overlaps with the channel region T1A of the first transistor of the next row pixel driving circuit to serve as the gate of the first transistor T1 of the next row pixel driving circuit.

[0151] Figure 19 This is a partial structural diagram of the second gate layer GT2 in the first layout example of this disclosure. Figure 20 This is a schematic diagram of a partial structural stacking of the second gate layer GT2 and the first source / drain metal layer SD1 in the first layout example of this disclosure. Figure 21 This is a partial structural diagram of the second semiconductor layer OSCL in the first layout example of this disclosure. Figure 22 This is a schematic diagram of a partial stacking structure of the second gate layer GT2 and the second semiconductor layer OSCL in the first layout example of this disclosure. Figure 23 This is a schematic diagram of a partial stacking structure of the second semiconductor layer OSCL and the first source / drain metal layer SD1, as shown in the first layout example of this disclosure.

[0152] See Figures 19-23 The second gate layer GT2 is provided with a second electrode CP2 of a storage capacitor, which is part of the drive power supply voltage node. The second electrode CP2 of the storage capacitor is electrically connected to the fifth conductive structure MA5 located in the first source / drain metal layer SD1 through a via. The second electrode CP2 of the storage capacitor has a fourteenth bottom via region HA14, and the fifth conductive structure MA5 has a fourteenth top via region HB14. The fourteenth bottom via region HA14 and the fourteenth top via region HB14 overlap and are connected through vias. Optionally, the second electrodes CP2 of adjacent storage capacitors in the same row are electrically connected to each other to create a gridded distribution of the drive power supply voltage VDD, improving the uniformity of the drive power supply voltage VDD distribution.

[0153] The second gate layer GT2 is provided with a second scan signal bottom trace GNLA, which serves as the second scan signal terminal. The second scan signal bottom trace GNLA is used to load the second scan signal Gate_N and extends along the row direction DH; the second scan signal bottom trace GNLA overlaps with the channel region T2A of the second transistor to serve as the bottom gate of the second transistor T2.

[0154] The second semiconductor layer OSCL has an active layer for the second transistor T2. This active layer includes the first terminal of the second transistor T2, the channel region T2A of the second transistor T2, and the second terminal T2D of the second transistor T2, connected sequentially. The second terminal T2D of the second transistor T2 is part of the first node N1. The second terminal T2D of the second transistor T2 is electrically connected to the first conductive structure MA1 located in the first source-drain metal layer SD1 through a via. The second terminal T2D of the second transistor T2 has a third bottom via region HA3, and the first conductive structure MA1 has a third top via region HB3. The third bottom via region HA3 and the third top via region HB3 overlap and are connected through vias. The first terminal of the second transistor T2 is part of the third node N3. The first terminal of the second transistor T2 is electrically connected to the third conductive structure MA3 located in the first source-drain metal layer SD1 through a via. Among them, the first electrode of the second transistor T2 has a seventh bottom via region HA7, and the third conductive structure MA3 has a seventh top via region HB7. The seventh bottom via region HA7 and the seventh top via region HB7 overlap each other and are connected by vias.

[0155] Figure 3 See the partial schematic diagram of this first type of layout example. Figure 3 The gate T4G of the fourth transistor T4 overlaps with the second terminal T2D of the second transistor T2 to create a large coupling capacitance between the first scan signal terminal and the first node N1.

[0156] Figure 24 This is a partial structural schematic diagram of the third gate layer GT3 in the first layout example of this disclosure. Figure 25 This is a schematic diagram of a partial stacking structure of the second semiconductor layer OSCL and the third gate layer GT3, as shown in the first layout example of this disclosure. Figure 26 This is a schematic diagram of a partial stacking structure of the third gate layer GT3 and the first source / drain metal layer SD1 in the first layout example of this disclosure.

[0157] See Figures 24-26The third gate layer GT3 has a first initialization voltage trace VTL1, which serves as the first initialization voltage terminal. The first initialization voltage trace VTL1 is used to apply the first initialization voltage Vinit1 and extends along the row direction DH. The first initialization voltage trace VTL1 is electrically connected to the seventh conductive structure MA7 located in the first source / drain metal layer SD1 via a via. Specifically, the first initialization voltage trace VTL1 has a twentieth bottom via region HA20, and the seventh conductive structure MA7 has a twentieth top via region HB20. The twentieth bottom via region HA20 and the twentieth top via region HB20 overlap and are connected vias.

[0158] The third gate layer GT3 has a second initialization voltage trace VTL2 serving as the second initialization voltage terminal. The second initialization voltage trace VTL2 is used to apply the second initialization voltage Vinit2 and extends along the row direction DH. The second initialization voltage trace VTL2 is electrically connected to the eighth conductive structure MA8 located in the first source / drain metal layer SD1 via a via. Specifically, the second initialization voltage trace VTL2 has a twenty-second bottom via region HA22, and the eighth conductive structure MA8 has a twenty-second top via region HB22. The twenty-second bottom via region HA22 and the twenty-second top via region HB22 overlap and are connected vias.

[0159] The third gate layer GT3 has a third initialization voltage trace VTL3 serving as the third initialization voltage terminal. The third initialization voltage trace VTL3 is used to apply the third initialization voltage Vinit3 and extends along the row direction DH. The third initialization voltage trace VTL3 is electrically connected to the ninth conductive structure MA9 located in the first source / drain metal layer SD1 via a via. Specifically, the third initialization voltage trace VTL3 has a twenty-fourth bottom via region HA24, and the ninth conductive structure MA9 has a twenty-fourth top via region HB24. The twenty-fourth bottom via region HA24 and the twenty-fourth top via region HB24 overlap and are connected vias.

[0160] The third gate layer GT3 is provided with a second scan signal top trace GNLB, which serves as the second scan signal terminal. The second scan signal top trace GNLB is used to load the second scan signal Gate_N and extends along the row direction DH; the second scan signal top trace GNLB overlaps with the channel region T2A of the second transistor to serve as the top gate of the second transistor T2.

[0161] Figure 27 This is a partial structural diagram of the second source / drain metal layer SD2 in the first layout example of this disclosure. Figure 28 This is a schematic diagram of the local structural stacking of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 in the first layout example of this disclosure. Figure 29This is a partial structural diagram of the third source / drain metal layer SD3, as shown in the first layout example of this disclosure. Figure 30 This is a schematic diagram of the local structural stacking of the second source / drain metal layer SD2 and the third source / drain metal layer SD3 in the first layout example of this disclosure.

[0162] See Figures 27-30 The second source / drain metal layer SD2 has a tenth conductive structure MB1 as part of the fourth node N4. The tenth conductive structure MB1 is electrically connected to the thirteenth conductive structure MC1 located in the third source / drain metal layer SD3 through vias. The tenth conductive structure MB1 has an eleventh bottom via region HA11, and the thirteenth conductive structure MC1 has an eleventh top via region HB11. The eleventh bottom via region HA11 and the eleventh top via region HB11 overlap each other and are connected by vias.

[0163] The second source / drain metal layer SD2 has an eleventh conductive structure MB2 as part of the drive power supply voltage node. The eleventh conductive structure MB2 is electrically connected via a via to the drive power supply voltage trace VDDL located on the third source / drain metal layer SD3, and also via a via to the fifth conductive structure MA5 located on the first source / drain metal layer SD1. The eleventh conductive structure MB2 has a twelfth bottom via region HA12 and a thirteenth top via region HB13; the fifth conductive structure MA5 has a thirteenth bottom via region HA13, which overlaps with and is connected to the thirteenth top via region HB13 via a via. The drive power supply voltage trace VDDL has a twelfth top via region HB12, which overlaps with and is connected to the twelfth top via region HB12 via a via. Optionally, the eleventh conductive structure MB2 extends along the row direction DH to form a trace, which grids the distribution of the drive power supply voltage VDD, improving the uniformity of the drive power supply voltage VDD.

[0164] The second source-drain metal layer SD2 has a twelfth conductive structure MB3 as part of the drive power supply voltage node. The twelfth conductive structure MB3 is electrically connected to the data trace DL located on the third source-drain metal layer SD3 via a via. The twelfth conductive structure MB3 has an eighteenth bottom via region HA18, and the data trace DL has an eighteenth top via region HB18. The eighteenth bottom via region HA18 and the eighteenth top via region HB18 overlap and are connected by vias.

[0165] The third source-drain metal layer SD3 is provided with a thirteenth conductive structure MC1, which is part of the fourth node N4. The thirteenth conductive structure MC1 is used to electrically connect to the pixel electrode through a via so that the driving current of the pixel driving circuit is applied to the light-emitting element LD.

[0166] The third source-drain metal layer SD3 is provided with a drive power supply voltage VDD, which serves as the drive power supply voltage terminal. The drive power supply voltage trace VDDL is used to load the drive power supply voltage VDD and extends along the column direction DV.

[0167] The third source-drain metal layer SD3 has a data trace DL that serves as the data voltage terminal. The data trace DL is used to load the data voltage Vdata and extends along the column direction DV.

[0168] In the first layout example of this disclosure, the display panel PNL is further provided with multiple auxiliary traces extending along the column direction DV. The auxiliary traces may include one or more types, and any one of the auxiliary traces can improve the uniformity of the voltage distribution by connecting to a certain voltage trace. The auxiliary traces can avoid the traces extending along the row direction DH by bridging them. Optionally, the auxiliary traces may include alternating main trace segments and bridging trace segments; the main trace segments may be disposed on the first source / drain metal layer SD1 and extend along the column direction DV; the bridging trace segments may be disposed on the second gate layer GT2 and extend along the column direction DV. The main trace segments and bridging trace segments can be connected by vias. Thus, with the help of the bridging traces, the auxiliary traces can avoid traces such as the first scan signal trace GPL.

[0169] As an example of auxiliary routing Figure 13 The diagram illustrates the main trace segment VTX1, which is an auxiliary trace used to load the second initialization voltage Vinit2. Figure 19 The diagram illustrates a bridging trace segment VTX2 used for the auxiliary trace to apply the second initialization voltage Vinit2. Figure 20 The auxiliary wiring is illustrated in the diagram. See also... Figure 20 The auxiliary trace used to apply the second initialization voltage Vinit2 includes a main trace segment VTX1 disposed on the first source-drain metal layer SD1, and a bridging trace segment VTX2 disposed on the second gate layer GT2. The main trace segment VTX1 and the bridging trace segment VTX2 are electrically connected through a via. In the first source-drain metal layer SD1, adjacent main trace segments VTX1 are disconnected to avoid the first scan signal trace GPL; the bridging trace segment VTX2 crosses the first scan signal trace GPL to ensure the electrical continuity of the auxiliary trace. See also Figure 26 At the intersection of the auxiliary trace and the second initialization voltage trace VTL2, the main trace segment VTX1 can be electrically connected to the second initialization voltage trace VTL2 through a via.

[0170] This disclosure also provides a second layout example in which the display panel PNL does not have a third source / drain metal layer SD3 and no auxiliary traces. The first semiconductor layer PSCL, the first gate layer GT1, the second gate layer GT2, the second semiconductor layer OSCL, and the third gate layer GT3 in this second layout example are substantially the same as those in the first layout example. Figure 31 This is a partial structural diagram of the first source / drain metal layer SD1 in the second layout example. Figure 32 This is a partial structural diagram of the second source / drain metal layer SD2 in the second layout example. Figure 33 This is a schematic diagram of a partial stack-up structure of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 in this second layout example. See also Figure 31 The structure of the first source / drain metal layer SD1 in this second layout example is largely similar to that in the first layout example. The main difference is that the fifth conductive structure MA5 has a side branch structure, which is used to electrically connect with the driving power supply voltage trace VDDL disposed on the second source / drain metal layer SD2 through vias. Specifically, the fifth conductive structure MA5 has a twenty-fourth bottom via region HA24, and the driving power supply voltage trace VDDL located on the second source / drain metal layer SD2 has a twenty-fourth top via region HB24. The twenty-fourth bottom via region HA24 and the twenty-fourth top via region HB24 overlap and are electrically connected through vias. The second source / drain metal layer SD2 is provided with a fourteenth conductive structure MB4, which has a tenth top via region HB10. The tenth top via region HB10 overlaps with the tenth bottom via region HA10 on the fourth conductive structure MA4 and is connected through vias. Thus, the fourteenth conductive structure MB4 can be used as the output terminal of the pixel driving circuit and electrically connected to the light-emitting element LD. The data trace DL on the second source-drain metal layer SD2 is provided with a seventeenth top via region HB17. This seventeenth top via region HB17 can overlap with the seventeenth bottom via region HA17 located in the sixth conductive structure MA6 and be electrically connected through the via, so that the data voltage Vdata can be applied to the first pole of the fourth transistor T4 through the sixth conductive structure MA6.

[0171] It is understood that the improved pixel driving circuit provided in this disclosure, namely the first pixel driving circuit PDC1, is not limited to the circuit of the present invention. Figure 1 The layout of the example structure is not limited to the first or second layout example of this disclosure.

[0172] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a substrate, a driving layer, and a pixel layer stacked sequentially; the driving layer having a pixel driving circuit for driving sub-pixels; The pixel driving circuit includes a second transistor, a third transistor, a fourth transistor, and a storage capacitor; the second electrode of the second transistor is electrically connected to the gate of the third transistor and the first electrode of the storage capacitor; the fourth transistor is used to write data voltage to the storage capacitor; the third transistor is used to control the magnitude of the output driving current according to the voltage on the gate of the third transistor; the display panel is provided with a first scan signal trace for electrical connection with the gate of the fourth transistor; the gate of the fourth transistor and the first scan signal trace are located in different film layers; The pixel driving circuit includes at least a first pixel driving circuit; In the first pixel driving circuit, the gate of the fourth transistor has a first coupling structure, and the second electrode of the second transistor has a second coupling structure; The orthographic projection of the first coupling structure on the substrate at least partially overlaps with the orthographic projection of the second coupling structure on the substrate.

2. The display panel according to claim 1, wherein, In the first pixel driving circuit, the width of the second coupling structure is greater than the width of the channel region of the second transistor; The extension direction of the first coupling structure is parallel to the length direction of the second coupling structure.

3. The display panel according to claim 2, wherein, In the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; in the column direction, the orthographic projection of the second coupling structure on the substrate does not exceed the orthographic projection of the first coupling structure on the substrate, or the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

4. The display panel according to claim 1, wherein, In the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; Along the direction of travel, both ends of the first coupling structure extend beyond the second coupling structure; Along the column direction, the orthographic projection of the first coupling structure on the substrate does not exceed the orthographic projection of the second coupling structure on the substrate.

5. The display panel according to claim 4, wherein, In the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, and the first coupling structure connected in sequence; the second metal portion is connected to the first scan signal trace through a via. The width of the first coupling structure is smaller than the width of the first metal part.

6. The display panel according to claim 4, wherein, In the first pixel driving circuit, the second electrode of the second transistor includes the second coupling structure and the first connection portion; the first connection portion extends along the column direction, one end of the first connection portion is connected to one end of the second coupling structure away from the channel region of the fourth transistor, and the other end of the first connection portion is electrically connected to the channel region of the second transistor.

7. The display panel according to claim 1, wherein, In the first pixel driving circuit, both the first coupling structure and the second coupling structure extend along the row direction; along the row direction, one end of the first coupling structure does not extend beyond the second coupling structure. The gate of the fourth transistor includes a first metal portion, a second metal portion, and the first coupling structure connected in sequence. The second metal part is connected to the first scan signal trace via a via; the width of the first coupling structure is greater than the width of the first metal part; The width of the second coupling structure is greater than the width of the channel region of the second transistor.

8. The display panel according to claim 7, wherein, In the first pixel driving circuit, the second electrode of the second transistor includes a second coupling structure, a second connection portion, and a first connection portion connected in sequence; the second connection portion extends along the row direction, and the first connection portion extends along the column direction; the width of the second connection portion and the first connection portion is smaller than the width of the second coupling structure.

9. The display panel according to claim 1, wherein, In the first pixel driving circuit, the gate of the fourth transistor includes a first metal portion, a second metal portion, a third metal portion and the first coupling structure connected in sequence, and the second metal portion is connected to the first scan signal trace through a via; the gate of the fourth transistor extends along the row direction, and the dimension of the first coupling structure in the column direction is larger than the dimension of the third metal portion in the column direction; The second electrode of the second transistor includes a second coupling structure, a first connection portion, and a second connection portion connected in sequence; the first connection portion extends along the row direction, and the second connection portion extends along the column direction; the dimension of the second coupling structure in the column direction is larger than the dimension of the second connection portion in the column direction.

10. The display panel according to claim 1, wherein, The third and fourth transistors are P-type thin-film transistors.

11. The display panel according to claim 1, wherein, The pixel layer has multiple sub-pixels of different colors; the pixel driving circuit used to drive the sub-pixel with the highest luminous efficiency is the first pixel driving circuit.

12. The display panel according to claim 1, wherein, Each pixel driving circuit is the same as the first pixel driving circuit.

13. The display panel according to claim 12, wherein, The pixel layer has multiple sub-pixels of different colors, and the sub-pixels include a first sub-pixel and a second sub-pixel, wherein the luminous efficiency of the first sub-pixel is greater than that of the second sub-pixel; The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the first pixel driving circuit. In the first pixel driving circuit that drives the first sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is the first area; in the first pixel driving circuit that drives the second sub-pixel, the overlapping area between the gate of the fourth transistor and the second electrode of the second transistor is the second area; the first area is greater than the second area.

14. The display panel according to claim 1, wherein, The pixel layer has multiple sub-pixels of different colors, and the sub-pixels include a first sub-pixel and a second sub-pixel, wherein the luminous efficiency of the first sub-pixel is greater than that of the second sub-pixel; The pixel driving circuit includes a second pixel driving circuit, wherein the gate of the fourth transistor of the second pixel driving circuit does not overlap with the second electrode of the second transistor; The pixel driving circuit of the first sub-pixel is the first pixel driving circuit, and the pixel driving circuit of the second sub-pixel is the second pixel driving circuit.

15. A display device comprising a display panel as described in any one of claims 1 to 14, and a driving module comprising driving the display panel.

Images