Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a gate region and source / drain regions located on both sides of the gate region; forming an initial gate structure on the gate region, the initial gate structure including an initial gate dielectric layer and an initial gate layer located on the initial gate dielectric layer; forming a sidewall structure on the sidewalls of the initial gate structure, the sidewall structure including a first sidewall and a second sidewall; forming a barrier structure on the substrate, the barrier structure having a barrier opening; forming a source / drain opening in the source / drain region; forming an initial source / drain doping layer in the source / drain opening, the initial source / drain doping layer filling the source / drain opening and extending into the barrier opening; removing the first sidewall; and annealing the initial gate structure and the initial source / drain doping layer in a hydrogen atmosphere to form the initial gate structure into a gate structure and the initial source / drain doping layer into a source / drain doping layer, thereby effectively improving the line width roughness of the gate structure and the source / drain doping layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration to achieve faster computing speeds, larger data storage capacities, and more functions. Correspondingly, semiconductor processes are placing increasingly stringent requirements on etching, with gate etching being particularly critical. The gate etching quality not only determines the gate size of the semiconductor device, but also electrical parameters such as the saturation drain current of the semiconductor device.

[0003] The prior art process for forming a semiconductor device includes the following steps: providing a substrate; sequentially forming a gate dielectric film on the surface of the substrate and a gate film on the surface of the gate dielectric film; forming a hard mask material layer on the surface of the gate film; forming a patterned photoresist layer on the surface of the hard mask material layer; etching the hard mask material layer using the patterned photoresist layer as a mask to form a hard mask layer on the surface of the gate film; removing the patterned photoresist layer; etching the gate film using the hard mask layer as a mask to form a gate on the surface of the gate dielectric film.

[0004] However, the semiconductor structure formed by the existing technology still has many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the line width roughness of a gate structure and a source-drain doping layer.

[0006] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, which is characterized by comprising: providing a substrate, the substrate comprising a gate region and source and drain regions located on both sides of the gate region; forming an initial gate structure on the gate region, the initial gate structure comprising an initial gate dielectric layer and an initial gate layer located on the initial gate dielectric layer; forming a sidewall structure on the sidewall of the initial gate structure, the sidewall structure comprising a first sidewall located on the sidewall of the initial gate structure and a second sidewall located on the sidewall of the first sidewall; forming a blocking structure on the substrate, the blocking structure having a blocking opening, the blocking opening exposing The top surface of the source and drain region is exposed; the source and drain region is etched using the blocking structure as a mask to form a source and drain opening in the source and drain region; an initial source and drain doping layer is formed in the source and drain opening, wherein the initial source and drain doping layer fills the source and drain opening and extends into the blocking opening; after forming the initial source and drain doping layer, the first sidewall is removed to form a gap between the second sidewall and the initial gate structure; the initial gate structure and the initial source and drain doping layer are annealed in a hydrogen atmosphere to form a gate structure from the initial gate structure, the gate structure is in contact with the second sidewall, and the initial source and drain doping layer forms a source and drain doping layer.

[0007] Optionally, the method for forming the blocking structure includes: forming an auxiliary structure on the source and drain region; forming a blocking material layer on the sidewall and top surface of the auxiliary structure, the top surface of the substrate, the sidewall and top surface of the sidewall structure, and the top surface of the initial gate structure; forming a sacrificial layer on the blocking material layer, the sacrificial layer exposing the blocking material layer located on the top surface of the auxiliary structure, the sidewall structure and the top surface of the initial gate structure; using the sacrificial layer as a mask, etching back to remove the blocking material layer located on the top surface of the auxiliary structure, the sidewall structure and the top surface of the initial gate structure to form the blocking structure; after forming the blocking structure, removing the sacrificial layer; after removing the sacrificial layer, removing the auxiliary structure.

[0008] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material layer on the surface of the barrier material layer; and etching back the sacrificial material layer to form the sacrificial layer.

[0009] Optionally, the material of the sacrificial layer includes: an organic anti-reflective coating material.

[0010] Optionally, the process of removing the sacrificial layer includes: a dry ashing process or a wet etching process.

[0011] Optionally, the thickness of the barrier material layer is 5 nm to 10 nm.

[0012] Optionally, the material of the barrier material layer is different from the material of the auxiliary structure.

[0013] Optionally, the material of the barrier material layer includes: Si3N4.

[0014] Optionally, the material of the auxiliary structure includes: SiO2.

[0015] Optionally, the material of the first sidewall is different from the material of the second sidewall.

[0016] Optionally, the material of the first sidewall spacer includes one or more of SiBCN, SiN, SiOCN and SiO2.

[0017] Optionally, the material of the second sidewall spacer includes one or more of SiBCN, SiN, SiOCN and SiO2.

[0018] Optionally, the thickness of the first sidewall spacer is 1 nm to 8 nm; the thickness of the second sidewall spacer is 1 nm to 8 nm.

[0019] Optionally, the process of removing the first sidewall spacer includes: a wet etching process; process parameters of the wet etching process include: an etching solution including: an HF solution, wherein the volume ratio of H2O to HF in the HF solution is 10:1 to 1000:1.

[0020] Optionally, the process of removing the first side wall includes: a dry etching process; the process parameters of the dry etching process include: etching gas includes: NF3 gas and NH3 gas; the total gas flow rate is 10sccm~800sccm; the etching power is 5W~200W, the etching pressure is 1Torr~20mTorr; the etching temperature is 20℃~50℃.

[0021] Optionally, the material of the initial gate layer includes: polysilicon or metal.

[0022] Optionally, the process for forming the initial source / drain doping layer includes: an epitaxial growth process; and the material of the initial source / drain doping layer includes: silicon germanium.

[0023] Optionally, process parameters of the annealing treatment in a hydrogen atmosphere include: an annealing temperature of 900° C. to 1500° C.; an annealing pressure of 5 Torr to 30 Torr; and an annealing time of 2 min to 30 min.

[0024] Optionally, after the annealing treatment, the method further includes: removing the blocking structure.

[0025] Optionally, the process of removing the blocking structure includes: a wet etching process; the process parameters of the wet etching process include: an etching solution including: an H3PO4 solution.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the method for forming a semiconductor structure according to the technical solution of the present invention, the initial gate structure and the initial source-drain doped layer are annealed in a hydrogen atmosphere to form a gate structure, the gate structure is in contact with the second sidewall spacer, and the initial source-drain doped layer is formed into a source-drain doped layer, thereby effectively improving the line width roughness of the gate structure and the source-drain doped layer. When the line width roughness of the gate structure is improved, it can effectively improve the Vt mismatch and high LOFF problems, thereby improving the electrical performance of the device structure. When the line width roughness of the source-drain doped layer is improved, it is conducive to the subsequent formation of metal silicide on the source-drain doped layer, thereby reducing contact resistance and RC delay through the metal silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 13 1 is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the semiconductor structure formed by the prior art still has many problems, which will be described in detail below.

[0030] When the critical dimensions of semiconductor devices drop below 90nm, the impact of line width roughness (LWR) on integrated circuit processing technology can no longer be ignored, becoming one of the bottlenecks that seriously restrict the sustainable development of integrated circuits and related industries.

[0031] However, the gate formed by the etching process in the prior art has a high line width roughness, which may lead to Vt mismatch and high LOFF problems, thereby affecting the electrical performance of the ultimately formed semiconductor structure.

[0032] On this basis, the present invention provides a method for forming a semiconductor structure, wherein the initial gate structure and the initial source-drain doped layer are annealed in a hydrogen atmosphere to form a gate structure, the gate structure is in contact with the second sidewall spacer, and the initial source-drain doped layer is formed into a source-drain doped layer, thereby effectively improving the line width roughness of the gate structure and the source-drain doped layer. When the line width roughness of the gate structure is improved, the Vt mismatch and high LOFF problems can be effectively improved, thereby improving the electrical performance of the device structure; when the line width roughness of the source-drain doped layer is improved, it is conducive to the subsequent formation of metal silicide on the source-drain doped layer, and the metal silicide reduces the contact resistance and reduces the RC delay.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 13 1 is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0035] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a gate region I and source and drain regions II located on both sides of the gate region I.

[0036] In this embodiment, the substrate 100 is an insulating substrate Silicon on Insulator (SOI).

[0037] In other embodiments, the substrate may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0038] In this embodiment, the gate region I is used to subsequently form a gate structure on the gate region I, and the source and drain region II is used to subsequently form a source and drain doping layer in the source and drain region II.

[0039] In this embodiment, the method further includes forming a shallow trench isolation structure (not shown) in the substrate 100 .

[0040] Please refer to Figure 2 , an initial gate structure is formed on the gate region I, wherein the initial gate structure includes an initial gate dielectric layer 101 and an initial gate layer 102 located on the initial gate dielectric layer 101.

[0041] In this embodiment, the method for forming the initial gate structure includes: forming a gate dielectric material layer (not shown) on the substrate 100; forming a gate material layer (not shown) on the gate dielectric material layer; and performing a patterning process on the gate dielectric material layer and the gate material layer to form the initial gate dielectric layer 101 and the initial gate layer 102.

[0042] The formation process of the gate dielectric material layer and the gate material layer includes: one of: low pressure chemical vapor deposition process (LPCVD), plasma enhanced chemical vapor deposition process (PECVD), ultra-high vacuum chemical vapor deposition process (UHVCVD), rapid thermal chemical vapor deposition process (RTCVD), physical vapor deposition process (PVD), atomic layer deposition process (ALD) and molecular beam epitaxy process (MBE).

[0043] In this embodiment, the gate dielectric material layer and the gate material layer are formed by a chemical vapor deposition process.

[0044] In this embodiment, the material of the initial gate dielectric layer 101 is SiO 2 .

[0045] In this embodiment, the material of the initial gate layer 102 is polysilicon; in other embodiments, the material of the initial gate layer may also be metal.

[0046] Please refer to Figure 3 A sidewall spacer structure is formed on the sidewall of the initial gate structure, and the sidewall spacer structure includes a first sidewall spacer 103 located on the sidewall of the initial gate structure and a second sidewall spacer 104 located on the sidewall of the first sidewall spacer 103 .

[0047] In this embodiment, the material of the first sidewall 103 is different from the material of the second sidewall 104 .

[0048] The material of the first sidewall spacer 103 includes one or more of SiBCN, SiN, SiOCN and SiO 2 ; the material of the second sidewall spacer 104 includes one or more of SiBCN, SiN, SiOCN and SiO 2 .

[0049] In this embodiment, the first sidewall spacer 103 is made of SiBCN, and the second sidewall spacer 104 is made of SiN.

[0050] In this embodiment, the thickness of the first sidewall spacer 103 is 1 nm to 8 nm; the thickness of the second sidewall spacer 104 is 1 nm to 8 nm.

[0051] After forming the sidewall structure, the method further includes forming a blocking structure on the substrate 100, wherein the blocking structure has a blocking opening, and the blocking opening exposes the top surface of the source and drain region II. Figures 4 to 8 .

[0052] Please refer to Figure 4 , forming an auxiliary structure 105 on the source and drain region II.

[0053] In this embodiment, the method for forming the auxiliary structure 105 includes: forming an auxiliary material layer (not shown) on the substrate 100 ; and patterning the auxiliary material layer to form the auxiliary structure 105 .

[0054] In this embodiment, the auxiliary structure 105 is made of SiO2.

[0055] Please refer to Figure 5 A barrier material layer 106 is formed on the sidewalls and top surface of the auxiliary structure 105, the top surface of the substrate 100, the sidewalls and top surface of the spacer structure, and the top surface of the initial gate structure.

[0056] The formation process of the barrier material layer 106 includes: one of: low pressure chemical vapor deposition process (LPCVD), plasma enhanced chemical vapor deposition process (PECVD), ultra-high vacuum chemical vapor deposition process (UHVCVD), rapid thermal chemical vapor deposition process (RTCVD), physical vapor deposition process (PVD), atomic layer deposition process (ALD) and molecular beam epitaxy process (MBE).

[0057] In this embodiment, the barrier material layer 106 is formed by a low pressure chemical vapor deposition process.

[0058] In this embodiment, the thickness of the barrier material layer 106 is 5 nm to 10 nm.

[0059] In this embodiment, the material of the barrier material layer 106 is different from that of the auxiliary structure 105 , in order to reduce etching damage to the barrier structure during the subsequent removal of the auxiliary structure 105 .

[0060] In this embodiment, the barrier material layer 106 is made of Si 3 N 4 .

[0061] Please refer to Figure 6 A sacrificial layer 107 is formed on the barrier material layer 106 , and the sacrificial layer 107 exposes the barrier material layer 106 located on the top surface of the auxiliary structure 105 , and the top surfaces of the spacer structure and the initial gate structure.

[0062] In this embodiment, the method for forming the sacrificial layer 107 includes: forming a sacrificial material layer (not shown) on the surface of the barrier material layer 106 ; and etching back the sacrificial material layer to form the sacrificial layer 107 .

[0063] In this embodiment, the sacrificial material layer is formed by a spin coating process.

[0064] In this embodiment, the sacrificial layer 107 is made of an organic anti-reflective coating material.

[0065] In this embodiment, the etching gas for etching back the sacrificial material layer includes: O2 and SO2; the total flow rate of the etching gas is 2 sccm to 80 sccm; the etching power is 100 W to 2000 W; and the etching pressure is 2 mTorr to 30 mTorr.

[0066] Please refer to Figure 7 Using the sacrificial layer 107 as a mask, the blocking material layer 106 located on the top surface of the auxiliary structure 105 and the top surfaces of the sidewall structure and the initial gate structure is etched back to form the blocking structure 108 .

[0067] In this embodiment, the etching gas used for back etching to remove the blocking material layer 106 located on the top surface of the auxiliary structure 105, as well as the top surface of the sidewall structure and the initial gate structure is CF4 plasma; the total gas flow rate is 2sccm~100sccm; the etching power is 50W~2000W; and the etching pressure is 2mTorr~30mTorr.

[0068] In this embodiment, a blocking opening 109 is defined in the blocking structure 108 , and the blocking opening 109 exposes the top surface of the source / drain region II.

[0069] Please refer to Figure 8 After forming the blocking structure 105, the sacrificial layer is removed; after removing the sacrificial layer, the auxiliary structure is removed.

[0070] The process of removing the sacrificial layer 107 includes a dry ashing process or a wet etching process. In the dry ashing process, the plasma gas source is oxygen or nitrogen and the carrier gas is hydrogen; in the wet etching process, the etching solution is H3PO4.

[0071] In this embodiment, the process of removing the sacrificial layer 107 adopts a dry ashing process.

[0072] Please refer to Figure 9 The source / drain region II is etched using the blocking structure 108 as a mask to form a source / drain opening 110 in the source / drain region.

[0073] In this embodiment, the source / drain openings 110 define the size and position of the subsequently formed source / drain doped layers.

[0074] In this embodiment, the process of etching the source / drain region II adopts a wet etching process.

[0075] Please refer to Figure 10 , an initial source-drain doping layer 111 is formed in the source-drain opening 110 , and the initial source-drain doping layer 111 fills the source-drain opening 110 and extends into the blocking opening 109 .

[0076] In this embodiment, the initial source / drain doping layer 111 is formed by an epitaxial growth process.

[0077] In this embodiment, the material of the initial source / drain doping layer 111 is silicon germanium.

[0078] In this embodiment, the initial source-drain doped layer 111 contains source-drain ions, which are doped into the initial source-drain doped layer 111 through an in-situ doping process during the epitaxial growth process.

[0079] The source and drain ions include: N-type ions or P-type ions. In this embodiment, the source and drain ions are N-type ions.

[0080] Please refer to Figure 11 After forming the initial source-drain doped layer 111 , the first sidewall spacer 103 is removed, and a gap 112 is formed between the second sidewall spacer 104 and the initial gate structure.

[0081] In this embodiment, the process of removing the first sidewall spacer 103 adopts a wet etching process; the process parameters of the wet etching process include: the etching solution includes: HF solution, wherein the volume ratio of H2O and HF in the HF solution is 10:1 to 1000:1.

[0082] In other embodiments, the process of removing the first side wall can also adopt a dry etching process; the process parameters of the dry etching process include: etching gas includes: NF3 gas and NH3 gas; the total gas flow rate is 10sccm~800sccm; etching power is 5W~200W, etching pressure is 1Torr~20mTorr; etching temperature is 20℃~50℃.

[0083] Please refer to Figure 12 , the initial gate structure and the initial source-drain doped layer 111 are annealed in a hydrogen atmosphere so that the initial gate structure forms a gate structure, the gate structure contacts the second sidewall 104, and the initial source-drain doped layer 111 forms a source-drain doped layer 113.

[0084] In this embodiment, the gate structure includes a gate dielectric layer 114 and a gate layer 115 located on the gate dielectric layer 114 .

[0085] In this embodiment, the gate dielectric layer 114 is formed from the initial gate dielectric layer, so the material of the gate dielectric layer 115 is also SiO 2 .

[0086] In this embodiment, the gate layer 115 is formed by the initial gate layer, so the material of the gate layer 115 is also polysilicon; in other embodiments, when the material of the initial gate layer is metal, the material of the gate layer is also metal.

[0087] In this embodiment, the process parameters of the annealing treatment in a hydrogen atmosphere include: an annealing temperature of 900° C. to 1500° C.; an annealing pressure of 5 Torr to 30 Torr; and an annealing time of 2 min to 30 min.

[0088] In this embodiment, since the initial gate structure will be extended during the annealing process, the gap 112 provides space for the extension of the initial gate structure.

[0089] In this embodiment, the annealing process in a hydrogen atmosphere can remove the natural oxide layer in the epitaxial silicon. The heated hydrogen facilitates the migration of silicon at a temperature below the melting point of silicon (1414°C), rounding the sharp corners formed in the etching step, effectively improving the line width roughness of the gate structure and the source / drain doped layer 113. When the line width roughness of the gate structure is improved, the Vt mismatch and high LOFF issues can be effectively alleviated, thereby improving the electrical performance of the device structure. When the line width roughness of the source / drain doped layer 113 is improved, it is conducive to the subsequent formation of metal silicide on the source / drain doped layer 113, which reduces the contact resistance and reduces the RC delay.

[0090] Please refer to Figure 13 After the annealing process, the blocking structure 108 is removed.

[0091] In this embodiment, the process of removing the blocking structure 108 includes: a wet etching process; the process parameters of the wet etching process include: an etching solution including: an H 3 PO 4 solution.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a gate region and source and drain regions located on both sides of the gate region; forming an initial gate structure on the gate region, the initial gate structure comprising an initial gate dielectric layer and an initial gate layer located on the initial gate dielectric layer; forming a sidewall spacer structure on a sidewall of the initial gate structure, wherein the sidewall spacer structure includes a first sidewall spacer located on the sidewall of the initial gate structure and a second sidewall spacer located on a sidewall of the first sidewall spacer; forming a blocking structure on the substrate, wherein the blocking structure has a blocking opening therein, and the blocking opening exposes the top surface of the source and drain regions; Etching the source / drain region using the blocking structure as a mask to form source / drain openings in the source / drain region; forming an initial source-drain doping layer in the source-drain opening, wherein the initial source-drain doping layer completely fills the source-drain opening and extends into the blocking opening; After forming the initial source-drain doped layer, removing the first sidewall spacer to form a gap between the second sidewall spacer and the initial gate structure; Annealing is performed on the initial gate structure and the initial source-drain doped layer in a hydrogen atmosphere, so that the initial gate structure forms a gate structure, the gate structure contacts the second sidewall spacer, and the initial source-drain doped layer forms a source-drain doped layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the blocking structure includes: forming an auxiliary structure on the source and drain region; forming a blocking material layer on the sidewall and top surface of the auxiliary structure, the top surface of the substrate, the sidewall and top surface of the sidewall structure, and the top surface of the initial gate structure; forming a sacrificial layer on the blocking material layer, the sacrificial layer exposing the blocking material layer located on the top surface of the auxiliary structure, the sidewall structure and the top surface of the initial gate structure; using the sacrificial layer as a mask, etching back to remove the blocking material layer located on the top surface of the auxiliary structure, the sidewall structure and the top surface of the initial gate structure to form the blocking structure; after forming the blocking structure, removing the sacrificial layer; and after removing the sacrificial layer, removing the auxiliary structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the sacrificial layer includes: forming a sacrificial material layer on the surface of the barrier material layer; and etching back the sacrificial material layer to form the sacrificial layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: The material of the sacrificial layer includes: organic anti-reflection coating material.

5. The method for forming a semiconductor structure according to claim 2, wherein: The process of removing the sacrificial layer includes a dry ashing process or a wet etching process.

6. The method for forming a semiconductor structure according to claim 2, wherein: The thickness of the barrier material layer is 5 nm to 10 nm.

7. The method for forming a semiconductor structure according to claim 2, wherein: The material of the barrier material layer is different from the material of the auxiliary structure.

8. The method for forming a semiconductor structure according to claim 2, wherein: The material of the barrier material layer includes: Si3N4.

9. The method for forming a semiconductor structure according to claim 2, wherein: The material of the auxiliary structure includes: SiO2.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sidewall spacer is different from the material of the second sidewall spacer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first sidewall spacer includes one or more of SiBCN, SiN, SiOCN and SiO2.

12. The method for forming a semiconductor structure according to claim 10, wherein: The material of the second sidewall spacer includes one or more of SiBCN, SiN, SiOCN and SiO2.

13. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first sidewall spacer is 1 nm to 8 nm; the thickness of the second sidewall spacer is 1 nm to 8 nm.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first sidewall spacer includes: a wet etching process; the process parameters of the wet etching process include: the etching solution includes: an HF solution, wherein the volume ratio of H2O to HF in the HF solution is 10:1 to 1000:

1.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the first side wall includes: a dry etching process; the process parameters of the dry etching process include: etching gas includes: NF3 gas and NH3 gas; the total gas flow rate is 10sccm~800sccm; the etching power is 5W~200W, the etching pressure is 1Torr~20mTorr; the etching temperature is 20℃~50℃.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial gate layer includes: polysilicon or metal.

17. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the initial source-drain doped layer includes an epitaxial growth process; and the material of the initial source-drain doped layer includes silicon germanium.

18. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the annealing treatment in the hydrogen atmosphere include: an annealing temperature of 900° C. to 1500° C.; an annealing pressure of 5 Torr to 30 Torr; and an annealing time of 2 min to 30 min.

19. The method for forming a semiconductor structure according to claim 1, wherein: After the annealing process, the method further includes: removing the blocking structure.

20. The method for forming a semiconductor structure according to claim 19, wherein: The process of removing the blocking structure includes: a wet etching process; the process parameters of the wet etching process include: an etching solution including: an H3PO4 solution.

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