Application of protective ALD or PECVD layer on semiconductor die connected to substrate via sintered layer

Abstract

The present disclosure relates to application of a protective ALD or PECVD layer over a semiconductor die connected to a substrate via a sintered layer. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; applying a layer of sinter paste to the substrate; placing a semiconductor die on or over the sintered paste layer; performing a sintering process to convert the sintered paste layer into a sintered layer; and applying a protective layer onto the semiconductor die and the sintered layer by atomic layer deposition or by plasma enhanced chemical layer deposition.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device by connecting a semiconductor die to a substrate via a sintering layer and applying a protective layer on the semiconductor die and on a portion of the sintering layer by atomic layer deposition, and to a semiconductor device. Background Art

[0002] An electronic device (e.g., a power electronic device) may include a semiconductor die or semiconductor chip attached to a chip pad of a substrate, such as DCB (direct copper bonding), AMB (active metal brazing), or a lead frame. One example of a bonding technique for attaching the die to the pad includes sintering, wherein a paste layer is arranged between the die and the pad and pressure and / or temperature is applied to produce a sintered metal layer from the paste layer.

[0003] However, experience with such sintered semiconductor die-substrate compounds has shown that corrosion problems may occur. Specifically, as is well known in the industry, when exposed to moisture at elevated temperatures, the following two types of corrosion in the die back metallization stack will cause significant technical problems. Specifically, two types of corrosion are known, and the situation they have in common is related to the degradation of the metal layer / interface in the chip back metallization stack. The first type of corrosion is halide-induced corrosion of the various layers (e.g., aluminum layer) in the back metallization stack. The second type of corrosion is oxidative corrosion at the interface between the various layers of the chip back metallization stack (e.g., NiV / Ag or Ni / Ag or NiSi / Ag interface), which is caused by oxygen diffused through the sintered layer and the lowest Ag layer of the back metallization stack. These two corrosion problems may weaken and / or ultimately destroy the interconnection.

[0004] For these and other reasons, there is a need for the present disclosure. Summary of the invention

[0005] Due to the growing demand for higher operating temperatures of power modules, especially in automotive applications, currently basically all power module manufacturers are introducing new packaging technologies. One core technology is the so-called low temperature joining technology (LTJT), which is generally referred to as silver sintering. An example of silver sintering as a die attach technology will be explained below. In short, fine silver powder (usually provided in the form of paste) is placed between the two parts to be joined, which can be (for example) a die and a DCB (direct copper bonding) or AMB (active metal brazing) substrate. After that, the entire assembly is heated to a temperature between 200 and 300°C, preferably (but not necessarily) under externally applied pressure, for example, in a pressurizer at a pressure in the range of 5 to 30 MPa for a duration in the range of 1 to 60 minutes. Under these conditions, the fine silver particles begin to sinter, that is, they "grow together" or sinter, thereby forming a fairly compact silver layer by a diffusion mechanism. Since this layer consists essentially of pure silver (Ag), it exhibits a melting point of 961°C, which is much higher than that of solder interconnects. This is a major factor in the superior properties of silver sintered interconnects when operating at elevated temperatures (e.g., T>=175°C) compared to solder interconnects.

[0006] The process described above can also be performed with fine particles composed of metals other than Ag (e.g., Cu or precious metal powders or mixtures thereof). The present disclosure is independent of the nature of the particulate metal used to make the sintered interconnect. Therefore, the term silver sintering continues to be used here, but it implies that Cu or other sintering materials will also be beneficial to some extent.

[0007] Sintered bonds differ fundamentally from soldered bonds in two main aspects: the first is related to the microstructure of the sintered layer, regardless of the material it is made of (e.g., Ag, Cu, etc.), while the second is specifically applicable to sintered layers made of Ag. Both are described below.

[0008] Figure 1 A metallographic cross section of a semiconductor die 13 attached to a copper substrate 11 by a sintered silver layer 12 is shown. Depending on the exact nature of the process involved in making this sintered layer 12, there will often be some degree of open porosity (via the sintered layer 12) near the edge of the semiconductor die 13. Figure 1). In this context, the term "open" refers to the presence of a network of interconnected pores that have connectivity to the outside. This region includes a bulge 12A of the sintered layer 12 that does not cover the semiconductor die 13 but often extends laterally below the semiconductor die 13. The extent of the region with open pores near the semiconductor die 13 depends strongly on the exact nature and conditions of the process used to manufacture the sintered layer 12, but in principle always exists to a certain extent. In addition to this microstructural porosity, the sintered layer composed of silver has another type of permeability. It is well known that at elevated temperatures, silver becomes highly permeable to oxygen. That is, oxygen can easily diffuse through the bulk silver even in the absence of an open pore network.

[0009] Although the aforementioned aspects are generally not a problem from a mechanical / thermal / electrical point of view, they will contribute to certain corrosion mechanisms in the sintered joint. Firstly, the areas close to the die edge, i.e. those areas with open porosity, can trap substances during further processing of the sintered die-substrate arrangement. In the simplest form, this could be water, but could also be highly corrosive substances from subsequent chemical process steps. These trapped substances can then cause or promote corrosion in two ways:

[0010] 1) The trapped material directly corrodes the sintered layer material and the die or substrate surface to which the sintered layer is attached.

[0011] 2) The trapped material may gradually leave voids in the sintered layer and subsequently affect the sidewalls of the semiconductor die and other susceptible areas adjacent to the edge of the sintered bond.

[0012] However, the capture of corrosive species may not occur only during processing. Moisture and other corrosive species may also be introduced during operation of the power device. Since most encapsulation materials are permeable to water corrosion to some extent, water can pass through the encapsulation material and travel into the open pores of the sintered layer. The situation becomes more serious in the case where the moisture carries additional species that are corrosive (most notably halides, such as chlorine (Cl)) or carries additional species that have the ability to change the electrical characteristics of the tube core (for example, alkali metals, such as potassium (K) or sodium (Na)).

[0013] The second type of corrosion applies to sintered joints that include only silver. Most commonly, silver is present as the sintering material itself, but it is also common to have a terminating silver layer on the back of the die and / or the substrate surface to facilitate sintering. Due to the aforementioned reasons that silver is permeable to oxygen, oxygen can diffuse through all of these silver layers at typical processing temperatures and also under conditions that a power device may experience during operation. Thus, oxygen can corrode the material layers that are located below the terminating silver metallization layers of the die and / or substrate.

[0014] The present disclosure provides a solution to the above-mentioned problems, which is to manufacture a protective layer that can successfully improve the robustness of the semiconductor die against corrosion / degradation caused by moisture and / or corrosive / harmful elements. The focus will be on sintered die-substrate arrangements, because the failure mechanism described above is unique to these arrangements, because the solder die attach layers are generally dense and do not contain areas with open porosity. They are also not composed of pure silver and are therefore impermeable to oxygen at elevated temperatures.

[0015] A first aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: providing a substrate; providing a semiconductor die; applying a sintering paste layer on one or both of the substrate and the semiconductor die; placing the semiconductor die on the substrate; performing a sintering process to convert the sintering paste layer into a sintering layer; and applying a protective layer to the semiconductor die and a portion of the sintering layer by atomic layer deposition (ALD) or by plasma enhanced chemical vapor deposition (PECVD).

[0016] According to an embodiment of the method of the first aspect, a frit paste drying process may be performed after applying the frit paste layer.

[0017] According to an embodiment of the method of the first aspect, the protective layer comprises an oxide layer, in particular a metal oxide layer, for example, one or more of an Al2O3, ZrO, TiO, Ta2O5 layer or a HfO2 layer. Otherwise, the oxide layer may also comprise a SiO layer.

[0018] According to an embodiment of the method of the first aspect, the protective layer comprises a sandwich structure, which comprises two or more layers of different materials stacked on each other. Specifically, the sandwich structure may comprise two or more layers of the aforementioned materials.

[0019] According to an embodiment of the method of the first aspect, the protective layer comprises a thickness in the range of 3 nm to 200 nm.

[0020] According to an embodiment of the method of the first aspect, applying the protective layer by atomic layer deposition is performed at a temperature lying in the temperature range between room temperature and 250°C.

[0021] According to an embodiment of the method of the first aspect, applying the protective layer by plasma enhanced chemical vapor deposition is performed at a temperature lying in the temperature range between 200°C and 400°C.

[0022] According to an embodiment of the method of the first aspect, the semiconductor die comprises a back metallization layer, and wherein the sintering paste layer is applied to the back metallization layer. The back metallization layer may, for example, comprise a single layer or two or more layers in the form of a layer stack. The layer stack may, for example, comprise two or more layers consisting of Al, Ti, NiV and Ag, wherein the Al layer may be applied directly to the back of the semiconductor die, and the Ag layer may be the lowest layer in direct contact with the sintering layer.

[0023] According to an embodiment of the method of the first aspect, applying the frit paste layer comprises one or more of a printing process, a dispensing process or a process of transferring the paste from a film onto the substrate or the semiconductor die.

[0024] According to an embodiment of the method of the first aspect, wherein the sintered paste layer comprises silver particles embedded in the paste.

[0025] According to an embodiment of the method of the first aspect, the substrate is one or more of a base board, a direct copper bond (DCB), an active metal brazing (AMB), an insulated metal substrate (IMS) and a lead frame.

[0026] A second aspect of the present disclosure relates to a semiconductor device comprising: a substrate; a sintered layer disposed on the substrate; a semiconductor die disposed on or over the sintered layer; and a protective layer applied to the semiconductor die and the sintered layer by atomic layer deposition.

[0027] According to an embodiment of the semiconductor device of the second aspect, the protective layer comprises an oxide layer, in particular a metal oxide layer, for example, one or more of Al2O3, ZrO, TiO, Ta2O5 or HfO2 layers. Otherwise, the oxide layer may also comprise a SiO layer.

[0028] According to an embodiment of the semiconductor device of the second aspect, the protection layer comprises a sandwich structure, which comprises two or more layers of different materials stacked on each other. Specifically, the sandwich structure may comprise two or more layers of the aforementioned materials.

[0029] According to an embodiment of the semiconductor device of the second aspect, the protection layer comprises a thickness in the range of 3 nm to 200 nm.

[0030] According to an embodiment of the semiconductor device of the second aspect, the semiconductor die includes a back metallization layer, and the semiconductor die is arranged so that the back metallization layer is located on or above the sintered layer. The back metallization layer may (for example) include a single layer or two or more layers in the form of a layer stack. The layer stack may include two or more layers consisting of Al, Ti, Ni, NiV, NiSi and Ag, wherein the Al layer may be directly applied to the back of the semiconductor die, and the Ag layer may be the lowest layer in direct contact with the sintered layer.

[0031] According to an embodiment of the semiconductor device of the second aspect, wherein the sintering paste layer comprises silver particles embedded in the paste.

[0032] According to an embodiment of the semiconductor device of the second aspect, the substrate is one or more of a base board, a direct copper bonding (DCB), an active metal brazing (AMB), an insulated metal substrate (IMS), and a lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and together with the written description serve to explain the principles of the embodiments. Other embodiments and many of the expected advantages of the embodiments will be readily appreciated as they will be better understood by reference to the detailed description below.

[0034] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0035] Figure 1 As already described above a metallographic cross section of a semiconductor die attached to a copper substrate by means of a sintered silver layer is shown.

[0036] Figure 2A and Figure 2B An example of a semiconductor device including a semiconductor die attached to a substrate via a sintering layer without using a protective layer is shown ( Figure 2A ) and the same semiconductor device after corrosion damage ( Figure 2B ) is shown in a cross-sectional side view.

[0037] Figure 3 A cross-sectional side view representation of an example of a semiconductor device according to the second aspect is shown, the semiconductor device comprising a semiconductor fin die attached to a substrate via a sintering layer and a protective layer covering the semiconductor die and portions of the sintering layer.

[0038] Figure 4 A cross-sectional side view representation of an example of a semiconductor device according to the second aspect is shown, the semiconductor device corresponding to Figure 2A and Figure 2B An example of a semiconductor device shown in , this time with a protective layer covering the semiconductor die and part of the sintered layer.

[0039] Figure 5 A schematic side view illustrating one cycle of an atomic layer deposition process is shown. DETAILED DESCRIPTION

[0040] In the detailed description section below, reference will be made to the accompanying drawings that constitute a part thereof, in which specific embodiments in which the present disclosure can be practiced are shown by way of example. In this regard, directional terms such as "top", "bottom", "front", "back", "leading", "trailing", etc. will be used with reference to the orientation of the (multiple) drawings being described. Since the components of the embodiments may be placed in many different orientations, the directional terms are only used for illustrative purposes and are not limiting in any way. It should be understood that other embodiments may be adopted and structural and logical changes may be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limited sense, and the scope of the present disclosure is defined by the appended claims.

[0041] It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0042] As used in this specification, the terms "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" are not intended to mean that elements or layers must be directly in contact together; intervening elements or layers may be provided between the elements that are "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled", respectively. However, according to the present disclosure, the above-mentioned terms may also optionally have the specific meaning that the elements or layers are directly in contact together, that is, no intervening elements or layers are provided between the elements that are "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled", respectively.

[0043] In addition, the word "on" used herein in connection with a part, element or material layer formed or located "on" a surface can be used to indicate that the part, element or material layer can be positioned (e.g., placed, formed, deposited, etc.) indirectly on the implied surface, wherein one or more additional parts, elements or layers are arranged between the implied surface and the part, element or material layer. However, the word "on" used in connection with a part, element or material layer formed or located "on" a surface can optionally also have the following specific meaning: the part, element or material layer can be positioned (e.g., placed, formed, deposited, etc.) directly on the implied surface, for example, in direct contact with it.

[0044] Detailed Description

[0045] Figure 2A and Figure 2B An example of a semiconductor device including a semiconductor die attached to a substrate via a sintering layer without using a protective layer is shown ( Figure 2A ) and the same semiconductor device after corrosion damage ( Figure 2B ) is shown in a cross-sectional side view.

[0046] More specifically, Figure 2A A semiconductor device 10 is shown comprising a substrate 11, a sintered layer 12 applied to the substrate 11, and a semiconductor die 13 arranged above the sintered layer 12. The substrate 11 is a direct copper bonded part comprising a central ceramic layer 11.1, an upper metal layer 11.2 and a lower metal layer 11.2. A backside metallization stack 14 is arranged on the backside of the semiconductor die 13, the backside metallization stack comprising an Al layer 14.1, a Ti layer 14.2, a NiV layer 14.3 and an Ag layer 14.4, which are arranged in this order starting from the backside of the semiconductor die 13.

[0047] The semiconductor die 13 may be a semiconductor power transistor die, such as an IGBT, a MOSFET, a SiCMOS, or a CoolMOS. Here, the term "power semiconductor transistor die" may refer to a semiconductor die that provides at least one of a high voltage blocking capability or a high current carrying capability. The power semiconductor die may be configured for a high current having a maximum current value of several amperes (e.g., 10A, 250A, 600A, 1000A) or a maximum current value that may be as high as or even exceed 1000A. Similarly, the voltage associated with such a current value may have a value of several volts to tens, hundreds, or even thousands of volts.

[0048] Figure 2B The same semiconductor device 10 is shown, but this time with additional arrows drawn to illustrate the damaging effects of foreign matter entering the device. Thus, the upper arrow illustrates that penetrating chlorine may lead to decomposition of the Al layer 14.1, as illustrated by the depression thereby created in the Al layer 14.1, while the lower arrow illustrates the formation of an undesirable NiV oxide layer 14.3A below the NiV layer 14.3 due to penetration of oxygen or water.

[0049] The sintering paste layer applied before the sintering process is carried out has silver particles embedded in the paste, which are baked together by the sintering process under the effect of pressure and / or temperature, thereby forming a continuous conductive layer. However, the sintering process also causes the sintered material to flow out at the side edges and form lateral bulges 12A with a relatively high porosity, as explained above. Due to their porosity and the porosity also present in the edge area of ​​the sintered layer 12, undesired penetration of foreign matter is promoted. As an alternative to silver, metals such as copper or precious metal powders or mixtures thereof can also be used.

[0050] Figure 3 A cross-sectional side view representation of an example of a semiconductor device according to the second aspect is shown, the semiconductor device comprising a semiconductor die attached to a substrate via a sintering layer and a protective layer covering the semiconductor die and parts of the sintering layer.

[0051] More specifically, Figure 3 A semiconductor device 20 is shown comprising a substrate 1, a sintered layer 2 applied to the substrate 1, and a semiconductor die 3 arranged above the sintered layer 2. The sintered layer further comprises a bulge 2A as shown in FIG. 2. A back metallization 4 is arranged on the back side of the semiconductor die 3. The back metallization 4 may be a single layer or two or more layers in the form of a layer stack. The latter example will be described in connection with FIG. Figure 4 The substrate 1 may be one or more of a base board, direct copper bonding (DCB), active metal brazing (AMB), insulated metal substrate (IMS), and a lead frame.

[0052] A protective layer 5 is additionally applied to the upper and side surfaces of the semiconductor die 3, the side surfaces of the back metallization 4 and parts of the sintered layer 2 and the bulge 2A to protect the entire assembly from direct reactions with undesirable substances. This protective layer 5 can be deposited by atomic layer deposition and can, for example, comprise Al2O3.

[0053] Figure 4 A cross-sectional side view representation of an example of a semiconductor device according to the second aspect is shown, which corresponds to the example of a semiconductor device as shown in FIG. 2 , this time with a protection layer covering the semiconductor die and part of the sintered layer.

[0054] More specifically, Figure 4A semiconductor device 30 is shown comprising a substrate 11, a sintered layer 12 applied to the substrate 11, and a semiconductor die 13 arranged above the sintered layer 12. The substrate 11 is a direct copper bond comprising a central ceramic layer 12.1, an upper metal layer 12.2 and a lower metal layer 12.2. A backside metallization stack 14 is arranged on the backside of the semiconductor die 13, the backside metallization stack comprising an Al layer 14.1, a Ti layer 14.2, a NiV layer 14.3 and an Ag layer 14.4, which are arranged in this order starting from the backside of the semiconductor die 13.

[0055] So far, the semiconductor device 30 is still Figure 2A and Figure 2B The same semiconductor device 10 is shown. However, now a protective layer 15 is additionally applied to the upper and side surfaces of the semiconductor die 13, the side surfaces of the metallization stack 14, and parts of the sintered layer 12 and the bulge 12A to protect the entire assembly from the penetration of undesirable substances. This protective layer 15 can be deposited by atomic layer deposition and can, for example, include Al2O3.

[0056] Figure 5 A schematic side view illustrating one cycle of an atomic layer deposition process is shown.

[0057] ALD relies on sequential self-limiting surface reactions between gas-phase precursor molecules and solid surfaces to achieve atomic-layer control over deposition, such as Figure 5 Steps 1 to 4 in are schematically shown. The surface is first exposed to a precursor, which reacts with all the initial surface sites. Afterwards, after purging the byproducts produced by this first reaction, the surface is exposed to an oxidant. This reaction regenerates the initial functional groups and prepares the surface for the next exposure to the precursor. By repeating this sequence, the film is grown to the desired thickness.

[0058] exist Figure 5The initial situation is shown in the leftmost simplified diagram of , where a substrate terminated with OH groups is provided. Such a substrate is exposed to a pulse of trimethylaluminum vapor (TMA, typically with an exposure time of several seconds) as a precursor (step 1). TMA molecules are adsorbed on all exposed surfaces in the chamber and within pores, holes, etc. in the sample. This deposition is self-limiting because the TMA molecules are chemically adsorbed by reacting with OH groups on the surface. Once all available OH groups are consumed, there will be no more TMA adsorption (step 2). The TMA pulse is followed by emptying the reaction chamber by purging or pumping out, where (for example) water vapor is introduced after the pulse of the reagent (step 3). The water vapor reacts with the adsorbed TMA and hydrolyzes the residual methyl groups. This surface reaction brings about the formation of a (sub) monoatomic layer of aluminum oxide. Then, the presence of a first aluminum oxide layer terminated with OH groups will be noted (step 4). Therefore, the ALD process can be repeated over and over again, depositing each film in a manner of one (often fractional) atomic layer at a time.

[0059] As an alternative to the ALD process, a plasma enhanced chemical vapor deposition (PECVD) process can also be used to deposit the protective layer 5 or 15. As is well known, PECVD is a chemical vapor deposition process used to deposit thin films from a gaseous state (steam) to a solid state on a substrate. Chemical reactions are involved in this process, which occur after the plasma of the reaction gas is established. The plasma is generally established by radio frequency (RF) alternating current (AC) or direct current (DC) discharge between two electrodes, and the space between the two electrodes is filled with a reaction gas. In order to deposit Al2O3, for example, the process gases N2O and Al(CH3)3 used need to be dissociated and rearranged to form Al2O3 and other molecules. Compared with ALD films, the mass density of PECVD Al2O3 films is normally significantly lower.

[0060] Example

[0061] Hereinafter, the following specific examples of the present disclosure will be described.

[0062] Example 1 is a method for manufacturing a semiconductor device, the method comprising: providing a substrate; providing a semiconductor die; applying a sintering paste layer on one or both of the substrate and the semiconductor die; placing the semiconductor die on the substrate; performing a sintering process to convert the sintering paste layer into a sintering layer; and depositing a protective layer onto the semiconductor die and a portion of the sintering layer by atomic layer deposition or by plasma enhanced chemical vapor deposition.

[0063] Example 2 is the method according to Example 1, further comprising: a frit paste drying process after applying the frit paste layer.

[0064] Example 3 is the method according to Example 1 or 2, wherein the protective layer comprises an oxide layer.

[0065] Example 4 is the method according to Example 3, wherein the protective layer comprises a metal oxide layer.

[0066] Example 5 is a method according to Example 4, wherein the protective layer includes one or more of Al2O3, ZrO, TiO, or Ta2O5.

[0067] Example 6 is the method according to Example 3, wherein the protective layer comprises SiO.

[0068] Example 7 is a method according to any one of the preceding examples, wherein the protective layer comprises a sandwich structure including two or more layers of different materials stacked on top of each other.

[0069] Example 8 is a method according to any of the preceding examples, wherein the protective layer comprises a thickness in a range between 3 nm and 200 nm.

[0070] Example 9 is the method of any of the preceding examples, wherein the semiconductor die includes a backside metallization layer, and wherein the frit paste layer is applied to the backside metallization layer.

[0071] Example 10 is the method of any of the preceding examples, wherein applying the frit paste layer comprises a printing process.

[0072] Example 11 is the method of any of Examples 1 to 9, wherein applying the sintering paste layer includes transferring the paste from a film to the substrate.

[0073] Example 12 is a semiconductor device comprising: a substrate; a sintered layer disposed on the substrate; a semiconductor die disposed on or over the sintered layer; and a protective layer applied to the semiconductor die and the sintered layer by atomic layer deposition or by plasma enhanced chemical vapor deposition.

[0074] Example 13 is a semiconductor device according to Example 12, wherein the protective layer includes an oxide layer.

[0075] Example 14 is a semiconductor device according to Example 13, wherein the protective layer includes a metal oxide layer.

[0076] Example 15 is a semiconductor device according to Example 14, wherein the protective layer includes one or more of Al2O3, ZrO, TiO, Ta2O5 or HfO2.

[0077] Example 16 is a semiconductor device according to Example 13, wherein the protective layer includes SiO.

[0078] Example 17 is a semiconductor device according to any one of Examples 12 to 16, wherein the protective layer includes a single layer or a sandwich structure including two or more layers of different materials stacked on each other.

[0079] Example 18 is a semiconductor device according to any one of Examples 12 to 17, wherein the protective layer comprises a thickness in a range between 3 nm and 200 nm.

[0080] Example 19 is a semiconductor device according to any one of Examples 11 to 18, wherein the semiconductor die includes a back side metallization layer, and the semiconductor die is arranged such that the back side metallization layer is located on or over the sintering layer.

[0081] In addition, although specific features or aspects of embodiments of the present disclosure may have been disclosed in connection with only one of several embodiments, such features or aspects may be combined with one or more other features or aspects of other embodiments where it is expected and advantageous for any given or specific application. In addition, to the extent that the terms "including," "having," "with," or variations thereof are used in specific embodiments and / or claims, it is intended that such terms be presented as inclusive in a manner similar to the term "comprising." In addition, it should be understood that embodiments of the present disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming mechanisms. Moreover, the term "exemplary" is meant only as an example and is not meant to be optimal or ideal. It should also be recognized that, for the purpose of making understanding simple and easy, the features and / or elements illustrated herein are illustrated as having specific dimensions relative to each other, and the actual dimensions may be significantly different from those illustrated herein.

[0082] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that various alternative and / or equivalent implementations may be substituted for the illustrated and described specific embodiments without departing from the scope of the present disclosure. The present application is intended to cover any adjustments or variations of the specific embodiments discussed herein. Therefore, it is intended that the present disclosure be limited only by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; providing semiconductor dies; applying a sintering paste layer on one or both of the substrate and the semiconductor die; placing the semiconductor die on the substrate; performing a sintering process to convert the sintering paste layer into a sintered layer; as well as A protective layer is deposited onto the semiconductor die and portions of the sintered layer by atomic layer deposition or by plasma enhanced chemical vapor deposition.

2. The method according to claim 1, further comprising: Sinter paste drying process after application of the sinter paste layer.

3. The method according to claim 1 or 2, wherein: The protection layer includes an oxide layer.

4. The method according to claim 3, wherein: The protective layer includes a metal oxide layer.

5. The method according to claim 4, wherein: The protective layer includes one or more of Al2O3, ZrO, TiO or Ta2O5.

6. The method according to claim 3, wherein: The protective layer includes SiO.

7. A method according to any one of the preceding claims, wherein: The protective layer includes a sandwich structure including two or more layers of different materials stacked on top of each other.

8. A method according to any one of the preceding claims, wherein: The protective layer comprises a thickness ranging between 3 nm and 200 nm.

9. A method according to any one of the preceding claims, wherein: The semiconductor die includes a backside metallization layer, and wherein, The frit paste layer is applied to the back side metallization layer.

10. A method according to any one of the preceding claims, wherein: Applying the frit paste layer includes a printing process.

11. The method according to any one of claims 1 to 9, wherein: Applying the sintering paste layer includes transferring paste from a film to the substrate.

12. A semiconductor device (20; 30), comprising: Substrate (1; 11)； Sintered layer (2; 12), the sintered layer (2; 12) is arranged on the substrate (1; 11) on; a semiconductor die (3; 13), the semiconductor die (3; 13) being arranged on or above the sintered layer (2; 12); as well as A protective layer (5; 15) is applied to the semiconductor die (3; 13) and the sintered layer (2; 12) by atomic layer deposition or by plasma enhanced chemical vapor deposition.

13. The semiconductor device (20; 30) according to claim 12, wherein: The protective layer (5; 15) comprises an oxide layer.

14. The semiconductor device (20; 30) according to claim 13, wherein: The protective layer (5; 15) comprises a metal oxide layer.

15. The semiconductor device (20; 30) according to claim 14, wherein The protective layer (5; 15) includes one or more of Al2O3, ZrO, TiO, Ta2O5 or HfO2.

16. The semiconductor device (20; 30) according to claim 13, wherein: The protective layer (5; 15) comprises SiO.

17. The semiconductor device (20; 30) according to any one of claims 12 to 16, wherein: The protective layer (5; 15) comprises a single layer or a sandwich structure, wherein the sandwich structure comprises two or more layers of different materials stacked on top of each other.

18. The semiconductor device (20; 30) according to any one of claims 12 to 17, wherein: The protective layer (5; 15) comprises a thickness ranging between 3 nm and 200 nm.

19. The semiconductor device (20; 30) according to any one of claims 11 to 18, wherein: The semiconductor die (3; 13) comprises a backside metallization layer (4; 14), and the semiconductor die (3; 13) is arranged such that the backside metallization layer (4; 14) is located on or above the sintering layer (2; 12).

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