Power semiconductor module device and manufacturing method thereof

Abstract

The present application provides a method comprising: filling a housing with a first material having a first density, thereby forming a first pre-layer in the form of a liquid or gel, in which the housing comprises sidewalls and a substrate having at least one semiconductor body arranged thereon is arranged in the housing or forms a ground surface of the housing, and in which the first material has a second density, thereby forming a second pre-layer in the form of a liquid or gel, a first pre-layer partially filling the housing and fully covering the substrate and the at least one semiconductor body disposed thereon; filling the housing with a second material different from the first material and having a second density, the first density being higher than the second density so as to form a liquid or gel-like second pre-layer, the first pre-layer being formed between the second pre-layer and the substrate due to its higher density; and performing a curing step to simultaneously cure the first material and the second material and form a solid first layer and a solid second layer wherein the second layer is permanently adhered to the first layer.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor module arrangement and a method for producing such a power semiconductor module arrangement. Background Art

[0002] A power semiconductor module device generally includes at least one substrate. A semiconductor device including a plurality of controllable semiconductor elements (e.g., two or more IGBTs) is arranged on each substrate of at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on, for example, the first metallization layer. Most power semiconductor module devices also include an encapsulant that at least partially fills the interior of the housing, thereby covering any components and electrical connections arranged on at least one substrate. The encapsulant is generally configured to electrically insulate regions with different electrical potentials within the housing and protect the components and electrical connections of the power semiconductor module from certain environmental conditions and mechanical damage.

[0003] During the use of the power semiconductor module device, heat may be generated. This is because high current densities of up to 1000A are regulated and controlled in the housing, especially in areas with relatively high resistance. In addition, at least some controllable semiconductor elements of the power semiconductor module device perform multiple switching operations during the operation of the power semiconductor module device. For example, when multiple switching operations are performed in a short time, the controllable semiconductor elements generate heat. Most of the heat generated during the operation of the power semiconductor module device is dissipated from the controllable semiconductor elements to the substrate, and further dissipated to the heat sink through the optional substrate. However, the encapsulant in direct contact with the controllable semiconductor elements may also be heated, and local hot spots may occur. Due to the heat, the material of the encapsulant may become brittle over time, which may lead to failure of the power semiconductor module device. Therefore, the encapsulant may include at least one thermally stable layer directly adjacent to the substrate and a mechanically stable upper layer covering the thermally stable layer, which does not significantly change its physical properties at the operating temperature and does not become brittle during the service life of the power semiconductor module device, thereby protecting the thermally stable layer and the substrate from certain environmental conditions and mechanical damage.

[0004] There is a need for a thermally and mechanically stable power semiconductor module arrangement and a method which allows for the production of such a power semiconductor module arrangement at low cost. Summary of the invention

[0005] A method includes: filling a first material having a first density in a shell to form a first liquid or gel-like pre-layer, wherein the shell includes side walls, and a substrate on which at least one semiconductor body is arranged is arranged in the shell or forms a ground surface of the shell, and wherein the first pre-layer partially fills the shell and completely covers the substrate and the at least one semiconductor body arranged thereon; filling the shell with a second material different from the first material and having a second density, wherein the first density is higher than the second density, thereby forming a liquid or gel-like second pre-layer, wherein the first pre-layer is formed between the second pre-layer and the substrate due to its higher density; and performing a curing step to simultaneously cure the first material and the second material and form a solid first layer and a solid second layer, wherein the second layer is permanently adhered to the first layer.

[0006] A power semiconductor module device comprises: a substrate arranged in a housing or forming a grounded surface of the housing, the housing comprising side walls; at least one semiconductor body arranged on the substrate; a solid first layer partially filling the housing and completely covering the substrate and the at least one semiconductor body arranged thereon; and a solid second layer arranged adjacent to the first layer, wherein the first layer is arranged between the second layer and the substrate, the first layer comprises a first material or consists of the first material, the second layer comprises a second material different from the first material or consists of the second material, and the second layer is permanently adhered to the first layer.

[0007] The present invention may be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but are intended to illustrate the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding components in different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0009] Figure 2 is a cross-sectional view of a power semiconductor module device according to an embodiment of the present disclosure.

[0010] Figure 3 is a cross-sectional view of a power semiconductor module device.

[0011] Figure 4 The chemical formula of the functionalized polydiorganosilicon used as the encapsulant in the module assembly is schematically shown.

[0012] Figure 5 A conventional method for forming a multilayer encapsulant is schematically shown.

[0013] Figure 6 A method for forming a multi-layer encapsulant according to an embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that the features and principles described for various examples can be combined with each other unless otherwise explicitly stated. In the specification and in the claims, certain elements are designated as "first element", "second element", "third element", etc., which should not be understood as enumerative. On the contrary, these designations are only used to refer to different "elements". That is, for example, the presence of a "third element" does not necessarily require the presence of a "first element" and a "second element". The wires or electrical connections described herein may be a single conductive element, or may include at least two individual conductive elements connected in series and / or in parallel. The wires and electrical connections may include metal and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or contained in a semiconductor chip. The semiconductor body has an electrically connectable pad and includes at least one semiconductor element with an electrode.

[0015] refer to Figure 1 , a cross-sectional view of a power semiconductor module device 100 is shown. The power semiconductor module device 100 comprises a housing 7 and a substrate 10. The substrate 10 comprises a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0016] Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 may be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. Alternatively, the dielectric insulating layer 11 may be composed of an organic compound and include one or more of the following materials: Al2O3, AlN, SiC, BeO, BN, or Si3N4. For example, the substrate 10 may be a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). The insulated metal substrate typically includes a dielectric insulating layer 11, which includes (filling) material, such as epoxy resin or polyimide. The material of the dielectric insulating layer 11 can be filled with, for example, ceramic particles. Such particles can include, for example, SiO2, Al2O3, AlN, SiN or BN, and can have a diameter between about 1 μm and about 50 μm. The substrate 10 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can be composed of or include a cured resin.

[0017] The substrate 10 is arranged in the housing 7. Figure 1 In the example shown, the substrate 10 is arranged on a base plate 64 forming the base surface of the housing 7, while the housing 7 itself only includes side walls and an optional top or lid. In some power semiconductor module devices 100, more than one substrate 10 is arranged on the same base plate 64 and in the same housing 7. The base plate 64 can include a layer of metal material, such as copper or AlSiC. However, other materials are also possible. However, the base plate 64 can also be omitted. For example, the substrate 10 itself can form the ground surface of the housing 7.

[0018] One or more semiconductor bodies 20 may be arranged on at least one substrate 10. Each semiconductor body 20 arranged on at least one substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

[0019] One or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. Figure 1 In FIG. 2 , only two semiconductor bodies 20 are shown by way of example. Figure 1The second metallization layer 112 of the substrate 10 in the embodiment is a continuous layer. According to another example, the second metallization layer 112 may be a structured layer. According to other examples, the second metallization layer 112 may be completely omitted. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. In this context, "structured layer" means that the corresponding metallization layer is not a continuous layer, but includes recesses between different parts of the layer. These recesses are Figure 1 Schematically shown in . The first metallization layer 111 in this example includes three different parts. Different semiconductor bodies 20 can be mounted to the same or different parts of the first metallization layer 111. Different parts of the first metallization layer 111 may not be electrically connected, or may be electrically connected to one or more other parts using electrical connections 3 (e.g., bonding wires). The semiconductor bodies 20 can be electrically connected to each other or to the first metallization layer 111 using, for example, electrical connections 3. Instead of bonding wires, the electrical connection 3 can also include, for example, bonding ribbons, connecting plates, or conductor tracks, just to name a few examples. One or more semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 via a conductive connection layer 60. Such a conductive connection layer 60 can be a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as sintered silver (Ag) powder. One or more substrates 10 can be mechanically and thermally connected to the base plate 64 via a connection layer 62. The connection layer 62 can be an electrically insulating adhesive layer, a solder layer, a conductive adhesive layer, or a sintered metal powder layer, such as sintered silver (Ag) powder.

[0020] Figure 1 The power semiconductor module device 100 shown in FIG. 1 further includes a terminal element 4. The terminal element 4 provides an electrical connection between the interior and the exterior of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 with a second end 42, while a first end 41 of the terminal element 4 protrudes out of the housing 7. The terminal element 4 can be electrically contacted from the outside at its first end 41.

[0021] Arranging the terminal element 4 in the center of the substrate 10 is only an example. According to other examples, the terminal element 4 may be arranged closer to or adjacent to the side wall of the housing 7. The second end 42 of the terminal element 4 may be connected to the conductive connection layer ( Figure 1 The terminal element 4 is electrically and mechanically connected to the substrate 10 (not specifically shown). Such a conductive connection layer can be a solder layer, a conductive adhesive layer or a sintered metal powder layer, such as sintered silver (Ag) powder. Alternatively, the terminal element 4 can also be coupled to the substrate by ultrasonic welding.

[0022] The power semiconductor module device 100 also includes an encapsulant 5. The encapsulant 5 may be composed of or include a cured silicone gel, or may be a rigid molding compound. The encapsulant 5 may at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the substrate 10. The terminal element 4 may be partially embedded in the encapsulant 5. However, at least its first end 41 is not covered by the encapsulant 5, and protrudes from the encapsulant 5 through the housing 7 to the outside of the housing 7. The encapsulant 5 is configured to protect the components and electrical connections of the power semiconductor module 100, in particular the components arranged in the housing 7, from certain environmental conditions and mechanical damage. The encapsulant 5 is also configured to electrically insulate regions with different electrical potentials (e.g., different portions of the first metallization layer 111) from each other. The silicone material used to form the encapsulant can generally insulate up to 23.000V / mm. Therefore, compared with, for example, air, the silicone material provides better insulation performance, and air can provide electrical insulation of up to about 3.000V / mm.

[0023] During the use of the power semiconductor module device 100, the encapsulant 5 may be heated to a certain extent. This is because at least some of the semiconductor bodies 20 of the power semiconductor module device 100 usually perform multiple switching operations during the operation of the power semiconductor module device 100. When multiple switching operations are performed in a short period of time, for example, the semiconductor body 20 generates heat, which may rise to a temperature above a certain maximum threshold in the worst case. In addition, the high current density of up to 1000A that is regulated and controlled in the housing (especially in areas with relatively high resistance) also causes heat. The heat generated during the use of the power semiconductor module device 100 is usually mostly dissipated from the semiconductor body 20 to the substrate 10, and further dissipated to, for example, a heat sink (not specifically shown) through the (optional) base plate 64. However, a certain amount of heat is always transferred to the encapsulant 5 that is in direct contact with the semiconductor body 20. The encapsulant 5 is usually a cured silicone layer or a rigid molding compound.

[0024] When (repeatedly) exposed to heat over a long period of time (e.g., within the expected service life of a power semiconductor module device), the encapsulant 5 may thermally degrade and may become brittle or, under certain conditions, liquefy. That is, cracks may form in the encapsulant 5, or bubbles may form due to evaporation of water, or it may partially liquefy, thereby forming a mechanically unstable encapsulant 5. Specifically, local hot spots may occur in the encapsulant 5 in the area directly adjacent to the semiconductor body 20. Careful selection of the thermal stability properties of the encapsulant material (typically achieved with thermally stable additives) often interferes with other key encapsulant properties, such as its mechanical strength, or interferes with the ability of the encapsulant 5 to adhere to the die 20 or the first metallization layer 111. This trade-off between thermal stability and mechanical stability and adhesion behavior must be well balanced and often shortens the module life. Typically, the failure mechanism resulting from these trade-offs is proportional to the thickness of the thermally optimized encapsulant layer because the upward mechanical force between the expanded encapsulant 5 near the hot spot and the cold area adjacent to the housing 7 is large. Typical failure mechanisms include delamination of the encapsulant from the die 20, the first metallization layer 111, the insulating layer 11 or the housing 7, thereby creating an area filled with air, which reduces the electrical insulation capacity of the encapsulant body. Due to heat, bubbles may also form in the material of the encapsulant 5. Such bubbles usually appear in areas (hot spots) close to the semiconductor body 20. Since the encapsulant 5 is a cured silicone layer or a rigid molding compound, the bubbles cannot move to other areas of the encapsulant 5. The encapsulant 5 may no longer be able to protect the components and electrical connections of the power semiconductor module 100 from environmental conditions and mechanical damage, and reduce the electrical insulation capacity of the encapsulant body, resulting in fatal discharges in the module. Therefore, bubbles, delamination or cracks filled with air in the wrong area of ​​the module (for example, in or near the recess between different parts of the first metallization layer 111) may cause fatal discharges.

[0025] Reference now Figure 2 , schematically shows a power semiconductor module device 100 according to an embodiment of the present disclosure. The power semiconductor module device 100 generally corresponds to the above Figure 1 The power semiconductor module device 100 described above. Figure 2In the example shown, the encapsulant includes two layers, namely a first layer 50 and a second layer 52. The first layer 50 partially fills the housing 7 and completely covers the substrate 10 and the at least one semiconductor body 20 arranged thereon. The second layer 52 is arranged adjacent to the first layer 50, so that the first layer 50 is arranged between the second layer 52 and the substrate 10. For example, the second layer 52 can be arranged away from the top of the housing 7. That is, the area arranged between the first layer 50 and the top of the housing 7 can be only partially filled with the material of the second layer 52, and a cavity can remain between the second layer 52 and the top of the housing 7. For example, the cavity can be filled with air.

[0026] The first layer 50 and the second layer 52 may be composed of different materials, thereby providing different properties. For example, the first layer 50 may be a thermally stable layer that can withstand the high temperatures that occur in the power semiconductor module device. Therefore, the first layer 50 will not become brittle during the service life of the power semiconductor module device. However, the first layer 50 may not protect the substrate 10 and the components mounted thereon (e.g., the semiconductor body 20 and the electrical connection 3) from environmental conditions and mechanical damage. In addition, the first layer 50 may have low mechanical strength or adhesion capabilities, which will lead to delamination and cracks in the substrate 10 when the module is fully filled, resulting in high mechanical stresses in the encapsulant itself and at the interface. By arranging the second layer 52 on top of the first layer 50, protection from environmental conditions and reduction of mechanical stress can be achieved. The second layer 52 can be a mechanically stable layer, but not thermally stable. This multilayer structure can also reduce mechanical stress in the thermally stable first layer 50, because the mechanically stable and protective second layer 52 allows the thickness of the first thermally stable layer 50 to be reduced. The mechanical stress in the encapsulant 5 caused by different temperature regions is generally proportional to the layer thickness. Therefore, the reduction in the thickness of the first layer 50, which has poor mechanical stability, allows a more stable construction. However, since the first layer 50 is arranged between the second layer 52 and the substrate 10, the second layer 52 is not exposed to the high temperatures generated near the substrate 10 (i.e., near the semiconductor body 20 arranged on the semiconductor substrate 10). Therefore, the encapsulant is a multilayer encapsulant, which includes at least two layers, each of which is used for a different purpose. The thermally stable first layer 50 and the mechanically stable second layer 52 are only examples. The different layers can have any specific characteristics that may be required for a specific power semiconductor module device. In general, the encapsulant of the power semiconductor module 100 can include even more than two layers.

[0027] Reference now Figure 3, a method for forming a power semiconductor module device according to an embodiment of the present disclosure will be discussed. The method for forming a power semiconductor module device according to an embodiment of the present disclosure includes: filling a first material having a first density ρ1 in a housing 7, thereby forming a first pre-layer 54 in a liquid or gel state. The housing 7 includes a side wall, and a substrate 10 is arranged thereon, and the substrate 10 having at least one semiconductor body 20 arranged thereon is arranged in the housing 7 or forms a ground surface of the housing 7. The first pre-layer 54 partially fills the housing 7 and completely covers the substrate 10 and the at least one semiconductor body 20 arranged thereon. The method also includes: filling a second material different from the first material and having a second density ρ2 in the housing 7, wherein the first density ρ1 is higher than the second density ρ2, thereby forming a second pre-layer 56 in a liquid or gel state composed of the second material. The first pre-layer 54 is formed between the second pre-layer 56 and the substrate 10 due to its higher density ρ1. In order to ensure the separation of the two miscible phases, the material of the first layer and / or the second layer may have a certain viscosity to reduce diffusion and convection during the filling process and reduce the storage time to the subsequent curing and fixing steps. The viscosity of the first layer and / or the second layer may be at least 450 mPa·s or 2000 mPa·s to limit convection or diffusion to a localized interface area of ​​1 mm for 5 minutes or 10 minutes. This may also include lower viscosity encapsulant materials that require a more precise dispensing process and a fast curing / fixing step.

[0028] According to one example, the first density ρ1 of the first material is greater than 0.98 g / cm at a given temperature. 3 , and the second density ρ2 of the second material is less than 0.98 g / cm at the given temperature 3 The difference between the first density ρ1 and the second density ρ2 may be large enough to ensure that the first and second materials are completely separated to form two separate pre-layers. For example, the difference between the first density ρ1 and the second density ρ2 may be at least 0.005 g / cm 3 , or at least 0.1g / cm 3 .

[0029] The method further includes performing a curing step, thereby curing the first material and the second material and simultaneously forming a solid first layer 50 and a solid second layer 52 (see Figure 2 ). Since the method includes only a single curing step, during which the first material and the second material are cured simultaneously, the second layer 52 is permanently adhered to the first layer 50. This will be discussed below with respect to Figure 5 and Figure 6 The resulting solid first layer 50 partially fills the shell 7 and completely covers the substrate 10 and the at least one semiconductor body 20 arranged thereon. Due to the higher density of the first material, the first layer 50 is formed between the substrate 10 and the second layer 52 .

[0030] The first pre-layer 54 may have a first thickness d54 in the vertical direction y. The resulting first layer 50 may have a second thickness d50 in the vertical direction y, and the second thickness d50 may be substantially equal to the first thickness d54 or may be slightly greater than the first thickness d54. This is because the first material of the first pre-layer 54 may expand to a certain extent when heated during the curing step. The second pre-layer 56 may have a third thickness d56 in the vertical direction y, and the resulting second layer 52 may have a fourth thickness d52 in the vertical direction y. The fourth thickness d52 may be substantially equal to or may be slightly greater than the third thickness d56, similar to the description of the first pre-layer 54 and the resulting first layer 50.

[0031] The first layer 50 may have a thickness d50 in the vertical direction y, for example, between 5 mm and 20 mm (millimeters). According to one example, the thickness d50 of the first layer 50 is between 12 mm and 18 mm, for example, the thickness d50 of the first layer 50 may be 15 mm. In this way, the amount of the first material is sufficient to effectively prevent any heat generated by the semiconductor body 20 from, for example, significantly heating the second layer 52. That is, the first layer 50 having a certain thickness d50 can provide sufficient protection for the second layer 52. The thickness d52 of the second layer 52 may be equal to the thickness of the first layer 50. However, the thickness d50 of the first layer 50 may also be greater than the thickness d52 of the second layer 52, such as Figure 2 and Figure 3 As schematically shown in FIG. 1 . The smaller thickness d52 of the second layer 52 may be sufficient for the second layer 52 to provide sufficient protection for the substrate 10 and the components mounted thereon from environmental conditions and mechanical damage. The second layer 52 may have a thickness d52 of, for example, between 3 mm and 9 mm. According to one example, the thickness d52 of the second layer 52 may be between 5 mm and 7 mm, for example, the thickness d52 of the second layer 52 may be 6 mm.

[0032] The first material and the second material can be filled into the housing 7 simultaneously or successively. The first material and the second material are substantially not mixed when they are filled into the housing 7. Due to the different densities and viscosities, the first material will descend and form a first pre-layer 54 adjacent to the substrate 10, while the second material will rise and form a second pre-layer 56 on top of the first pre-layer 54. This effect occurs automatically without any further support measures.

[0033] According to other embodiments of the present disclosure, the second material may first be filled into the housing 7, and in a subsequent second step, the first material may be injected below the second pre-layer 56 formed by the second material. In this way, turbulence that may occur in the first and second materials during the filling process may be reduced or even avoided. However, typically, since the two materials are separated due to different densities, the slight mixing effect of the two materials during the filling process will disappear in only a few seconds. This is followed by a single curing step. The curing step may include heating the power semiconductor module device 100 or at least the first pre-layer 54 and the second pre-layer 56 to a temperature of, for example, up to 150°C. A certain amount of pressure may also be applied during the curing step. If the materials used to form the first pre-layer 54 and the second pre-layer 56 are designed to cure at a lower temperature, the first pre-layer 54 and the second pre-layer 56 may also be cured in a single curing step that is typically performed at room temperature.

[0034] According to embodiments of the present disclosure, the first and second materials may both include a silicone encapsulant. A pure silicone encapsulant typically includes a base polymer in an amount of >99 vol%. The silicone material may also include a filler in an amount of >80 vol%. The silicone encapsulant may include a base polymer containing methyl, phenyl, vinyl, hydride, and partially fluorinated alkyl side groups, such as Figure 4 The average chain length of the polymer n is variable. Low molecular weight silicones with an average molecular weight of 200 g / mol and long chain silicone polymers with an average molecular weight of 500.000 g / mol and above are commercially available. The density of the silicone base polymer depends on the substitution pattern and the chain length. For example, short chain vinylated polymethylsiloxane (PDMS) shows a density of 0.90 g / cm 3 Increasing the molecular weight of polymethylsiloxane also results in an increase in density to 0.98 g / cm 3 The partial substitution of methyl groups with phenyl groups results in a base silicone polymer with a density between 0.95 g / cm 3 and 1.11 g / cm 3 Fluorination of the organic substituents allows the density of the silicone base polymer to be further increased to 1.22 g / cm 3 . In addition to these typical properties of silicone encapsulant materials, the branching of the silicone polymer also affects the density. Silicone base polymers can also be copolymerized. For example, copolymerization with polyacrylates produces UV-curable silicone encapsulants. The density of copolymers is typically between the densities of the pure polymers. The given densities of typical silicone base polymers are only examples, and there may be more variations of substitution patterns for higher or lower densities. All given densities are typical values ​​at room temperature. If elevated temperatures are applied, the density may decrease.

[0035] According to another embodiment of the present disclosure, the first and second materials may include or consist of a first base polymer and a second base polymer mixed with a filler. The filler may be added to increase the density of the base polymer to a desired first density ρ1 of the final silicone encapsulant mixture. In general, the density of the final silicone encapsulant mixture may be increased by adding a filler having a higher density than the silicone base polymer (e.g., SiO2, TiO2, Cu, or CaCO3).

[0036] According to an embodiment of the present disclosure, the silicone base polymer can be combined with a density of less than 0.90 g / cm 3 Solvents (e.g., with a density of 0.79 g / cm 3 The first and second materials may be mixed with isopropyl alcohol (isopropyl alcohol) to affect the density of the first material and the second material. According to one example, the second pre-layer 56 may include between 10 vol% and 30 vol% isopropyl alcohol, such as 20 vol% isopropyl alcohol. However, the isopropyl alcohol typically evaporates during the curing step and is no longer present in the cured second layer 52 because the boiling point of isopropyl alcohol is only 82°C.

[0037] According to an embodiment of the present disclosure, a first layer 50 having a first density ρ1 and a second layer 52 having a second, lower density ρ2 are formed inside the shell. The densities of the first layer 50 and the second layer 52 can be selected by their silicone base polymer chain lengths, the substitution pattern of each silicone base polymer, and the amount and density of fillers, or by mixing the silicone base polymer with a low-density solvent. Each combination of these effects can be used to build the two layers within the module. It includes but is not limited to: 1. The first layer 50 includes a first silicone base polymer having a high average molecular weight and therefore a high density ρ1, and the second layer 52 includes the same silicone base polymer substitution but with a lower average molecular weight and a lower density ρ2. 2. The first layer 50 includes a first silicone base polymer with a variable average molecular weight and a specific density ρ1, and the second layer 52 includes different silicone base polymers with a variable average molecular weight and a density ρ2, wherein the density ρ1 is higher than the density ρ2. 3. The first layer 50 includes a first silicone base polymer with a variable substitution pattern and a variable average molecular weight and has High-density filler, and the mixture has a defined density ρ1, and the second layer 52 includes a second silicone base polymer with a variable substitution pattern and a variable average molecular weight and has no filler, and has a defined density ρ2, wherein the density ρ1 is higher than the density ρ2. 4. The first layer 50 includes a first silicone base polymer with a variable substitution pattern and a variable average molecular weight, which has a defined density ρ1, and the second layer 52 includes a second silicone base polymer with a variable substitution pattern and a variable average molecular weight, which is mixed with a low-density volatile solvent, and the mixture has a defined density ρ2, wherein the density ρ1 is higher than the density ρ2. The embodiment is also not limited to silicone base polymers, and is also applicable to non-silicone polymers such as epoxy molding compounds. At the same time, curing is also not limited to heat-induced curing, and can also be performed by ultraviolet light or a condensation reaction with ambient water. Therefore, the first layer 50 with a defined density ρ1 or the second layer 52 with a defined density ρ2 can be exchanged with a polymer solution or liquid epoxy molding compound or potting compound having a density ρ1 higher than the density ρ2.

[0038] When cured, the second layer 52 adheres to the first layer 50. This will be discussed below in conjunction with Figure 5 and Figure 6 Give a description. Figure 5The conventional method for forming a multilayer encapsulant is schematically shown. In the conventional method, a first material is filled into a housing to form a first pre-layer. The first pre-layer is then cured to form the first layer. The second material is then filled into the housing on top of the cured first layer and a second curing step is performed. The two layers obtained can be regarded as completely independent layers. In other words, there is no adhesion between the two cured layers, and the second layer can be pulled down from the first layer with relatively little force without damaging the first or second layer. This may even lead to unnecessary delamination of the second layer. This is because encapsulant materials such as silicone gels or epoxy molding compounds have functional chemical groups, such as vinyl, hydrides in the case of silicone, and epoxy groups separated in the main chain of its base polymer or in low molecular weight networked molecules. These materials can also include adhesion promoter molecules, which are typically composed of mono / di / trialkoxysilyl, mono / di / triacetoxysilyl, etc., which are designed to react with functional groups on different surfaces to improve the adhesion of encapsulant materials. These reactive silyl groups can also be connected to the base polymer. The list of these chemically reactive groups must be understood as examples, and other functional groups can be used. However, when curing the first pre-layer 54, most or even all functional groups of any networking agent and base polymer stain present in the first pre-layer 54 are consumed, and the first layer of the highly networked solid obtained has only very little ability in chemical reactions, or even no ability to engage with other surfaces. During the curing / hardening process of silicone gel, the Pt catalyst that is usually present in the corresponding material connects the networking agent that is also present in the material to the base polymer stain. Although the presence of adhesion promoter may allow the first layer of the obtained to be attached to different surfaces during the curing step, its reactivity and concentration are significantly reduced after curing is completed. Therefore, it is almost impossible for any material to be adhered to a fully cured (silicone) gel layer.

[0039] When forming a multilayer encapsulant by the method described herein, the situation is different. Since the liquid or gel-like first pre-layer 54 and the liquid or gel-like second pre-layer 56 are cured in the same curing step, the base polymer system and networking agent of the first material and the base polymer system and networking agent of the second material can diffuse to the interface between the first pre-layer 54 and the second pre-layer 56. The base polymer systems of different pre-layers 54 and 56 can be permanently attached to each other at this interface, thereby permanently adhering the second layer 52 to the first layer 50. That is, the base polymer system of the first pre-layer 54 can be aggregated with the base polymer system of the second pre-layer 56 at the interface between the first pre-layer 54 and the second pre-layer 56. The resulting second layer 52 is still separated from the first layer 50 because no material mixing occurs during the curing step. However, the second layer 52 is permanently adhered to the first layer 50, and if the first layer 50 and the second layer 52 are not destroyed, the second layer 52 cannot be pulled off from the first layer 50.

[0040] The method can be performed in just a few steps and is therefore very cost-effective since it can be implemented in a quick and easy manner. The resulting power semiconductor module device reduces or avoids embrittlement of the encapsulant during the service life of the power semiconductor module device. The reason is that each layer can be composed of a material with chemical and physical properties optimized for that area, for example, a particularly thermally stable layer next to the hottest module part and a mechanically stable second layer. At the same time, the power semiconductor module device is fully protected from certain environmental conditions and mechanical damage. In this way, the service life of the power semiconductor module device can be significantly increased. During the curing step, the formation of bubbles, cracks and delamination in the first and second layers 50, 52 can be significantly reduced or even completely avoided.

Claims

1. A method comprising: Filling a first material having a first density (ρ1) in a shell (7) to form a first liquid or gel-like pre-layer (54), wherein the shell (7) comprises a side wall, and a substrate (10) on which at least one semiconductor body (20) is arranged is arranged in the shell (7) or forms a ground surface of the shell (7), and wherein the first pre-layer (54) partially fills the shell (7) and completely covers the substrate (10) and the at least one semiconductor body (20) arranged on the substrate (10); Filling the shell (7) with a second material different from the first material and having a second density (ρ2), wherein the first density (ρ1) is higher than the second density (ρ2), thereby forming a second liquid or gel-like pre-layer (56), wherein the first pre-layer (54) is formed between the second pre-layer (56) and the substrate (10) due to its higher density (ρ1); and A curing step is performed to simultaneously cure the first material and the second material and form a solid first layer (50) and a solid second layer (52), wherein the second layer (52) is permanently adhered to the first layer (50).

2. The method according to claim 1, wherein Filling the shell (7) with the first material having the first density (ρ1) includes filling the shell (7) with a first silicone material, and Filling the shell (7) with the second material having the second density (ρ2) includes filling the shell (7) with a second silicone material.

3. The method according to claim 1 or 2, wherein: The step of filling the first material in the shell (7) and the step of filling the second material in the shell (7) are performed continuously.

4. The method according to claim 3, wherein: In a first step, the housing (7) is filled with the second material, and in a subsequent second step, the first material is injected below the second pre-layer (56) formed of the second material.

5. A method according to any one of the preceding claims, wherein: The curing step comprises heating at least the liquid or gel-like first pre-layer (54) and the liquid or gel-like second pre-layer (56) to a temperature of up to 150°C.

6. A method according to any one of the preceding claims, wherein: The difference between the first density (ρ1) and the second density (ρ2) is at least 0.005 g / cm 3 , or at least 0.1 g / cm 3 .

7. A method according to any one of the preceding claims, wherein: The first material comprises or consists of a first base polymer, and the second material comprises or consists of a second base polymer different from the first base polymer.

8. The method according to any one of claims 1 to 6, wherein: The first material comprises or consists of a first base polymer, and the second material comprises or consists of a second base polymer and isopropanol, wherein the isopropanol contained in the second material reduces the density of the second base polymer to a desired second density (ρ2) and evaporates during the curing step.

9. The method according to any one of claims 1 to 6, wherein: The first material comprises or consists of a first base polymer mixed with a filler, and the second material comprises or consists of a second base polymer, wherein the filler increases the density of the first base polymer to a desired first density (ρ1).

10. The method according to any one of claims 7 to 9, wherein: The first base polymer is polymethylphenylsiloxane (PPMS), and the second base polymer is polydimethylsiloxane (PDMS).

11. A method according to any one of the preceding claims, wherein: The first material has a viscosity of at least 450 mPa·s or at least 2000 mPa·s, and / or the second material has a viscosity of at least 450 mPa·s or at least 2000 mPa·s.

12. A power semiconductor module device (100), comprising: A substrate (10) arranged in a housing (7) or forming a ground surface of the housing (7), the housing (7) comprising a side wall; at least one semiconductor body (20) arranged on the substrate (10); a solid first layer (50) which partially fills the housing (7) and completely covers the substrate (10) and the at least one semiconductor body (20) arranged thereon; as well as a solid second layer (52) disposed adjacent to said first layer (50), wherein The first layer (50) is arranged between the second layer (52) and the substrate (10), The first layer (50) comprises or consists of a first material, The second layer (52) comprises or consists of a second material different from the first material, and The second layer (52) is permanently adhered to the first layer (50).

13. The power semiconductor module device according to claim 12, wherein: The first layer (50) and the second layer (52) both include or consist of silicone material.

14. The power semiconductor module device according to claim 13, wherein: The first layer (50) and the second layer (52) are cured silicone layers.

15. The power semiconductor module arrangement according to any one of claims 12 to 14, wherein: The second layer (52) is arranged away from the top of the housing (7).

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