Integrated circuit packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides an integrated circuit packaging structure and a manufacturing method thereof. A method of manufacturing an integrated circuit package structure includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap fill layer on the first dielectric liner. The first thermal conductivity value of the gap filling layer is higher than the second thermal conductivity value of the silicon oxide. The method further includes etching the gap fill layer and the first dielectric pad to form a through-opening, where the metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric pad backing the through-opening, filling the through-opening with a conductive material to form a through-via connected to the metal pad, and forming a redistribution structure, a redistribution structure is over and electrically connected to the top die and the through-vias.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated circuit packaging structure and a method for manufacturing the same. Background Art

[0002] Integrated circuit packages may have multiple package components, such as device dies and package substrates, bonded together to increase functionality and integration levels. Due to the high level of integration, heat dissipation has become a serious issue. In addition, warping may occur due to differences between different materials of multiple package components. Warping may cause no-bonding issues, and some conductive parts that are intended to bond to each other do not bond, resulting in circuit failure. These issues need to be addressed. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for manufacturing an integrated circuit packaging structure is provided, comprising: bonding a top die to a bottom die; depositing a first dielectric liner on the top die; depositing a gap filling layer on the first dielectric liner, wherein a first thermal conductivity value of the gap filling layer is higher than a second thermal conductivity value of silicon oxide; etching the gap filling layer and the first dielectric liner to form a through opening, wherein a metal pad in the bottom die is exposed to the through opening; depositing a second dielectric liner of the pad through opening; filling the through opening with a conductive material to form a through hole connected to the metal pad; and forming a redistribution structure, the redistribution structure being above the top die and the through hole and electrically connected to the top die and the through hole.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit packaging structure is provided, comprising: a bottom die; a top die above and bonded to the bottom die, wherein the top die comprises a top metal pad; a dielectric liner comprising a vertical portion on a sidewall of the top die and a horizontal portion on the bottom die; a gap fill layer overlapping the horizontal portion of the dielectric liner, wherein a first thermal conductivity value of the gap fill layer is higher than a second thermal conductivity value of silicon dioxide; a through-hole penetrating the dielectric liner and the gap fill layer, wherein the through-hole contacts the top metal pad; and a redistribution structure above and electrically coupled to the top die and the through-hole.

[0005] According to another aspect of an embodiment of the present application, an integrated circuit packaging structure is provided, comprising: a bottom die; a top die above and bonded to the bottom die; a first dielectric liner comprising a first portion on a sidewall of the top die and a second portion on a top surface of the bottom die; a gap-filling layer contacting the first dielectric liner, wherein the gap-filling layer comprises a first sublayer comprising a semiconductor material; a through-hole penetrating the first dielectric liner and the gap-filling layer; and a second dielectric liner surrounding the through-hole, wherein the second dielectric liner electrically insulates the through-hole from the gap-filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1-Figure 12 A process for forming a package with an improved gap-fill structure is shown in accordance with some embodiments.

[0008] Fig.13 and Fig.14 A package with an improved gap-fill structure according to an alternative embodiment is shown.

[0009] Fig.15 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0012] A method for forming a package with a gap-filling region having improved heat dissipation capabilities and the resulting structure are provided. Heat generated by the device die can be dissipated through the gap-filling region. Stress and warpage in the resulting package can also be reduced. The embodiments discussed herein are intended to provide examples of how the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0013] Figures 1 to 12 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.15 In the process shown.

[0014] Figure 1 2 shows a cross-sectional view of the process of forming the package component 20. Fig.15 As shown, the corresponding process is shown as process 202 in process flow 200. According to some embodiments, package assembly 20 is a device wafer, which includes a device die 20'. Device die 20' may include active devices and possible passive devices, which are represented as integrated circuit devices 24. According to alternative embodiments, package assembly 20 is an interposer die, which has no active devices and may or may not include passive devices. According to yet another alternative embodiment, package assembly 20 is or includes a package (e.g., an integrated fan-out (InFO) package), a redistribution structure including redistribution lines, etc.

[0015] According to some embodiments, the package assembly 20 includes a semiconductor substrate 22 and components formed over the semiconductor substrate 22. The semiconductor substrate 22 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. The semiconductor substrate 22 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate.

[0016] According to some embodiments, package assembly 20 includes an integrated circuit device 24 formed at a top surface of a semiconductor substrate. According to some embodiments, integrated circuit device 24 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit device 24 are not shown here.

[0017] An interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 22 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit device 24. According to some embodiments, the ILD 28 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 28 can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments, the ILD 28 can also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0018] Contact plug 30 is formed in ILD 28 for electrically connecting integrated circuit device 24 to overlying metal lines and vias. According to some embodiments of the present disclosure, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plug 30 may include forming a contact opening in ILD 28, filling the contact opening with a conductive material, and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of contact plug 30 flush with the top surface of ILD 28.

[0019] An interconnect structure 32 is formed over semiconductor substrate 22. Interconnect structure 32 includes a plurality of dielectric layers 34, and a plurality of conductive features in dielectric layers 34, such as metal lines / pads 36 and vias 38, in accordance with some embodiments.

[0020] According to some embodiments, dielectric layer 34 may include a low-k dielectric layer (also referred to as an intermetallic dielectric (IMD)). For example, the dielectric constant (k value) of the low-k dielectric layer may be lower than about 3.5 or 3.0. The low-k dielectric layer may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0021] Forming metal lines 36 and vias 38 in dielectric layer 34 may include a single damascene process and / or a dual damascene process. In a single damascene process for forming metal lines or vias, a trench or via opening is first formed in one of dielectric layers 34, and then the trench or via opening is filled with a conductive material. A planarization process such as a CMP process is then performed to remove excess portions of the conductive material above the top surface of the dielectric layer, leaving metal lines or vias in the corresponding trenches or via openings. In a dual damascene process, trenches and via openings are formed in the dielectric layer, and the via openings are located below the trenches and connected to the trenches. Conductive materials are then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material on the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0022] Metal line 36 includes a top conductive (metal) feature (denoted as 36T), such as a metal line, metal pad, or via, in a top dielectric layer (denoted as dielectric layer 34T), which is the top layer of dielectric layer 34. According to some embodiments, dielectric layer 34T is formed of a low-k dielectric material similar to the material of lower dielectric layer 34. Metal feature 36T in top dielectric layer 34T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0023] The interconnect structure 32 may also include a passivation layer (not shown) that is above the underlying dielectric layer 34 and may be in contact with the dielectric layer 34. The passivation layer may be formed of a non-low-k dielectric material, which may include silicon and another element including oxygen, nitrogen, carbon, etc. The material of the passivation layer may be represented by SiO x N y C z , wherein x is in a range between about 0 and about 2, y is in a range between about 0 and about 1.33, z is in a range between about 0 and about 1, and x, y, and z will not all be equal to 0. For example, the passivation layer may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc.

[0024] The bonding layer 41 and the bonding pad 40 are formed as the top portion of the interconnect structure 32. The bonding layer 41 can be formed of a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The bonding pad 40 may include copper and may be formed by a damascene process. The bonding layer 41 and the bonding pad 40 are planarized so that their top surfaces are coplanar, which may be due to a chemical mechanical polishing (CMP) process performed in the formation of the bonding pad 40.

[0025] refer to Figure 2, device die 42 (also referred to as the top die) is bonded to device die 20 ′ (also referred to as the bottom die) in package assembly 20 . Fig.15 As shown, the corresponding process is shown as process 204 in process flow 200. According to some embodiments, each device die 42 may be a logic die, which may be a central processing unit (CPU) die, a microcontroller (MCU) die, an input output (IO) die, or a baseband die, etc. The device die 42 may also include a memory die.

[0026] Device die 42 may include semiconductor substrate 44. Through silicon vias (TSVs) 46 (sometimes referred to as through semiconductor vias or through vias) are formed to extend into semiconductor substrate 44. TSVs 46 are used to connect integrated circuit devices and metal lines formed on the front side (bottom side shown) of semiconductor substrate 44 to the back side, and to connect device die 20' to subsequently formed redistribution structures. In addition, device die 42 includes interconnect structures 48 for connecting to active devices and passive devices in device die 42. Interconnect structures 48 include metal lines and vias.

[0027] Each of the device dies 42 includes a bonding pad 51 and a bonding layer 52 (also referred to as a bonding film) located at the bottom surface of the device die 42 shown. The bottom surface of the bonding pad 51 can be coplanar with the bottom surface of the bonding layer 52. According to some embodiments, the bonding layer 52 can be formed of a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The bonding pad 51 may include copper and may be formed by a damascene process. The bonding layer 52 and the bonding pad 51 are planarized so that their surfaces are coplanar, which may be caused by CMP in the formation of the bonding pad 51.

[0028] The bonding may be achieved by hybrid bonding. For example, the bonding pad 51 is bonded to the bonding pad 40 by direct metal-to-metal bonding. According to some embodiments, the direct metal-to-metal bonding is a direct copper-to-copper bonding. In addition, the bonding layer 52 is bonded to the bonding layer 41 by, for example, fusion bonding that produces Si-O-Si bonds. Figure 2 The structure shown is hereinafter referred to as a reconstituted wafer 50 , and more components are subsequently formed to further expand the reconstituted wafer 50 in subsequent processes.

[0029] According to some embodiments, a backside grinding process may be performed to thin device die 42. By thinning device die 42, the aspect ratio of the gaps between adjacent device dies 42 is reduced to facilitate gap filling. Otherwise, gap filling may be difficult due to the high aspect ratio of the gaps. After the backside grinding process, TSVs 46 may be exposed. Alternatively, TSVs 46 may not be exposed at this time, and backside grinding may be stopped when there is a thin layer of substrate covering TSVs 46. According to these embodiments, TSVs 46 may be exposed at the backside grinding process. Figure 5 is revealed in the steps shown.

[0030] Figure 3 and Figure 4 The formation of multiple gap-fill layers is shown. In accordance with some embodiments, the gap-fill layers include a dielectric liner 54 , and a gap-fill layer 56 over and in contact with the dielectric liner 54 .

[0031] refer to Figure 3 , depositing dielectric liner 54. Fig.15 As shown, the corresponding process is shown as process 206 in process flow 200. Dielectric liner 54 can be deposited using a conformal deposition method, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), etc. Dielectric liner 54 is formed of a dielectric material having good adhesion to the sidewalls of device die 42 and the top surfaces of bonding layer 41 and bonding pad 40. According to some embodiments, dielectric liner 54 is formed of a nitride-containing material, such as silicon nitride, SiON, SiCN, etc. Dielectric liner 54 extends on the sidewalls of device die 42 and contacts the sidewalls of device die 42.

[0032] Figure 4 The gap fill layer 56 is shown formed on and in contact with the dielectric liner 54. Fig.15 As shown, the corresponding process is shown as process 208 in process flow 200. The thermal conductivity of gap fill layer 56 is higher than the thermal conductivity of silicon oxide. For example, the thermal conductivity of silicon oxide can be in a range between about 1.1 W / m·K and about 1.3 W / m·K. Therefore, the thermal conductivity of gap fill layer 56 can be equal to or higher than about 1.5 W / m·K, and can be in a range between about 1.5 W / mm·K and about 500 W / m·K.

[0033] According to some embodiments, the gap filling layer 56 is a single layer, and the entire gap filling layer is formed of a uniform material. The material of the gap filling layer 56 is different from the material of the dielectric liner 54. According to some embodiments, the gap filling layer 56 is formed of a semiconductor material such as silicon, a III-V semiconductor, etc. When silicon is used, the gap filling layer 56 is formed of amorphous silicon, which may not be doped with any p-type and n-type impurities and is therefore intrinsic. Therefore, the gap filling layer 56 is intrinsic. This will keep the conductivity value of the gap filling layer 56 low, and therefore the leakage current through the gap filling layer is low.

[0034] Amorphous silicon may have a thermal conductivity of about 1.8 W / m·K, which is significantly greater than the thermal conductivity of silicon oxide. According to an alternative embodiment, gap fill layer 56 comprises primarily amorphous silicon with a small percentage (e.g., less than 10%) of polycrystalline silicon. Since the thermal conductivity of crystalline silicon is much higher than, for example, the thermal conductivity of amorphous silicon (e.g., about 100 times higher), doping even a small amount of polycrystalline silicon into the amorphous silicon of gap fill layer 56 may significantly improve the thermal conductivity of gap fill layer 56, for example, by about 5 W / m·K or more.

[0035] According to some embodiments where gap fill layer 56 includes polysilicon, the polysilicon may be polycrystalline islands (grains) completely surrounded by and separated from amorphous silicon. The generation of a small amount of polysilicon may be achieved by, for example, slightly increasing the deposition temperature of gap fill layer 56, reducing the deposition rate, etc. The generation of a small amount of polysilicon may also be achieved by, for example, slightly increasing the deposition temperature of gap fill layer 56, reducing the deposition rate, etc. Figure 4 or Figure 5 This is achieved by annealing the gap filling layer 56 after the process shown.

[0036] According to some embodiments, gap-fill layer 56 is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or the like.

[0037] The use of amorphous silicon to form gap fill layer 56 has some advantageous features. The thermal conductivity is relatively high, so heat can be more effectively dissipated through gap fill layer 56 to other components such as a heat sink. In addition, the coefficient of thermal expansion (CTE) of amorphous silicon is closer to the thermal expansion rate of semiconductor substrate 22 than other materials. Therefore, stress and warpage in the resulting package are reduced.

[0038] According to an alternative embodiment in which the gap filling layer 56 includes a semiconductor material, the gap filling layer 56 can be formed of or include a III-V semiconductor, which can be formed of GaAs, InP, GaN, GaP and / or the like, or a combination thereof. Or include the above materials. The III-V semiconductor can have a high thermal conductivity value. For example, GaAs can have a thermal conductivity equal to about 52 Watts / m·k, InP can have a thermal conductivity equal to about 68 Watts / m·k, GaN can have a thermal conductivity equal to 130 Watts / m·k, GaP can have a thermal conductivity of about 110 Watts / m·k, and InN can have a thermal conductivity in a range between about 45 Watts / m·k-about 175 Watts / m·k. Therefore, compared to silicon oxide, the III-V compound semiconductor can have a very high thermal conductivity value.

[0039] According to some embodiments, the III-V compound semiconductor forming gap-fill layer 56 may not be doped with impurities that cause it to be n-type and / or p-type. Therefore, gap-fill layer 56 may be intrinsic or unintentionally doped. This will keep the conductivity value low, and therefore the leakage current (if any) through gap-fill layer 56 is low.

[0040] According to an alternative embodiment, the gap filling layer 56 is formed of or includes a dielectric material having a higher thermal conductivity than silicon oxide. For example, the gap filling layer 56 can be formed of a silicon-based dielectric, such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, etc. The thermal conductivity value of the dielectric material can be greater than about 1.5 W / m·k, and can be in the range of about 1.5 W / m·k and about 10 W / m·k. The corresponding gap filling layer 56 can also have an amorphous structure.

[0041] According to an alternative embodiment, the gap-filling layer 56 has a multi-layer structure including a plurality of layers. For example, Figure 4 It is shown that the example gap filling layer 56 may include sublayers 56A, 56B, 56C and 56D, which are also collectively referred to as sublayers 56. According to various embodiments, the gap filling layer 56 may include two sublayers, three sublayers, four sublayers, five sublayers or more. According to some embodiments, adjacent sublayers 56 are formed of different materials. Sublayers that are not in contact with each other may be formed of the same material or different materials. According to some embodiments, sublayers 56A and 56C are formed of the same material, and / or sublayers 56B and 56D are formed of the same material. According to alternative embodiments, sublayers 56A and 56C are formed of different materials, and / or sublayers 56B and 56D are formed of different materials.

[0042] According to some embodiments in which the gap-filling layer 56 has a multi-layer structure, the dielectric sublayer (if any) in the gap-filling layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon carbide, silicon oxycarbide, etc. The semiconductor sublayer (if any) in the gap-filling layer 56 may include amorphous silicon (with or without small polycrystalline islands), or may include a III-V semiconductor material, such as GaAs, InP, GaN, GaP, InN, etc., or a combination thereof.

[0043] In addition, the sub-layer may have a hybrid structure including a semiconductor layer and a dielectric layer. For example, sub-layer 56A or 56B may be a dielectric layer (and have low leakage), while sub-layer 56B or 56C may be a semiconductor layer with high thermal conductivity.

[0044] According to some embodiments, Figure 4 As shown, lower sub-layers 56A, 56B, and 56C are conformal layers, which can be formed by ALD, CVD, etc. Top sub-layers such as sub-layer 56D can be conformal or non-conformal. According to alternative embodiments, some or all of the sub-layers in the gap fill layer are non-conformal. This can be achieved by bottom-up deposition, such as flowable chemical vapor deposition (FCVD), spin coating, etc.

[0045] The gap filling layer 56 is formed to have a multilayer structure with some advantageous features. For example, by adopting a sublayer, the requirements of having low leakage current and high thermal conductivity can be met at the same time. In an exemplary embodiment, some sublayers, such as 56A and / or 56C, are formed of a dielectric material with low leakage current and are therefore used as a leakage barrier. Other sublayers such as 56B and / or 56D can be formed of a material with high thermal conductivity. The dielectric material can have a small thickness so that its effect on thermal conductivity is small. The high thermal conductivity layer can have a thickness greater than the thickness of the leakage barrier layer so that the resulting gap filling layer 56 has a generally higher thermal resistance.

[0046] The material and thickness of the sub-layers can be adjusted to reduce the stress in the resulting gap fill layer 56. According to some embodiments, sub-layer 56A is a dielectric layer formed of a silicon-containing dielectric material, and the bottom horizontal portion of sub-layer 56A can have a top surface 56A-T that is flush or substantially flush with the bottom surface 44-B of substrate 44 (e.g., a variation of less than about 0.1 μm). The overlying sub-layers 56B, 56C, and 56D can be formed as a single layer, rather than a multi-layer. The single layer can be formed of amorphous silicon. Therefore, gap fill layer 56 can have a structure similar to device die 42, which has a silicon region and a dielectric region below the silicon region. This structure will significantly reduce stress and warpage.

[0047] refer to Figure 5, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the gap fill layer 56 and the dielectric liner 54, thereby exposing the semiconductor 44 of the device die 42. Fig.15 As shown, the corresponding process is shown as process 210 in process flow 200. In addition, the top surface of through-hole 46 is exposed. The remaining portion of dielectric liner 54 and gap-filling layer 56 is collectively referred to as gap-filling region 62 or isolation region 62.

[0048] Figures 6 to 9 The formation of a through hole 72 penetrating the gap-filling region 62 is shown. Figure 6 , forming a bottom anti-reflective coating (BARC) 64 and a photoresist 66. According to some embodiments, the BARC 64 may be formed of a cross-linked photoresist, a SiON layer, etc. The photoresist 66 is patterned and used to etch the BARC 64, and then the gap-fill region 62 is etched.

[0049] According to some embodiments, the etching of the gap filling region 62 is performed by a Bosch process. The Bosch process may include etching the top portion of the gap filling region 62 to form an opening 68, forming a first protective layer on the sidewalls of the opening 68, further etching the gap filling region 62 to extend the opening 68 downward, forming a second protective layer on the sidewalls of the opening 68, and etching the gap filling region 62 to extend the opening 68 downward. The protective layer may be formed of a polymer, an inorganic dielectric material, etc. The process is repeated until the opening 68 extends to the dielectric liner 54. The protective layer is then removed to form a dielectric liner 54 such as the dielectric liner 54. Figure 6 The structure shown in FIG. 4 is thus exposed to expose the dielectric liner 54. Thus, an opening 68 is formed. Fig.15 As shown, the corresponding process is shown as process 212 in process flow 200 .

[0050] During the etching process, dielectric liner 54 may serve as an etch stop layer. Another etching process is then performed to etch through dielectric liner 54, exposing bonding pad 40 underneath.

[0051] According to some embodiments, by using the Bosch process, the etching rate is increased to a range between, for example, about 3 μm and about 100 μm. This improves yield. When using the Bosch process, the resulting opening 68 can have multiple lateral protrusions between the vertical and straight portions of the sidewalls. According to an alternative embodiment, etching is performed without using the Bosch process (no protective layer is formed in the opening 68 and the sidewalls of the gap filling region 62 are not lined). The sidewalls of the gap filling region 62 facing the opening 68 can therefore be straight. The photoresist 66 is removed after the etching process.

[0052] According to an alternative embodiment in which gap-fill region 62 includes multiple sub-layers 56, the lower sub-layers can be used as etch stop layers for the corresponding overlying sub-layers. For example, sub-layer 56A can be used as an etch stop layer for etching sub-layer 56B, or as an etch stop layer for etching sub-layers 56B, 56C, and 56D. Sub-layer 56B can be used as an etch stop layer for etching sub-layer 56C, or as an etch stop layer for etching sub-layers 56C and 56D.

[0053] Next, if Figure 7 As shown, a dielectric liner 71 is formed in the opening 68. Fig.15 As shown, the corresponding process is shown as process 214 in process flow 200. Dielectric liner 71 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, etc. Dielectric liner 71 may be formed as a conformal layer, which may be formed by ALD, CVD, etc.

[0054] Figure 8 2 shows the removal of the horizontal portion of the dielectric liner 71 by, for example, an anisotropic etching process. Fig.15 As shown, the corresponding process is shown as process 216 in process flow 200 .

[0055] In subsequent processes, such as Fig. 9 As shown, a conductive material is filled into the opening 68, and then a planarization process is performed to remove excess conductive material to form a through hole 72. Fig.15 As shown, the corresponding process is shown as process 218 in process flow 200. According to an alternative embodiment, no through via is formed in gap-fill region 62.

[0056] refer to Fig.10 , forming a (backside) interconnect structure 74 on the back side of the device die 42. Fig.15 As shown, the corresponding process is shown as process 220 in process flow 200. Interconnect structure 74 includes redistribution line (RDL) 76 (which also includes metal pads) and dielectric layer 78. According to some embodiments, dielectric layer 78 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, etc. RDL 76 can be formed using a damascene process, which includes etching dielectric layer 78 to form an opening, depositing a conductive barrier layer into the opening, plating a metal material such as copper or a copper alloy, and performing a planarization process to remove excess portions of RDL 76. Alternatively, RDL 76 can be formed by an electroplating process.

[0057] Electrical connectors 82 are formed on interconnect structure 74 and are electrically connected to device die 42 and possibly through vias 72 through RDL 76. According to some embodiments, electrical connectors 82 include solder areas, metal bumps, etc. Reconstructed wafer 50 is thereby formed.

[0058] In subsequent processes, such as Fig.11 As shown, the reconstructed wafer 50 is singulated in a sawing process to form individual packages 50'. Fig.15 As shown, a corresponding process is shown as process 222 in process flow 200 . Discrete package 50 ′ may include device dies 20 ′ and 42 .

[0059] Fig.12 FIG. 8 shows the bonding of package 50′ to package assembly 84 according to some embodiments. Fig.15 As shown, the corresponding process is shown as process 224 in process flow 200. Package component 84 can be an interposer, a package substrate, a package including a device die, etc. Bottom filler 86 can be distributed in the gap between package 50' and package component 84. In this way, package 88 is formed.

[0060] In such Fig.12 In the structure shown, the through hole 72 can have a plurality of lateral protrusions that protrude laterally beyond the vertical and straight sidewalls of the overlying portion of the through hole 72. The protrusions are caused by the formation of a protective layer in the Bosch process. According to some embodiments, the position of the protrusions can be at any height of the through hole 72, depending on the position where the etching is stopped by forming the protective layer.

[0061] exist Fig.12 In the illustrated structure, heat generated in device die 20' can pass through device die 42 and gap-filling region 62 and dissipate to package assembly 84. By using gap-filling layer 56 with high thermal conductivity, more heat can be dissipated through gap-filling region 62.

[0062] According to an alternative embodiment, a heat sink may be below and connected to device die 20'. Thus, with gap fill region 62 having a high thermal conductivity value, heat generated in device die 42 may be dissipated to the gap fill region and from the gap fill region to device die 20' and the heat sink. Due to the high thermal conductivity value of gap fill layer 56, the thermal resistance in this heat dissipation path is reduced. Thus, in addition to the thermal path from device die 42 directly into device die 20' and to the heat sink, another heat dissipation path through gap fill region 62 also has a reduced thermal resistance.

[0063] Fig.13A package 88 formed according to alternative embodiments is shown. According to these embodiments, the gap filling region 62 can have a multilayer structure in which some of the sublayers are used as etch stop layers for etching the capping sublayers. For example, the sublayer 56C can be used as an etch stop layer, which can be etched by an isotropic etching process (which can be a dry etching process or a wet etching process). An undercut can be formed in the etch stop layer, and accordingly, the through hole 72 has a protruding portion that extends laterally to the etch stop layer, while the portions in the overlying layer and the underlying layer do not have a lateral protruding portion. The materials and structures of the sublayers have been discussed with reference to the previous embodiments.

[0064] Fig.14 FIG. 8 shows a package 88 formed according to yet another alternative embodiment. According to these embodiments, the through-hole 72 may have straight edges. Figure 6 ), the same etching gas configured to etch all sub-layers 56 may be used, and the Bosch process is not used. Therefore, the sidewalls of the gap-filling region 62 facing the opening 68 may be straight. The resulting through-hole 72 also has straight edges, such as Fig.14 shown.

[0065] In the above embodiments, some processes and features are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate to allow testing of a 3D package or 3DIC, using a probe and / or a probe card, and the like. Verification testing may be performed on both an intermediate structure and a final structure. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to increase yield and reduce cost.

[0066] Embodiments of the present disclosure have several advantageous features. By forming an isolation region with a high thermal conductivity value, heat dissipation through the isolation region is improved. The material and structure of the isolation region are selected so that stress and warpage of the resulting package are also reduced.

[0067] According to some embodiments of the present disclosure, a method for manufacturing an integrated circuit packaging structure includes: bonding a top die to a bottom die; depositing a first dielectric liner on the top die; depositing a gap filling layer on the first dielectric liner, wherein a first thermal conductivity value of the gap filling layer is higher than a second thermal conductivity value of silicon oxide; etching the gap filling layer and the first dielectric liner to form a through opening, wherein a metal pad in the bottom die is exposed to the through opening; depositing a second dielectric liner that liner the through opening; filling the through opening with a conductive material to form a through hole connected to the metal pad; and forming a redistribution structure, the redistribution structure being above the top die and the through hole and electrically connected to the top die and the through hole.

[0068] In one embodiment, depositing the gap fill layer comprises: depositing a first sublayer comprising a first material; and depositing a second sublayer over the first sublayer, wherein the second sublayer comprises a second material different from the first material. In one embodiment, a first one of the first sublayer and the second sublayer comprises amorphous silicon, and a second one of the first sublayer and the second sublayer comprises a dielectric material. In one embodiment, the gap fill layer comprises a first plurality of sublayers and a second plurality of sublayers stacked alternately, wherein the first plurality of sublayers comprises the first material, and the second plurality of sublayers comprises the second material.

[0069] In one embodiment, etching the gap fill layer comprises etching the second sublayer, wherein the first sublayer is used as an etch stop layer. In one embodiment, etching the gap fill layer is performed by a Bosch process. In one embodiment, etching the gap fill layer is not stopped until the first dielectric liner is exposed. In one embodiment, depositing the gap fill layer comprises depositing an amorphous silicon layer. In one embodiment, depositing the gap fill layer comprises depositing an amorphous silicon-based dielectric layer. In one embodiment, depositing the gap fill layer comprises depositing a III-V compound semiconductor layer.

[0070] According to some embodiments of the present disclosure, an integrated circuit packaging structure includes: a bottom die; a top die above and bonded to the bottom die, wherein the top die includes a top metal pad; a dielectric liner including a vertical portion on a sidewall of the top die and a horizontal portion on the bottom die; a gap fill layer overlapping the horizontal portion of the dielectric liner, wherein a first thermal conductivity value of the gap fill layer is higher than a second thermal conductivity value of silicon dioxide; a through-hole extending through the dielectric liner and the gap fill layer, wherein the through-hole contacts the top metal pad; and a redistribution structure above and electrically coupled to the top die and the through-hole.

[0071] In one embodiment, the gap fill layer comprises an amorphous silicon-based dielectric material. In one embodiment, the gap fill layer comprises a semiconductor material. In one embodiment, the gap fill layer comprises: a first sublayer, the first sublayer comprising a first material; and a second sublayer, above the first sublayer, wherein the second sublayer comprises a second material different from the first material. In one embodiment, a first one of the first sublayer and the second sublayer comprises a semiconductor, and a second one of the first sublayer and the second sublayer comprises a dielectric material.

[0072] According to some embodiments of the present disclosure, an integrated circuit packaging structure includes: a bottom die; a top die above and bonded to the bottom die; a first dielectric liner including a first portion on a sidewall of the top die and a second portion on a top surface of the bottom die; a gap filling layer contacting the first dielectric liner, wherein the gap filling layer includes a first sublayer, the first sublayer including a semiconductor material; a through hole extending through the first dielectric liner and the gap filling layer; and a second dielectric liner surrounding the through hole, wherein the second dielectric liner electrically insulates the through hole from the gap filling layer. In one embodiment, the semiconductor material of the gap filling layer includes a III-V compound semiconductor material. In one embodiment, the semiconductor material of the gap filling layer includes amorphous silicon. In one embodiment, the gap filling layer also includes a second sublayer contacting the first sublayer, and wherein the second sublayer is formed of a material different from the first sublayer.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing an integrated circuit package structure, comprising: bonding the top die to the bottom die; depositing a first dielectric liner on the top die; depositing a gap-filling layer on the first dielectric liner, wherein a first thermal conductivity value of the gap-filling layer is higher than a second thermal conductivity value of silicon oxide; etching the gap-fill layer and the first dielectric liner to form a through opening, wherein a metal pad in the bottom die is exposed to the through opening; depositing a second dielectric liner lining the through opening; filling the through opening with a conductive material to form a through hole connected to the metal pad; as well as A redistribution structure is formed over and electrically connected to the top die and the through vias.

2. The method according to claim 1, wherein: Depositing the gap-filling layer comprises: depositing a first sub-layer comprising a first material; and A second sublayer is deposited over the first sublayer, wherein the second sublayer includes a second material different from the first material.

3. The method according to claim 2, wherein: Etching the gap-fill layer includes etching the second sub-layer, wherein the first sub-layer serves as an etch stop layer.

4. The method according to claim 1, wherein: The etching of the gap-fill layer is performed by a Bosch process.

5. The method according to claim 1, wherein: The etching of the gap-fill layer is performed until the first dielectric liner is exposed.

6. An integrated circuit packaging structure, comprising: bottom die; a top die over and bonded to the bottom die, wherein the top die includes a top metal pad; a dielectric liner including a vertical portion on a sidewall of the top die and a horizontal portion on the bottom die; a gap-fill layer overlapping the horizontal portion of the dielectric liner, wherein a first thermal conductivity value of the gap-fill layer is higher than a second thermal conductivity value of silicon dioxide; a through hole extending through the dielectric liner and the gap-filling layer, wherein the through hole contacts the top metal pad; and A redistribution structure is over and electrically coupled to the top die and the through via.

7. The integrated circuit packaging structure according to claim 6, wherein: The gap-filling layer includes an amorphous silicon-based dielectric material.

8. The integrated circuit package structure according to claim 6, wherein: The gap-fill layer includes a semiconductor material.

9. The integrated circuit package structure according to claim 6, wherein: The gap filling layer comprises: a first sublayer comprising a first material; and A second sub-layer is above the first sub-layer, wherein the second sub-layer includes a second material different from the first material.

10. An integrated circuit packaging structure, comprising: bottom die; a top die over and bonded to the bottom die; a first dielectric liner including a first portion on a sidewall of the top die and a second portion on a top surface of the bottom die; a gap-filling layer contacting the first dielectric liner, wherein the gap-filling layer comprises a first sub-layer, and the first sub-layer comprises a semiconductor material; a through hole penetrating the first dielectric liner and the gap-filling layer; and A second dielectric liner surrounds the through hole, wherein the second dielectric liner electrically insulates the through hole from the gap-filling layer.

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