Lead frame suitable for quad flat no-lead packaging and semiconductor device

Abstract

The invention relates to a lead frame suitable for quad flat no-lead packaging. The lead frame comprises a crystal grain bonding area and a plurality of pins. The crystal grain bonding area is used for arranging crystal grains. The plurality of pins are arranged on the periphery of the crystal grain bonding area and comprise at least one first pin and a plurality of second pins. The first pin is arranged on one side of the crystal grain bonding area and comprises a first edge pin, an internal pin and a first extension part. The internal pin is connected to the lower surface of one end of the first extension part, the first edge pin is connected to the lower surface of the other end of the first extension part, and the internal pin is closer to the grain bonding area than the first edge pin. Each second pin comprises a second edge pin and a second extension part; the second edge pin is connected to the lower surface of one end of the second extension part, and the other end of the second extension part is closer to the crystal grain bonding area than the end connected with the second edge pin.

Description

Technical Field

[0001] The present invention relates to a design of a lead frame for enhancing power integrity, and more particularly to a lead frame and a semiconductor device suitable for a quad flat no-lead package. Background Art

[0002] The lead frame of the traditional quad flat no-lead (QFN) package has the advantage of low cost compared to the ball grid array (BGA) package or flip chip package. And its heat dissipation effect is better than other packaging methods because when the die is bonded to the lead frame with a metal exposed pad, the heat can be directly discharged through the large area of ​​the metal exposed pad.

[0003] However, the QFN package is a wire-bonded lead frame package, and its signal and power integrity (power integrity and signal integrity) bandwidth is limited by the impedance of the wires and internal pins. The longer the wire length, the greater the impedance. Therefore, in scenarios with high-speed signals that require high signal and power integrity, QFN packages often have design difficulties due to the long wire length. As a result, most chip packages that include high-speed signals currently still use BGA packages or flip-chip packages that have better signal power integrity but are more expensive. Summary of the invention

[0004] In one embodiment, a lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set a die. A plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin.

[0005] In one embodiment, a lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set a die. A plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin. The upper surface of one end of the first extension connected to the internal pin is used for wire bonding to the die.

[0006] In one embodiment, a lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set a die. A plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin. The upper surface of the first extension connected to one end of the internal pin is used for wire bonding to the die. The first pin is used to transmit a power signal.

[0007] In one embodiment, a semiconductor device includes a die, a lead frame suitable for QFN packaging, and a package. The lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set the die. The plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin, and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin. The package is used to cover the die and part of the lead frame.

[0008] In one embodiment, a semiconductor device includes a die, a lead frame suitable for QFN packaging, and a package body. The lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set the die. The plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin, and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin. The package body is used to cover the die and part of the lead frame. The upper surface of the first extension connected to one end of the internal pin is used for wire bonding to the die.

[0009] In one embodiment, a semiconductor device includes a die, a lead frame suitable for QFN packaging, and a package body. The lead frame suitable for QFN packaging includes a die bonding area and a plurality of pins. The die bonding area is used to set the die. The plurality of pins are arranged around the die bonding area and include at least one first pin and a plurality of second pins. The first pin is arranged on one side of the die bonding area and includes a first edge pin, an internal pin, and a first extension. The internal pin is connected to the lower surface of one end of the first extension, the first edge pin is connected to the lower surface of the other end of the first extension, and the internal pin is closer to the die bonding area than the first edge pin. Each second pin includes a second edge pin and a second extension. The second edge pin is connected to the lower surface of one end of the second extension, and the other end of the second extension is closer to the die bonding area than the end connected to the second edge pin. The package body is used to cover the die and part of the lead frame. The upper surface of the first extension connected to one end of the internal pin is used for wire bonding to the die. The first pin is used to transmit a power signal.

[0010] The detailed features and advantages of the present invention are described in detail in the following embodiments, and the contents are sufficient to enable any technical personnel in the field to understand the technical content of the present invention and implement it accordingly. Moreover, according to the contents disclosed in this specification, the scope of the patent application and the drawings, any technical personnel in the field can easily understand the relevant purposes and advantages of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A top view of an embodiment of a lead frame and die suitable for QFN packaging;

[0012] Figure 2 A top view of another embodiment of a lead frame and die suitable for QFN packaging;

[0013] Figure 3 A bottom view of another embodiment of a lead frame and a die suitable for QFN packaging;

[0014] Figure 4 for Figure 3 A cross-sectional view of a lead frame and a die suitable for QFN packaging along section line 4;

[0015] Figure 5A is a schematic diagram of an embodiment of a first pin;

[0016] Figure 5B is a schematic diagram of an embodiment of a second pin;

[0017] Fig. 6A A schematic diagram of an embodiment of a first pin connected to a pad of a die through wire bonding;

[0018] Figure 6B A schematic diagram of an embodiment of a second pin connected to a pad of a die through wire bonding;

[0019] Fig. 7A A schematic diagram of an embodiment in which the second pin is connected to a decoupling capacitor through a circuit board;

[0020] Figure 7B A schematic diagram of an embodiment in which a first pin is connected to a decoupling capacitor through a circuit board;

[0021] Figure 8 A top view of a semiconductor device according to an embodiment of the present invention is shown.

[0022] Description of reference numerals:

[0023] 1: Lead frame 2: Die 11: Die bonding area

[0024] 12: Pin 121: First pin 1211: First edge pin

[0025] 1212: internal pin 1213: first extension 122, 1220: second pin

[0026] 1221: second edge pin 1222: second extension portion 123: ground pin

[0027] 1231: Ground center pin 1232: Ground extension 1233: Ground edge pin

[0028] 4: Cross-section line 21: Pad 31: Lead

[0029] 101: Circuit board 102: Routing 131~133: Decoupling capacitor

[0030] 10: Semiconductor device 3: Package DETAILED DESCRIPTION

[0031] Figure 1 FIG. 1 is a top view of a lead frame 1 and a die 2 for a QFN package. Figure 1 , the lead frame 1 includes a die bonding area 11 and a plurality of pins 12. The die bonding area 11 is used to set the die 2. The plurality of pins 12 are arranged around the die bonding area 11. The plurality of pins 12 include a first pin 121 and a plurality of second pins 122. For the sake of convenience of explanation, it is taken as an example that a die 2 is set in the die bonding area 11, but the present invention is not limited thereto. The die bonding area 11 can be used to set a plurality of die 2, that is, a plurality of die 2 can be set in the die bonding area 11 at the same time. In some embodiments, the die bonding area 11 allows the die 2 to be adhered and fixed to the die bonding area 11 by epoxy (such as silver glue) or die attach film, which is also a die bonding process (Die Bond).

[0032] Figure 2 FIG. 1 is a top view of another embodiment of a lead frame 1 and a die 2 suitable for a QFN package. Figure 2 In some embodiments, the lead frame 1 includes a plurality of first pins 121, and the plurality of first pins 121 are disposed on one side of the die bonding region 11. Figure 2 In the embodiment of FIG. 5 , the lead frame 1 includes five first pins 121 for illustration, but the number of the first pins 121 is not limited thereto.

[0033] Figure 3 FIG. 1 is a bottom view of another embodiment of a lead frame 1 and a die 2 suitable for QFN packaging. Figure 4 for Figure 3 A cross-sectional view of a lead frame 1 and a die 2 suitable for QFN packaging along a section line 4 is shown. Figure 5A FIG. 1 is a schematic diagram of an embodiment of the first pin 121. Figures 3 to 5A The first lead 121 includes a first edge pin 1211, an inner pin 1212 and a first extension portion 1213. The inner pin 1212 is connected to the lower surface of one end of the first extension portion 1213, and the first edge pin 1211 is connected to the lower surface of the other end of the first extension portion 1213. The inner pin 1212 is closer to the die bonding area 11 than the first edge pin 1211.

[0034] Figure 5B FIG. 1 is a schematic diagram of an embodiment of the second pin 122. Figure 3 , Figure 4 and Figure 5BEach second lead 122 includes a second edge pin 1221 and a second extension 1222. The second edge pin 1221 is connected to the lower surface of one end of the second extension 1222, and the end of the second extension 1222 not connected to the second edge pin 1221 is closer to the die bonding region 11 than the end of the second extension 1222 connected to the second edge pin 1221.

[0035] Fig. 6A FIG. 1 is a schematic diagram of an embodiment of connecting the first pin 121 to the pad 21 of the die 2 through wire bonding. Fig. 6A . The first extension portion 1213 of the first pin 121 is connected to the upper surface of one end of the internal pin 1212 and is connected to the pad 21 of the die 2 via the lead 31. That is, the upper surface of the first extension portion 1213 of the first pin 121 is connected to the internal pin 1212 and is welded to one end of the lead 31, while the other end of the lead 31 is welded to the pad 21 of the die 2. In some embodiments, the upper surface of the first extension portion 1213 of the first pin 121 connected to the internal pin 1212 can also be connected to the pad of the die bonding area 11 via the lead 31. That is, the upper surface of the first extension portion 1213 of the first pin 121 is connected to the internal pin 1212 and is welded to one end of the lead 31, while the other end of the lead 31 is welded to the pad of the die bonding area 11. In some embodiments, the upper surface of the first extension portion 1213 of the first lead 121 connected to one end of the internal pin 1212 can be wired to the pad 21 of the die 2 or the pad of the die bonding area 11 via more than one lead 31, so that one first lead 121 can transmit one or more identical signals at a time. In some embodiments, the pad of the die bonding area 11 is a metal exposed pad (EPAD).

[0036] Figure 6B FIG. 1 is a schematic diagram of an embodiment of connecting the second pin 122 to the pad 21 of the die 2 through wire bonding. Figure 6B. The upper surface of the second extension portion 1222 of the second pin 122 at one end not connected to the second edge pin 1221 is wire-bonded to the pad 21 of the die 2 via the lead 31. The upper surface of the second extension portion 1222 of the second pin 122 at one end not connected to the second edge pin 1221 is wire-bonded to the pad 21 of the die 2 via the lead 31. That is, the upper surface of the second extension portion 1222 of the second pin 122 at one end not connected to the second edge pin 1221 is welded to one end of the lead 31, and the other end of the lead 31 is welded to the pad 21 of the die 2. In some embodiments, the upper surface of the second extension portion 1222 of the second pin 122 at one end not connected to the second edge pin 1221 may also be wire-bonded to the pad of the die bonding area 11 via the lead 31. That is, the upper surface of the end of the second extension portion 1222 of the second pin 122 that is not connected to the second edge pin 1221 is welded to one end of the lead 31, and the other end of the lead 31 is welded to the pad of the die bonding area 11. In some embodiments, the upper surface of the end of the second extension portion 1222 of the second pin 122 that is not connected to the second edge pin 1221 can be wire-bonded to the pad 21 of the die 2 or the pad of the die bonding area 11 via more than one lead 31, so that one second pin 122 can transmit one or more identical signals at a time.

[0037] In some embodiments, the first pin 121 and the second pin 122 are used to transmit high-speed signals, but the present invention is not limited thereto, and the first pin 121 and the second pin 122 may also be used to transmit low-speed signals. In some embodiments, the first pin 121 is used to transmit a power signal and the second pin 122 is used to transmit a differential signal, but the present invention is not limited thereto, and the first pin 121 may also be used to transmit a differential signal or a ground signal and the second pin 122 may also be used to transmit a power signal or a ground signal.

[0038] Fig. 7A FIG. 1 is a schematic diagram of an embodiment in which the second pin 122 is connected to the decoupling capacitor 131 through the circuit board 101 . Figure 7B FIG. 1 is a schematic diagram of an embodiment of connecting the first pin 121 to the decoupling capacitor 131 through the circuit board 101. Fig. 7A and Figure 7B The second pin 122 and the first pin 121 are connected to the decoupling capacitor 131 in the power supply through the wiring 102 of the circuit board 101. The wiring 102 includes the live wire and the ground wire of the power supply. For convenience of explanation, Figure 7B The decoupling capacitors 131 are respectively referred to as decoupling capacitors 132 and decoupling capacitors 133. Assume that Fig. 7A and Figure 7B The pad 21 is the same pad 21 of the same die 2 . Fig. 7A and Figure 7BOne of the evaluation conditions of the power integrity is the equivalent inductance of the path from the pad 21 to the decoupling capacitor 131. The larger the equivalent inductance, the greater the voltage jitter on the path, and the equivalent inductance is proportional to the length of the path. Fig. 7A and Figure 7B It can be seen that Fig. 7A The length of the path from the pad 21 to the decoupling capacitor 131 is significantly greater than Figure 7B The length of the path from the pad 21 to the decoupling capacitor 133. In other words, Fig. 7A The equivalent inductance of the path from the pad 21 to the decoupling capacitor 131 is greater than Figure 7B The equivalent inductance of the path from the pad 21 to the decoupling capacitor 133 is Figure 7B The power integrity of the embodiment is better than Fig. 7A And because the first pin 121 has two pins (a first edge pin 1211 and an inner pin 1212), Figure 7B The embodiment has two power paths. If both power paths are used, the power current can also be dispersed, thereby enhancing power integrity.

[0039] Depend on Figure 3 and FIG. 6A to FIG. 7B It can be seen that the length of the lead 31 connecting the first extension 1213 of the first pin 121 to the upper surface of one end of the internal pin 1212 and the pad 21 of the die 2 is shorter than the length of the lead 31 connecting the second extension 1222 of the second pin 122 to the upper surface of one end not connected to the second edge pin 1221 and the pad 21 of the die 2. Therefore, the lead 31 connecting the first extension 1213 of the first pin 121 to the upper surface of one end of the internal pin 1212 and the pad 21 of the die 2 has a smaller impedance than the lead 31 connecting the second extension 1222 of the second pin 122 to the upper surface of one end not connected to the second edge pin 1221 and the pad 21 of the die 2. The traditional QFN package is a package that uses a lead frame that only includes a plurality of second pins 122 to be wired to the die 2. Therefore, the signal transmitted by the first pin 121 in the lead frame 1 of the present invention has a lower impedance because the lead 31 used to connect the first pin 121 and the die 2 has a shorter path length from the pad 21 of the die 2 to the power supply through the wiring design of the circuit board 101, and has higher signal and power integrity than the prior art. Therefore, the lead frame 1 can be applied to high-speed signal chip packaging.

[0040] See also Figure 3 and Figure 4In some embodiments, the plurality of pins 12 further include a ground pin 123, and the ground pin 123 includes a ground center pin 1231, a plurality of ground extensions 1232, and a plurality of ground edge pins 1233. One end of each ground extension 1232 is connected to one of the plurality of ground edge pins 1233, and the other end of each ground extension 1232 is connected to the ground center pin 1231. One end of each ground extension 1232 connected to the ground center pin 1231 is closer to the die bonding area 11 than one end of each ground extension 1232 connected to the ground edge pin 1233. In some embodiments, the ground center pin 1231 is disposed directly below the die bonding area 11, and the upper surface of the ground center pin 1231 is connected to the lower surface of the die bonding area 11. In some embodiments, the ground center pin 1231 may be, but is not limited to, a solder pad of the die bonding area 11.

[0041] In some embodiments, the ground pin 123 is used to transmit a high-speed signal, but the present invention is not limited thereto, and the ground pin 123 can also be used to transmit a low-speed signal. In some embodiments, the ground pin 123 can be, but is not limited to, used to transmit a ground signal.

[0042] In some embodiments, the ground pins 123 are disposed at four corners of the die bonding region 11 , but the invention is not limited thereto.

[0043] See also Figure 2 and Figure 3 In some embodiments, part of the second pin 122 (i.e. Figure 2 and Figure 3 The second pin 1220 shown in the figure has a second extending portion 1222 that is slightly retracted because the second pin 1220 is different in length from the first pin 121 or because the first pin 121 compresses the space of the second extending portion 1222 .

[0044] In some embodiments, the plurality of first pins 121 are disposed on the same side of the die bonding region 11 , but the present invention is not limited thereto. The plurality of first pins 121 may also be disposed on multiple sides or two symmetrical sides of the die bonding region 11 at the same time.

[0045] In some embodiments, the length of the first edge pin 1211 and the second edge pin 1221 is 400 micrometers (μm), the length of the second pin 1220 is 1000 μm, the length of the other second pins 122 other than the second pin 1220 is 1700 μm, and the length of the first pin 121 is 2160 μm, but the present invention is not limited thereto.

[0046] Figure 8 FIG. 1 is a top view of an embodiment of a semiconductor device 10. Figure 8The semiconductor device 10 includes a die 2, a lead frame 1 suitable for QFN packaging, and a package body 3. The lead frame 1 includes a die bonding area 11 and a plurality of pins 12. The die bonding area 11 is used to set the die 2. The plurality of pins 12 are arranged around the die bonding area 11. The plurality of pins 12 include a plurality of first pins 121 and a plurality of second pins 122. The plurality of first pins 121 are arranged on one side of the die bonding area 11. The first pin 121 includes a first edge pin 1211, an inner pin 1212, and a first extension 1213. The inner pin 1212 is connected to the lower surface of one end of the first extension 1213, the first edge pin 1211 is connected to the lower surface of the other end of the first extension 1213, and the inner pin 1212 is closer to the die bonding area 11 than the first edge pin 1211. Each second pin 122 includes a second edge pin 1221 and a second extension 1222. The second edge pin 1221 is connected to the lower surface of one end of the second extension 1222. The end of the second extension 1222 not connected to the second edge pin 1221 is closer to the die bonding region 11 than the end of the second extension 1222 connected to the second edge pin 1221. The package 3 is used to cover the die 2 and part of the lead frame 1.

[0047] In some embodiments, the material of the package body 3 can be selected according to the impedance system used by the semiconductor device 10. In some embodiments, the material of the package body 3 is a common epoxy resin packaging material or an alumina epoxy resin packaging material, but the invention is not limited thereto.

[0048] In some embodiments, the lead frame 1 may have a distribution position or quantity of the plurality of pins 12 at one of its plurality of corners different from the distribution position or quantity of the plurality of pins 12 at other corners, so that the user can identify the direction in which the lead frame 1 and the semiconductor device 10 including the lead frame 1 are disposed. In some embodiments, the shape of one of the plurality of corners of the die bonding area 11 may be configured to be different from the shapes of the plurality of pins 12 at other corners. For example, one of the plurality of corners of the die bonding area 11 is a missing corner, while the other corners are not missing corners, so that the user can identify the direction in which the lead frame 1 and the semiconductor device 10 including the lead frame 1 are disposed.

[0049] In summary, in some embodiments, the signal transmitted by the first pin 121 in the lead frame 1 has a lower impedance because the lead 31 used to connect the first pin 121 and the die 2 has a shorter path length from the pad 21 of the die 2 to the power supply through the wiring design of the circuit board 101, and has higher signal and power integrity than the prior art. Therefore, the lead frame 1 can be applied to chip packaging of high-speed signals.

[0050] Although the technical content of the present invention has been disclosed as above in the form of preferred embodiments, this is not intended to limit the present invention. Any changes and modifications made by any person skilled in the art without departing from the spirit of the present invention shall fall within the scope of patent protection of the present invention. Therefore, the scope of patent protection of the present invention shall be based on the definition of the claims of the present invention.

Claims

1. A lead frame suitable for a quad flat no-lead package, characterized in that: include: a die bonding region, used for setting a die; and A plurality of pins are arranged around the die bonding area, and the plurality of pins include: At least one first pin is disposed on one side of the die bonding area, the first pin includes a first edge pin, an inner pin and a first extension, the inner pin is connected to a lower surface of one end of the first extension, the first edge pin is connected to a lower surface of the other end of the first extension, and the inner pin is closer to the die bonding area than the first edge pin; and A plurality of second pins, each of which includes a second edge pin and a second extension portion, wherein the second edge pin is connected to the lower surface of one end of the second extension portion, and the other end of the second extension portion is closer to the die bonding area than the end connected to the second edge pin.

2. The lead frame according to claim 1, characterized in that: The upper surface of one end of the first extension portion connected to the internal pin is used for wire bonding connection to the die.

3. The lead frame according to claim 2, characterized in that: The first pin is used to transmit a power signal.

4. The lead frame according to claim 3, characterized in that: The upper surface of the other end of the second extension portion is used for wire bonding connection to the die.

5. The lead frame according to claim 4, characterized in that: The plurality of pins further comprises: A ground pin, the ground pin comprising a ground center pin, a plurality of ground extensions and a plurality of ground edge pins, one end of each of the ground extensions being connected to one of the plurality of ground edge pins, the other end of each of the ground extensions being connected to the ground center pin, and the other end of each of the ground extensions being closer to the die bonding area than the end connected to the ground edge pin.

6. A semiconductor device, characterized in that: include: One grain; A lead frame suitable for QFN package, comprising: a die bonding region for arranging the die; and A plurality of pins are arranged around the die bonding area, and the plurality of pins include: at least one first pin disposed on one side of the die bonding region, the first pin comprising a first edge pin, an inner pin and a first extension, the inner pin being connected to a lower surface of one end of the first extension, the first edge pin being connected to a lower surface of the other end of the first extension, and the inner pin being closer to the die bonding region than the first edge pin; and A plurality of second pins, each of the second pins comprises a second edge pin and a second extension portion, The second edge pin is connected to a lower surface of one end of the second extension portion, and the other end of the second extension portion is closer to the die bonding area than the end connected to the second edge pin; and A package is used to cover the die and part of the lead frame.

7. The semiconductor device according to claim 6, wherein: The upper surface of one end of the first extension portion connected to the internal pin is used for wire bonding connection to the die.

8. The semiconductor device according to claim 7, wherein: The first pin is used to transmit a power signal.

9. The semiconductor device according to claim 8, wherein: The upper surface of the other end of the second extension portion is used for wire bonding connection to the die.

10. The semiconductor device according to claim 9, wherein: The plurality of pins further comprises: A ground pin, the ground pin comprising a ground center pin, a plurality of ground extensions and a plurality of ground edge pins, one end of each of the ground extensions being connected to one of the plurality of ground edge pins, the other end of each of the ground extensions being connected to the ground center pin, and the other end of each of the ground extensions being closer to the die bonding area than the end connected to the ground edge pin.

Images