Packaged semiconductor device and method of manufacture

Abstract

The invention relates to a packaged semiconductor device and a manufacturing method. A packaged semiconductor device having a top surface and a bottom surface opposite the top surface; the package semiconductor device includes a device die having a first surface and a second surface opposite to the first surface, arranged in a central region of the package semiconductor device, the first surface of the device die being arranged to face a bottom surface of the package semiconductor device, the second surface being arranged to face a top surface of the package semiconductor device; a plurality of peripheral platforms exposed to the bottom surface of the packaged semiconductor device and arranged in an edge region of the bottom surface and surrounding the device die; connection lines connected to the second surface of the device die, each connection line providing an electrical connection between a corresponding connection pad and a corresponding one of the plurality of peripheral platforms on the second surface of the device die; and a molding compound at least partially encapsulating the device die and the plurality of peripheral platforms. The plurality of peripheral platforms are made of a material having a mass fraction of tin of at least 95%.

Description

Technical Field

[0001] The present invention relates to a packaged semiconductor device and a method for manufacturing a packaged semiconductor device. Background Art

[0002] Leadless packaged semiconductor devices, such as quad flat no lead (QFN) packaged devices, have compact size due to the peripheral platform on the bottom surface being within the outline of the package. QFN packaged devices are manufactured by placing and connecting a chip die to a lead frame and molding the connected article. There is still a demand for QFN and similar packaged devices to become more compact. Summary of the invention

[0003] This Summary is provided to introduce a selected, simplified version of the concepts that are detailed in the Detailed Description below. This Summary is not intended to identify key or essential features of the claims nor is it intended to limit the scope of the claims.

[0004] According to one embodiment, a packaged semiconductor device has a top surface and a bottom surface opposite to the top surface; the packaged semiconductor device includes:

[0005] a device die having a first surface and a second surface opposite the first surface, wherein the device die is arranged in a central region of the packaged semiconductor device, and wherein the first surface of the device die is arranged toward a bottom surface of the packaged semiconductor device and the second surface of the device die is arranged toward a top surface of the packaged semiconductor device;

[0006] a plurality of peripheral platforms, the plurality of peripheral platforms being exposed to the bottom surface of the packaged semiconductor device and arranged at the edge region of the bottom surface and surrounding the device die;

[0007] connecting wires connected to the second surface of the device die, wherein each connecting wire provides an electrical connection between a corresponding connection pad on the second surface of the device die and a corresponding one of a plurality of peripheral platforms; and

[0008] a molding compound at least partially encapsulating the device die and the plurality of peripheral platforms;

[0009] The plurality of peripheral platforms are made of a material having a mass fraction of tin of at least 95%.

[0010] In one or more embodiments, the thickness of the connecting line is in the range of 10 microns to 20 microns.

[0011] In one or more embodiments, the active area of ​​the device die faces the second surface of the device die.

[0012] In one or more embodiments, the molding compound is exposed to a bottom surface of the packaged semiconductor device.

[0013] In one or more embodiments, the connection lines are disposed on a top surface of the molding compound.

[0014] In one or more embodiments, the melting point of the molding compound is lower than the eutectic temperature of the peripheral platform.

[0015] In one or more embodiments, the packaged semiconductor device further includes a coating disposed on a top surface of the packaged semiconductor device.

[0016] In one or more embodiments, a thickness of the coating layer between the mold compound and the top surface of the packaged semiconductor device is equal to or greater than a thickness of a connection line.

[0017] In one or more embodiments, the thickness of the coating is in the range of 25 microns and 40 microns.

[0018] According to another embodiment, a method of manufacturing a packaged semiconductor device includes:

[0019] providing a patterned paste material on a carrier, the paste material having a mass fraction of at least 95% tin;

[0020] reflowing the patterned paste material to form a plurality of arranged peripheral mesas;

[0021] placing the device die so that the device die is surrounded by the plurality of arranged peripheral platforms;

[0022] filling a molding compound to integrate the peripheral platform with the device die into an integral part, the integral part having a first surface; and

[0023] A connection line is formed between a connection pad on the first surface of the device die on the first surface of the monolithic piece and one of the plurality of arranged peripheral platforms to provide an electrical connection therebetween.

[0024] In one or more embodiments, providing the patterned paste material on the carrier includes printing the paste material through meshes of a screen.

[0025] In one or more embodiments, providing the patterned paste material on the carrier includes printing the paste material on the first plate, and the method further includes:

[0026] Prior to reflowing the patterned paste material, applying a tape strip on the patterned paste material such that after reflow, the plurality of arranged peripheral platforms are located between the first plate and the tape strip; and

[0027] removing the first plate; wherein

[0028] The placing of the device die includes placing the device die on a first side of the tape, the plurality of arranged peripheral platforms being arranged on the first side of the tape.

[0029] In one or more embodiments, the method further comprises removing the tape after the filling of the molding compound.

[0030] In one or more embodiments, the method further comprises:

[0031] applying a second plate on a second side of the strip opposite the first side; and

[0032] The strip and the second plate are removed after the filling of the molding compound.

[0033] In one or more embodiments, the first plate is a ceramic plate, the strip is a high temperature strip, and the second plate is a dense support plate.

[0034] In one or more embodiments, placing the device die on the first side of the tape includes facing the first side surface of the device die toward the tape.

[0035] In one or more embodiments, the method further comprises coating the first surface of the monolithic part with a coating, wherein the coating covers the connection line.

[0036] In one or more embodiments, coating the first surface of the monolithic part with a coating includes applying the coating to a thickness equal to or greater than a thickness of the connection line.

[0037] In one or more embodiments, the thickness of the connecting line is in the range of 10 microns and 20 microns.

[0038] In one or more embodiments, filling the molding compound to integrate the peripheral platform and the device die into an integral part includes:

[0039] Placing the peripheral platform and the device die into the mold cavity;

[0040] The mold cavity is filled with a molding compound to integrate the peripheral platform with the device die into a unitary part. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to make the foregoing of the present invention understood in a more specific manner, a further detailed description of the present invention can be obtained with reference to the embodiments, some of which are shown by the attached illustrations. The accompanying illustrations only show typical embodiments of the present invention, and because the present invention can have other equally effective embodiments, the accompanying illustrations should not be construed as limiting the scope of the present invention. The accompanying drawings are drawn for ease of understanding rather than for measuring the present invention. For those skilled in the art, the benefits of the claimed subject matter will be readily understood after reading this description and in conjunction with the accompanying illustrations. In the accompanying drawings, similar reference numerals are used to indicate similar elements, and:

[0042] Figure 1 is a cross-sectional view of a packaged semiconductor device of one embodiment;

[0043] Figure 2 is a flow chart of manufacturing a packaged semiconductor device in one embodiment;

[0044] Figures 3 to 14 is based on Figure 2 A method of manufacturing a packaged semiconductor device in an article of manufacture; and

[0045] Fig.15 is a partial plan view of an article after placement of a device die according to another embodiment. DETAILED DESCRIPTION

[0046] Figure 1 1 is a cross-sectional view of a packaged semiconductor device according to an embodiment. The packaged semiconductor device 100 has a top surface 102 and a bottom surface 104 opposite to the top surface 102. The packaged semiconductor device 100 includes a device die 106 located in a central region of the semiconductor device 100. The device die 106 has a first surface 108 and a second surface 110 opposite to the first surface 108. Figure 1 It can be seen that the first surface 108 of the device die 106 is arranged toward the bottom surface 104 , while the second surface 110 is arranged toward the top surface 102 .

[0047] The packaged semiconductor device 100 further includes a plurality of peripheral platforms 112 arranged near the periphery of the bottom surface 104 and surrounding the device die 106. Typically, the thickness of the device die 106 measured from the first surface 108 to the second surface 110 is in the range of 5 mils (0.125 mm) and 15 mils (0.375 mm). The thickness of each peripheral platform 112 can be equal to, greater than, or less than the thickness of the device die 106, and further, typically about 5 mils, about 0.125 mm. The peripheral platforms 112 are connected to the device die 106 by corresponding connection wires 114. In particular, the connection wires 114 are attached to the second surface 110 of the device die 106. Each connection wire 114 connects a corresponding connection pad (not shown) on the second surface 110 of the device die 106 to a corresponding one of the plurality of peripheral platforms 112. The device die 106 is placed in the semiconductor device 100 so that the active area of ​​the device die 106 faces the second plane 110 to provide connection to the connection wires 114 on the second plane 110. In various embodiments, the connection wires 114 may be implemented as a copper tape material or the like having a flat shape with a thickness ranging from 10 microns to 20 microns.

[0048] The packaged semiconductor device 100 further includes a molding compound 116 that at least partially molds the device die 106 and the peripheral platform 112. The molding compound 116 is electrically isolating. The molding compound 116 fills the gap between the device die 106 and the peripheral platform 112 to a thickness equal to or greater than the thickness of the device die 106, so that the molding compound is exposed at the bottom surface 104 of the packaged semiconductor device 100 and forms a part of the bottom surface 104. The second surface 110 of the device die 106 is coplanar with the surface of the molding compound 116, so that the connection wire 114 can contact the second surface 110, which means that the connection wire 114 is arranged above the molding compound 116.

[0049] According to an embodiment, the peripheral platform 112 is made of a material having a mass percentage of at least 95% tin. In particular, the peripheral platform 112 is formed by printing a paste material onto the mesh of the screen and reflowing the printed paste material. The paste material includes a high mass fraction of tin and has a eutectic temperature of at least 210 degrees Celsius (210°C). For example, some lead-free high-tin paste materials have a higher eutectic temperature of 280°C. The material used for the peripheral platform 112 is selected to have a melting point high enough for the peripheral platform 112 so that the peripheral platform 112 does not melt when the final packaged semiconductor device 100 is mounted on a printed circuit board (PCB) by a surface mounting process (SMT). In the SMT process, solder paste is used to mount the packaged semiconductor device on the PCB and then reflow. The melting point of the solder paste is lower than that of the high-tin paste material.

[0050] Also considering the material used for the peripheral platform 112, the melting point of the molding compound 116 of the semiconductor device 100 is lower than the eutectic temperature of the peripheral platform 112. Conveniently, the molding compound 116 of the semiconductor device 100 is selected from epoxy molding compound (EMC) material, which has a melting point of about 175°C.

[0051] The packaged semiconductor device 100 may include a coating 118 disposed on the top surface 102. The coating 118 protects the second surface 110 of the device die 106 exposed from the molding compound 116, the connection wires 114, and the exposed portion of the peripheral platform 112 from corrosion caused by oxidation, moisture, etc. The thickness of the coating 118 is at least equal to the thickness of the connection wires 114, preferably in the range of 25 microns and 40 microns. The coating 118 can be disposed by spraying a paint or conformal coating on the top surface 102, which can isolate and protect the covered components after curing.

[0052] The packaged semiconductor device 100 includes a peripheral platform 112 formed of a tin-containing paste material to replace a conventional lead frame to provide external connections to the device die 106. Since the connecting wires 114 are arranged in close proximity to the surface of the die (rather than requiring a flex loop as in the case of conventional wire bonding), the packaged semiconductor device 100 can be manufactured with a thickness as compact as 0.05 mm to 0.1 mm.

[0053] Figure 2 The present invention is a flow chart of a method for manufacturing a packaged semiconductor device. The method can be implemented as follows: Figure 1 The method is based on the packaged semiconductor device 100. Figure 2 And refer to Figures 3 to 14 describe, Figures 3 to 14 Shown in Figure 2 Cross-sectional views of the manufactured component at various steps.

[0054] Step 202 of the method includes disposing a paste material. Figure 3, the paste material 302 is placed on a support plate or carrier 304. The support plate 304 is typically a non-wetting plate, such as a ceramic plate, or includes a peeling layer on its surface. The paste material 302 is arranged on the support plate 304 to form a patterned paste material. In some embodiments, the paste material 302 is printed into the mesh 306 of the screen 308 that has been subjected to a non-wetting treatment. Known screen printing processes can be used to arrange the paste material 302. The paste material 302 can be printed to have a thickness equal to or similar to that of the screen 308. Typically, the screen 308 has a thickness of 5 mils, which is approximately 0.125 mm. In some embodiments, the thickness of the screen 308 is equal to the thickness of the device die of the semiconductor device that will be placed to manufacture the package. In this embodiment, the paste material 302 includes tin, and as previously described, the mass ratio of tin is at least 95% to have a relatively high eutectic temperature.

[0055] Figure 4 A partial plan view of a screen 308 is shown. The screen 308 has mesh holes 306 that are aligned in intersecting directions. The area 310 surrounded by the mesh holes 306 will not have paste material printed on it after the screen 308 is placed on the support plate 304, and the area 310 will be used to place the device die. The screen is shown as an array of cells, each cell including a corresponding area 310 and surrounding mesh holes 306. As will be described below, each cell of the array will form a corresponding packaged semiconductor device. Figure 4 As can be seen, the paste material 302 will be printed to conform to the mesh 306. The paste material 302, after reflow and final curing as described below, forms an area that will eventually become two peripheral platforms (one for each of the two dies). This area will also include a sacrificial area that will be discarded due to subsequent sawing and kerf width loss, as will be described in further detail.

[0056] exist Figure 2 In step 304 of the method, a high temperature tape is applied to the screen 308 , covering the screen 308 and the printed paste material 302 . Figure 5 308 and the covered tape. The high temperature tape 312 is attached to the wire mesh 308 and the paste material 302, and there is typically a holding plate 314 on the other side of the high temperature tape 312 for applying a force to push the high temperature tape 312 toward the wire mesh 308 and the paste material 302, thereby ensuring that the high temperature tape 312 is reliably attached to the paste material 302.

[0057] After step 204, the printed paste material 302 is reflowed in step 206 of the method. Figure 5, the component is heated to at least the eutectic temperature of the paste material 302. In particular, the support plate 304 is heated, thereby raising the temperature of the paste material 302 located in the mesh 306 on the support plate 304. As described, the paste material 302 has a eutectic temperature of at least 210°C, and the reflow step 206 heats the paste material 302 until it is in a molten state, and the volatile solvent in the paste material 302 is volatilized. Subsequently, it is cooled, and the molten metal elements in the paste material solidify to form a peripheral platform for the semiconductor device to be manufactured. It can be understood that the resulting peripheral platform is sandwiched between the support plate 304 and the high-temperature strip 312, which mainly includes tin, or a tin alloy with a high tin content.

[0058] refer to Figure 2 and Figure 6 The method further includes step 208, turning over the product obtained in the previous step 206, so that the holding plate 314, also known as the support plate, is located at the bottom and supports the high temperature strip 312, the peripheral platform 112 (with Figure 1 ), screen 308, and support plate 304. To support and hold high temperature tape 312, peripheral platform 112, screen 308, and support plate 304, support plate 314 is selected to be sufficiently dense. Due to the flipping, screen 308 and support plate 304 are located at the top and are easy to remove. Because screen 308 has been non-wetting treated and high temperature tape 312 is sticky, peripheral platform 112 remains on high temperature tape 312.

[0059] In step 210 of the method, the device die is placed on the high temperature tape 312 and positioned to be surrounded by the peripheral platform. Figure 7 , which is a cross-sectional view of the product obtained after step 210; and reference Figure 8 , which is a plan view of the product after the device die is placed, as described above in conjunction with Figure 4 As described, the device die 106 is placed in the central area 310 and is surrounded by a plurality of arranged areas 802. It can be understood that the areas 802 and the device die 106 are both arranged on one side of the high-temperature strip 312, and the support plate 314 is located on the second side opposite to the high-temperature strip 312. When the device die is placed on the strip 312, the device die 106 has a first surface 108 away from the high-temperature strip 312, and a second surface 110 facing and contacting the high-temperature strip 312. As described above, the active area or active layer of the device die 106 faces the second surface 110. The area 802 is generally elliptical, and the two ends 804 of the area 802 will become peripheral platforms for providing external connections to adjacent device dies, respectively. The sacrificial area 806 between the two ends 804 will be removed in subsequent sawing and / or etching, such as Figure 8 Shown by the dashed line.

[0060] Back to Figure 2 The method further includes step 212 of filling the gap between the device die 106 and the peripheral platform 112 with a molding compound to integrate the peripheral platform 112 and the device die 106 together. Fig. 9 As shown, the peripheral platform 112 and the device die 106 are placed in a mold cavity (not shown), and the molding compound 116 is filled or injected into the mold cavity to integrate the peripheral platform 112 and the device die 106 into an integral part 316, which includes the peripheral platform 112, the device die 106 and the filled molding compound 116. The integral part 316 has a first surface or top surface 318 and a second surface or bottom surface 320. The second surface 320 is in contact with the high temperature tape 312. As described above, considering the material used for the peripheral platform 112, the molding compound 116 should be selected to have a melting point lower than the eutectic temperature of the peripheral platform 112. Typically, the molding compound 116 is selected from an epoxy molding compound (EMC) material, which has a melting point of about 175°C.

[0061] After the molding compound 116 is cured and the monolithic part 316 exits the mold cavity, the high temperature tape 312 and the support plate 314 are removed. After the high temperature tape 312 and the support plate 314 are removed, the second surface 110 of the device die 106, i.e., the surface near the active area of ​​the device die 106, is exposed. The thickness of the applied molding compound 116 measured from the first surface 318 to the second surface 320 is equal to or greater than the greater of the thickness of the peripheral platform 112 and the device die 106, so that the molding compound 116 is thick enough to protect the device die 106 and the peripheral platform 112. This means that after the tape 312 and the support plate 314 are removed, generally only the molding compound 116 is exposed on the first surface 318 of the monolithic part 316.

[0062] At step 214, the monolithic part 316 is flipped over so that the first surface 318 supports the monolithic part 316. At step 214, bonding wires are also applied to provide electrical connections between the device die and the peripheral platform. Fig.10As shown, each connection wire 114 has a first end, which contacts a contact pad (not shown) on the device die 106 and provides an electrical connection to the contact pad; and has a second end, which contacts one of the contact pads of the peripheral platform 112 corresponding to the device die 106 and provides an electrical connection to the peripheral platform 112. The connection wire 114 is connected to the integral part 316 on the second surface 320, so that the resulting packaged semiconductor device can have a size that is as compact as possible. The connection wire 114 can be any of a number of compact connection means, such as a copper strip having a flat shape. In an embodiment, the connection wire 114 has a thickness of 10 microns to 20 microns. In some embodiments, the connection wire 114 can be applied by 3D printing technology, or so-called "jet printing" technology, which distributes functional liquids, such as conductive inks, as traces to form conductive wires.

[0063] Fig.11 A partial view of an example is shown, where each semiconductor device has a row of peripheral platforms 112 on each side. The peripheral platforms 112 generally have a semi-elliptical shape, corresponding to the mesh of the wire screen, but with some rounded features due to the reflow process. Fig.11 In the embodiment, each of the connection wires 114 is connected from the device die 106 to a corresponding one of the peripheral platforms 112. Fig.12 Another example is shown in which each semiconductor device has about two columns of peripheral mesas 112 on each side. Fig.12 The peripheral platforms in are configured as circular (this depends on the mesh of the screen that allows the paste material to be printed), and the connecting wires 114 are also connected from the device tube core 106 to the corresponding one of the peripheral platforms 112, but the connecting wires 114 are routed to avoid contact with each other and avoid contact with other peripheral platforms 112.

[0064] exist Figure 2 In the method, step 216 is followed by coating the second surface to which the connecting wire has been applied with a coating. Fig.13, the coating 118 is applied to the second surface 320 to cover the second surface 320 and the connection wire 114. As described above, the coating 118 can be a conformal coating or paint or other possible coating to protect the second surface 110 of the device die 106, the peripheral platform 112 exposed on the second surface 320 of the self-molding compound 116, and the connection wire 114 from moisture, acid or other rust or corrosion. The coating 118 is applied to the second surface 320 to a thickness that is typically equal to or greater than the thickness of the connection wire 114. In an example, the coating is applied by conformal coating and the applied coating material flows onto the connection wire 114. As described above, the thickness of the connection wire may typically be in the range of 10 microns to 20 microns. In an embodiment, the thickness of the coating 118 is within the range of 25 microns and 40 microns. Step 216 further includes, optionally, grinding the integral part 316 thin from the first surface 318. The overall part 316 is ground thin to ensure that the peripheral platform 112 on the first surface 318 is properly exposed and there is no excess molding compound underneath. As shown, the second surface 320 is coated and isolated, and the peripheral platform 112 is exposed on the first surface 318 via back grinding to provide external connections for the packaged semiconductor device 100.

[0065] Figure 2 Step 218 of the method is to separate the individual monolithic components from each other, each of which has a device die integrated therein. This step can be performed by laser scribing, sawing or etching along predetermined scribing lines, cutting paths or dicing paths between adjacent monolithic components. Figure 8 and Fig.14 In the array, each peripheral platform 112 may be part of a larger area shared by adjacent integral components, and step 218 separates the area including a pair of peripheral platforms 112 by sawing or other appropriate techniques, so that each packaged semiconductor device 100 includes a separate peripheral platform 112.

[0066] In the described embodiments, the packaged semiconductor device has a peripheral platform formed by screen printing and reflow, without the need for existing lead frames, bumps, etc. The resulting semiconductor device can be very thin and compact, typically having a minimum thickness of 0.05 mm to 0.1 mm, which is thin compared to existing packaged semiconductor devices.

[0067] Fig.15 is with Figure 8 15. The screen for printing the paste material used to form the peripheral platform 1502 is configured so that the adjacent central area for receiving the device tube core 1504 does not share the same central area as shown in FIG. Figure 8The paste material area indicated by 802 in FIG. Here, a peripheral platform 1502 in the peripheral area of ​​one device die 1504 is separated from the peripheral platform 1502 for an adjacent device die 1504 by a gap 1506. When the molding compound is dispensed, the gap 1506 is filled with the molding compound. In the subsequent singulation process, the molding compound filled in the gap 1506 will be removed, as shown by the dotted line in the figure. If the singulation step is implemented to be wide enough to reach the edge of the corresponding peripheral platform, the peripheral platform 1502 is exposed on the cut formed by singulation; if the singulation step does not reach the edge of the peripheral platform, the peripheral platform 1502 is not exposed on the cut formed by singulation.

[0068] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art to form a clear understanding of and implement the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0069] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and other positional relationships may be substituted when the orientation of the device changes during manufacture or operation. As mentioned above, those positional relationships are described only for the sake of clarity and are not limiting.

[0070] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and non-restrictive. In the drawings, the dimensions of the various elements may be exaggerated for illustrative purposes and may not be drawn to a specific scale. This description should also include discontinuous changes in tolerances and properties of various components and working methods. Various weakened implementations of the invention should also be included.

[0071] The word "comprising" used in this description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form such as "one" or "an" is used to refer to a certain or uncertain element, the plural number of the element should be included. Thus, the word "comprising" should not be understood to be limited to the items listed thereafter, and should not be understood to exclude other elements or steps; the scope of the description "the device includes items A and B" should not be limited to a device that only includes elements A and B. This description indicates that, for the purpose of this description, only elements A and B of the device are relevant. Although coupling generally includes inductive connection and connection generally means connection through, for example, wires, the "connection", "coupling" and "coupling" described here all indicate that there is an electrical connection between the coupled or connected elements, and do not mean that there are no intermediate elements between them. When describing transistors and their connections, the words gate, drain, and source are interchangeable with gate, drain, source, and gate terminal, drain terminal, and source terminal.

[0072] It will be apparent to those skilled in the art that various detailed changes may be made without departing from the scope of the claims of the present invention.

Claims

1. A packaged semiconductor device, characterized in that: The packaged semiconductor device has a top surface and a bottom surface opposite the top surface; The packaged semiconductor device comprises: a device die having a first surface and a second surface opposite the first surface, wherein the device die is arranged in a central region of the packaged semiconductor device, and wherein the first surface of the device die is arranged toward a bottom surface of the packaged semiconductor device and the second surface of the device die is arranged toward a top surface of the packaged semiconductor device; a plurality of peripheral platforms, the plurality of peripheral platforms being exposed to the bottom surface of the packaged semiconductor device and arranged at the edge region of the bottom surface and surrounding the device die; connecting wires connected to the second surface of the device die, wherein each connecting wire provides an electrical connection between a corresponding connection pad on the second surface of the device die and a corresponding one of a plurality of peripheral platforms; and a molding compound at least partially encapsulating the device die and the plurality of peripheral platforms; The plurality of peripheral platforms are made of a material having a mass fraction of tin of at least 95%.

2. The packaged semiconductor device according to claim 1, wherein: The connection lines are disposed over a top surface of the molding compound.

3. The packaged semiconductor device according to claim 1, wherein: The molding compound has a melting point below the eutectic temperature of the peripheral platform.

4. The packaged semiconductor device according to claim 1, wherein: Further included is a coating disposed on a top surface of the packaged semiconductor device.

5. The packaged semiconductor device according to claim 4, characterized in that The thickness of the coating between the mold compound and the top surface of the packaged semiconductor device is equal to or greater than the thickness of the connecting wire.

6. A method for manufacturing a packaged semiconductor device, characterized in that: include: providing a patterned paste material on a carrier, the paste material having a mass fraction of at least 95% tin; reflowing the patterned paste material to form a plurality of arranged peripheral mesas; placing the device die so that the device die is surrounded by the plurality of arranged peripheral platforms; filling a molding compound to integrate the peripheral platform and the device die into an integral part, wherein the integral part has a first surface; as well as A connection line is formed between a connection pad on the first surface of the device die on the first surface of the monolithic piece and one of the plurality of arranged peripheral platforms to provide an electrical connection therebetween.

7. The method according to claim 6, characterized in that Providing the patterned paste material on the carrier includes printing the paste material on the first plate, and the method further includes: Prior to reflowing the patterned paste material, applying a tape strip on the patterned paste material such that after reflow, the plurality of arranged peripheral platforms are located between the first plate and the tape strip; and removing the first plate; wherein The placing of the device die includes placing the device die on a first side of the tape, the plurality of arranged peripheral platforms being arranged on the first side of the tape.

8. The method according to claim 6, characterized in that The method further includes coating the first surface of the integral part with a coating, wherein the coating covers the connecting line.

9. The method according to claim 8, characterized in that Coating the first surface of the monolithic part with a coating includes applying the coating to a thickness equal to or greater than a thickness of the connection line.

10. The method according to claim 6, characterized in that The filling of the molding compound to integrate the peripheral platform and the device die into an integral part comprises: Placing the peripheral platform and the device die into the mold cavity; The mold cavity is filled with a molding compound to integrate the peripheral platform with the device die into a unitary part.

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