Semiconductor package

Abstract

A semiconductor package includes: a redistribution substrate including a first surface and a second surface opposite to each other; the semiconductor chip is positioned on the first surface of the redistribution substrate; and a connection terminal, wherein the connection terminal is located on the second surface of the redistribution substrate. The redistribution substrate includes: an insulating layer; a redistribution pattern, the redistribution pattern being located in the insulating layer; and a lower bump pattern which is located between the redistribution pattern and the connection terminal. The lower bump pattern includes: a via portion penetrating the insulating layer and connected to the redistribution pattern; and a protrusion that protrudes into the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package. Background Art

[0002] Integrated circuit chips can be formed in semiconductor packages to be compatible with electronic products. In a typical semiconductor package, the semiconductor chip can be mounted on a printed circuit board and can be electrically connected to the printed circuit board through bonding wires or bumps. With the development of the electronics industry, various technologies for improving the reliability of semiconductor packages and for miniaturizing semiconductor packages have been studied. Summary of the invention

[0003] In some implementations, the disclosed devices and techniques may provide semiconductor packages with improved reliability.

[0004] In general, various aspects of the subject matter described in this specification can be implemented in a semiconductor package, the semiconductor package comprising: a redistribution substrate, the redistribution substrate comprising a first surface and a second surface opposite to each other; a semiconductor chip, the semiconductor chip being located on the first surface of the redistribution substrate; and a connection terminal, the connection terminal being located on the second surface of the redistribution substrate. The redistribution substrate may include: an insulating layer; a redistribution pattern, the redistribution pattern being located in the insulating layer; and a lower bump pattern, the lower bump pattern being located between the redistribution pattern and the connection terminal. The lower bump pattern may include: a via portion, the via portion penetrating the insulating layer and connected to the redistribution pattern; and a protrusion, the protrusion protruding into the insulating layer.

[0005] Another general aspect can be implemented in a semiconductor package, the semiconductor package comprising: a redistribution substrate, the redistribution substrate comprising a first surface and a second surface opposite to each other; a semiconductor chip, the semiconductor chip being located on the first surface of the redistribution substrate; and a connection terminal, the connection terminal being located on the second surface of the redistribution substrate. The redistribution substrate may include: an insulating layer; a redistribution pattern, the redistribution pattern being located in the insulating layer; and a lower bump pattern, the lower bump pattern being located between the redistribution pattern and the connection terminal. The insulating layer may include: a through hole, the through hole exposing the redistribution pattern; and a recess, the recess being spaced apart from the through hole in a first direction parallel to the second surface of the redistribution substrate. The lower bump pattern may fill the through hole and the recess.

[0006] Another general aspect can be implemented in a semiconductor package, the semiconductor package comprising: a lower semiconductor package; and an upper semiconductor package, the upper semiconductor package being located on the lower semiconductor package. The lower semiconductor package may include: a lower redistribution substrate; an upper redistribution substrate, the upper redistribution substrate being located on the lower redistribution substrate; and a semiconductor chip, the semiconductor chip being located between the lower redistribution substrate and the upper redistribution substrate. The lower redistribution substrate may include: a plurality of insulating layers; a redistribution pattern, the redistribution pattern being disposed in the insulating layer; and an under bump metal (UBM), the under bump metal being disposed on a lowermost insulating layer of the plurality of insulating layers. The under bump metal may include: a seed / barrier pattern; and a conductive pattern, the conductive pattern being located on the seed / barrier pattern. The under bump metal may include: a via portion, the via portion penetrating the lowermost insulating layer so as to contact one of the redistribution patterns that is adjacent thereto in a vertical direction; and a protrusion, the protrusion protruding into the lowermost insulating layer. The protrusion may be spaced apart from the one redistribution pattern, and a height of the protrusion may be smaller than a height of the via portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view showing an example of a semiconductor package.

[0008] Figure 2 is a bottom view showing an example of a lower bump pattern of a semiconductor package.

[0009] Figure 3A It is along Figure 2 A cross-sectional view taken along line II'.

[0010] Figure 3B It is along Figure 2 A cross-sectional view taken along line II-II'.

[0011] Figure 4 is corresponding to Figure 2 Cross-sectional view along line II'.

[0012] Figure 5 is a bottom view showing an example of a lower bump pattern of a semiconductor package.

[0013] Figure 6 It is along Figure 5 A cross-sectional view taken along line III-III'.

[0014] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7Fand Figure 7G is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor package.

[0015] Fig. 8A yes Figure 7B Magnified view of area "bb".

[0016] Figure 8B yes Figure 7C Magnified view of area "cc".

[0017] Figure 8C is a top view showing an example of a schematic shape of a mask pattern.

[0018] Fig.8D yes Fig.7D Magnified view of area “dd”.

[0019] Fig. 8E yes Fig. 7E Magnified view of area “ee”.

[0020] Figure 8F yes Figure 7F Magnified view of area “ff”.

[0021] Fig. 9 is a cross-sectional view showing an example of a semiconductor package.

[0022] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor package. DETAILED DESCRIPTION

[0023] Figure 1 is a cross-sectional view showing a semiconductor package.

[0024] refer to Figure 1 , the semiconductor package 1000 includes a first semiconductor package PK1 and a second semiconductor package PK2 located on the first semiconductor package PK1. The semiconductor package 1000 may have a package-on-package (PoP) structure. In some embodiments, the first semiconductor package PK1 and the second semiconductor package PK2 may be referred to as a lower semiconductor package PK1 and an upper semiconductor package PK2, respectively.

[0025] For example, the first semiconductor package PK1 may be a fan-out panel level package type semiconductor package.

[0026] The first semiconductor package PK1 may include a first redistribution substrate 100, a connection substrate 400, a first semiconductor chip 300, a second redistribution substrate 200, and a sealing member 500. In some embodiments, the first and second redistribution substrates 100 and 200 may be referred to as lower and upper redistribution substrates 100 and 200, respectively.

[0027] The first redistribution substrate 100 may include a plurality of first insulating layers 110 and 110B, first redistribution patterns 120 , lower bump patterns 130 , and external connection terminals 180 .

[0028] The first redistribution substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a may refer to the top surface of the uppermost first insulating layer 110 of the first insulating layers 110 and 110B. The second surface 100b may refer to the bottom surface of the lowermost first insulating layer 110B of the first insulating layers 110 and 110B.

[0029] In some embodiments, the first direction D1 may be defined as a direction parallel to the second surface 100b. The second direction D2 may be defined as a direction perpendicular to the second surface 100b.

[0030] Each of the first insulating layers 110 and 110B may include a photosensitive polymer. Each of the first insulating layers 110 and 110B may include at least one of photosensitive polyimide, polybenzoxazole, phenol-based polymer, benzocyclobutene-based polymer, or Ajinomoto build-up film (ABF).

[0031] In some embodiments, the interface between the first insulating layers 110 and 110B adjacent to each other may not be observed. In other words, the first insulating layers 110 and 110B may be regarded as a single insulating layer.

[0032] Each of the first redistribution patterns 120 may include a seed / barrier pattern SP and a conductive pattern CP. The conductive pattern CP may be disposed on the seed / barrier pattern SP. The seed / barrier pattern SP may include copper (Cu) / titanium (Ti) or titanium nitride (TiN). The conductive pattern CP may include copper. In the present disclosure, a "seed / barrier layer" is a layer that can be used as one or both of a seed layer and a barrier layer.

[0033] The lowermost first redistribution pattern 120 among the first redistribution patterns 120 may contact the lower bump pattern 130. In some embodiments, the lower bump pattern 130 may be referred to as an under bump metal (UBM) or an under bump metal layer (UBM). The lower bump pattern 130 may include a seed / barrier pattern SP and a conductive pattern CP. The thickness of the seed / barrier pattern SP may range from 1 μm to 2 μm, and the thickness of the conductive pattern CP may range from 10 μm to 20 μm.

[0034] The shape of the lower bump pattern 130 will be described in detail below. The external connection terminal 180 may be disposed on the lower bump pattern 130. The external connection terminal 180 may include at least one of a solder ball, a column, or a bump. The external connection terminal 180 may include a conductive material such as tin (Sn) and / or silver (Ag).

[0035] The connection substrate 400 may be disposed on the first surface 100a of the first redistribution substrate 100. The connection substrate 400 may have a cavity 400c penetrating a central portion of the connection substrate 400. For example, the connection substrate 400 may be manufactured by forming the cavity 400c in a printed circuit board (PCB). The connection substrate 400 may include a base layer 410 and a conductive structure 420.

[0036] Each of the base layers 410 may include at least one of a phenolic resin, a thermosetting resin (e.g., an epoxy resin), a thermoplastic resin (e.g., a polyimide), or an insulating material obtained by impregnating a thermosetting or thermoplastic resin with a material (e.g., an inorganic filler and / or glass fiber (or glass cloth or glass fabric). For example, the base layer 410 may include at least one of a prepreg, an Ajinomoto built-up film (ABF), a flame retardant 4 (FR4), a tetrafunctional epoxy resin, polyphenylene ether, bismaleimide triazine (BT), epoxy resin / polyphenylene ether, polyamide staple fiber mat, cyanate ester, polyimide, or a liquid crystal polymer.

[0037] The conductive structure 420 may include a first connection pad 421 , a second connection pad 422 , a connection line 423 , and a connection via 424 .

[0038] The first connection pad 421 may be provided at the bottom surface of the connection substrate 400. The connection line 423 may be provided between the base layers 410. The connection path 424 may penetrate the base layer 410 to connect to the connection line 423. The second connection pad 422 may be provided on the top surface of the connection substrate 400 and may be connected to a corresponding one of the connection paths 424. The second connection pad 422 may be electrically connected to the first connection pad 421 through the connection path 424 and the connection line 423. Figure 1Different, the second connection pad 422 may not be aligned with the first connection pad 421 in the second direction D2. The number or arrangement of the second connection pads 422 may be different from the number or arrangement of the first connection pads 421. For example, each of the first connection pad 421, the second connection pad 422 and the connection line 423 may include at least one of electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, or copper alloy. The connection path 424 may include at least one of copper, nickel, stainless steel, or beryllium copper.

[0039] The first semiconductor chip 300 may be disposed in the cavity 400c of the connection substrate 400. More particularly, the first semiconductor chip 300 may be disposed on the first redistribution substrate 100 so that the first chip pad 310 of the first semiconductor chip 300 faces the first redistribution substrate 100. The horizontal cross-sectional area of ​​the cavity 400c may be greater than the horizontal cross-sectional area of ​​the first semiconductor chip 300. The first semiconductor chip 300 may be spaced apart from the inner side surface of the connection substrate 400 in the cavity 400c. The first semiconductor chip 300 may be a logic chip. For example, the first semiconductor chip 300 may be a central processing unit (CPU), a microprocessing unit (MPU), a graphics processing unit (GPU), or an application processor (AP).

[0040] The sealing member 500 can fill the gap between the inner side surface of the first semiconductor chip 300 and the connection substrate 400. The sealing member 500 can cover the top surface of the first semiconductor chip 300 and the top surface of the connection substrate 400. The sealing member 500 may include a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or a resin formed by providing a reinforcing material (e.g., an inorganic filler) to a thermosetting or thermoplastic resin. For example, the sealing member 500 may include an Ajinomoto stacked film (ABF).

[0041] The second redistribution substrate 200 may be disposed on the sealing member 500. The second redistribution substrate 200 may include second insulating layers 210 and 210T, second redistribution patterns 220, and bonding pads 230. The second insulating layers 210 and 210T may include the same / similar materials as the first insulating layers 110 and 110B. The lowermost second redistribution pattern 220 among the second redistribution patterns 220 may be connected to or contact the second connection pads 422 of the connection substrate 400. The bonding pads 230 may be disposed on the uppermost second redistribution pattern 220 of the second redistribution patterns 220. For example, the top surface of the bonding pad 230 may protrude from the top surface of the uppermost second insulating layer 210T. Each of the second redistribution pattern 220 and the bonding pad 230 may include a seed / barrier pattern SP and a conductive pattern CP located on the seed / barrier pattern SP, and may include the same / similar materials as the first redistribution pattern 120 and the lower bump pattern 130.

[0042] The second semiconductor package PK2 may be disposed on the second redistribution substrate 200. The second semiconductor package PK2 may include a packaging substrate 600, a second semiconductor chip 700, and a molding member 800. For example, the packaging substrate 600 may be a printed circuit board. The first metal pad 610 and the second metal pad 620 may be disposed on the bottom surface and the top surface of the packaging substrate 600, respectively. For example, the second semiconductor chip 700 may be a memory chip such as a DRAM chip or a NAND flash chip. The type of the second semiconductor chip 700 may be different from the type of the first semiconductor chip 300. The second chip pad 710 disposed on the surface of the second semiconductor chip 700 may be connected to the second metal pad 620 of the packaging substrate 600 by a wire bonding method. In some embodiments, the second semiconductor chip 700 may be connected to the packaging substrate 600 by a flip chip bonding method instead of a wire bonding method.

[0043] The package connection terminal 680 may be disposed between the first semiconductor package PK1 and the second semiconductor package PK2. The package connection terminal 680 may contact the bonding pad 230 and the first metal pad 610. The package connection terminal 680 may electrically connect the first semiconductor package PK1 and the second semiconductor package PK2. For example, the second semiconductor chip 700 may be electrically connected to the first semiconductor chip 300 and the external connection terminal 180 through the bonding wire, the package substrate 600, the package connection terminal 680, the second redistribution substrate 200, the connection substrate 400, and the first redistribution substrate 100. The package connection terminal 680 may include at least one of a solder ball, a column, or a bump. The package connection terminal 680 may include a conductive material such as tin (Sn) and / or silver (Ag).

[0044] Figure 2 is a bottom view showing a lower bump pattern of a semiconductor package. Figure 3A It is along Figure 2 A cross-sectional view taken along line II'. Figure 3A yes Figure 1 Magnified view of area "aa". Figure 3B It is along Figure 2 A cross-sectional view taken along line II-II'.

[0045] refer to Figure 1 , Figure 2 , Figure 3A and Figure 3B , the lowermost first insulating layer 110B of the first insulating layers 110 and 110B includes a through hole VH and a recess RS. The through hole VH and the recess RS may be spaced apart from each other in the first direction D1. The through hole VH may expose the bottom surface of the conductive pattern CP of the first redistribution pattern 120 adjacent thereto in the second direction D2. The recess RS may not expose the bottom surface of the conductive pattern CP of the first redistribution pattern 120, for example, the recess RS is spaced apart from the redistribution pattern 120 and separated from the redistribution pattern 120. The through hole VH may have a first depth X1 in the second direction D2, and the recess RS may have a second depth X2 in the second direction D2. The second depth X2 may be less than the first depth X1. The second depth X2 may be greater than 1 / 8 of the first depth X1. In particular, the second depth X2 may be greater than 1 / 8 of the first depth X1, and may be less than 1 / 4 of the first depth X1. For example, the first depth X1 may range from 20 μm to 30 μm, and the second depth X2 may range from 5 μm to 15 μm.

[0046] The lower bump pattern 130 may fill the through hole VH and the recess RS, and may extend laterally on the bottom surface (e.g., the second surface 100b) of the lowest first insulating layer 110B between the through hole VH and the recess RS. The seed / barrier pattern SP of the lower bump pattern 130 may partially fill the through hole VH and the recess RS. The conductive pattern CP of the lower bump pattern 130 may partially fill the through hole VH. The conductive pattern CP of the lower bump pattern 130 may completely fill the recess RS. The lower bump pattern 130 may include a via portion 130V, a protrusion 130P, and a connecting portion 130L. The connecting portion 130L may connect the via portion 130V and the protrusion 130P. When viewed in a cross-sectional view, the lower bump pattern 130 may have a W-shape or a W-like shape. In the present disclosure, a W-shaped shape may mean having a first horizontal portion connected to two inclined portions (e.g., a passage portion 130V at both ends of the first horizontal portion) and a second horizontal portion and a third horizontal portion (e.g., a connecting portion 130L) at both ends of the two inclined portions, wherein the first horizontal portion has a greater height than the second horizontal portion and the third horizontal portion.

[0047] The via portion 130V may include a portion of the seed / barrier pattern SP and a portion of the conductive pattern CP filling the via hole VH. The via portion 130V may penetrate the lowermost first insulating layer 110B to contact the first redistribution pattern 120 adjacent thereto in the second direction D2. Figure 2 , when viewed in a top plan view, the via portion 130V may have a circular shape.

[0048] Each protrusion 130P may include another portion of the seed / barrier pattern SP and another portion of the conductive pattern CP that fills the recess RS. The protrusion 130P may protrude into the lowermost first insulating layer 110B. The protrusion 130P may be spaced apart from the first redistribution pattern 120 adjacent thereto in the second direction D2. The protrusion 130P may be disposed at an edge of the lower bump pattern 130. The level of the top surface 130PS of the protrusion 130P may be higher than the level of the bottom surface (e.g., the second surface 100b) of the lowermost first insulating layer 110B, and may be lower than the level of the top surface 130VS of the via portion 130V. Similar to Figure 2 When viewed in a top view, the protrusion 130P may constitute a segmented annular shape. When viewed in a top view, the protrusion 130P may surround the via portion 130V.

[0049] The connection portion 130L may include a remaining portion of the seed / barrier pattern SP and a remaining portion of the conductive pattern CP disposed on, for example, the second surface 100b of the lowermost first insulating layer 110B. The connection portion 130L may be disposed between the via portion 130V and the protrusion 130P and may have a ring shape when viewed in a top view, similar to Figure 2 The connection portion 130L may include an extension 130LE extending between the protrusions 130P.

[0050] Comparing the via portion 130V and the protrusion 130P, the via portion 130V may have a first height H1, and the protrusion 130P may have a second height H2. The second height H2 may be less than the first height H1. The second height H2 may be greater than 1 / 8 of the first height H1. The via portion 130V and the protrusion 130P may be spaced apart from each other in the first direction D1.

[0051] The via portion 130V may have a first width W1 in the first direction D1, and the protrusion 130P may have a second width W2 in the first direction D1. The second width W2 may be smaller than the first width W1. For example, the second width W2 may range from 1 / 13 to 1 / 10 of the first width W1. For example, the first width W1 may range from 130 μm to 170 μm, and the second width W2 may range from 10 μm to 15 μm.

[0052] In the semiconductor package according to the comparative example, the lower bump pattern 130 may not include a protrusion. At the operating temperature (e.g., -40 degrees Celsius to 85 degrees Celsius) of the semiconductor package according to the comparative example, due to the difference in thermal expansion coefficient between the lower bump pattern 130 and the lowermost first insulating layer 110B, stress (e.g., 5.5 GPa) may be strongly applied to the edge portion of the lower bump pattern 130 and the lowermost first insulating layer 110B that are in contact with each other. Therefore, cracks may easily occur in the lowermost first insulating layer 110B. In addition, the lower bump pattern 130 may be easily peeled off from the bottom surface of the lowermost first insulating layer 110B.

[0053] In some embodiments, the lower bump pattern 130 may include a protrusion 130P protruding into the lowermost first insulating layer 110B. As a result, a contact area between the lower bump pattern 130 and the first insulating layer 110B may increase.

[0054] In some embodiments, the second height H2 of the protrusion 130P may be less than the first height H1 of the via portion 130V. If the second height H2 is equal to the first height H1, the portion of the lowermost first insulating layer 110B disposed between the via portion 130V and the protrusion 130P may be isolated from another portion of the lowermost first insulating layer 110B. In this case, the stress caused by thermal mismatch (e.g., different thermal expansion coefficients) is dispersed, and the stress density may be reduced. In addition, the second height H2 of the protrusion 130P may be greater than 1 / 8 of the first height H1 of the via portion 130V (or the second depth X2 may be greater than 1 / 8 of the first depth X1 of the through hole VH, e.g., 4 μm to 24 μm). For example, if the second height H2 is less than 1 / 8 of the first height H1, the contact area between the protrusion 130P and the first insulating layer 110B may be small, and thus the effect of reducing stress may not be great (e.g., 4.3 Gpa). The stress reducing effect may increase as the second height H2 of the protrusion 130P increases, but when the second height H2 is ¼ or more of the first height H1 , the stress reducing effect may not be large (eg, 3.x Gpa).

[0055] In some embodiments, the semiconductor package may include a lower bump pattern 130 including a protrusion 130P, and thus the stress may be reduced by about 45% or more (e.g., 3.036 GPa) at an operating temperature (e.g., -40 degrees Celsius to 85 degrees Celsius) of the semiconductor package as compared to the comparative example. As a result, the interface between the lowermost first insulating layer 110B and the lower bump pattern 130 may be stabilized to improve the reliability of the semiconductor package.

[0056] Figure 4 is corresponding to Figure 2 In the following, reference will be omitted. Figures 1 to 3B Description of the same features as mentioned. Reference Figure 4 , the conductive pattern CP of the lower bump pattern 130 may completely fill the remaining portion of the via hole VH that is not filled with the seed / barrier pattern SP.

[0057] Figure 5 is a bottom view showing a lower bump pattern of a semiconductor package. Figure 6 It is along Figure 5 Hereinafter, reference to Figures 1 to 4 Description of the same features as mentioned. Reference Figure 5 and Figure 6, the connection portion 130L of the lower bump pattern 130 may include a first portion P1 and a second portion P2. The first portion P1 may be disposed between the via portion 130V and the protrusion 130P. The second portion P2 may be connected to the first portion P1, wherein the protrusion 130P is interposed between the second portion and the first portion. The first portion P1 and the second portion P2 may be connected to each other through an extension 130LE in a gap between the protrusions 130P.

[0058] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G is a cross-sectional view illustrating a method of manufacturing a semiconductor package. Fig. 8A yes Figure 7B Magnified view of area "bb". Figure 8B yes Figure 7C Magnified view of area "cc". Figure 8C is a top view showing a schematic shape of a mask pattern. Fig.8D yes Fig.7D Magnified view of area “dd”. Fig. 8E yes Fig. 7E Magnified view of area “ee”. Figure 8F yes Figure 7F Magnified view of area “ff”.

[0059] refer to Fig. 7A , a first carrier substrate CR1 having a surface on which a first adhesive layer AD1 is formed may be provided. A connection substrate 400 having a cavity 400c formed therein may be provided on the first carrier substrate CR1. The first semiconductor chip 300 may be provided in the cavity 400c. The first adhesive layer AD1 may adhere the connection substrate 400 and the first semiconductor chip 300 to the first carrier substrate CR1. A sealing member 500 may be formed in a space between the connection substrate 400 and the first semiconductor chip 300. For example, the formation of the sealing member 500 may include injecting an Ajinomoto stacked film (ABF) and applying heat to the injected Ajinomoto stacked film (ABF).

[0060] refer to Figure 7B and Fig. 8A, the second carrier substrate CR2 and the second adhesive layer AD2 may be disposed in contact with the sealing member 500. In addition, the first adhesive layer AD1 and the first carrier substrate CR1 may be removed. In this process, the chip pad 310 of the first semiconductor chip 300 and the first connection pad 421 of the connection substrate 400 may be exposed. The first insulating layer 110 and the first redistribution pattern 120 may be formed on the first semiconductor chip 300 and the connection substrate 400. The first insulating layer 110 and the first redistribution pattern 120 may be formed as a multilayer structure. Each first insulating layer 110 may be formed using a coating, exposure, development and hardening process of a photosensitive insulating material (e.g., a photo-imageable dielectric (PID) layer). The formation of each first redistribution pattern 120 may include: forming a first seed / barrier layer on the first insulating layer 110; forming a first photomask pattern that defines a formation space for a conductive pattern CP; forming a conductive pattern CP on the first seed / barrier layer by an electroplating method; removing the first photomask pattern; and patterning the first seed / barrier layer using the conductive pattern CP as an etching mask to form a seed / barrier pattern SP.

[0061] The formation of the lowermost first insulating layer 110B may include coating or forming a photosensitive insulating material (eg, a photo-imageable dielectric (PID) layer) or an Ajinomoto built-up film (ABF) covering the lowermost first redistribution pattern 120 .

[0062] refer to Figure 7C , Figure 8B and Figure 8C ,include Figure 8C The mask pattern MSK of the first opening OP1 may be disposed on the lowermost first insulating layer 110B. The first opening OP1 may define a region where a Figure 7C and Figure 8B The mask pattern MSK may include a first region R1 and a second region R2 in addition to the first opening OP1. For example, when light is irradiated to the mask pattern MSK, the first region R1 may not transmit light, and the second region R2 may not transmit a certain percentage or more of light. More specifically, the second region R2 may be a phase shift mask (PSM) and may reduce the contrast of light passing through the second region R2. The second region R2 may define a region where a light source is to be formed. Figure 7C and Figure 8BThe region of the recess RS. Subsequently, a development process may be performed on the lowermost first insulating layer 110B. As a result of the development process, a portion of the lowermost first insulating layer 110B vertically overlapping with the first opening OP1 of the mask pattern MSK may be removed to form a through hole VH. A portion of the lowermost first insulating layer 110B vertically overlapping with the second region R2 of the mask pattern MSK may be removed to form the recess RS. A portion of the lowermost first insulating layer 110B vertically overlapping with the first region R1 of the mask pattern MSK may not be removed. The amount of insulating material of the first insulating layer 110B removed when forming the recess RS may be less than the amount of insulating material of the first insulating layer 110B removed when forming the through hole VH. Next, a hardening process may be performed on the lowermost first insulating layer 110B.

[0063] refer to Fig.7D and Fig.8D , a second seed / barrier layer SL may be formed to partially fill the through hole VH and the recess RS. The second seed / barrier layer SL may cover the exposed surface of the lowermost first insulating layer 110B. A second photomask pattern PM may be formed on the top surface of the second seed / barrier layer SL. The second photomask pattern PM may include an opening defining a formation space of the lower bump pattern 130. The second photomask pattern PM may be formed using a coating, exposure, and development process of a photoresist layer. The second seed / barrier layer SL may be exposed through the second photomask pattern PM.

[0064] refer to Fig. 7E and Fig. 8E By performing an electroplating process using the second seed / barrier layer SL as an electrode, a conductive pattern CP may be formed on the second seed / barrier layer SL. The conductive pattern CP may fill at least a portion of the through hole VH and may completely fill the recess RS.

[0065] refer to Figure 7F and Figure 8F , the second photomask pattern PM may be removed. Subsequently, a patterning process may be performed on the second seed / barrier layer SL to form a seed / barrier pattern SP. The patterning process may include a process of etching the second seed / barrier layer SL using the conductive pattern CP as an etching mask. Since the seed / barrier pattern SP is formed, a lower bump pattern 130 including the seed / barrier pattern SP and the conductive pattern CP may be formed.

[0066] refer to Figure 7G, the external connection terminal 180 may be formed on the lower bump pattern 130. Next, the second carrier substrate CR2 may be separated from the sealing member 500. The second adhesive layer AD2 may also be removed. The second connection pad 422 of the connection substrate 400 may be exposed. For example, exposing the second connection pad 422 may include performing a laser drilling process. The second redistribution pattern 220 and the second insulating layer 210 may be alternately and repeatedly formed on the sealing member 500. The second insulating layer 210 may be formed by a method substantially the same as the first insulating layer 110. The second redistribution pattern 220 may be formed by a method substantially the same as the first redistribution pattern 120. The bonding pad 230 may be formed to penetrate the uppermost second insulating layer 210T. The bonding pad 230 may contact the second redistribution pattern 220 adjacent thereto in the second direction D2. Next, the second semiconductor package PK2 may be connected to the first semiconductor package PK1 by using the package connection terminal 680. As a result, the semiconductor package 1000 may be manufactured.

[0067] Fig. 9 is a cross-sectional view showing a semiconductor package. Hereinafter, for ease and convenience of explanation, descriptions of the same features as those mentioned above will be omitted. Fig. 9 , in some embodiments, the semiconductor package 2000 does not include the sealing member 500 and the connection substrate 400. More specifically, the first semiconductor package PK1 may include a molding member 900 instead of the sealing member 500. The first semiconductor package PK1 may include a conductive pillar 910 instead of the connection substrate 400. The molding member 900 may be disposed between the first redistribution substrate 100 and the second redistribution substrate 200. For example, the molding member 900 may include an epoxy molding compound (EMC). The conductive pillar 910 may penetrate the molding member 900 and may be disposed between the first redistribution substrate 100 and the second redistribution substrate 200. The conductive pillar 910 may be spaced apart from the first semiconductor chip 300 in the first direction D1. The conductive pillar 910 may contact the first redistribution pattern 120 and the second redistribution pattern 220. In other words, the conductive pillar 910 may be electrically connected to the first redistribution pattern 120 and the second redistribution pattern 220.

[0068] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a cross-sectional view illustrating a method of manufacturing a semiconductor package.

[0069] refer to Fig. 10A, a first carrier substrate CR1 having a surface on which a first adhesive layer AD1 is formed may be provided. For example, the conductive pillar 910 may be formed using an electroplating method. The first semiconductor chip 300 may be disposed on the first carrier substrate CR1 and may be spaced apart from the conductive pillar 910 in the first direction D1. Next, a molding member 900 may be formed to fill a space between the first semiconductor chip 300 and the conductive pillar 910 and a space between the conductive pillars 910. In some embodiments, a grinding process that exposes the top surface of the conductive pillar 910 may be performed after the formation of the molding member 900.

[0070] refer to Fig. 10B , the second carrier substrate CR2 and the second adhesive layer AD2 are disposed in contact with the molding member 900. In addition, the first adhesive layer AD1 and the first carrier substrate CR1 are removed. In this process, the chip pad 310 of the first semiconductor chip 300 and the surface of the conductive pillar 910 may be exposed. The first insulating layer 110 and the first redistribution pattern 120 may be formed on the first semiconductor chip 300 and the conductive pillar 910. The first insulating layer 110, the first redistribution pattern 120, the through hole VH, and the recess RS may be formed by the above reference Figure 7B and Figure 7C The method is formed by the same method as described.

[0071] refer to Fig. 10C , the lower bump pattern 130 and the first redistribution substrate 100 can be made by referring to the above Fig.7D , Fig. 7E and Figure 7F The method is formed by the same method as described.

[0072] refer to Fig. 10D , can be obtained by referring to the above Figure 7G The second redistribution substrate 200 is formed in the same manner as described above, and a sawing process may be performed.

[0073] Reference again Fig. 9 , the second semiconductor package PK2 may be disposed on the first semiconductor package PK1 to manufacture the semiconductor package 2000 .

[0074] The semiconductor package may include a lower bump pattern disposed on the lowermost insulating layer. The lower bump pattern may include a protrusion protruding into the lowermost insulating layer. The protrusion of the lower bump pattern may reduce the stress applied to the lowermost insulating layer and may prevent the lower bump pattern from being peeled off from the lowermost insulating layer. In other words, the reliability of the interface between the lower bump pattern and the lowermost insulating layer may be increased to improve the reliability of the semiconductor package.

[0075] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described above as working in certain combinations, and even initially claimed as such, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

[0076] While embodiments of the inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor package, comprising: a redistribution substrate, the redistribution substrate comprising a first surface and a second surface, the first surface and the second surface being opposite to each other; a semiconductor chip disposed on the first surface of the redistribution substrate; as well as a connecting terminal, wherein the connecting terminal is arranged on the second surface of the redistribution substrate, The redistribution substrate includes an insulating layer, a redistribution pattern located in the insulating layer, and a lower bump pattern located between the redistribution pattern and the connection terminal. The lower bump pattern includes: i) a via portion extending through the insulating layer and connected to the redistribution pattern; and ii) a protrusion protruding into the insulating layer.

2. The semiconductor package according to claim 1, wherein: The passage portion has a first height, wherein the protrusion has a second height, and Wherein, the second height is smaller than the first height.

3. The semiconductor package according to claim 2, wherein: The second height is greater than 1 / 8 of the first height.

4. The semiconductor package according to claim 1, wherein: The via portion and the protrusion are spaced apart from each other in a first direction parallel to the second surface of the redistribution substrate.

5. The semiconductor package according to claim 1, wherein: The protrusion comprises a plurality of protrusions, and Wherein, the plurality of protrusions form a segmented annular shape.

6. The semiconductor package according to claim 5, wherein: The lower bump pattern further includes a connection portion disposed between the via portion and the plurality of protrusions to connect the via portion and the plurality of protrusions, and Wherein, the connecting portion includes an extension portion extending between the plurality of protrusions.

7. The semiconductor package according to claim 5, wherein: The lower bump pattern further includes a connection portion connecting the via portion and the plurality of protrusions, Wherein, the connecting part comprises: a first portion disposed between the passage portion and the plurality of protrusions; a second portion, the second portion being spaced apart from the first portion, the plurality of protrusions being interposed between the second portion and the first portion; and an extension portion extending between the plurality of protrusions, Wherein, the extending portion connects the first portion and the second portion.

8. The semiconductor package according to claim 1, wherein: The via portion has a first width in a first direction parallel to the second surface of the redistribution substrate, wherein the protrusion has a second width in the first direction, and The second width is smaller than the first width.

9. The semiconductor package according to claim 8, wherein: The first width ranges from 130 μm to 170 μm, and The second width is in a range of 10 μm to 15 μm. 10 . The semiconductor package according to claim 1 , further comprising a connection substrate located on the first surface of the redistribution substrate, in, The connection substrate includes a cavity, and The semiconductor chip is arranged in the cavity.

11. The semiconductor package according to claim 1, further comprising: a molding member covering the semiconductor chip and the redistribution substrate; as well as a conductive pillar extending through the molding member and connected to the redistribution pattern, The conductive pillar is spaced apart from the semiconductor chip in a first direction parallel to the first surface of the redistribution substrate.

12. The semiconductor package according to claim 1, wherein The semiconductor chip includes a chip pad facing the first surface of the redistribution substrate, and Wherein, the chip pad contacts the redistribution pattern.

13. The semiconductor package according to claim 1, wherein: The protrusion is disposed at an edge of the lower bump pattern.

14. The semiconductor package according to claim 1, wherein The level of the top surface of the protrusion is lower than the level of the top surface of the via portion.

15. The semiconductor package according to claim 1, wherein The lower bump pattern has a W-shape or a W-like shape.

16. A semiconductor package, comprising: a redistribution substrate, the redistribution substrate comprising a first surface and a second surface, the first surface and the second surface being opposite to each other; a semiconductor chip, wherein the semiconductor chip is located on the first surface of the redistribution substrate; as well as a connecting terminal, wherein the connecting terminal is located on the second surface of the redistribution substrate, Wherein, the redistribution substrate comprises: Insulation layer; a redistribution pattern located in the insulating layer; and a lower bump pattern, the lower bump pattern being located between the redistribution pattern and the connection terminal, Wherein, the insulating layer comprises: a through hole exposing the redistribution pattern; and a recessed portion spaced apart from the through hole in a first direction parallel to the second surface of the redistribution substrate, Wherein, the lower bump pattern fills the through hole and the recess.

17. The semiconductor package according to claim 16, wherein: The recess is spaced apart from the redistribution pattern and is separated from the redistribution pattern.

18. The semiconductor package according to claim 16, wherein: The depth of the recess is smaller than the depth of the through hole and greater than 1 / 8 of the depth of the through hole.

19. The semiconductor package according to claim 16, wherein: The depth of the through hole ranges from 20 μm to 30 μm, and Wherein, the depth of the concave portion ranges from 4 μm to 24 μm.

20. A semiconductor package, comprising: a lower semiconductor package; as well as an upper semiconductor package, the upper semiconductor package being located on the lower semiconductor package, Wherein, the lower semiconductor package comprises: a lower redistribution substrate; an upper redistribution substrate, the upper redistribution substrate being located on the lower redistribution substrate; and a semiconductor chip, wherein the semiconductor chip is located between the lower redistribution substrate and the upper redistribution substrate, Wherein, the lower redistribution substrate comprises: Multiple insulation layers; a redistribution pattern disposed in the insulating layer; and an underbump metal disposed on a lowermost insulating layer among the plurality of insulating layers, Wherein, the lower bump metal comprises: seed / block pattern; and a conductive pattern, the conductive pattern being located on the seed / barrier pattern, wherein the lower bump metal comprises: a via portion extending through the lowermost insulating layer and contacting one of the redistribution patterns adjacent thereto in a vertical direction; and a protrusion protruding into the lowermost insulating layer, wherein the protrusion is spaced apart from the one redistribution pattern, and Wherein, the height of the protrusion is smaller than the height of the passage portion.

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