Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a first dielectric layer and a first conductive structure. The first dielectric layer includes a stack structure. The stacked structure comprises a low dielectric constant dielectric layer, an etching stop layer and a carbon-rich dielectric layer located between the low dielectric constant dielectric layer and the etching stop layer, and the carbon content of the carbon-rich dielectric layer exceeds 15%. The first conductive structure is disposed within the first dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and in particular to a semiconductor device with a dielectric layer and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) are constructed by forming various active components and the interconnection structure in a substrate or different film layers. Generally speaking, the manufacturing process of the interconnection structure first etches a through hole or a circuit pattern in a dielectric layer, then fills the through hole or the circuit pattern with a conductive material such as copper, and flattens it to complete the manufacturing of the interconnection structure. In the back-end processes of semiconductor devices, the frequent use of plasma makes it easy for excess charges to accumulate on the conductive material filled in the through hole or the circuit pattern. The accumulation of excess charges often forms a current and enters the circuit from the conductive material, penetrates the gate dielectric layer (gate oxide), or derives a threshold voltage shift, causing damage to the components of the front-end manufacturing process, which is a structural defect (plasma induced damage, PID) caused by the antenna effect.

[0003] However, in the advanced semiconductor industry, components are gradually miniaturized and the integration of components is continuously improved. The antenna effect has a significant impact on the operating performance of semiconductor devices. The layout of the circuit needs to take into account the appropriate antenna ratio (Antennaratio, AR), that is, the ratio between the area of ​​the metal wire and the area of ​​the gate dielectric layer. If the antenna ratio is smaller, the impact of the antenna effect is smaller, and the yield and reliability of the semiconductor device can be improved accordingly. However, the limitation of the antenna ratio has caused the difficulty and complexity of circuit design and manufacturing processes to continue to increase. In addition, the use of improved designs such as parallel connection of transistors still has a certain chance of current concentration on transistors with smaller resistance, and the problem caused by the antenna effect cannot be effectively solved. Therefore, the improvement of the existing technology is a topic that relevant technical personnel attach great importance to. Summary of the invention

[0004] The present invention aims to provide a semiconductor device and a method for forming the same, which additionally provides a carbon-rich dielectric layer in the dielectric layer to effectively improve the antenna effect while significantly increasing the antenna ratio. As a result, the semiconductor device of the present invention can have significantly improved reliability and yield, thereby achieving better operating performance.

[0005] An embodiment of the present invention provides a semiconductor device, comprising a first dielectric layer and a first conductive structure. The first dielectric layer comprises a stacked structure. The stacked structure comprises a low-k dielectric layer, an etch stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etch stop layer, wherein the carbon content of the carbon-rich dielectric layer exceeds 15%. The first conductive structure is disposed in the first dielectric layer.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising the following steps: forming a first dielectric layer, the first dielectric layer comprising a stacked structure, the stacked structure comprising a low-k dielectric layer, an etch stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etch stop layer, wherein the carbon content of the carbon-rich dielectric layer exceeds 15%. forming a first conductive structure in the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device in a first embodiment of the present invention;

[0008] Figures 2 to 4 Schematic diagram of a method for forming a semiconductor device in a first embodiment of the present invention, wherein:

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device after a dielectric layer is formed;

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device after a through hole is formed; and

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after a conductive layer is formed;

[0012] Figure 5 is a cross-sectional schematic diagram of a semiconductor device in a second embodiment of the present invention;

[0013] Figure 6 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention.

[0014] Explanation of symbols

[0015] 10, 30, 40: Semiconductor devices

[0016] 100: Base

[0017] 102: Shallow Trench Isolation

[0018] 110: Dielectric layer

[0019] 112: Plug

[0020] 120: First dielectric layer

[0021] 122, 322, 422: Etch stop layer

[0022] 124, 324, 424: Carbon-rich dielectric layer

[0023] 126, 326, 426: Low dielectric constant dielectric layer

[0024] 128, 328, 428: Adhesive layer

[0025] 128a, 328a, 428a: Starting layer

[0026] 128b, 328b, 428b: transition layer

[0027] 130: first conductive structure

[0028] 140: Gate structure

[0029] 142: Gate dielectric layer

[0030] 144: Gate

[0031] 146: Source / Drain

[0032] 222: Etch stop material layer

[0033] 224: Carbon-rich dielectric material layer

[0034] 226: Low dielectric constant dielectric material layer

[0035] 228: Adhesive material layer

[0036] 228a: Starting material layer

[0037] 228b: Transition material layer

[0038] 230: Perforation

[0039] 232: Conductive materials

[0040] 320, 420, 420a: second dielectric layer

[0041] 330, 430: second conductive structure

[0042] R1, R2, R3: Surface area

[0043] R31, R32, R33, R34, R35: Surface area

[0044] R41, R42, R43, R44, R45: Surface area DETAILED DESCRIPTION

[0045] In order to enable a person skilled in the art who is familiar with the technical field to which the present invention belongs to further understand the present invention, several preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings. Moreover, without departing from the spirit of the present invention, the technical features of the different embodiments described below can be replaced, reorganized, or mixed with each other to form other embodiments.

[0046] Please refer to Figure 1 As shown, what is illustrated is a cross-sectional schematic diagram of a semiconductor device 10 in a first embodiment of the present invention. The semiconductor device 10 includes a first dielectric layer 120 and a first conductive structure 130. The first conductive structure 130 is disposed in the first dielectric layer 120, and includes, for example, various elements made of conductive materials, such as wires, plugs, metal layers or metal wiring layers (redistribution layers, RDL), etc., but is not limited thereto. The first dielectric layer 120 includes a stacked structure in detail, and the stacked structure includes an etch stop layer 122, a low dielectric constant dielectric layer 126, and a carbon-rich dielectric layer 124 located between the etch stop layer 122 and the low dielectric constant dielectric layer 126. It should be particularly noted that the carbon content of the carbon-rich dielectric layer 124 exceeds 15%. Therefore, by disposing the carbon-rich dielectric layer 124 in the middle of the stacked structure of the first dielectric layer 120, preferably, the carbon-rich dielectric layer 124 is not directly disposed on the top surface or the bottom surface of the first dielectric layer 120, free radicals and charged substances (including ions and electrons) that may accumulate on the first conductive structure 130 are neutralized, thereby reducing the chance of structural damage to the semiconductor device 10 caused by plasma in the back-end manufacturing process, thereby effectively avoiding the antenna effect.

[0047] Specifically, the carbon content of the carbon-rich dielectric layer 124 is, for example, about 15% to 90%, preferably about 15% to 50%, but not limited thereto. In the manufacturing process of forming the carbon-rich dielectric layer 124, a relatively high carbon content will simultaneously produce relatively more precursor substances, thereby having a stronger ability to neutralize unstable charges, so that the effect of stabilizing charges can be achieved more effectively. Among them, the carbon content of the carbon-rich dielectric layer 124 is preferably higher than the carbon content of the low dielectric constant dielectric layer 126, for example, about 3% to 10% more than the carbon content of the low dielectric constant dielectric layer 126, preferably about 5% more, but not limited thereto. In one embodiment, the low-k dielectric layer 126 includes, for example, a dielectric material having a dielectric constant lower than 3, preferably a dielectric material having a dielectric constant between 2.5 and 2.9, such as fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), porous carbon oxide or spin-on glass, etc., but not limited thereto. In another embodiment, the carbon-rich dielectric layer 124 includes, for example, a dielectric material having a dielectric constant lower than that of the low-k dielectric layer 126, preferably a dielectric material having a dielectric constant lower than 2.5, more preferably a dielectric material having a dielectric constant between 2 and 2.4, such as a carbon-rich organic compound such as terpinene, but not limited thereto; and the etch stop layer 122 includes, for example, a dielectric material having a dielectric constant greater than that of the low-k dielectric layer 126, such as nitrogen doped carbide, etc., but not limited thereto.

[0048] In this embodiment, the etching stop layer 122, the carbon rich dielectric layer 124 and the low dielectric constant dielectric layer 126 are sequentially stacked on a substrate 100 from bottom to top, for example. Figure 1As shown. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as silicon carbide or silicon germanium), or a silicon-on-insulator substrate, and at least one shallow trench isolation 102 is disposed in the substrate 100 to surround and define a plurality of active areas (not shown) in the substrate 100, but the invention is not limited thereto. In addition, the stacked structure of the first dielectric layer 120 may further selectively include an adhesive layer 128 disposed between the etching stop layer 122 and the carbon-rich dielectric layer 124 to strengthen the bonding between the etching stop layer 122 and the carbon-rich dielectric layer 124 to prevent film peeling. In one embodiment, the adhesion layer 128 includes, for example, an initiation layer 128a and a transition layer 128b stacked sequentially from bottom to top between the etching stop layer 122 and the carbon-rich dielectric layer 124, wherein the initiation layer 128a and the transition layer 128b respectively include dielectric materials composed of carbon, oxygen, hydrogen and / or silicon, but the present invention is not limited thereto.

[0049] For example Figure 1 As shown, the semiconductor device 10 further includes a dielectric layer 110 and a gate structure 140 disposed between the first dielectric layer 120 and the substrate 100. The gate structure 140 is disposed on the substrate 100, and further includes a gate dielectric layer 142 and a gate 144 sequentially stacked on the top surface of the substrate 100, and two source / drain electrodes 146 disposed in the substrate 100. The dielectric layer 110 covers the gate structure 140 and the substrate 100, and a plug 112 is further disposed in the dielectric layer 110, which electrically connects the gate structure 140 below and the first conductive structure 130 above. In this configuration, the dielectric layer 110 serves as an interlayer dielectric layer (ILD) of the semiconductor device 10, and the plug 112 serves as a contact plug or a zero-layer metal interconnect layer (metal 0, M0) of the semiconductor device 10. Furthermore, the first dielectric layer 120 serves as an intermetal dielectric layer (ILD) of the semiconductor device 10, and the first conductive structure 130 serves as a first metal interconnect layer (metal 1, M1) of the semiconductor device 10. The aforementioned interconnect layers are sequentially disposed on the gate structure 140, so that the gate structure 140 can be electrically connected to other active (active) elements and / or passive (passive) elements through other connecting elements in subsequent manufacturing processes, thereby achieving the desired operating performance.

[0050] According to the semiconductor device 10 of the present embodiment, the carbon-rich dielectric layer 124 is disposed inside the intermetallic dielectric layer (first dielectric layer 120), and the precursor material in the carbon-rich dielectric layer 124 is used to neutralize the free radicals and charged materials generated by the back-end deposition process or etching process, thereby preventing unstable charges from accumulating on the metal interconnect layer (first conductive structure 130), and effectively reducing the chance of structural damage to the semiconductor device 10 caused by plasma in the back-end process. As a result, the semiconductor device 10 of the present embodiment can effectively improve the antenna effect, and the antenna ratio (AR) of the semiconductor device 10 does not need to be limited by the prior art for the antenna ratio (such as AR2000), wherein the antenna ratio is the ratio of the exposed area of ​​the metal wire to the surface area of ​​the gate dielectric layer, and the smaller the antenna ratio is, the less affected by the antenna effect is. For example, in the semiconductor device 10 of the present embodiment, the ratio (R2+R3 / R1) of the sum of the surface area R2 of the plug 112 and the surface area R3 of the first conductive structure 130 to the surface area R1 of the gate 144 (or the gate dielectric layer 142) of the gate structure 140 can reach above AR5000 and below AR100000, preferably between AR5000 and AR100000, but not limited thereto. Moreover, the ratio (R2 / R1) of the surface area R2 of the first conductive structure 130 to the surface area R1 of the gate 144 (or the gate dielectric layer 142) of the gate structure 140 can also reach above AR5000 and below AR100000, preferably between AR5000 and AR100000. Therefore, the semiconductor device 10 of the present embodiment has significantly improved device reliability and yield, thereby achieving better operating performance.

[0051] In order to enable a person skilled in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, a method for forming the semiconductor device 10 of the present invention will be further described below.

[0052] Please refer to Figures 2 to 4 FIG. 1 is a schematic diagram of a method for forming a semiconductor device in accordance with a first embodiment of the present invention. Figure 2 As shown, a substrate 100 is provided, a shallow trench isolation 102 is formed in the substrate 100 , and a gate structure 140 is formed on and in the substrate 100 . Next, a dielectric layer 110 and a plug 112 are formed on the substrate 100 and the gate structure 140 .

[0053] Then, Figure 2As shown, an etch stop material layer 222, a carbon-rich dielectric material layer 224, and a low-k dielectric material layer 226 are sequentially formed on the dielectric layer 110 and the plug 112. The carbon content of the carbon-rich dielectric material layer 224 is higher than 15%, for example, about 15% to 90%, preferably about 15% to 50%, and the carbon content of the carbon-rich dielectric material layer 224 is preferably higher than the carbon content of the low-k dielectric material layer 222, for example, about 3% to 10% more, preferably about 5% more, but not limited thereto. In one embodiment, the low dielectric constant dielectric material layer 226, for example, includes a dielectric material having a dielectric constant lower than 3, preferably includes a dielectric material having a dielectric constant between 2.5 and 2.9, such as fluorine silicon glass, carbon silicon oxide, porous carbon oxide or spin-on silicon glass, etc. The carbon-rich dielectric material layer 224, for example, includes a dielectric material having a dielectric constant less than the dielectric constant of the low dielectric constant dielectric material layer 226, preferably includes a dielectric material having a dielectric constant less than 2.5, and more preferably includes a dielectric material having a dielectric constant between 2 and 2.4, such as a carbon-rich organic compound such as pine alcohol, and the etch stop material layer 222, for example, includes a dielectric material having a dielectric constant greater than the dielectric constant of the low dielectric constant dielectric material layer 226, such as nitrogen-doped carbon, but is not limited to the foregoing. In one embodiment, an adhesion material layer 228 may be additionally formed between the etching stop material layer 222 and the carbon-rich dielectric material layer 224 to strengthen the bonding between the etching stop material layer 222 and the carbon-rich dielectric material layer 224. The adhesion material layer 228, for example, includes a starting material layer 228a and a transition material layer 228b sequentially stacked from bottom to top between the etching stop material layer 222 and the carbon-rich dielectric material layer 224, wherein the starting material layer 228a and the transition material layer 228b respectively include dielectric materials composed of carbon, oxygen, hydrogen and silicon, but the present invention is not limited thereto.

[0054] like Figure 3 As shown, an etching process is performed through a mask layer (not shown), such as a dry etching process containing plasma. The etching process is performed by using the etching stop material layer 222 as an etching barrier to sequentially etch through the low-k dielectric material layer 226, the carbon-rich dielectric material layer 224, and the etching stop material layer 222, and finally forming at least one through hole 230 in the low-k dielectric material layer 226, the carbon-rich dielectric material layer 224, and the etching stop material layer 222. Part of the top surface of the plug 112 is exposed from the bottom of the through hole 230. Then, the mask layer is completely removed.

[0055] like Figure 4As shown, a deposition process is performed to fill the through-hole 230 with a conductive material 232, fill the through-hole 230, and further cover the top surface of the low-k dielectric material layer 226. In one embodiment, the conductive material 232 includes, for example, a barrier layer (not shown) formed on the sidewalls of the through-hole 230 and the top surface of the low-k dielectric material layer 226, and a metal layer (not shown) that fills the through-hole 230 and covers the barrier layer, but is not limited thereto. In other words, the conductive material 232 is partially formed inside the through-hole 230 and partially formed outside the through-hole 230. Subsequently, a planarization process is performed to remove the conductive material 232 formed outside the through-hole 230, so as to form a planarized conductive layer 232 as shown in FIG. Figure 1 The first conductive structure 130 shown in FIG. 1 is also formed simultaneously as shown in FIG. Figure 1 The low-k dielectric layer 126 , the carbon-rich dielectric layer 124 with a carbon content exceeding 15%, and the etch stop layer 122 stacked in sequence together constitute the first dielectric layer 120 , so that the first conductive structure 130 is formed in the first dielectric layer 120 .

[0056] Those skilled in the art should be able to easily understand that in order to meet actual needs, the semiconductor device and the method for forming the semiconductor device of the present invention may also have other aspects, not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the method for forming the semiconductor device of the present invention. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same parts. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0057] Please refer to Figure 5 , which is a cross-sectional schematic diagram of a semiconductor device 30 in a second embodiment of the present invention. The structure of the semiconductor device 30 is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The semiconductor device 30 includes a plurality of second dielectric layers 320 additionally disposed on the first dielectric layer 110 and a plurality of second conductive structures 330, each conductive structure 330 being disposed in each second dielectric layer 320.

[0058] In detail, each second conductive structure 330 includes, for example, various elements made of conductive materials, such as wires, plugs, metal layers or metal wiring layers, but is not limited thereto. Each second dielectric layer 320 includes an etching stop layer 322, a carbon-rich dielectric layer 324 and a low-k dielectric layer 326 stacked in sequence, wherein the carbon content of the carbon-rich dielectric layer 324 in each second dielectric layer 320 exceeds 15%, for example, about 15% to 90%, preferably about 15% to 50%, but is not limited thereto. It should be noted that the carbon content of the carbon-rich dielectric layer 324 is preferably higher than the carbon content of the low-k dielectric layer 322, for example, about 3% to 10% more, preferably about 5% more, but is not limited thereto. In addition, each second dielectric layer 120 may also selectively include an adhesion layer 328 disposed between the etching stop layer 322 and the carbon-rich dielectric layer 324 to strengthen the bonding between the etching stop layer 322 and the carbon-rich dielectric layer 324 to prevent film peeling or structural collapse. In one embodiment, the adhesion layer 328 includes, for example, a starting layer 328a and a transition layer 328b stacked in sequence from bottom to top, which respectively include dielectric materials composed of carbon, oxygen, hydrogen and silicon, but is not limited thereto.

[0059] Those skilled in the art should easily understand that the specific number of second dielectric layers 320 and / or the specific pattern or surface area of ​​the second conductive structure 330 of each layer in this embodiment are only examples and can be adjusted according to actual device requirements. Figure 5 The figures shown are limited. For example, in another embodiment, one, two or N layers (N is a positive integer greater than 2) of the second dielectric layer 320 having the carbon-rich dielectric layer 324 disposed therein may be selectively disposed on the first dielectric layer 110, and the surface areas R32, R33, R34, and R35 of the second conductive structure 330 disposed in the one, two or N layers of the second dielectric layer 320 may be different from each other, or have various desired patterns. In addition, the material selection and dielectric constant of the etching stop layer 322, the carbon-rich dielectric layer 324, and the low-k dielectric layer 326 of the present embodiment are substantially the same as those of the etching stop layer 122, the carbon-rich dielectric layer 124, and the low-k dielectric layer 126 in the aforementioned first embodiment, and therefore will not be described in detail.

[0060] Under this configuration, the dielectric layer 110 also serves as an interlayer dielectric layer of the semiconductor device 30, and the plug 112 serves as a contact plug or a zero-th metal interconnect layer of the semiconductor device 30, and the first dielectric layer 120 and each second dielectric layer 320 serve as an intermetallic dielectric layer of the semiconductor device 30, respectively, so that the first conductive structure 130 serves as a first metal interconnect layer of the semiconductor device 30, and each second conductive structure 330 serves as a second metal interconnect layer (metal 2, M2), a third metal interconnect layer (metal 3, M3) to an n-th (n is a positive integer greater than 3) metal interconnect layer of the semiconductor device 30 in sequence. In this way, the semiconductor device 30 of the present embodiment can not only neutralize the free radicals and charged substances generated by the back-end deposition process or etching process by setting the carbon-rich dielectric layers 124 and 324 inside each intermetallic dielectric layer, but also avoid the accumulation of unstable charges on the metal interconnect layers of each layer (such as the first conductive structure 130 and the second conductive structure 330), thereby increasing the semiconductor device 30's tolerance to the antenna effect, and further more effectively reducing the chance of structural damage to the semiconductor device 30 caused by plasma in the back-end manufacturing process.

[0061] Therefore, the semiconductor device 30 of the present embodiment also has significantly improved component reliability and yield, and is not subject to the limitation of the prior art on the antenna ratio (such as AR2000), so that the ratio ((R2+R31+R32+R33+R34+R35) / R1) of the surface area R2 of the plug 112 and the sum of the metal interconnect layers of each layer (R2+R31+R32+R33+R34+R35) to the surface area R1 of the gate 144 (or the gate dielectric layer 142) of the gate structure 140 can reach a range of above AR5000 and below AR100000, preferably between AR5000 and AR100000, but not limited thereto.

[0062] Please refer to Figure 6 , which is a cross-sectional schematic diagram of a semiconductor device 40 in a third embodiment of the present invention. The structure of the semiconductor device 40 is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities are not repeated. The semiconductor device 40 includes a plurality of second dielectric layers 420, 420a additionally disposed on the first dielectric layer 110 and a plurality of second conductive structures 430, wherein each second conductive structure 430 is disposed in each second dielectric layer 420, 420a.

[0063] In detail, each second conductive structure 430 includes, for example, various elements made of conductive materials, such as wires, plugs, metal layers or metal wiring layers, but is not limited thereto. Each second dielectric layer 420, 420a includes an etching stop layer 422, an adhesive layer 428 and a low dielectric constant dielectric layer 426 stacked in sequence. In one embodiment, the adhesive layer 428 includes, for example, a starting layer 428a and a transition layer 428b stacked in sequence from bottom to top, or the adhesive layer 428 may be omitted, but is not limited thereto. It should be particularly noted that a carbon-rich dielectric layer 424 is additionally disposed in at least one second dielectric layer 420, preferably in the second dielectric layer 420 of the second conductive structure 430 having a relatively large surface area R42, wherein the surface area R42 of the second conductive structure 430 is, for example, greater than the surface area R2 of the first conductive structure 130, but is not limited thereto. That is to say, in this embodiment, no carbon-rich dielectric layer is set in other second dielectric layers 420a, or, in another embodiment, the carbon-rich dielectric layer 124 in the first dielectric layer 110 can be omitted, and the carbon-rich dielectric layer 424 is only set in the dielectric layer (i.e., the second dielectric layer 420) of the metal interconnect layer (i.e., the second conductive structure 430) with the largest surface area.

[0064] The carbon-rich dielectric layer 424 is specifically disposed between the etching stop layer 422 and the low-k dielectric layer 426 and is located on the adhesion layer 428. The carbon content of the carbon-rich dielectric layer 424 exceeds 15%, for example, about 15% to 90%, preferably about 15% to 50%, and the carbon content of the carbon-rich dielectric layer 424 is preferably higher than the carbon content of the low-k dielectric layer 422, for example, about 3% to 10% more, preferably about 5% more, but not limited thereto. In one embodiment, when the surface area R42 of the second conductive structure 430 is greater than the surface area R2 of the first conductive structure 130, the carbon content of the carbon-rich dielectric layer 424 in the second dielectric layer 420 of the second conductive structure 430 is preferably higher than the carbon content of the carbon-rich dielectric layer 124 in the first dielectric layer 120, but not limited thereto.

[0065] Those skilled in the art should easily understand that the specific number of second dielectric layers 420, 420a and / or the specific pattern of the second conductive structure 430 of each layer or its surface area R42, R43, R44, R45, etc. in this embodiment are also only examples and can be adjusted according to actual device requirements. Figure 6 Furthermore, the material selection and dielectric constant of the etching stop layer 422, the carbon-rich dielectric layer 424 and the low-k dielectric layer 426 of this embodiment are substantially the same as those of the etching stop layer 122, the carbon-rich dielectric layer 124 and the low-k dielectric layer 126 of the first embodiment, and thus will not be described in detail.

[0066] Under this setting, the dielectric layer 110 also serves as the interlayer dielectric layer of the semiconductor device 40, and the plug 112 serves as the contact plug or the zeroth metal interconnect layer of the semiconductor device 40, and the first dielectric layer 120 and each second dielectric layer 420, 420a serve as the metal inter-dielectric layers of the semiconductor device 40, respectively, so that the first conductive structure 130 serves as the first metal interconnect layer of the semiconductor device 40, and each layer of the second conductive structure 430 serves as the second metal interconnect layer, the third metal interconnect layer to the Mth metal interconnect layer (M is a positive integer greater than 4) of the semiconductor device 40 in sequence. In this way, the semiconductor device 40 of the present embodiment can also achieve the goal of neutralizing free radicals and charged substances generated by the back-end deposition process or etching process by disposing the carbon-rich dielectric layer 124, 424 inside at least one intermetallic dielectric layer (the first dielectric layer 120 and / or the second dielectric layer 420a), especially inside the intermetallic dielectric layer of the metal interconnect layer with a relatively large surface area, thereby avoiding the accumulation of unstable charges on the metal interconnect layers of each layer (such as the first conductive structure 130 and / or the second conductive structure 430), especially on the metal interconnect layers with a larger surface area (such as the second conductive structure 430), thereby effectively reducing the chance of structural damage to the semiconductor device 40 caused by plasma in the back-end manufacturing process.

[0067] Therefore, the semiconductor device 40 of the present embodiment also has significantly improved component reliability and yield, and is not subject to the limitation of the antenna ratio (AR2000) in the prior art, so that the ratio ((R2+R41+R42+R43+R44+R45) / R1) of the surface area R2 of the plug 112 and the sum of the metal interconnect layers of each layer (R2+R41+R42+R43+R44+R45) to the surface area R1 of the gate 144 (or the gate dielectric layer 142) of the gate structure 140 can reach a range of above AR5000 and below AR100000, preferably between AR5000 and AR100000, but not limited thereto.

[0068] In general, the semiconductor device and its formation method of the present invention is to set a carbon-rich dielectric layer with a carbon content of more than 15% and a dielectric constant of less than 2.5 inside at least one intermetallic dielectric layer, preferably inside the intermetallic dielectric layer above the metal interconnect layer with a relatively large surface area, or inside each intermetallic dielectric layer, and the precursor in the carbon-rich dielectric layer neutralizes the free radicals and charged substances generated in the back-end manufacturing process (such as the deposition manufacturing process or the etching manufacturing process), thereby avoiding the accumulation of unstable charges on the metal interconnect layer, and effectively reducing the chance of structural damage to the semiconductor device caused by plasma in the back-end manufacturing process. As a result, the semiconductor device of the present invention can effectively improve the antenna effect under the premise of a significant increase in the antenna ratio, and has significantly improved reliability and yield.

[0069] It should be additionally explained that although the aforementioned embodiments are described using a semiconductor device having a metal interconnect layer as an implementation, those skilled in the art should be able to easily understand that the method of the present invention of using an additional carbon-rich dielectric layer (carbon content exceeding 15% and dielectric constant less than 2.5) to neutralize free radicals and charged species can also be applied to the dielectric layers of other semiconductor structures to improve the structural reliability and yield of other semiconductor structures.

[0070] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: A first dielectric layer, comprising a stack structure, the stack structure comprising a low-k dielectric layer, an etch stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etch stop layer, wherein the carbon content of the carbon-rich dielectric layer exceeds 15%; and The first conductive structure is disposed in the first dielectric layer.

2. The semiconductor device according to claim 1, wherein: The etch stop layer includes nitrogen doped carbon.

3. The semiconductor device according to claim 1, wherein: The dielectric constant of the low dielectric constant dielectric layer is between 2.5 and 2.9, and the dielectric constant of the carbon-rich dielectric layer is smaller than the dielectric constant of the low dielectric constant dielectric layer.

4. The semiconductor device according to claim 3, wherein: The dielectric constant of the etch stop layer is greater than the dielectric constant of the low-k dielectric layer.

5. The semiconductor device according to claim 1, wherein: The carbon content of the carbon-rich dielectric layer is 3% to 10% higher than the carbon content of the low dielectric constant dielectric layer.

6. The semiconductor device according to claim 1, wherein: The stack structure also includes an adhesive layer.

7. The semiconductor device according to claim 6, wherein: The adhesion layer includes an initiation layer and a transition layer sequentially stacked between the etching stop layer and the carbon-rich dielectric layer.

8. The semiconductor device according to claim 7, wherein: The initiation layer or the transition layer includes carbon, oxygen, hydrogen or silicon.

9. The semiconductor device according to claim 1, further comprising: A plurality of second dielectric layers are sequentially stacked on the first dielectric layer; as well as A plurality of second conductive structures are respectively disposed in each of the second dielectric layers, wherein at least one of the second dielectric layers includes another carbon-rich dielectric layer disposed therein, and the carbon content of the other carbon-rich dielectric layer is higher than 15%.

10. The semiconductor device according to claim 1, further comprising: A plurality of second dielectric layers are sequentially stacked on the first dielectric layer; as well as A plurality of second conductive structures are respectively disposed in each of the second dielectric layers, wherein each of the second dielectric layers comprises another carbon-rich dielectric layer disposed in each of the second dielectric layers, and the carbon content of the another carbon-rich dielectric layer is higher than 15%.

11. The semiconductor device according to claim 9, wherein: The surface area of ​​one of the second conductive structures is greater than the surface area of ​​the first conductive structure, and the other carbon-rich dielectric layer is disposed above the one of the second conductive structures.

12. The semiconductor device according to claim 1, further comprising: A gate is disposed below the first dielectric layer, wherein a ratio between a surface area of ​​the first conductive structure and a surface area of ​​the gate is greater than AR5000 and less than AR100000.

13. A method for forming a semiconductor device, comprising: forming a first dielectric layer, the first dielectric layer comprising a stacked structure, the stacked structure comprising a low-k dielectric layer, an etch stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etch stop layer, wherein the carbon content of the carbon-rich dielectric layer exceeds 15%; and A first conductive structure is formed within the first dielectric layer.

14. The method for forming a semiconductor device according to claim 13, wherein: Forming the first dielectric layer further includes: forming an etch stop material layer, a carbon-rich dielectric material layer, and a low-k dielectric material layer in sequence; and An adhesion material layer is formed between the etch stop material layer and the carbon rich dielectric material layer.

15. The method for forming a semiconductor device according to claim 14, wherein: Forming the first conductive structure further includes: forming through holes in the low-k dielectric material layer, the carbon-rich dielectric material layer, and the etch stop material layer; and forming a conductive material to fill the through hole; and The conductive material is partially removed to form the first conductive structure, and the low-k dielectric layer, the carbon-rich dielectric layer and the etching stop layer are formed at the same time.

16. The method for forming a semiconductor device according to claim 13, further comprising: forming a plurality of second dielectric layers on the first dielectric layer, and stacking them sequentially on the first dielectric layer; as well as A plurality of second conductive structures are respectively formed in each of the second dielectric layers, wherein each of the second dielectric layers comprises another carbon-rich dielectric layer disposed in each of the second dielectric layers, and the carbon content of the another carbon-rich dielectric layer is higher than 15%.

17. The method for forming a semiconductor device according to claim 13, further comprising: forming a plurality of second dielectric layers on the first dielectric layer, and stacking them sequentially on the first dielectric layer; as well as A plurality of second conductive structures are formed and are respectively located in each of the second dielectric layers, wherein at least one of the second dielectric layers includes another carbon-rich dielectric layer disposed therein, and the carbon content of the another carbon-rich dielectric layer is higher than 15%.

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