Power cover structure for multi-chip semiconductor package

Abstract

The invention relates to a power cover structure for a multi-chip semiconductor package. A multi-chip semiconductor package, the multi-chip semiconductor package comprising: a dielectric interconnect layer having an upper surface and a bottom surface; at least one common source pad disposed on an upper surface of the interconnect layer; at least one common gate pad disposed on an upper surface of the interconnect layer; and a plurality of semiconductor devices each including a gate pad and at least one source pad bonded to the interconnect layer, where the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and where the source pads of the plurality of semiconductor devices are electrically connected in parallel with each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with each other.

Description

Technical Field The present disclosure relates generally to semiconductor packaging, and more particularly to multi-chip semiconductor packages having interconnect power overlay structures. Background Art Power semiconductor devices, such as switches and rectifiers, are key components of power electronic circuits, such as switch mode power supplies, inverters, rectifiers, etc. High power applications typically require multi-chip assemblies that include multiple power semiconductor devices connected together to carry large currents and support high voltages. When connecting the individual devices into a multi-chip assembly, it is important to maintain layout symmetry and low inductance interconnects to ensure good load sharing, minimize voltage and current overshoots, and reduce switching losses. The top surface of each power semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), includes a gate pad and at least one source pad that are electrically connected to the gate pads and source pads of other devices in the multi-chip assembly. Complex wiring configurations and wire bonding to a common gate pad and at least one common source pad are typically used to form electrical connections to multiple gate pads and source pads. The common gate pad and at least one common source pad of the multi-chip semiconductor assembly can be connected to an external power electronic circuit so that the multi-chip semiconductor assembly operates as a single power processing unit. An alternative to wire bonding of the gate pad and the source pad may be to use one or more planar interconnect layers separated by an interconnect layer disposed above the top surface of the semiconductor device. The interconnect layer may include metallized vias extending through the interconnect layer to electrically couple the source pad and the gate pad to a common gate pad and a common source pad disposed on an upper interconnect layer of the multi-chip semiconductor assembly, thereby delivering power to the semiconductor device through the metallized vias. In order to establish a proper electrical connection with an external power electronic circuit, the common gate pad and common source pad on the topmost interconnect layer need sufficient surface area to solder, sinter, copper bond, copper clamp or otherwise connect the common gate pad and source pad of the multi-chip assembly to the external power electronic circuit. However, the available surface area of ​​the common gate pad and common source pad is usually limited by the total surface area of ​​the multi-chip semiconductor assembly. In addition, direct soldering, sintering, copper bonding and copper clamping to the smaller common gate pad and common source pad will introduce bonding stress to the multi-chip semiconductor assembly and form a less reliable interconnection. In addition, connecting multiple gate pads together into a common gate pad of a multi-chip semiconductor assembly and connecting multiple source pads together into a common source pad of a multi-chip semiconductor assembly requires good layout symmetry, resulting in matching inductances of each connection to ensure good load sharing between the individual devices. Implementing high current power modules requires connecting multiple semiconductor devices in parallel. For example, building a 480A power module will require connecting eight devices in parallel, each with a rated current of approximately 60A. Due to the different individual characteristics of the eight devices and the challenge of connecting each device to an external power electronic circuit so that each switch receives a signal to turn on or off at the same time, connecting eight devices in parallel is challenging in ensuring that all eight devices share current equally. This is driven by the gate-source parasitic impedance, which is driven by the geometry of the trace connectors between the devices. The more devices are connected in parallel, the more complex it is to balance the impedance to ensure that each device switches at the same time and shares the current. One solution is to connect two larger semiconductor devices in parallel, each with a rated current of approximately 240A. A device rated at 240 A will be much larger than one rated at 60 A. This will make packaging and interconnection easier, however, device yield will be significantly reduced. Finally, semiconductor fabrication processes inherently result in different characteristics of individual semiconductor devices from wafer to wafer and within a wafer. Therefore, building a multi-chip semiconductor assembly from individual devices having similar characteristics will further preserve the full performance of the individual devices within the multi-chip assembly. Summary of the invention In one aspect, a multi-chip semiconductor package is disclosed. The package includes: an interconnect layer having an upper surface and a bottom surface, wherein the interconnect layer includes a dielectric material; at least one common source pad disposed on the upper surface of the interconnect layer; at least one common gate pad disposed on the upper surface of the interconnect layer; and a plurality of semiconductor devices, each semiconductor device including a gate pad and at least one source pad bonded to the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel to each other. In another aspect, a method of manufacturing a multi-chip semiconductor package is disclosed. The method includes forming at least one source via and at least one gate via through an interconnect layer, aligning at least one source pad and a gate pad of a plurality of semiconductor devices with the at least one source via and at least one gate via, respectively, and bonding the plurality of semiconductor devices to the interconnect layer, wherein a surface area of ​​the interconnect layer is substantially equal to a surface area of ​​a footprint defined by the plurality of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS The subject matter of the present disclosure will be explained in more detail hereinafter with reference to exemplary embodiments shown in the drawings. Figure 1 is a perspective view of one embodiment of a semiconductor device; Figure 2 is a perspective view of one embodiment of a molding of a multi-chip semiconductor package; Figure 3 is a perspective view of one embodiment of a multi-chip semiconductor package; Figure 4 yes Figure 3 A plan view of a multi-chip semiconductor package; Figure 5 yes Figure 3 An exploded view of a multi-chip semiconductor package; Figure 6 yes Figure 3 An exploded view of a multi-chip semiconductor package; Figure 7 yes Figure 3 A cross-sectional view of a multi-chip semiconductor package taken along line AA'; Figure 8 yes Figure 3 A cross-sectional view of a multi-chip semiconductor package taken along line BB'; Fig.9A is a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Fig. 9B is a semi-transparent plan view of an example interconnect layer and associated wiring according to one or more embodiments of the present disclosure; Fig. 9C yes Fig. 9B A cross-sectional view of the interconnect layer and associated wiring taken along line CC'; Fig.9D yes Fig. 9B A cross-sectional view of the interconnect layer and associated wiring taken along line D-D'; Fig. 10A is a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Fig. 10B is a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Fig.11 and Fig.12 is a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Fig.13A is a plan view of an example first interconnect layer and associated wiring according to one or more embodiments of the present disclosure; Fig. 13Bis a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Fig. 13C is a plan view of example interconnect layers and associated wiring according to one or more embodiments of the present disclosure; Figures 14A-14B is a cross-sectional view of an example backside structure; and Figures 15A-15B One embodiment of a method of manufacturing a multi-chip semiconductor package is shown. The reference numerals used in the drawings and their meanings are listed in summary form in the reference numeral list. In principle, in the figures, identical components are provided with identical reference numerals. DETAILED DESCRIPTION In the following specification and claims, reference will be made to a number of terms which shall be defined to have the following meanings. As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. The terms "optional" or "optionally" mean that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not occur. Unless otherwise indicated, approximate language as used herein (such as "generally", "substantially" and "approximately") indicates that the term so modified may apply only to an approximate degree, as recognized by those of ordinary skill in the art, rather than an absolute or perfect degree. Therefore, a value modified by one or more terms (such as "approximately", "approximately" and "substantially") is not limited to the precise value specified. In at least some instances, the approximate language may correspond to the precision of the instrument used to measure the value. Here and throughout the specification and claims, range limitations may be identified. Unless otherwise indicated by context or language, such ranges may be combined and / or interchanged, and include all subranges contained therein. In addition, unless otherwise indicated, the terms "first", "second", etc. are used herein merely as labels and are not intended to impose order, position, or hierarchical requirements on the items to which these terms refer. Furthermore, for example, reference to a "second" item does not require or exclude the presence of, for example, a "first" or lower numbered item or a "third" or higher numbered item. Embodiments of the present disclosure generally relate to structures and methods for packaging multiple semiconductor devices, and more specifically to multi-chip semiconductor packages with interconnected power overlay (POL) structures. The methods, systems, and devices described herein overcome at least some of the disadvantages of at least some known multi-chip semiconductor packages. More specifically, the systems and devices described herein provide a POL package configured as a redistribution layer (RDL) directly above multiple semiconductor devices. Therefore, the POL package is also referred to as a POL-RDL package herein. Relative to the footprint of the molding defined by the semiconductor device (or more generally, relative to the footprint of the semiconductor device), the POL-RDL package includes an excessively large surface area, which increases the available surface area for placing common gate pads, common source pads, and overlapping contact pads. The excessively large surface area also allows for the placement of common source pads, common gate pads, and gate bridges, as well as additional interconnect layers and more complex configurations of interconnect layers. A multi-chip semiconductor package is disclosed. The multi-chip semiconductor package includes at least one interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of at least one interconnect layer, at least one common gate pad disposed on the upper surface of at least one interconnect layer, and a plurality of semiconductor devices. Each semiconductor device has a gate pad and at least one source pad bonded to the bottom surface of a first interconnect layer of at least one interconnect layer. The bottom surface of the first interconnect layer has an adhesive layer. The source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other. The gate pads of the plurality of semiconductor devices are electrically connected to the at least one common gate pad, and the gate pads of the plurality of semiconductor devices are electrically connected in parallel to each other. As used herein, the term "wiring" refers to metallized vias disposed within through-hole paths of an interconnect layer, and to trace connections, pads, contacts, and contact pads disposed on an interconnect layer. Wiring may also include surface mount resistors, thin film resistors, and associated pads for placement of surface mount resistors after fabrication. Additional interconnect layers and wiring may be laminated or otherwise fabricated above the first interconnect layer to facilitate additional wiring configurations. As used herein, the terms "package gate pad" and "package source pad" refer to a common gate pad and a common source pad on the topmost interconnect layer that are electrically connected to an external power electronic circuit. Any first interconnect layer and additional interconnect layers disclosed herein may be directly connected to an external power electronic circuit, or may have additional interconnect layers and wiring. Therefore, the terms "package gate pad," "package source pad," "common gate pad," and "common source pad" may be used interchangeably. Figure 1 A perspective view of one embodiment of a semiconductor device 100 is shown. Figure 21 shows a perspective view of a molding 102 including at least two semiconductor devices 100 (also referred to as a plurality of semiconductor devices 100). Figure 1 and Figure 2 As shown, the semiconductor device 100 includes a dielectric material 106 defining an upper surface 101. The semiconductor device 100 also includes a gate pad 120 and at least one source pad 110 disposed on the upper surface 101 of the semiconductor device 100. The at least one source pad 110 includes a top contact surface 112. Likewise, the gate pad 120 includes a top contact surface 122. The top contact surfaces 112, 122 of each of the gate pad 120 and the at least one source pad 110 are electrically isolated from each other by the dielectric material 106. In some embodiments, at least a portion of the gate pad 120 and the at least one source pad 110 extend at least partially below the upper surface 101. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are flush with the surface of the dielectric material 106. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are below the surface of the dielectric material 106. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are above the surface of the dielectric material 106. like Figure 2 As shown, the molding 102 includes an underfill material 103 defining an upper surface 104, and a plurality of semiconductor devices 100 at least partially disposed in the molding 102 and surrounded by the underfill material 103. The plurality of semiconductor devices 100 embedded in the molding 102 define a footprint 105 (eg, Figure 4 best shown in ). Figure 3-8 One or more embodiments of a multi-chip semiconductor package 200 are shown. Figure 3 shows a perspective view of a multi-chip semiconductor package 200, Figure 4 A partially transparent plan view of a semiconductor package 200 is shown, and Figure 5 and Figure 6 An exploded view of semiconductor package 200 is shown. Figure 7 and Figure 8 They are shown along Figure 4 2 is a cross-sectional view of the semiconductor package 200 taken along lines AA′ and BB′. The multi-chip semiconductor package 200 operates as a metal oxide semiconductor field effect transistor (MOSFET) having two or more semiconductor devices 100. The multi-chip semiconductor package 200 includes a POL-RDL package 250 having at least one common source pad 280 and a gate bridge 290. The POL-RDL package 250 includes a first interconnect layer 260 and an adhesive layer 262 (such as a first interconnect layer 260 and an adhesive layer 262) disposed on the molding 102. Figure 5 In some embodiments, the first interconnect layer 260 is in the form of a stack or film and may be formed from one of a variety of dielectric materials, such as Polyimide, Polyetherimide, polytetrafluoroethylene (PTFE), Polysulfone materials (e.g. Polysulfone, polyphenol sulfone) or another polymer film such as liquid crystal polymer (LCP), bismaleimide-triazine resin, Ajinomoto ABF or polyimide material. In one embodiment, the POL-RDL package 250 has a total thickness in the range of 25 microns to 300 microns. In some embodiments, the POL-RDL package 250 (which may include any number of interconnect layers 260, trace connections, source pads, and gate pads) is completely fabricated and positioned over the molding 102 (along with multiple semiconductor devices 100 embedded in the molding 102), and the first interconnect layer 260 is bonded to the source pad 110 and the gate pad 120 by the bonding layer 262. That is, the bonding layer 262 is positioned between the first interconnect layer 260 and the molding 102. In some embodiments, the semiconductor devices 100 can be bonded directly to the bonding layer 262 without the molding. The molding material or underfill material can be deposited between the semiconductor devices 100 at a later stage. In operation, in the source via 264 and the gate via 266 extending through the first interconnect layer 260 (and in the example shown below with reference to Figures 9A-14BThe first interconnect layer 260 is formed with metallized vias (in any number of additional interconnect layers as further described in detail), associated metal interconnect structures and wiring are constructed above the first interconnect layer 260 (and in any number of additional interconnect layers), and an adhesive layer 262 is applied to the bottom surface of the first interconnect layer 260. According to one or more configurations, the semiconductor device 100 (as part of the molding 102 or separately) is aligned with the source via 264 and the gate via 266 extending through the first interconnect layer 160, and the molding 102 is cured to form the multi-chip semiconductor package 200. It should be understood that any of the steps in the fabrication can be performed in a different order. As an example, the source via 264 and the gate via 266 can be filled before aligning and bonding the semiconductor device 100 (as part of the molding 102 or separately). At least one common source pad 280 and a gate bridge 290 are formed on the upper surface 261 of the first interconnect layer 260. The source via 264 and the gate via 266 extend through the first interconnect layer 260 and the adhesive layer 262. Figure 7 and Figure 8 As best shown in FIG. 1 , the POL-RDL package 250 of the multi-chip semiconductor package 200 further includes a metal interconnect structure 267 that extends through the source through via 264 and the gate through via 266. The metal interconnect structure 267 electrically couples the top contact surface 112 of each source pad 110 to at least one common source pad 280 of the POL-RDL package 250, and similarly, the metal interconnect structure 267 electrically couples the top contact surface 122 of the gate pad 120 to the gate bridge 290 of the POL-RDL package 250. In some embodiments, the metal interconnect structure 267 is formed by filling the source via 264 and the gate via 266 with a conductive material (i.e., conductive epoxy, paste, or solder, etc.). In some embodiments, the vias have a copper plated and sputtered adhesion layer, such as titanium or titanium tungsten. In some embodiments, the metal interconnect structure 267 is formed during the deposition of at least one common source pad 280 and gate bridge 290. As an example, when the at least one common source pad 280 and gate bridge 290 are deposited, the source via 264 and the gate via 266 are also filled. Subsequently, the at least one common source pad 280 and the gate bridge 290 are electroplated or otherwise plated or fabricated to a desired thickness. In some embodiments, gate bridge 290 includes a common gate pad 292 and a gate contact 296 connected by a trace connector 294. Figure 6 As best shown in FIG. 1 , each gate contact 296 of the gate bridge 290 is aligned with the gate pads 120 of the plurality of semiconductor devices 100. Figure 7 and Figure 8As shown, a common gate pad 292, a trace connection 294, and a gate contact 296 are disposed on the first interconnect layer 260 of the POL-RDL package 250, and the gate contact 296 is electrically connected to the gate pad 120 through the metal interconnect structure 267. The trace connection 294 extends from the common gate pad 292 to the gate contact 296, and may have any number of branches and bends to establish an electrical connection between the common gate pad 292 and the gate contact 296. In the illustrated embodiment, the gate bridge 290 has an I-shape, wherein each end is a pair of gate contacts 296 aligned with the gate pads 120 of the plurality of semiconductor devices 100, however, as shown in FIG. Figures 11 to 13A As shown, gate bridge 290 may have other shapes and configurations, but maintain equal path lengths, as described in further detail below. like Figure 4 As shown, the trace connector 294 of the gate bridge 290 has the same length between the common gate pad 292 and the gate contact 296, so that the common gate pad 292 and the gate contact 296 have equal resistivity values. The length of the trace connector 294 affects the inductance. To alternatively achieve substantially equal resistivity, the length of the common gate pad 292 and the trace connector 294 can be made similar to all gate pads 120 of the semiconductor device 100. However, depending on how the source is connected, it can create asymmetry in the gate-source loop inductance, which is a key parameter. The POL-RDL package 250 provides flexibility in optimizing the gate-source loop inductance depending on how it is oriented and connected to the next level circuit. For example, the resistivity and trace length of two semiconductor devices 100 are different from the other two semiconductor devices 100, so that the final gate-source loop to each device is similar / equal. To achieve trace connections 294 with equal lengths and equal resistivity values, semiconductor devices 100 may be oriented or positioned on adhesive layer 262 and first interconnect layer 260 such that the gate pad 120 of each semiconductor device is equal in length to the common gate pad 292 of gate bridge 290. In some embodiments, any trace connection 294 may include a surface mount resistor or a thin film resistor to balance the resistivity values. like Figure 2 , Figure 4 and Figure 7As shown, the peripheral edge 108 of the underfill material 103 defines the surface area of ​​the molding 102. Each of the plurality of semiconductor devices 100 is spaced apart from the peripheral edge 108 of the molding 102, and the placement of the plurality of semiconductor devices 100 in the molding 102 defines a footprint 105 of the molding 102 (note that the footprint 105, as defined herein, generally has a smaller surface than the molding 102 itself). It should be understood that in some embodiments, the plurality of semiconductor devices 100 are directly bonded to the first interconnect layer 260 (and bonding layer 262) without the use of the molding 102, and in such embodiments, the footprint 105 is defined as the placement of the plurality of semiconductor devices 100 on the bottom surface of the first interconnect layer 260. Therefore, the footprint 105 is defined as the outermost edge of the plurality of semiconductor devices 100. The first interconnect layer 260 of the POL-RDL package 250 is generally placed over the entire molding 102 and has a surface area greater than the footprint 105 of the molding 102, such that a peripheral edge 268 of the first interconnect layer 260 extends beyond the footprint 105 of the molding 102 and the outermost edges of the plurality of semiconductor devices 100 (note that the peripheral edge 268 does not extend beyond the perimeter of the molding itself 102). In some embodiments, the adhesive layer 262 extends to the peripheral edge 268 of the first interconnect layer 260. In some embodiments, the overhang region 274 of the POL-RDL package 250 increases the available surface area of ​​the first interconnect layer 260 for placement of a larger common source pad 280 and a larger common gate pad 292. The overhang region 274 also allows for placement of a more complex configuration of common source pads 280, gate bridges 290, common gate pads 292, and trace connections for the common source pads 280 and common gate pads 292, as described in further detail below. Thus, the POL-RDL package 250 facilitates improved routing and more robust connection of at least one common source pad 280 and common gate pad 292 to an external power electronic circuit or to an additional interconnect layer disposed above the first interconnect layer 260 (as described in further detail below). Connection of the external power electronic circuit—either directly to the at least one common source pad 280 and common gate pad 292, or through an additional interconnect layer—enables the source pads 110 of multiple semiconductor devices 100 to be used for electrical control and switching. As an example, the source pads 110 of the plurality of semiconductor devices 100 may be configured to switch on and off thousands of times per second the power received from the corresponding gate pads 120. At least one common source pad 280 and a common gate pad 292 establish input-output (I / O) connections for the source pads 110 and the corresponding gate pads 120 through the metal interconnect structure 267. The input-output (I / O) connections enable the multi-chip semiconductor package 200 to be connected to an external power electronic circuit, such as a printed circuit board (PCB). In at least some embodiments, the surface area of ​​the POL-RDL package 250 (e.g., the surface area of ​​the first interconnect layer 260) is substantially equal to the surface area of ​​the footprint 105 defined by the plurality of semiconductor devices 100. For example, the surface area of ​​the POL-RDL package 250 may be between 10% greater than the surface area of ​​the footprint 105 and 10% less than the surface area of ​​the footprint, more particularly, between 5% greater than the surface area of ​​the footprint 105 and 5% less than the surface area of ​​the footprint, and even more particularly, between 2% greater than the surface area of ​​the footprint 105 and 5% less than the surface area of ​​the footprint.

[0054] 9A to 9D An embodiment of a wiring 300 of an interconnect layer 302 positioned above the first interconnect layer 260 is shown. Fig.9A A top view of the interconnect layer 302 and associated wiring 300 is shown. Fig. 9B A top semi-transparent view of the interconnect layer 302 and associated wiring 300 is shown. Fig. 9C shows a cross-sectional view of the interconnect layer 302 and associated wiring 300 taken along line CC', and Fig.9D3. A cross-sectional view of interconnect layer 302 and associated wiring 300 is shown. Interconnect layer 302 is stacked on POL-RDL package 250 (and in particular first interconnect layer 260), and includes similar Figure 1-8 The pads and trace connections of the components shown in multi-chip semiconductor package 200. An interconnect layer 302 is applied over the first interconnect layer 260 of the POL-RDL package 250. The interconnect layer 302 includes at least one package contact pad 370 and a package gate pad 390 that facilitates connection of the multi-chip semiconductor package 200 to an external power electronic circuit. The electrical connection includes one or more of soldering, sintering, copper bonding, copper clips, etc. In some embodiments, additional interconnect layers may be laminated over the interconnect layer 302 to facilitate more complex routing from the at least one package contact pad 370 and the package gate pad 390. In some embodiments, at least one package contact pad 370 is a Kelvin contact. Trace connector 372 extends from at least one package contact pad 370 to an attachment pad 374 and may have any number of branches and bends to establish electrical connection to underlying structures such as common source pad 280 of first interconnect layer 260. Common source pad 280 of first interconnect layer 260 is electrically connected to attachment pad 374 by a metal interconnect via 362 extending through interconnect layer 302. Interconnect via 362 is aligned with at least one common source pad 280 for deposition of a metal interconnect structure extending through interconnect via 362. The interconnect layer 302 includes a gate via 392 for connecting the common gate pad 292 to the package gate pad 390 on the interconnect layer 302. In some embodiments, the metal interconnect structure is formed by filling the interconnect via 362 and the gate via 392 with a conductive material (i.e., conductive epoxy, paste, solder, etc.). In some embodiments, the metal interconnect structure is formed during the deposition of at least one package contact pad 370, trace connection 372, attachment pad 374, and package gate pad 390. The larger surface area of ​​the overhang area 274 and the POL-RDL package 250 facilitates complex routing. Fig. 9B As shown, the trace connector 372 extends into the overhang region, however, it should be understood that the trace connector 372 can extend across at least one common source pad 280 of the first interconnect layer 260. By way of example and not limitation, Fig. 10A An embodiment is shown in which the trace connection 372 extends across at least one common source pad 280 of the first interconnect layer 260 . Reference Fig.9A and Fig. 9B, the trace connection 372 extends at least partially into the overhang region 274, and the gate bridge 290 has an I-shape. Each of the gate contact 296 and the trace connection 294 of the gate bridge 290 is equidistant from the common gate pad 292, so that the gate contact 296 has the same resistivity. In the illustrated embodiment, the interconnect layer 302 includes two common contact pads 370, and each common contact pad 370 is connected to two corresponding semiconductor devices 100 through an attachment pad 374 and a trace connection 372. In some embodiments, each semiconductor device 100 has at least one attachment pad 374. The two common contact pads 370 and the common gate pad 292 are configured as input-output (I / O) connections of the multi-chip semiconductor package 200 to an external power electronic circuit. like Fig. 10B As shown, in some embodiments, the gate attach pad 394 is electrically connected to the common gate pad 292 of the gate bridge 290 through the gate through hole via 392 (eg, Fig. 9B 394). The package gate pad 390 is electrically connected to the gate attachment pad 394 via a trace connector 396. In some embodiments, the trace connector 396 includes a surface mounted resistor 398. In some embodiments, the resistor 398 can be connected after fabrication so that the resistance value can be changed after fabrication to meet different application requirements. In some embodiments, the trace connector 396 includes an attachment pad for mounting the surface mounted resistor 398 after fabrication. Fig.11 and Fig.12 A further embodiment of wiring (400, 500) on the interconnect layer 302 is shown. Fig.11 and Fig.12 In the figure, at least one common source pad 280 is omitted for clarity of the drawing. like Fig.11 As shown, one embodiment of the wiring 400 includes two common source pads or Kelvin pads 470, and each common contact pad 470 is connected to two corresponding semiconductor devices 100 through a trace connection 472. The gate bridge 490 includes a common gate pad 492 at least partially disposed in the overhang region 274 and a gate contact 496 connected to each corresponding semiconductor device 100 through a trace connection 494. like Fig.12As shown, another embodiment of the wiring 500 includes two common contact pads or Kelvin pads 570 disposed at least partially in the overhang area 274, and each common contact pad 570 is connected to two corresponding semiconductor devices 100 through a trace connection 572. In some embodiments, the two common contact pads 570 are Kelvin contacts. The gate bridge 590 includes a common gate pad 592 disposed at least partially in the overhang area 274 and a gate contact 596 connected to each corresponding semiconductor device 100 through a trace connection 594. The overhang region 274 and larger surface area of ​​the POL-RDL package 250 facilitates the use of a large range of common gate pads (292, 492, 592), common contact pads (370, 470, 570), and associated trace connections (294, 494, 594, 372, 472, 572). Placing the common gate pads (292, 492, 592) and at least one package contact pad 370 at least partially on the overhang region 274 also facilitates improved creepage control between components. The POL-RDL package 250 also enables an improved elastic (Young's) modulus of the first interconnect layer 260, which reduces bonding stress on the semiconductor device 100. The first interconnect layer 260 of the POL-RDL package 250 may be polyimide, which has an elastic modulus of approximately 2.5 GPa, while the semiconductor device 100, which may be SiO2, may have an elastic modulus of approximately 70 GPa. The lower elastic modulus can absorb the bonding stress, thereby reducing the bonding stress on the semiconductor device 100. Therefore, the POL-RDL package 250 can buffer the stress during wire bonding to protect the semiconductor device 100. The trace connectors (294, 494, 594, 372, 472, 572) may have varying resistivity values ​​and various trace configuration structures. Using different types of trace configurations enables selective adjustment of the resistivity value between the common gate pad (292, 492, 592) and the gate contact (296, 496, 596). The common gate pad and the common contact pad may then be connected to the package gate pad and the package contact pad on the additional interconnect layer. Notably, the additional resistance reduces crosstalk, thereby improving the efficiency of the semiconductor device 100. According to the embodiments described herein, the resistance value may be selectively adjusted for a particular application without changing the semiconductor device 100 during fabrication and assembly. This allows for simplified fabrication and binning of multiple semiconductor devices 100 during fabrication.

[0066] For example, the resistivity value of the trace connector (294, 494, 594, 372, 472, 572) can be changed by depositing the trace connector with a material having a different resistivity, by modifying the width of the trace connector, and / or by modifying the deposition thickness of the trace connector. An exemplary trace connector (294, 494, 594, 372, 472, 572) having a length of 2 mm, a width of 35 mm, and a thickness of 10 mm has a resistance of approximately 0.1 Ω. In some embodiments, the trace connector (294, 494, 594, 372, 472, 572) has a thickness in the range of 5-25 mm and a trace width of approximately 25 mm. In some embodiments, the trace connector (294, 494, 594, 372, 472, 572) is deposited to a depth in the range of 50 nanometers (nm) to 50 micrometers (μm). In some embodiments, the resistivity value of the trace connector (294, 494, 594, 372, 472, 572) is tuned or changed by changing the volume of the trace connector (294, 494, 594, 372, 472, 572), changing the cross-sectional area of ​​the trace connector (294, 494, 594, 372, 472, 572), and / or changing the material of the trace connector (294, 494, 594, 372, 472, 572). In some embodiments, the trace connector (294, 494, 594, 372, 472, 572) is made of a combination of a first material having a first resistivity value and a second material having a second resistivity value, and the second material is laminated or otherwise layered on top of the first material. The resistivity value of the trace connector (294, 494, 594, 372, 472, 572) can be selectively adjustable in the range of 10 mΩ (micro-ohms) to 100 mΩ. In some embodiments, the trace connector (294, 494, 594, 372, 472, 572) is a resistor. In addition, in some embodiments, the trace connector (294, 494, 594, 372, 472, 572) is a surface mounted resistor. In some embodiments, the resistor 176 can be connected after manufacturing so that the resistance value can be changed after manufacturing to meet different application requirements. In order to establish a proper connection to the external power electronic circuit, the common gate pad 292 of the gate bridge 290 and the at least one common source pad 280 must have sufficient surface area to make electrical connections. However, the complexity and surface area of ​​the at least one common source pad 280 and the gate bridge 290 are ultimately limited by the total surface area of ​​the first interconnect layer 260. As an example, in at least some known semiconductor assemblies, the gate pad in the POL package may have a surface area of ​​at most 0.6 square millimeters (mm 2) without the benefit of overhang region 274. Without the benefit of the additional surface area provided by overhang region 274, a larger gate pad would necessarily reduce the available area for placing the source pad, resulting in a lower current rating for each multi-chip semiconductor package 200. In contrast, in at least some embodiments described herein, given the benefit of overhang region 274, common gate pad 292 of gate bridge 290 has a surface area of ​​0.5 mm 2 Up to 1.5mm 2 9-12, the overhang area 274 of the POL-RDL package 250 allows for redistribution and more complex configurations of the common gate pad 292 of the gate bridge 290, while still maintaining the current rating of the semiconductor device 100. As shown in FIGS. 9-12, similar to the gate bridge 290, the overhang area 274 of the POL-RDL package 250 allows for redistribution and more complex routing configurations of additional interconnect layers, while still maintaining the current rating of the multi-chip semiconductor package 200. Fig.13A An alternative embodiment of wiring 702 deployed on a first interconnect layer is shown, and Fig. 13B The associated wiring 800 of the interconnect layer disposed above the first interconnect layer is shown. The first and interconnect layers include wiring similar to those previously described with reference to Figure 1-10B Components of first interconnect layer 260 and interconnect layer 302 are depicted. like Fig.13A As shown, the wiring 700 of the first interconnect layer includes a first common source pad 710, a second common source pad 712, and a gate bridge 730. The common source pads (710, 712) are electrically connected to the underlying semiconductor device 100 through a source through-hole via 714 extending through the first interconnect layer. The gate bridge 730 includes a common gate pad 732 and a gate contact 734 connected by a trace connection 736. The trace connection 736 is electrically connected to the underlying semiconductor device 100 through a gate through-hole via 738 extending through the first interconnect layer. Fig. 13B As shown, the wiring 800 of the interconnect layer includes a package contact pad 810 electrically connected to the first common source pad 710 and the second common source pad 712, and a package gate pad 830 electrically connected to the common gate pad 732. The package contact pad 810 is electrically connected to the first common source pad 710 and the second common source pad 712 through the intermediate metal interconnect layer 802. like Fig. 13C As shown, in some embodiments, the gate attachment pad 832 is electrically connected to ( Fig.13A) common gate pad 732, and gate attachment pad 832 is connected to package gate pad 830 via trace connector 834. In some embodiments, trace connector 834 includes surface mounted resistor 836. In some embodiments, resistor 836 can be connected after fabrication so that the resistance value can be changed after fabrication to meet different application requirements. In some embodiments, trace connector 834 includes an attachment pad for mounting surface mounted resistor 836 after fabrication. Figures 14A-14B A cross-sectional view of a backside structure 900 connected to the bottom surface 111 of the semiconductor device 100 is shown. Fig. 9B The line C-C' is intercepted. like Fig.14A As shown, the bottom surface 111 of the semiconductor device 100 includes the drain pad and remains exposed. A sputtered layer 902 is sputtered on the bottom surface 111 of the drain pad. The sputtered layer 902 facilitates electrical and thermal contact with the back side using solder, sintered silver, or conductive glue. The sputtered layer 902 substantially covers the entire bottom surface 111 of the semiconductor device 100, and in some embodiments, the sputtered layer 902 substantially covers the molding. Fig. 14B As shown, a conductive plate 904 is then applied to the sputtered layer 902. In some embodiments, the conductive plate 720 is a direct bonded copper DBC type substrate. like Fig.14A As shown, a sputtered layer 902 and a conductive plate 904 are applied to the bottom surface 111 of the semiconductor device 100 before the molding 102 is applied. Fig. 14B As shown, the molding 102 extends below the bottom surface 111 of the semiconductor device 100, and the bottom surface 111 of the semiconductor device 100 remains partially exposed, so that a partial shell is formed. The sputtered layer 902 fills the gap in the shell so that the sputtered layer 902 is coplanar with the molding 102. Then the conductive plate 904 is applied to the sputtered layer 902. Figures 15A-15B One embodiment of a method 1000 of manufacturing a multi-chip semiconductor package, such as the aforementioned multi-chip semiconductor package 200, is shown. The method 1000 includes bonding 1002 a bonding layer to a first interconnect layer of a POL-RDL package, and forming 1004 at least one source via and at least one gate via through the first interconnect layer and the bonding layer. The method 1000 also includes aligning 1006 at least one source pad and a gate pad of the plurality of semiconductor devices with at least one source through via and at least one gate through via, respectively, and bonding 1008 the plurality of semiconductor devices to the bonding layer. The method also includes filling 1010 at least one source through via and at least one gate through via, respectively, defined in the first interconnect layer with at least one metallized through hole. The method 1000 also includes depositing 1012 at least one common source pad and gate bridge, respectively, over at least one gate through via. In some embodiments, the method 1000 further includes stacking 1014 an interconnect layer over the first interconnect layer and forming 1016 at least one source via and at least one gate via in the interconnect layer. The method 1000 further includes filling 1018 the at least one source via and at least one gate via, respectively, defined in the interconnect layer with at least one metallized via. The method 1000 further includes depositing 1020 a package contact pad and a package gate pad over the at least one source via and at least one gate via, respectively defined in the interconnect layer. In some embodiments, method 1000 further comprises depositing 1022 a sputtered layer stacked over the bottom surface of the plurality of semiconductor devices, the sputtered layer electrically connected to a drain connector of the at least one common source pad of the plurality of semiconductor devices. In some embodiments, method 1000 further comprises applying 1024 a conductive plate over the bottom surface of the sputtered layer. In some embodiments, the metallization layer is formed by a combination of sputtering and electroplating applications, but it should be recognized that other chemical plating methods of metal deposition may also be used. For example, a titanium adhesion layer and a copper seed layer may be first applied via a sputtering process, followed by an electroplating process to increase the thickness of the copper to a desired level. The applied metal material is then subsequently patterned into a metal interconnect having a desired shape and used as a vertical feed-through formed through the interconnect layer and the adhesion layer. The above embodiments overcome at least some of the disadvantages of semiconductor devices. Specifically, the embodiments improve the surface bonding to the contact pads of the POL structure. In particular, the overhang region of the POL structure reduces the bonding stress on the semiconductor device. The overhang region of the POL structure allows redistribution of the components of the second laminate interconnect layer and the POL-RDL package, and allows the contact pads to have a larger surface area. The overhang region also allows for more extensive use of trace connections with different resistivities. The POL-RDL package also allows multiple semiconductor devices to operate as a single device with a common gate pad and a common source pad. Individual semiconductor devices can be classified and grouped into devices with similar characteristics, thereby eliminating devices with wafer defects. In contrast to making a single large and complex semiconductor package, this allows the formation of a multi-chip semiconductor package that exceeds practical yield limits. In addition, when tiled together, the multi-chip semiconductor device allows a 5mOHM device. As an example and not a limitation, four 20mOHM semiconductor devices are classified into a multi-chip semiconductor package, and the semiconductor devices are connected in parallel with a common gate pad and a common source pad to obtain a 5mOHM device. As previously mentioned, combining multiple semiconductor devices together into a multi-chip semiconductor package requires matching semiconductor devices with similar characteristics, which is due to the inherent yield differences of individual semiconductor devices in semiconductor manufacturing and fabrication processes. In addition, the density limitations of multi-chip semiconductor package manufacturing and assembly increase the complexity of multi-chip semiconductor package design. Such factors can change the characteristics of semiconductor devices. POL-RDL packaging and the described systems and methods facilitate tiling semiconductor devices together. Each semiconductor device can be individually sorted to improve packaging without having to overcome the differences in defect density of larger semiconductor devices. The methods, systems, and compositions disclosed herein are not limited to the specific embodiments described herein, but rather, steps of methods, elements of systems, and / or elements of compositions may be utilized independently and separately from other steps and / or elements described herein. Although specific features of various embodiments may be shown in some drawings and not in other drawings, this is for convenience only. In addition, references to "one embodiment" in the above description are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the described features. In accordance with the principles of the present disclosure, any feature of a drawing may be referenced and / or claimed in combination with any feature of any other drawing. This written description uses examples, including the best mode, to enable any person skilled in the art to practice the disclosure, including making and using any device or system and performing any incorporated method. The patentable scope of the disclosure is defined by the claims and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that do not differ substantially from the literal language of the claims. This application also discloses a set of technical solutions, as follows: Technical Solution 1. A multi-chip semiconductor package, comprising: an interconnect layer having an upper surface and a bottom surface, wherein the interconnect layer comprises a dielectric material; at least one common source pad disposed on said upper surface of said interconnect layer; at least one common gate pad disposed on the upper surface of the interconnect layer; and a plurality of semiconductor devices, each of the plurality of semiconductor devices comprising a gate pad and at least one source pad bonded to the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to each other in parallel. Technical Solution 2. The multi-chip semiconductor package according to Technical Solution 1 further includes an adhesive layer disposed on the bottom surface of the interconnect layer. Technical Solution 3. The multi-chip semiconductor package according to Technical Solution 1 also includes a plurality of gate contacts deployed on the interconnect layer and electrically connected to the common gate pad through trace connectors, wherein each gate pad of each semiconductor device in the plurality of semiconductor devices is connected to an associated gate contact of the plurality of gate contacts. Technical Solution 4. A multi-chip semiconductor package according to Technical Solution 3, wherein the plurality of gate contacts are equidistant from the common gate pad. Technical Solution 5. A multi-chip semiconductor package according to Technical Solution 3, wherein the gate trace connections have equal resistivity values. Technical Solution 6. A multi-chip semiconductor package according to Technical Solution 5, wherein at least one of the trace connectors comprises one of a surface mount resistor and a thin film resistor. Technical Solution 7. A multi-chip semiconductor package according to Technical Solution 3, wherein the common gate pad and the at least one common source pad are configured to be electrically connected to an external power electronic circuit so that the POL-RDL package operates as a single processing unit. Technical Solution 8. The multi-chip semiconductor package according to Technical Solution 7 further includes a Kelvin contact electrically connected to the at least one common source pad to facilitate connecting the at least one common source pad to the external power electronic circuit. Technical Solution 9. The multi-chip semiconductor package according to Technical Solution 1 further comprises: an additional interconnect layer disposed above the interconnect layer; a package gate pad disposed on the additional interconnect layer and electrically connected to the common gate pad of the interconnect layer; and At least one package source pad disposed on the additional interconnect layer and electrically connected to the at least one common source pad of the interconnect layer. Technical Solution 10. A multi-chip semiconductor package according to Technical Solution 9, wherein the package gate pad is electrically connected to a gate attachment pad through a trace connection, and the gate attachment pad is connected to the common gate pad of the interconnect layer. Technical Solution 11. A multi-chip semiconductor package according to Technical Solution 10, wherein the trace connection electrically connected to the package gate pad comprises one of a surface mount resistor and a thin film resistor. Technical Solution 12. A multi-chip semiconductor package according to Technical Solution 9, wherein the package gate pad and the at least one package source pad are configured to be electrically connected to an external power electronic circuit so that the POL-RDL package operates as a single power switching unit. Technical Solution 13. A multi-chip semiconductor package according to Technical Solution 1, wherein a surface area of ​​the interconnect layer is substantially equal to a surface area of ​​an occupied space defined by the plurality of semiconductor devices. Technical Solution 14. A multi-chip semiconductor package according to Technical Solution 1, wherein the back sides of the semiconductor devices are electrically connected together through a conductive plate to form a common drain connection. Technical Solution 15. The multi-chip semiconductor package according to Technical Solution 14 further includes a molding member disposed between the interconnect layer and the conductive plate. Technical Solution 16. A method for manufacturing a multi-chip semiconductor package, the method comprising: forming at least one source via and at least one gate via through an interconnect layer, the interconnect layer comprising a dielectric material; aligning at least one source pad and a gate pad of a plurality of semiconductor devices with the at least one source via and the at least one gate via, respectively; and The plurality of semiconductor devices are bonded to the interconnect layer, wherein a surface area of ​​the interconnect layer is substantially equal to a surface area of ​​a footprint defined by the plurality of semiconductor devices. Technical Solution 17. The method according to Technical Solution 16 further includes: filling the at least one source via and the at least one gate via with at least one metallized via; and At least one common source pad and a gate bridge are deposited over the at least one gate through-hole via. Technical Solution 18. The method according to Technical Solution 17 further includes: stacking an additional interconnect layer over the first interconnect layer; forming at least one source via and at least one gate via in the additional interconnect layer; and The at least one source via and the at least one gate via, respectively, defined in the additional interconnect layer are filled with at least one second metallization through-hole. Technical Solution 19. The method according to Technical Solution 18 also includes depositing a package contact pad and a package gate pad on the at least one source through-hole passage and the at least one gate through-hole passage respectively defined in the additional interconnect layer. Technical solution 20. The method according to technical solution 16 further includes: depositing a sputtered layer stacked over bottom surfaces of the plurality of semiconductor devices to form a common drain connector; and A conductive plate is applied over the bottom surface of the sputtered layer.

Claims

1. A multi-chip semiconductor package, comprising: an interconnect layer having an upper surface and a bottom surface, wherein the interconnect layer comprises a dielectric material; at least one common source pad disposed on said upper surface of said interconnect layer; at least one common gate pad disposed on said upper surface of said interconnect layer; as well as a plurality of semiconductor devices, each of the plurality of semiconductor devices comprising a gate pad and at least one source pad bonded to the interconnect layer, wherein the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and wherein the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to each other in parallel. 2 . The multi-chip semiconductor package of claim 1 , further comprising an adhesive layer disposed on the bottom surface of the interconnect layer.

3. The multi-chip semiconductor package of claim 1 , further comprising a plurality of gate contacts disposed on the interconnect layer and electrically connected to the common gate pad via trace connections, wherein each gate pad of each semiconductor device of the plurality of semiconductor devices is connected to an associated gate contact of the plurality of gate contacts. 4 . The multi-chip semiconductor package according to claim 3 , wherein the plurality of gate contacts are equidistant from the common gate pad. 5 . The multi-chip semiconductor package of claim 3 , wherein the gate trace connections have equal resistivity values. 6 . The multi-chip semiconductor package of claim 5 , wherein at least one of the trace connections comprises one of a surface mount resistor and a thin film resistor. 7 . The multi-chip semiconductor package of claim 3 , wherein the common gate pad and the at least one common source pad are configured to be electrically connected to an external power electronic circuit such that the POL-RDL package operates as a single processing unit. 8 . The multi-chip semiconductor package of claim 7 , further comprising a Kelvin contact electrically connected to the at least one common source pad to facilitate connecting the at least one common source pad to the external power electronic circuit.

9. The multi-chip semiconductor package according to claim 1, further comprising: an additional interconnect layer disposed above the interconnect layer; a package gate pad disposed on the additional interconnect layer and electrically connected to the common gate pad of the interconnect layer; as well as At least one package source pad disposed on the additional interconnect layer and electrically connected to the at least one common source pad of the interconnect layer.

10. The multi-chip semiconductor package of claim 9, wherein the package gate pad is electrically connected to a gate attach pad through a trace connection, the gate attach pad being connected to the common gate pad of the interconnect layer.

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