Semiconductor structure and method of forming the same

Abstract

Embodiments of the present specification provide a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate comprising a plurality of chip regions and a scribe lane for separating the chip regions, wherein a groove structure is formed on the scribe lane; and a test structure adapted to perform electrical performance testing on the chip regions, the test structure comprising a first test portion and a second test portion, wherein the first test portion is embedded in the groove structure, and the second test portion is located above the first test portion. With the above scheme, the test structure can be prevented from peeling off the scribe lane, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This specification relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Currently, semiconductor structures are becoming smaller and smaller, and their manufacturing processes are becoming more and more complex. In order to ensure the reliability of the performance of semiconductor structures, it is usually necessary to design test structures within the semiconductor structures to test their performance.

[0003] In existing technologies, test structures are typically laid directly on the dicing track. However, when using a dicing wheel to dic the semiconductor structure, the impact of the dicing wheel and the scouring effect of water make it easy for the test structure to peel off the dicing track, leading to packaging abnormalities in the semiconductor structure. Summary of the Invention

[0004] This specification provides a semiconductor structure and a method for forming the same, which can avoid stripping dicing traces from the test structure and improve the performance of the semiconductor structure.

[0005] To address the above problems, embodiments of this specification provide a semiconductor structure, including:

[0006] The substrate includes multiple chip regions and scribe lines for separating the chip regions, wherein groove structures are formed on the scribe lines;

[0007] A test structure is provided for performing electrical performance tests on the chip region. The test structure includes a first test section and a second test section, wherein the first test section is embedded in the groove structure and the second test section is located on top of the first test section.

[0008] Optionally, the cross-section of the groove structure is trapezoidal.

[0009] Optionally, the second test section is a cubic structure.

[0010] Optionally, the first test section and the second test section are integrally formed.

[0011] Optionally, the test structure is made of metallic material.

[0012] Optionally, the metallic material includes any one of the following:

[0013] Aluminum, aluminum-copper, titanium-tungsten.

[0014] Accordingly, embodiments of this specification also provide a method for forming a semiconductor structure, including:

[0015] Provide a base;

[0016] Multiple chip regions and scribe lines for separating each chip region are formed on the substrate;

[0017] A groove structure is formed on the dicing channel;

[0018] A test structure is formed on the groove structure, which is suitable for performing electrical performance tests on the chip area. The test structure includes a first test section and a second test section, wherein the first test section is embedded in the groove structure and the second test section is located on top of the first test section.

[0019] Optionally, the cross-section of the groove structure is trapezoidal.

[0020] Optionally, the test structure is made of metallic material.

[0021] Optionally, the groove structure can be formed on the dicing track using a photolithography process.

[0022] Optionally, the test structure can be formed on the groove structure using a physical vapor deposition process.

[0023] Optionally, the physical vapor deposition process includes a magnetron sputtering process.

[0024] Optionally, forming a test structure on the groove structure specifically includes:

[0025] A preset shaped mask is provided and placed on the groove structure, wherein the shape of the second test part is the preset shape of the mask;

[0026] Based on the mask, a first test section and a second test section are formed, wherein the first test section and the second test section are integrally formed.

[0027] Compared with the prior art, the technical solutions of the embodiments in this specification have the following advantages:

[0028] The semiconductor structure provided in this specification includes a substrate and a test structure. The substrate includes multiple chip regions and scribe lines for separating the chip regions. A groove structure is formed on the scribe lines. The test structure includes a first test section and a second test section. The first test section is embedded in the groove structure, and the second test section is located above the first test section. Because the first test section is embedded in the groove structure, the test structure has a stronger bond with the scribe lines. When the semiconductor structure is diced using a dicing wheel, the possibility of the test structure being peeled off from the scribe lines can be reduced, thereby avoiding any impact on the subsequent packaging process of the semiconductor structure and improving the performance of the semiconductor structure.

[0029] Furthermore, by setting the cross-section of the groove structure to a trapezoidal structure, the test structure can be tightly embedded within it, so that the test structure will not peel off from the groove structure under the action of a large external force.

[0030] Furthermore, since the first test section and the second test section are integrally formed, the process flow can be simplified, and the bonding force between the entire test structure and the dicing channel can be enhanced, preventing the test structure from peeling off from the dicing channel.

[0031] In the semiconductor structure formation method provided in the embodiments of this specification, multiple chip regions and scribe lines for separating each chip region are formed on the substrate. A groove structure is formed on the scribe lines, and a test structure is formed on the groove structure. The test structure includes a first test part and a second test part, wherein the first test part is embedded in the groove structure, and the second test part is located above the first test part. Since the first test part is embedded in the groove structure, the test structure has a stronger bonding force with the scribe lines. When the semiconductor structure is diced using a dicing wheel, the possibility of the test structure being peeled off from the scribe lines can be reduced, thereby avoiding the impact on the subsequent packaging process of the semiconductor structure and improving the performance of the semiconductor structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0033] Figure 1 This diagram illustrates a semiconductor structure in the prior art.

[0034] Figure 2 It shows Figure 1 The image shown is a top view of a semiconductor structure in the prior art;

[0035] Figure 3 A schematic diagram of a semiconductor structure in an embodiment of this specification is shown;

[0036] Figures 4 to 8 The following is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method according to an embodiment of this specification;

[0037] Figure 9 A cross-sectional schematic diagram of another groove structure in an embodiment of this specification is shown;

[0038] Figure 10 A cross-sectional schematic diagram of another test structure in an embodiment of this specification is shown;

[0039] Figure 11 A cross-sectional schematic diagram of yet another groove structure in an embodiment of this specification is shown;

[0040] Figure 12 A cross-sectional schematic diagram of another test structure in an embodiment of this specification is shown. Detailed Implementation

[0041] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0042] Spatial relation terms, such as "located above," can be used here to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of devices in use and operation.

[0043] It is understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0044] As described in the background section, current semiconductor test structures are typically laid directly on the dicing track. When using a cutting wheel to dice the semiconductor structure, the impact of the cutting wheel and the scouring effect of water make it easy for the test structure to peel off from the dicing track, leading to packaging abnormalities in the semiconductor structure. This paper analyzes the reasons for poor semiconductor structure performance using a schematic diagram of a semiconductor structure.

[0045] Reference Figure 1 and Figure 2 ,in Figure 1 This diagram illustrates a semiconductor structure in the prior art. Figure 2 It shows Figure 1 The diagram shows a top view of a semiconductor structure in the prior art, the semiconductor structure comprising: a substrate including a plurality of chip regions 1 and scribe lines 2 for separating the chip regions; and a test structure 3 laid flat on the scribe lines 2.

[0046] In the aforementioned semiconductor structure, the test structure 3 is directly laid flat on the scribe line 2. The bonding force between the test structure 3 and the scribe line 2 is relatively weak. Therefore, when the semiconductor structure is diced using a cutting wheel, the test structure 3 may peel off from the scribe line 2 and fall onto the chip area 1, affecting the packaging of the semiconductor structure. For example, if the test structure 3 falls onto the chip surface, it may hit the peeled test structure 3 during chip packaging wire bonding, leading to poor soldering. The peeled test structure 3 may also adhere to the leads during device use, causing short circuits and damage to the device. All of these situations can lead to poor semiconductor structure performance.

[0047] To solve the above problems, the prior art usually removes the test structure 3 to prevent the dicing track 2 from being peeled off when the semiconductor structure is diced using a cutting wheel.

[0048] The existing method for removing the test structure 3 mainly involves laser grooving. First, a high-energy laser is used to ablate a layer on the surface of the test structure 3, which is then removed. Next, a cutting wheel is used to dice the semiconductor structure. However, laser cutting is costly, and the addition of the test structure 3 removal step increases the total production time, which is detrimental to manufacturing.

[0049] To address the aforementioned issues, the semiconductor structure provided in this specification includes a substrate and a test structure. The substrate includes multiple chip regions and scribe lines for separating these regions. A groove structure is formed on the scribe lines. The test structure includes a first test section and a second test section. The first test section is embedded within the groove structure, and the second test section is located above the first test section. Because the first test section is embedded within the groove structure, the test structure has a stronger bond with the scribe lines. When the semiconductor structure is diced using a dicing wheel, the possibility of the test structure peeling off from the scribe lines is reduced, thereby avoiding any impact on the subsequent packaging process of the semiconductor structure and improving its performance.

[0050] To enable those skilled in the art to better understand and implement the embodiments of this specification, the embodiments of this specification will be described in detail below with reference to the accompanying drawings.

[0051] First, this specification provides a semiconductor structure through its embodiments, referring to... Figure 3The diagram shows a schematic of a semiconductor structure, which includes: a substrate comprising a plurality of chip regions 10 and scribe lines 20 for separating the chip regions, wherein a groove structure is formed on the scribe lines 20; and a test structure 30 adapted to perform electrical performance testing on the chip regions 10, wherein the test structure 30 includes a first test section 31 and a second test section 32, wherein the first test section 31 is embedded in the groove structure and the second test section 32 is located on the first test section 31.

[0052] The substrate provides the basis for the process operation of semiconductor structure formation.

[0053] In the embodiments described in this specification, the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0054] In the embodiments described in this specification, the chip region 10 is the region where a semiconductor chip is formed.

[0055] In the embodiments described in this specification, the cross-section of the groove structure is trapezoidal. The trapezoidal cross-section of the groove structure allows the test structure 30 to be tightly embedded within it, thus preventing the test structure 30 from detaching from the groove structure even under significant external forces.

[0056] In the embodiments described in this specification, the second test unit 32 has a cubic structure. It should be noted that the embodiments described in this specification do not limit the specific structure of the second test unit 32.

[0057] In the embodiments described in this specification, the first test part 31 and the second test part 32 are integrally formed. Since the first test part 31 is embedded in the groove structure, and the second test part 32 is located on top of the first test part 31, by setting the first test part 31 and the second test part 32 as an integrally formed structure, the bonding force between the entire test structure 30 and the dicing channel can be enhanced, preventing the test structure 30 from peeling off from the dicing channel. In addition, the process flow can be simplified.

[0058] In the embodiments described in this specification, the test structure 30 is made of a metallic material. The use of a metallic material is suitable for testing the electrical performance of the chip region 10.

[0059] As a specific example, the metallic material can be aluminum. In other embodiments, the metallic material can also be one or more of aluminum, copper, titanium, and tungsten.

[0060] It should be noted that the embodiments in this specification do not limit the specific materials of the test structure 30, as long as the materials used are suitable for electrical performance testing of the chip region 10.

[0061] By employing the above-described semiconductor structure and utilizing the groove structure on the dicing track 20, the bonding force between the first test section 31, the second test section 32, and the dicing track 20 is enhanced. When the semiconductor structure is diced using a cutting wheel, the possibility of the test structure being peeled off from the dicing track can be reduced, thereby avoiding any impact on the subsequent packaging process of the semiconductor structure and improving the performance of the semiconductor structure.

[0062] Accordingly, embodiments of this specification also provide a method for forming a semiconductor structure. Figures 4 to 8 This is a schematic diagram of the structure corresponding to each step in an embodiment of a semiconductor structure formation method of the present invention.

[0063] Reference Figure 4 A substrate is provided on which a plurality of chip regions 100 and scribe lines 200 for separating the chip regions are formed.

[0064] The substrate provides the basis for the process operation of semiconductor structure formation.

[0065] In the embodiments described in this specification, the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0066] In the embodiments described in this specification, the chip region 100 is the region where a semiconductor chip is formed.

[0067] Reference Figure 5 A groove structure H is formed on the dicing channel 200.

[0068] Reference Figures 6 to 7 A test structure 300 is formed on the groove structure H, which is suitable for performing electrical performance tests on the chip region 100. The test structure 300 includes a first test part 301 and a second test part 302, wherein the first test part 301 is embedded in the groove structure H, and the second test part 302 is located on the first test part 301.

[0069] In this embodiment of the specification, the step of forming the test structure 300 on the groove structure H may include:

[0070] A preset-shape mask 400 is provided and placed on the groove structure H, wherein the shape of the second test part 302 is the preset shape of the mask.

[0071] Based on the mask 400, a first test section 301 and a second test section 302 are formed, wherein the first test section 301 and the second test section 302 are integrally formed.

[0072] Reference Figure 8 Remove the mask 400 to form the test structure 300.

[0073] In the above embodiment, the test structure 300 is formed on the groove structure H. Since the first test part 301 is embedded in the groove structure H, the test structure 300 has a stronger bonding force with the dicing track 200. When the semiconductor structure is diced using a cutting wheel, the possibility of the test structure 300 peeling off from the dicing track 200 can be reduced, thereby avoiding the impact on the subsequent packaging process of the semiconductor structure and improving the performance of the semiconductor structure.

[0074] In the embodiments of this specification, in order to improve the smoothness of the test structure surface, a planarization process is performed on the test structure after its formation. As a specific example, a chemical mechanical polishing process is used to planarize the test structure.

[0075] It is understood that the embodiments in this specification do not limit the specific formation of the first test part 301 and the second test part 302. The first test part 301 and the second test part 302 may not be integrally formed, as long as the second test part 302 can be tightly combined with the first test part 301.

[0076] As a specific example, continue to refer to Figure 5 The cross-section of the groove structure H can be trapezoidal. The trapezoidal cross-section of the groove structure H allows the test structure 300 to be tightly embedded within it, thus preventing the test structure 300 from detaching from the groove structure H even under significant external force.

[0077] It is understood that the embodiments in this specification do not limit the specific structure of the groove structure H, as long as it enables the test structure to have a stronger bonding force with the scribe line. For example, refer to... Figure 9 and Figure 10 ,in Figure 9 A cross-sectional schematic diagram of another groove structure is shown. Figure 10 A schematic cross-sectional view of another test structure is shown, wherein the cross-section of the groove structure H can be rectangular; see reference. Figure 11 and Figure 12,in Figure 11 A cross-sectional schematic diagram of yet another groove structure is shown. Figure 12 A schematic cross-sectional view of another test structure is shown, wherein the cross-section of the sidewall of the groove structure H can also be a multi-triangular structure. Those skilled in the art will understand that it is acceptable as long as the maximum width of the cross-section of the groove structure H is greater than the width of its opening on the scribe line surface.

[0078] In the embodiments described in this specification, the test structure 300 is made of a metallic material. The use of a metallic material is suitable for testing the electrical performance of the chip region 100.

[0079] As a specific example, the metallic material can be aluminum. In other embodiments, the metallic material can also be one or more of aluminum, copper, titanium, and tungsten.

[0080] It should be noted that the embodiments in this specification do not limit the specific materials of the test structure 300, as long as the materials used are suitable for electrical performance testing of the chip region 100.

[0081] In the embodiments described in this specification, the groove structure H is formed on the scribe line 200 using a photolithography process. The groove structure formed by the photolithography process has a good morphology, which is beneficial for subsequent processes.

[0082] In the embodiments of this specification, the test structure 300 is formed on the groove structure H using a physical vapor deposition process.

[0083] As a specific example, the first test section 301 and the second test section 302 are formed in one step using a magnetron sputtering process. Magnetron sputtering offers a fast deposition rate and minimal substrate temperature rise, resulting in less damage to the substrate during the formation of the test structure 300. Furthermore, the test structure 300 formed using magnetron sputtering exhibits good uniformity, which is beneficial for subsequent electrical performance testing.

[0084] It is understood that the features described in the various embodiments or claims of this specification can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this invention. In particular, the features described in the various embodiments or claims of this specification can be combined or combined in various ways without departing from the spirit and guidance of this invention. All such combinations or combinations fall within the scope of this invention.

[0085] While the embodiments disclosed in this specification are as described above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple chip regions and scribe lines for separating the chip regions, wherein groove structures are formed on the scribe lines; A test structure is provided for performing electrical performance tests on the chip region. The test structure includes a first test section and a second test section, wherein the first test section is embedded in the groove structure and the second test section is located on top of the first test section.

2. The structure according to claim 1, characterized in that, The cross-section of the groove structure is trapezoidal.

3. The structure according to claim 2, characterized in that, The second test section has a cubic structure.

4. The structure according to claim 3, characterized in that, The first test section and the second test section are integrally formed structures.

5. The structure according to claim 4, characterized in that, The test structure is made of metallic material.

6. The structure according to claim 5, characterized in that, The metallic material includes any one of the following: Aluminum, aluminum-copper, titanium-tungsten.

7. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Multiple chip regions and scribe lines for separating each chip region are formed on the substrate; A groove structure is formed on the dicing channel; A test structure is formed on the groove structure, which is suitable for performing electrical performance tests on the chip area. The test structure includes a first test section and a second test section, wherein the first test section is embedded in the groove structure and the second test section is located on top of the first test section.

8. The method according to claim 7, characterized in that, The cross-section of the groove structure is trapezoidal.

9. The method according to claim 8, characterized in that, The test structure is made of metallic material.

10. The method according to claim 7, characterized in that, The groove structure is formed on the dicing track using photolithography.

11. The method according to claim 7, characterized in that, The test structure was formed on the groove structure using a physical vapor deposition process.

12. The method according to claim 11, characterized in that, The physical vapor deposition process includes magnetron sputtering.

13. The method according to claim 12, characterized in that, The formation of the test structure on the groove structure specifically includes: A preset shaped mask is provided and placed on the groove structure, wherein the shape of the second test part is the preset shape of the mask; Based on the mask, a first test section and a second test section are formed, wherein the first test section and the second test section are integrally formed.

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