Semiconductor test structure and test method thereof

Abstract

The present invention provides a semiconductor test structure and a test method thereof. By simulating the layout structure of a static random access memory (SRAM), the present invention designs a test unit comprising a first group of transistors and a second group of transistors. A first spacing is provided between the active region of the transistor connected to a shared contact structure and the gate. The first spacing of the plurality of test units is designed to gradually increase. Electrical tests are performed on the first and second transistors in the test units to obtain process window parameters for the first spacing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor test structure and a test method thereof. Background Art

[0002] As the process node decreases, the leakage of transistors (MOS) gradually increases. Among them, static random access memory (SRAM) has three main types of leakage during the process development stage: metal diffusion (such as metal tungsten (W), metal silicide (NiSi), etc.), active area dislocation (AA Dislocation), and structural structure (CT) over-etching resulting in deterioration of the isolation effect of the shallow trench isolation (STI) structure. Figure 1 As shown, at 65nm and below process nodes, the SRAM PMOS layout has a shared contact structure (SCT) 11, through which the gate polysilicon (Poly) 12 and the drain active area (AA) 13 are respectively connected. Figure 2 As shown, during the process, due to the problem of alignment accuracy (overlay) between the gate polysilicon 22 and the active area 23, a certain gap 24 exists between the active area 23 and the gate polysilicon 22 in the X direction. Figure 3 As shown, the gap 34 between the active area 33 and the gate polysilicon 32 may cause over-etching of the shared contact structure 31, and part of the shared contact structure 31 falls within the shallow trench isolation structure 35. The diffusion of metal tungsten (W) in the shared contact structure 31 increases the risk of leakage.

[0003] Therefore, how to monitor the alignment accuracy process window and avoid over-etching of the shared contact structure, which increases the risk of leakage, is a problem that needs to be solved at present. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to monitor the alignment accuracy process window to avoid the increased risk of leakage caused by over-etching of the shared contact structure, and to provide a semiconductor test structure and a test method thereof.

[0005] In order to solve the above problems, the present invention provides a semiconductor test structure, including multiple test units, each of the test units includes a substrate and a first group of transistors and a second group of transistors formed on the substrate, the substrate includes a first region and a second region arranged in parallel along a first direction; the first group of transistors includes a plurality of first transistors, the first transistors include: a first active region and a first gate, the first active region is located in the first region, a plurality of the first active regions extend along a second direction and are arranged at intervals, the first gate extends from the first region to the second region along the first direction and partially overlaps with the first active region, wherein the second direction forms an angle with the first direction; the second group of transistors includes a plurality of second transistors, the second transistors include: a second active region and a second gate, the second active region is located in the second region, a plurality of the second active regions extend along the second direction and are arranged at intervals, and the second active region and the first active region are at a second angle. The two transistors are staggered in the direction, the second gate extends from the second area to the first area along the first direction and partially overlaps with the second active area; in the second direction, the edge of the first active area and the edge of the adjacent second gate have a first spacing, and the edge of the second active area and the edge of the adjacent first gate have the first spacing; the first active area and the adjacent second gate are electrically connected to a first shared contact structure, and a plurality of the first shared contact structures are connected in parallel as the source lead-in terminal of the first transistor or the gate lead-in terminal of the second transistor; the second active area and the adjacent first gate are electrically connected to a second shared contact structure, and a plurality of the second shared contact structures are connected in parallel as the source lead-in terminal of the second transistor or the gate lead-in terminal of the first transistor; the first spacing of the plurality of test units gradually increases, and the process window parameters of the first spacing are obtained by performing electrical tests on the first transistor and the second transistor in the plurality of test units.

[0006] In order to solve the above problems, the present invention provides a semiconductor testing method, comprising the following steps: providing a semiconductor test structure, wherein the semiconductor test structure adopts the semiconductor test structure described in the present invention; performing electrical tests on the first transistor and the second transistor in each of the test units in the semiconductor test structure to obtain electrical test parameters; and statistically analyzing the first spacing corresponding to the test units whose electrical test parameters meet process requirements to obtain process window parameters of the first spacing.

[0007] The above technical solution simulates the layout structure of a static random access memory and designs a test unit including a first group of transistors and a second group of transistors. There is a first spacing between the active area and the gate connected to the shared contact structure in the transistor, and the first spacing of multiple test units is designed to gradually increase. By electrically testing the first transistor and the second transistor in the test unit respectively, the process window parameters of the first spacing are obtained.

[0008] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for describing the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0010] Figure 1 The figure is a schematic diagram of the structure of the PMOS layout of the static random access memory in the prior art.

[0011] Figure 2 The present invention is a schematic diagram of a structure in which a gap exists between the active region and the gate in a PMOS layout of a static random access memory in the prior art.

[0012] Figure 3 The figure is a schematic diagram of the structure of over-etching of the shared contact structure of static random access memory in the prior art.

[0013] Figure 4 FIG. 1 is a schematic structural diagram of an embodiment of the semiconductor test structure of the present invention.

[0014] Figure 5 FIG. 1 is a schematic diagram of a semiconductor test structure according to an embodiment of the present invention, in which the first pitch is a positive value.

[0015] Figure 6 FIG. 1 is a schematic diagram showing a semiconductor test structure according to an embodiment of the present invention, in which the first pitch is a negative value.

[0016] Figure 7 FIG. 1 is a structural diagram of an embodiment of a semiconductor testing method according to the present invention. DETAILED DESCRIPTION

[0017] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0018] In order to monitor the alignment accuracy process window and avoid the increased risk of leakage caused by over-etching of the shared contact structure, the present invention is based on the current SRAM design and optimizes and monitors the overlay process window by adjusting the experimental design (DOE) of the SCT area Poly and AA space.

[0019] See also Figures 4 to 6 ,in, Figure 4 FIG. 1 is a schematic structural diagram of an embodiment of a semiconductor test structure according to the present invention. Figure 5 This is a schematic diagram showing a positive first spacing X1 of an embodiment of the semiconductor test structure of the present invention. Figure 6 FIG. 1 is a schematic diagram showing a first spacing X1 of a semiconductor test structure according to an embodiment of the present invention, wherein the first spacing X1 is a negative value. The semiconductor test structure includes a plurality of test units 100, such as Figures 4 to 6 As shown, each of the test units 100 includes a substrate 40 and a first set of transistors 41 and a second set of transistors 42 formed on the substrate 40 . The substrate 40 includes a first region 401 and a second region 402 arranged in parallel along a first direction D1 .

[0020] The first group of transistors 41 includes a plurality of first transistors, each of which includes a first active region 411 and a first gate 412. The first active region 411 is located in the first region 401 and extends along a second direction D2 and is arranged in an interval. The first gate 412 extends along the first direction D1 from the first region 401 to the second region 402 and partially overlaps with the first active region 411. The second direction D2 forms an angle with the first direction D1.

[0021] The second group of transistors 42 includes a plurality of second transistors, each of which includes a second active area 421 and a second gate 422. The second active area 421 is located in the second region 402. The plurality of second active areas 421 extend along a second direction D2 and are arranged at intervals. The second active areas 421 and the first active areas 411 are arranged alternately in the second direction D2. The second gate 422 extends along the first direction D1 from the second region 402 to the first region 401 and partially overlaps with the second active area 421.

[0022] In the second direction D2 , an edge of the first active region 411 and an edge of the adjacent second gate 422 have a first distance X1 , and an edge of the second active region 421 and an edge of the adjacent first gate 412 have the first distance X1 .

[0023] The first active region 411 and the adjacent second gate 422 are electrically connected to a first shared contact structure 413 . A plurality of first shared contact structures 413 are connected in parallel to serve as the source terminal S1 of the first transistor or the gate terminal G2 of the second transistor.

[0024] The second active region 421 and the adjacent first gate 412 are electrically connected to a second shared contact structure 423 . A plurality of second shared contact structures 423 are connected in parallel to serve as the second transistor source terminal S2 or the first transistor gate terminal G1 .

[0025] The first spacing X1 of the plurality of test units is gradually increased, and the process window parameters of the first spacing X1 are obtained by performing electrical tests on the first transistors and the second transistors of the plurality of test units.

[0026] The above technical solution forms a plurality of test units with different first pitches by simulating the layout structure of a static random access memory, and obtains the process window parameters of the first pitch by electrically testing the first transistor and the second transistor in the test unit respectively.

[0027] In some embodiments, the first transistor is a first PMOS, and the first active region 411 is a first PMOS active region; the second transistor is a second PMOS, and the second active region 421 is a second PMOS active region.

[0028] In some embodiments, the first group of transistors 41 and the second group of transistors 42 are coupled to each other.

[0029] The present invention is based on the SRAM PMOS design and forms two mutually coupled groups of PMOS, one of which is a first group of transistors and the other is a second group of transistors. Metal wiring is redistributed to form a multi-finger structure (Mutifinger) PMOS. By testing the leakage of the Mutifinger PMOS, the layout design of the photo process or the first spacing between the active area and the gate is monitored and optimized.

[0030] In some embodiments, the first spacing X1 of one of the test units 100 takes a baseline value, and the first spacing X1 of the other test units 100 takes an offset value of the baseline value.

[0031] To monitor the leakage of the shared contact structure, the first spacing X1 is designed to be added or subtracted based on a reference value. In some embodiments, the reference value is a nm; the offset value of the reference value is [a-5nm, a+5nm].

[0032] In some embodiments, the value of the first spacing X1 includes positive and negative values, such as Figures 5 and 6 In this embodiment, the reference value of the first spacing X1 is 2nm, and the offset values ​​of the reference value are -3nm, -2nm, -1nm, 0nm, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, and 7nm. The process window and layout optimization solution are verified by leakage testing.

[0033] In some embodiments, the test unit 100 further includes: a first contact structure 414 located on the surface of each first active area 411, and multiple first contact structures 414 are connected in parallel to serve as the drain terminal D1 of the first transistor; a second contact structure 424 located on the surface of each second active area 421, and multiple second contact structures 424 are connected in parallel to serve as the drain terminal D1 of the second transistor.

[0034] In some embodiments, the first group of transistors 41 further includes a plurality of third transistors, each of which includes a third active region 415 located in the first region 401 and on a side of the first active region 411 away from the second active region 421. The third active region 415 extends along the second direction D2, and the first gate 412 partially overlaps with the third active region 415. The second group of transistors 42 further includes a plurality of fourth transistors, each of which includes a fourth active region 425 located in the second region 402 and on a side of the second active region 421 away from the first active region 411. The fourth active region 425 extends along the second direction D2, and the second gate 422 partially overlaps with the fourth active region 425.

[0035] In some embodiments, the third transistor is a first NMOS, and the third active region 415 is a first NMOS active region; the fourth transistor is a second NMOS, and the fourth active region 425 is a second NMOS active region.

[0036] In some embodiments, the test unit 100 further includes a first dummy gate 431 and a second dummy gate 432. The first dummy gate 431 is located in the first region 401 and is arranged parallel to the second gate 422 along a first direction D1. The first dummy gate 431 extends along the first direction D1 and partially overlaps with the third active region 415. The second dummy gate 432 is located in the second region 402 and is arranged parallel to the first gate 412 along the first direction D1. The second dummy gate 432 extends along the first direction D1 and partially overlaps with the fourth active region 425. The first dummy gate 431 and the second dummy gate 432 are used to support the membrane structure.

[0037] The first contact structure 414, the second contact structure 424, the third active area 415, the fourth active area 425, the first dummy gate 431, and the second dummy gate 432 are provided in the test unit 100 in order to restore the circuit structure in the SRAM PMOS layout in the test structure as much as possible, avoid test errors caused by process differences, and make the test results more real and effective.

[0038] Based on the same inventive concept, an embodiment of the present invention also provides a semiconductor testing method. Figure 7 , which is a structural diagram of an embodiment of the semiconductor testing method of the present invention. Figure 7 As shown, the semiconductor testing method includes the following steps: step S71, providing a semiconductor test structure, the semiconductor test structure adopts the semiconductor test structure described in the present invention; step S72, performing electrical tests on the first transistor and the second transistor in each of the test units in the semiconductor test structure to obtain electrical test parameters; step S73, counting the first spacing corresponding to the test units whose electrical test parameters meet the process requirements to obtain the process window parameters of the first spacing.

[0039] See also Figure 4 And step S71, providing a semiconductor test structure, wherein the semiconductor test structure adopts the semiconductor test structure as described in section 4 of the present invention.

[0040] See also Figure 4 And in step S72, electrical tests are performed on the first transistor and the second transistor in each of the test units 100 in the semiconductor test structure to obtain electrical test parameters.

[0041] In some embodiments, the electrical test includes performing a leakage test on the first shared contact structure 413 and the second shared contact structure 423 in the test unit 100 to obtain the process window parameters of the first spacing X1.

[0042] In some embodiments, leakage tests can be performed on the four terminals of the first transistor (including the source terminal S1, the gate terminal G1, the drain terminal D1 and the substrate terminal) to obtain the electrical test parameters of the first transistor. And leakage tests can be performed on the four terminals of the second transistor (including the source terminal S2, the gate terminal G2, the drain terminal D2 and the substrate terminal) to obtain the electrical test parameters of the second transistor. Among them, the leakage test on the source terminal S1 / S2 and the gate terminal G1 / G2 is to obtain the process window parameters of the first spacing X1. The leakage test on the drain terminal D1 / D2 is to obtain the process parameters of the contact structure Overlay. Therefore, this structure can not only be used to test the influence of the spacing between the gate and the active area on the leakage, but also can be used to test the influence of the contact structure Overlay on the leakage.

[0043] In some embodiments, the method further includes the following steps: if the difference between the electrical test parameters of the first transistor and the electrical test parameters of the second transistor in the same test unit 100 is less than a preset threshold value, the electrical test parameters are determined to be valid. Since the first transistor and the second transistor have mutually symmetrical structures and their parameters are the same, theoretically, the electrical test parameters of the first transistor and the electrical test parameters of the second transistor should be the same. However, due to actual process errors, one of the two transistors may have a larger offset. Therefore, the electrical test parameters of the first transistor and the second transistor are measured simultaneously and used as a comparison to improve the accuracy of the measurement.

[0044] See also Figure 4 And step S73 , counting the first spacing X1 corresponding to the test units 100 whose electrical test parameters meet process requirements, to obtain process window parameters of the first spacing X1 .

[0045] In some embodiments, the method further includes: sorting the first spacings X1 corresponding to all the test units 100 whose electrical test parameters meet process requirements, and confirming the process window parameter range according to the minimum and maximum values ​​of the first spacings X1.

[0046] The above technical solution forms a plurality of test units with different first pitches by simulating the layout structure of a static random access memory, and obtains the process window parameters of the first pitch by electrically testing the first transistor and the second transistor in the test unit respectively.

[0047] The semiconductor test structure of the present invention can be expanded to the back-end-of-line (BEOL) shared contact structure (ShareVia) to connect lines in different areas. The product can also be expanded to shared contact structures for similar applications such as non-volatile memory (NVM) and dynamic random access memory (DRAM) to solve the leakage problem caused by over-etching of the contact structure due to process variation.

[0048] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0049] Typically, a term can be understood at least in part from its usage in the context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a feature, structure or combination of features in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0050] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0051] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor test structure, characterized in that: The method comprises a plurality of test units, each of the test units comprising a substrate and a first group of transistors and a second group of transistors formed on the substrate, wherein the substrate comprises a first region and a second region arranged in parallel along a first direction; The first group of transistors includes a plurality of first transistors, each of the first transistors including: a first active region and a first gate, wherein the first active region is located in the first region, the plurality of first active regions extend along a second direction and are arranged at intervals, and the first gate extends along the first direction from the first region to the second region and partially overlaps with the first active region, wherein the second direction forms an angle with the first direction; The second group of transistors includes a plurality of second transistors, each of the second transistors including a second active region and a second gate, wherein the second active region is located in the second region, the plurality of second active regions extend along a second direction and are arranged at intervals, and the second active regions and the first active regions are arranged alternately in the second direction, and the second gate extends along the first direction from the second region to the first region and partially overlaps with the second active region; In the second direction, an edge of the first active region and an edge of the adjacent second gate have a first distance therebetween, and an edge of the second active region and an edge of the adjacent first gate have the first distance therebetween; The first active region and the adjacent second gate are electrically connected to a first shared contact structure, and a plurality of the first shared contact structures are connected in parallel to serve as the source terminal of the first transistor or the gate terminal of the second transistor; The second active region and the adjacent first gate are electrically connected to a second shared contact structure, and a plurality of the second shared contact structures are connected in parallel to serve as the source terminal of the second transistor or the gate terminal of the first transistor; The first spacing of the plurality of test units is gradually increased, and the process window parameters of the first spacing are obtained by performing electrical tests on the first transistors and the second transistors in the plurality of test units.

2. The semiconductor test structure according to claim 1, wherein: The first spacing of one of the test units is a reference value, and the first spacings of the other test units are offset values ​​of the reference value.

3. The semiconductor test structure according to claim 2, wherein: The reference value is a nm; the offset value of the reference value is in the range of [a-5nm, a+5nm].

4. The semiconductor test structure according to claim 1, wherein: The value of the first interval includes positive and negative values.

5. The semiconductor test structure according to claim 1, wherein: The first transistor is a first PMOS, and the first active area is a first PMOS active area; the second transistor is a second PMOS, and the second active area is a second PMOS active area.

6. The semiconductor test structure according to claim 1, wherein: The testing unit further includes: a first contact structure located on a surface of each of the first active regions, wherein a plurality of the first contact structures are connected in parallel to serve as a drain terminal of the first transistor; A second contact structure is located on the surface of each second active region, and a plurality of second contact structures are connected in parallel to serve as drain terminals of the second transistor.

7. The semiconductor test structure according to claim 1, wherein: The first group of transistors further includes a plurality of third transistors, each of the third transistors including a third active region located in the first region and on a side of the first active region away from the second active region, the third active region extending along the second direction, and the first gate partially overlapping the third active region; The second group of transistors also includes multiple fourth transistors, each of which includes a fourth active region located in the second region and on a side of the second active region away from the first active region. The fourth active region extends along the second direction, and the second gate also partially overlaps with the fourth active region.

8. The semiconductor test structure according to claim 7, wherein: The third transistor is a first NMOS, and the third active region is the first NMOS active region; the fourth transistor is a second NMOS, and the fourth active region is the second NMOS active region.

9. The semiconductor test structure according to claim 7, wherein: The testing unit further includes: a first dummy gate located in the first region and arranged in parallel with the second gate along a first direction, the first dummy gate extending along the first direction and partially overlapping with the third active region; The second dummy gate is located in the second region and arranged in parallel with the first gate along the first direction. The second dummy gate extends along the first direction and partially overlaps with the fourth active region.

10. A semiconductor testing method, characterized in that: The steps include: Providing a semiconductor test structure, wherein the semiconductor test structure adopts the semiconductor test structure according to any one of claims 1 to 9; Performing electrical tests on the first transistor and the second transistor in each of the test units in the semiconductor test structure to obtain electrical test parameters; The first spacing corresponding to the test units whose electrical test parameters meet process requirements is counted to obtain a process window parameter of the first spacing.

11. The method according to claim 10, characterized in that The method further includes the following step: if a difference between the electrical test parameter of the first transistor and the electrical test parameter of the second transistor in the same test unit is less than a preset threshold, determining that the electrical test parameter is valid.

12. The method according to claim 10, characterized in that The method further includes: sorting the first spacings corresponding to all the test units whose electrical test parameters meet process requirements, and confirming the process window parameter range according to the minimum and maximum values ​​of the first spacings.

13. The method according to claim 10, characterized in that The electrical test includes performing a leakage test on the first shared contact structure and the second shared contact structure in the test unit.

Images