Test Key test structure
By designing a new Test Key test structure, including an S-shaped active area and polysilicon layer, the problem of the existing technology being unable to reflect the true situation of the SRAM contact hole is solved, accurate monitoring of the contact hole resistance is achieved, and the chip yield is improved.
Patent Information
- Application Number
- CN202411622765.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2044-11-13
AI Technical Summary
The existing Test Key test structure cannot reflect the actual situation of the contact holes in the SRAM area, resulting in the inability to effectively monitor contact hole anomalies during process fluctuations, affecting chip yield.
A new Test Key test structure is designed, which includes an active area, contact holes and gate structure. By adding a polysilicon layer in the test structure, the contact hole resistance of the SRAM area is reflected. It includes an S-shaped active area and multiple gate structures, and the connection method is a contact hole connected by a metal layer.
Effectively monitor the contact hole resistance in the SRAM area, improve chip yield, and ensure test accuracy and consistency by considering the impact of polysilicon and sidewalls on the through hole.
Smart Images
Figure CN119495683B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a Test Key test structure. Background Art
[0002] Yield loss in 28nm HV chips is primarily related to SRAM (static random access memory), primarily due to abnormal contact hole (CT) resistance in the SRAM region. These abnormalities include CT open and NiSi abnormalities (NiSi formation within the contact hole). Furthermore, WAT CT RC cannot reflect the true condition of the SRAM contact holes. TEM slices reveal small spacing between polysilicon in the SRAM region, which can easily lead to process weaknesses.
[0003] The Test Key test structure is a specific test structure used for wafer acceptance testing (WAT). It is usually placed in the scribe groove and is tested by piercing the test pad with a test probe. This test structure is designed to save chip design area and cost, ensure test consistency and hardware reuse. The existing test key for testing contact holes RC is mainly divided into two test structures: Via Chain and Kelvin (such as Figure 1 and Figure 2 However, neither test structure defines polysilicon (Poly), and neither reflects the actual contact hole conditions in the SRAM area. Furthermore, process fluctuations during contact hole preparation can easily cause abnormal SRAM contact holes, preventing normal WAT from being shipped. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a Test Key test structure to solve the problem that the prior test structure cannot reflect the actual situation of the contact hole.
[0005] To achieve the above-mentioned and other related purposes, the present invention provides a Test Key test structure, which includes: an active area, a contact hole and a gate structure.
[0006] The active area includes a plurality of first regions extending in a first direction and spaced apart in a second direction, and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S-shape;
[0007] a plurality of gate structures arranged at intervals, extending along the second direction and overlapping with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure, and an intermediate gate structure located therebetween;
[0008] The contact hole is formed in the active area, and at least two intermediate contact holes arranged at intervals along the second direction are formed in each first area between two adjacent intermediate gate structures, namely a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on the side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on the side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact hole, the first intermediate contact hole and the second end contact hole are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two.
[0009] Optionally, the first end contact hole, the second end contact hole, the first middle contact hole, and the second middle contact hole are connected through a metal layer.
[0010] Optionally, when the first end contact hole, the first middle contact hole and the second end contact hole are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact hole, from left to right, and then from right to left, until they are connected to the second end contact hole.
[0011] Optionally, a nickel silicide layer is formed at the bottom of the contact hole.
[0012] Optionally, the number of the gate structures is 5.
[0013] Optionally, the number of the first areas is 5, and the number of the second areas is 4.
[0014] Optionally, the gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.
[0015] Optionally, the Test Key test structure is formed in a test key area to reflect the contact hole resistance of the SRAM device area.
[0016] Optionally, applicable technology nodes include 28nm.
[0017] As described above, the Test Key test structure of the present invention, by adding a polysilicon layer to the test structure, takes into account the impact of polysilicon and sidewalls on the through hole during WAT testing, thereby achieving the purpose of monitoring the contact hole resistance of the SRAM area. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Shown is a schematic diagram of the existing CT Via Chain test structure.
[0019] Figure 2 Shown is a schematic diagram of the existing CT Kelvin test structure.
[0020] Figure 3 Shown is a schematic diagram of the Test Key test structure of the present invention. DETAILED DESCRIPTION
[0021] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.
[0022] See also Figure 3 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.
[0023] This embodiment provides a Test Key test structure, which includes: an active area, a contact hole and a gate structure.
[0024] The active area includes a plurality of first regions extending in a first direction and spaced apart in a second direction, and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S-shape;
[0025] a plurality of gate structures arranged at intervals, extending along the second direction and overlapping with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure, and an intermediate gate structure located therebetween;
[0026] The contact hole is formed in the active area, and at least two intermediate contact holes arranged at intervals along the second direction are formed in each first area between two adjacent intermediate gate structures, namely a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on the side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on the side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact hole, the first intermediate contact hole and the second end contact hole are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two.
[0027] In this embodiment, the test structure can be formed simultaneously during the process of forming the NMOS device and the PMOS device in the SRAM device region. In this embodiment, X represents the first direction, and Y represents the second direction.
[0028] Specifically, the first end contact hole, the second end contact hole, the first middle contact hole, and the second middle contact hole are connected through a metal layer.
[0029] Specifically, when the first end contact hole, the first middle contact hole and the second end contact hole are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact hole, from left to right, and then from right to left, until they are connected to the second end contact hole.
[0030] Specifically, a nickel silicide layer is formed at the bottom of the contact hole.
[0031] Specifically, the number of the gate structures is 5.
[0032] Specifically, the number of the first areas is 5, and the number of the second areas is 4.
[0033] Specifically, the gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.
[0034] Specifically, the Test Key test structure is formed in the test key area and is used to reflect the contact hole resistance of the SRAM device area.
[0035] Specifically, applicable technology nodes include 28nm.
[0036] In summary, the Test Key structure of the present invention, by adding a polysilicon layer to the test structure, takes into account the impact of polysilicon and sidewall spacers on the via during WAT testing, achieving the goal of monitoring the contact resistance of the SRAM region. Therefore, the present invention effectively overcomes the shortcomings of the existing technology and has high industrial application value.
[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A Test Key test structure, characterized in that: The structure includes: an active area, a contact hole and a gate structure, The active area includes a plurality of first regions extending in a first direction and spaced apart in a second direction, and a plurality of second regions extending in the second direction, wherein the first regions are connected to the second regions so that the active area is distributed in an S-shape; a plurality of gate structures arranged at intervals, extending along the second direction and overlapping with the active area, wherein the gate structures include a first edge gate structure, a second edge gate structure, and an intermediate gate structure located therebetween; The contact holes are formed in the active area, and at least two intermediate contact holes are formed in each first area between two adjacent intermediate gate structures and are arranged at intervals along the second direction, namely a first intermediate contact hole and a second intermediate contact hole. A first end contact hole is formed on a side of the first edge gate structure away from the intermediate gate structure, and a second end contact hole is formed on a side of the second edge gate structure away from the intermediate gate structure, wherein the first end contact hole is located at the starting end of the S-shaped active area, and the second end contact hole is located at the end of the S-shaped active area, and the first end contact holes, the first intermediate contact holes, and the second end contact holes are connected in groups of two in sequence, and the second intermediate contact holes on the same first area are connected in groups of two; When the first end contact hole, the first middle contact hole and the second end contact hole are connected in groups of two in sequence, they are connected in groups of two starting from the first end contact hole, from left to right, and then from right to left, until they are connected to the second end contact hole; The gate structure includes polysilicon and sidewalls formed on both sides of the polysilicon.
2. The Test Key test structure according to claim 1, characterized in that: The first end contact hole, the second end contact hole, the first middle contact hole, and the second middle contact hole are connected through a metal layer.
3. The Test Key test structure according to claim 1, characterized in that: A nickel silicide layer is formed at the bottom of the contact hole.
4. The Test Key test structure according to claim 1, characterized in that: The number of the gate structures is 5.
5. The Test Key test structure according to claim 1, characterized in that: The number of the first regions is 5, and the number of the second regions is 4.
6. The Test Key test structure according to claim 1, characterized in that: The Test Key test structure is formed in the test key area and is used to reflect the contact hole resistance of the SRAM device area.
7. The Test Key test structure according to claim 1, characterized in that: Applicable technology nodes include 28nm.