Frequency compensation method for constant on-time circuit in chip

Abstract

The invention belongs to the field of chips, and provides a constant on-time circuit frequency compensation method in a chip, the method is applied to a frequency generation circuit of the chip, and the method comprises the following steps: based on a buffer, adding an input voltage or an output voltage of the chip to a resistor, and generating a compensation current on the resistor; the compensating circuit is used for mirroring the compensating current and supplying the obtained mirrored current to a comparator for regulating and controlling the current delay so as to regulate and control the output delay of the comparator, and the comparator is used for comparing the ramp signal with the output voltage and generating a control signal for regulating and controlling the frequency of the frequency generating circuit; the resistance is regulated and controlled, so that the output delay is matched with the output frequency of the chip; according to the invention, the problem that the internal frequency of the chip changes along with VIN or VOUT in the prior art can be solved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a frequency compensation method for a constant on-time circuit inside a chip. Background Art

[0002] The frequency inside the chip is determined by the on-time circuit, which generates a constant on-time Ton. The operating frequency fsw is obtained by the volt-second balance principle of the inductor. The chip detects VOUT (output voltage). When Vout is lower than the target value, PWM_L becomes low and the capacitor C starts to charge. Figure 1 As shown, when the currents I1 and I2 are the same, the voltage on the upper end of R1 is equal to Vramp, generating I2, and the mirror image of I2 generates I3. The sum of I3 and I4 gives I5 to charge the capacitor C. Therefore, TON is determined by the current generated by Vsw / 2Rm to charge the capacitor C to reach VOUT, which can be expressed as When Vramp is greater than VOUT, OSHOT_B becomes low, the voltage on capacitor C is cleared, and the chip continues to detect VOUT. When Vout is lower than the target value, the next cycle begins. Because capacitor C is charged only when Vsw is high, Vsw = Vin (VIN, input voltage). The frequency inside the chip is only determined by the resistance Rm and capacitor C of the on-time circuit. The frequency can be expressed as

[0003] The defects of the prior art are as follows:

[0004] 1. The frequency changes significantly with VIN;

[0005] like Figure 2 As shown, the OSHOT comparator has a delay and changes with the slope of the input signal (Vramp). Its slope can be expressed as:

[0006]

[0007] The delay T2 can be expressed as follows, where K1 is the coefficient between the Vramp signal and T2:

[0008] T 2 =K ramp K 1 ;

[0009] The relationship between delay T2 and Vin is expressed as follows:

[0010]

[0011] 2. The frequency changes significantly with VOUT;

[0012] like Figure 1As shown, since the I2 current changes with Vramp, the I1 and I2 currents are not always equal. When Vramp is small, I2 > Vramp / Rm, and when Vramp is large, I2 < Vramp / Rm. Then the relationship between the delay T1 and Vout can be expressed as follows, where Kout is the coefficient related to T1 and Vout:

[0013] Summary of the Invention

[0014] In view of the above technical problems, the present invention provides a method for frequency compensation of a constant on-time circuit inside a chip to solve the problem that the frequency inside the chip changes with VIN or VOUT in the prior art.

[0015] Other features and advantages of the present disclosure will become apparent from the following detailed description or will be partially learned through the practice of the present disclosure.

[0016] The present invention discloses a method for frequency compensation of a constant on-time circuit inside a chip, which is applied to a frequency generation circuit of the chip. The method includes:

[0017] Based on a buffer, adding the input voltage or output voltage of the chip to a resistor and generating a compensation current on the resistor;

[0018] Mirroring the compensation current and giving the obtained mirror current to a comparator with current-controlled delay to regulate the output delay of the comparator. The comparator compares a ramp signal and the output voltage to generate a control signal for regulating the frequency of the frequency generation circuit;

[0019] Regulating the size of the resistor so that the output delay matches the output frequency of the chip.

[0020] Further, the input voltage or the output voltage is input to the non-inverting input terminal of the buffer. The output terminal of the buffer is connected to its own inverting input terminal, and the output terminal of the buffer is connected to one end of the resistor to generate the compensation current, and the other end of the resistor is grounded.

[0021] Further, the mirror current is generated based on a mirror current source circuit, and the mirror current source circuit is a bipolar transistor circuit.

[0022] Further, the non-inverting input terminal of the comparator is connected to the output voltage, its inverting input terminal is connected to the ramp signal, and its control terminal inputs the mirror current.

[0023] The technical solution of the present disclosure has the following beneficial effects:

[0024] The current is generated by detecting the external voltage, and the generated current is input into the current control delay comparator, thereby compensating for the influence of the external condition change on the output frequency, making the output frequency more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a constant on-time circuit in the background technology of this specification;

[0026] Figure 2 A line graph of a constant on-time composition in the background technology of this specification;

[0027] Figure 3 It is a flow chart of a method for frequency compensation of a constant on-time circuit inside a chip in an embodiment of this specification;

[0028] Figure 4 It is a schematic diagram of a frequency compensation circuit of a constant on-time circuit inside a chip in an embodiment of this specification;

[0029] Figure 5 It is a line graph of the constant on-time composition in the embodiments of this specification. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0031] like Figure 3 As shown, the embodiment of this specification provides a method for frequency compensation of a constant on-time circuit inside a chip, the method is applied to a frequency generating circuit of the chip, and the method specifically includes steps S101-103:

[0032] In step S101, based on the buffer, the input voltage or output voltage of the chip is added to the resistor, and a compensation current is generated on the resistor;

[0033] In step S102, the compensation current is mirrored, and the obtained mirrored current is given to a comparator for current control delay to control the output delay of the comparator, and the comparator compares the ramp signal with the output voltage to generate a control signal for controlling the frequency of the frequency generating circuit;

[0034] In step S103, the value of the resistor is adjusted so that the output delay matches the output frequency of the chip.

[0035] Among them, Figure 4 As shown, the input voltage or the output voltage is input to the non-inverting input terminal of the buffer, the output terminal of the buffer is connected to its own inverting input terminal, and the output terminal of the buffer is connected to one end of the resistor to generate the compensation current, and the other end of the resistor is grounded. The mirror current is generated based on a mirror current source circuit, and the mirror current source circuit is a bipolar transistor circuit. The non-inverting input terminal of the comparator is connected to the output voltage, the inverting input terminal is connected to the ramp signal, and the control terminal inputs the mirror current.

[0036] Specifically, this embodiment is mainly used to compensate for the influence of the constant on-time inside the chip as the external conditions change. By detecting external signals, generating compensation current, and controlling the compensation time, a stable constant on-time is finally obtained. The overall architecture and on-time are as follows: Figure 4 , Figure 5 As shown, by introducing the influence of VIN / VOUT on the frequency respectively, the influence of each factor can be adjusted independently to obtain a high-precision frequency; for example, the VIN voltage is added to the resistor Rs through the buffer Buffer to generate a compensation current Is, and then the mirror current Is is obtained through the mirror current source and given to the comparator OSHOT to adjust the output delay T2 compared with VRAMP and VOUT. The coefficient of the mirror current Is and the output delay T2 delay increase is Kshot. By adjusting the size of the resistor Rs, the size of the output delay compensated by the introduction of VIN is adjusted, that is, the size of T2. Similarly, the same is true for VOUT. The expressions for Vin and Vout compensation are shown as follows:

[0037]

[0038]

[0039] Beneficial effects:

[0040] The current is generated by detecting the external voltage, and the generated current is input into the current control delay comparator, thereby compensating for the influence of the external condition change on the output frequency, making the output frequency more stable.

[0041] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A method for frequency compensation of a constant on-time circuit inside a chip, characterized in that: The method is applied to a frequency generating circuit of a chip, and the method comprises: Based on the buffer, the input voltage or output voltage of the chip is added to the resistor and a compensation current is generated in the resistor; Mirroring the compensation current, and providing the obtained mirror current to a current control delay comparator to control the output delay of the comparator, wherein the comparator compares the ramp signal with the output voltage to generate a control signal for controlling the frequency of the frequency generating circuit; The value of the resistor is adjusted so that the output delay matches the output frequency of the chip.

2. A method for frequency compensation of a constant on-time circuit inside a chip according to claim 1, characterized in that: The input voltage or the output voltage is input to the non-inverting input terminal of the buffer, the output terminal of the buffer is connected to its own inverting input terminal, and the output terminal of the buffer is connected to one end of the resistor to generate the compensation current, and the other end of the resistor is grounded.

3. A method for frequency compensation of a constant on-time circuit inside a chip according to claim 1, characterized in that: The mirror current is generated based on a mirror current source circuit, and the mirror current source circuit is a bipolar transistor circuit.

4. A method for frequency compensation of a constant on-time circuit inside a chip according to claim 1, characterized in that: The non-inverting input terminal of the comparator is connected to the output voltage, the inverting input terminal thereof is connected to the ramp signal, and the control terminal thereof is input with the mirror current.

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