A low common-mode noise driver and a manufacturing method thereof

Abstract

The application discloses a low common-mode noise driver and a manufacturing method thereof. The low common-mode noise driver comprises two cascaded current mode logic drivers; an input end of the first-stage current mode logic driver serves as an input end of the low common-mode noise driver, an output end of the first-stage current mode logic driver is electrically connected with an input end of the second-stage current mode logic driver, and an output end of the second-stage current mode logic driver serves as an output end of the low common-mode noise driver; the manufacturing method comprises the following steps: determining an equivalent circuit model containing a parasitic capacitor according to a field effect transistor used by the driver; predicting an output common-mode noise of the driver based on the equivalent circuit model; and optimizing circuit parameters based on a prediction result of the common-mode noise of the driver. The low common-mode noise driver has great improvement in the aspect of output common-mode noise suppression compared with a traditional sending end driver.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits and the field of electromagnetic compatibility, and in particular to a low common-mode noise driver and a manufacturing method thereof. BACKGROUND

[0002] With the development and application of artificial intelligence and big data technology, the amount of data presents an explosive growth. Under such a situation, how to efficiently and quickly process and transmit massive data has become a problem to be solved, and therefore various interface technologies have emerged. In mainstream interface technologies such as serial deserializers, a driver, as a key to connect the sending end of an interface with a channel, plays an important role in logic level conversion and impedance matching.

[0003] As a circuit module directly connected to an output channel, the common-mode noise output by the driver is a very important indicator. Fluctuation of the common-mode voltage output by the driver will cause crosstalk between channels, affecting signal quality. Considering design speed and area efficiency, current mode logic drivers are widely used in existing interface technologies. However, due to the influence of the parasitic capacitance of field effect transistors, the response speed of the traditional current mode logic driver to the rising and falling edges of the input signal is inconsistent at a high frequency input of gigahertz, resulting in a large fluctuation of the output common-mode voltage. This fluctuation of the common-mode voltage forms a large common-mode noise. This problem is a key problem in the field of interface electromagnetic compatibility.

[0004] Existing related researches reduce the fluctuation of the output common-mode voltage by adding a bypass capacitor at the output end. However, the size of the bypass capacitor used in this method is in the micro-farad level, and the huge area overhead makes it difficult to integrate the bypass capacitor in the sending end, which can only be externally hung between the sending end chip and the channel in the form of on-board. The bypass capacitor externally hung in this way will introduce additional parasitic parameters, greatly increasing the complexity of interface design. Therefore, a driver common-mode noise suppression technology that can be integrated into the sending end chip is needed. SUMMARY

[0005] To solve the problem of the output common-mode noise of the driver of the high-speed interface sending end, the present application provides a low common-mode noise driver and a manufacturing method thereof. The present application uses a cascaded current mode logic driver as a low common-mode noise driver, utilizes the characteristic that the output of the current mode logic driver is opposite to the input, and makes the high-speed input signal pass through a rising edge response and a falling edge response when passing through the designed low common-mode noise driver, so as to balance the mismatch of the field effect transistor in response to the rising and falling edges of the high-speed signal, and reduce the common-mode noise at the output end.

[0006] The technical solutions adopted by the present application are as follows:

[0007] I. A low common-mode noise driver

[0008] The low common-mode noise driver comprises two cascaded current mode logic drivers; an input end of the first stage current mode logic driver is an input end of the low common-mode noise driver, an output end of the first stage current mode logic driver is electrically connected with an input end of the second stage current mode logic driver, and an output end of the second stage current mode logic driver is an output end of the low common-mode noise driver.

[0009] The current mode logic driver comprises two common-source N-type field effect tubes, a common source is grounded through a constant current source, the drains of the two field effect tubes are respectively connected with a power supply through two load resistors with the same resistance, the gates of the two field effect tubes are input ends of the current mode logic driver, and the drains of the two field effect tubes are output ends of the current mode logic driver.

[0010] The drains of the two field effect tubes of the first stage current mode logic driver are electrically connected with the gates of the two field effect tubes of the second stage current mode logic driver.

[0011] II. A manufacturing method applied to the low common-mode noise driver

[0012] The manufacturing method comprises the following steps:

[0013] S1. Establishing a parasitic capacitance model of the field effect tube according to the performance parameters of the field effect tube, and establishing an equivalent circuit model of the low common-mode noise driver according to the parasitic capacitance model;

[0014] In the step S1, the parasitic capacitance model of the field effect tube comprises gate-drain parasitic capacitance, gate-source parasitic capacitance, drain junction capacitance and source junction capacitance of the field effect tube at each DC operating point.

[0015] In the step S1, the circuit equation of the equivalent circuit model is specifically:

[0016] V op1 =V DD -R L1 I p1

[0017] V on1 =V DD -R L1 I n1

[0018] I p1 =I ds(V ip -V s1 ,V op1 -V s1 )

[0019] I n1 =I ds (V in -V s1 ,V on1 -V s1 )

[0020] I ss1 =I p1 + I n1

[0021] V op2 =V DD -R L2 I p2

[0022] V on2 =V DD -R L2 I n2

[0023] I p2 =I ds (V op1 -V s2 ,V op2 -V s2 )

[0024] I p2 =I ds (V on1 -V s2 ,Vop2 -V s2 )

[0025] I ss2 =I p2 + I n2

[0026] wherein V DD is the power supply voltage, R L1 and R L2 are the load resistances of the first stage current mode logic driver and the second stage current mode logic driver respectively, V op1 and V on1 are the drain voltages of the two field effect transistors in the first stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first stage current mode logic driver, I p1 and I n1 are the source-drain currents of the two field effect transistors in the first stage current mode logic driver, V ip and V in are the gate voltages of the two field effect transistors in the first stage current mode logic driver, I ss1 is the tail current source of the first stage current mode logic driver;

[0027] V op2 and V on2 are the drain voltages of the two field effect transistors in the second stage current mode logic driver, V s2 is the voltage of the common source of the two field effect transistors in the second stage current mode logic driver, I p2 and I n2 are the source-drain currents of the two field effect transistors in the second stage current mode logic driver, I ss2 is the tail current source of the second stage current mode logic driver, I ds （V gs ,V ds ） is the function relationship of the source-drain current of the field effect transistor with respect to the gate-source voltage V gs and the source-drain voltage V ds .

[0028] S2, circuit analysis is performed on the equivalent circuit model of the low common mode noise driver to obtain time domain waveforms of output signal common mode noise under a plurality of different groups of circuit parameters to be optimized;

[0029] The step S2, the circuit analysis specifically is the dynamic response analysis of the driver in the input signal flip process and the critical swing analysis of the current mode logic driver.

[0030] The step S2, each group of to-be-optimized circuit parameters mainly consists of the load resistance and the tail current of the first-stage current mode logic driver.

[0031] Further, in the step S2, before the circuit analysis, the range of the product of the load resistance and the tail current of the second-stage current mode logic driver and the load resistance and the tail current of the first-stage current mode logic driver is set;

[0032] The load resistance of the second-stage current mode logic driver is matched with the channel impedance.

[0033] The product of the load resistance and the tail current of the second-stage current mode logic driver is matched with the target output swing of the low common-mode noise driver.

[0034] The product of the load resistance and the tail current of the first-stage current mode logic driver is greater than or equal to the critical swing of the second-stage current mode logic driver. The critical swing refers to the input swing that can just make the output swing of the current mode logic driver reach the maximum swing.

[0035] S3, according to the time-domain waveform of the output signal common-mode noise under each group of to-be-optimized circuit parameters, the output common-mode noise is predicted, the relationship function of the to-be-optimized circuit parameters and the output signal common-mode noise is obtained, the to-be-optimized circuit parameters corresponding to the minimum value of the output signal common-mode noise are obtained from the relationship function as the optimal circuit parameters, and the low common-mode noise driver is manufactured according to the optimal circuit parameters.

[0036] In the step S3, the process of the output common-mode noise prediction is specifically as follows: the time-domain waveform of the output signal common-mode noise under each group of to-be-optimized circuit parameters is subjected to Fourier transform, the frequency spectrum of the output signal common-mode noise is obtained, the maximum value of the alternating current component in the common-mode part of the frequency spectrum of the output signal common-mode noise is taken as the output signal common-mode noise corresponding to the to-be-optimized circuit parameters, and the functional relationship of the to-be-optimized circuit parameters and the output signal common-mode noise is obtained.

[0037] Compared with the prior art, the present application has the following beneficial effects:

[0038] 1. The low common-mode noise driver designed in the present application can be integrated in a chip like the traditional sending end driver, which not only makes the circuit have good integrity, but also does not introduce additional parasitic parameter problems. And compared with the traditional sending end driver, the driver designed in the present application has better output common-mode noise suppression effect.

[0039] 2、The low common mode noise driver used in the application has good process compatibility and area efficiency. Compared with the traditional large capacitor and common mode choke scheme, the application is based on the original current mode logic driver for cascading, without introducing additional circuit components, and has good process compatibility. In addition, the application also avoids using large capacitors and large inductors in integrated circuits, which occupy a large area of resources, and has high area efficiency.

[0040] 3、The driver circuit parameter optimization method proposed in the application uses a high-precision driver equivalent circuit model with parasitic capacitance, and derives the detailed functional relationship between the output common mode noise and the driver circuit parameters, improving the efficiency of the circuit parameter optimization process. And the obtained circuit parameter optimization result has high accuracy.

[0041] 4、The low common mode noise driver proposed in the application has great improvement in output common mode noise suppression compared with the traditional transmitter driver. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The schematic diagram of the current mode logic driver in one exemplary embodiment of the application.

[0043] Figure 2 The schematic diagram of the low common mode noise driver in one exemplary embodiment of the application.

[0044] Figure 3 The equivalent circuit model with parasitic parameters of the low common mode noise driver in one exemplary embodiment of the application.

[0045] Figure 4 The function relationship diagram of the output swing of the current mode logic driver about the input swing in one exemplary embodiment of the application.

[0046] Figure 5 The function relationship diagram of the output common mode noise about the load resistance R L1 and the tail current I SS1 of the first stage current mode logic driver in one exemplary embodiment of the application.

[0047] Figure 6 The time domain waveform diagram of the output common mode voltage of the low common mode noise driver after circuit parameter optimization when the input voltage flips in one exemplary embodiment of the application.

[0048] Figure 7 The frequency spectrum diagram of the output common mode voltage of the low common mode noise driver after circuit parameter optimization when the input voltage flips in one exemplary embodiment of the application. DETAILED DESCRIPTION

[0049] The application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the application is not limited to the following embodiments.

[0050] The first aspect of the application provides a low common mode noise driver. The low common mode noise driver is used to receive a differential input signal from a digital processing module output end of a high-speed interface transmitting end, generate a differential output signal and output to a channel.

[0051] As shown in Figure 1 and Figure 2 , the low common mode noise driver is mainly composed of two cascaded current mode logic drivers. The input end of the first stage current mode logic driver is the input end of the low common mode noise driver, the output end of the first stage current mode logic driver is electrically connected with the input end of the second stage current mode logic driver, and the output end of the second stage current mode logic driver is the output end of the low common mode noise driver. The first stage current mode logic driver receives a pair of differential input signals from the digital processing module output end of the high-speed interface transmitting end, and pre-processes the differential input signals. The first stage current mode logic driver outputs a first stage differential output signal as the differential input of the second stage current mode logic driver. The second stage current mode logic driver serves as an output driver and outputs a pair of differential output signals to the channel.

[0052] The application uses two cascaded current mode logic drivers, and utilizes the characteristic that the output of the current mode logic driver is opposite to the input, so that the differential input signals undergo a rising edge and a falling edge response, thereby balancing the characteristic of the response mismatch of the field effect tube.

[0053] As shown in Figure 1 , the current mode logic driver includes two N-type field effect tubes with a common source. The common source is connected to the ground through a constant current source. The drains of the two field effect tubes are respectively connected to the power supply through two load resistors with the same resistance. The gates of the two field effect tubes serve as the input end of the current mode logic driver and respectively receive two differential signals input to the current mode logic driver. The drains of the two field effect tubes serve as the output end of the current mode logic driver.

[0054] The drains of the two field effect tubes of the first stage current mode logic driver are electrically connected with the gates of the two field effect tubes of the second stage current mode logic driver.

[0055] Therefore, the gates of the two field effect tubes of the first stage current mode logic driver serve as the input end of the low common mode noise driver and receive a pair of differential input signals. The drains of the two field effect tubes of the second stage current mode logic driver serve as the output end of the low common mode noise driver and output a pair of differential output signals.

[0056] In the two current-mode logic drivers, other circuit parameters of the N-type field-effect transistors depend on the integrated circuit manufacturing process used and are not involved in the subsequent circuit parameter design optimization.

[0057] Specifically, the drains of the two field effect transistors are connected to the power supply, which means that the drains of the two field effect transistors are connected in parallel to the same power supply.

[0058] A second invention of the present invention provides a manufacturing method for the aforementioned low common-mode noise driver. This method optimizes the circuit parameters of the low common-mode noise driver by establishing an equivalent circuit model including parasitic capacitance, performing circuit analysis, and then performing common-mode noise prediction. The optimized circuit parameters are then used in the manufacture of the low common-mode noise driver.

[0059] The manufacturing method of the present invention specifically comprises the following steps:

[0060] S1. Establish an equivalent circuit model including parasitic capacitance: Establish a parasitic capacitance model for the field-effect transistor (FET) based on the performance parameters of the FET selected for the low common-mode noise driver. Establish an equivalent circuit model for the low common-mode noise driver including parasitic capacitance based on the parasitic capacitance model. The parasitic capacitance model for the FET is an equivalent model of a voltage-controlled current source and four parasitic capacitors, namely the gate-drain parasitic capacitance (gate-drain capacitance), the gate-source parasitic capacitance (gate-source capacitance), the drain junction capacitance, and the source junction capacitance.

[0061] In step S1, the circuit equation of the equivalent circuit model is specifically:

[0062] V op1 =V DD -R L1 I p1

[0063] V on1 =V DD -R L1 I n1

[0064] I p1 =I ds (V ip -V s1 ,V op1 -V s1)

[0065] I n1 =I ds (V in -V s1 ,V on1 -V s1 )

[0066] I ss1 =I p1 +I n1

[0067] V op2 =V DD -R L2 I p2

[0068] V on2 =V DD -R L2 I n2

[0069] I p2 =I ds (V op1 -V s2 ,V op2 -V s2 )

[0070] I p2 =I ds (V on1 -V s2 ,V op2 -V s2 )

[0071] Iss2 =I p2 +I n2

[0072] where V DD is the power supply voltage, R L1 and R L2 are the load resistances of the first stage current mode logic driver and the second stage current mode logic driver, respectively, V op1 and V on1 are the drain voltages of the two field effect transistors in the first stage current mode logic driver, which are also the differential output signals of the first stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first stage current mode logic driver, I p1 and I n1 are the source-drain currents of the two field effect transistors in the first stage current mode logic driver, V ip and V in are the gate voltages of the two field effect transistors in the first stage current mode logic driver, which are also the differential input signals of the first stage current mode logic driver / low common mode noise driver, I ss1 is the tail current source of the first stage current mode logic driver;

[0073] V op2 and V on2 are the drain voltages of the two field effect transistors in the second stage current mode logic driver, which are also the differential output signals of the final output of the low common mode noise driver, V s2 is the voltage of the common source of the two field effect transistors in the second stage current mode logic driver, I p2 and I n2 are the source-drain currents of the two field effect transistors in the second stage current mode logic driver, the gates of the two field effect transistors are connected to the drains of the first stage current mode logic driver, respectively, and the voltages are V op1 and V on1 , I ss2 is the tail current source of the second stage current mode logic driver, I ds (V gs ,V ds ) is the function relationship of the source-drain current of the field effect transistor with respect to its gate-source voltage V gs and source-drain voltage V ds

[0074] where the node voltages and current signs have been shown in Figure 3 ​The winning bid indicates, I ds (V gs ,V ds ) The function relationship of the source-drain current of the field effect tube with respect to the gate-source voltage V gs and the source-drain voltage V ds The solution of the above circuit equation is used as the initial condition of the circuit analysis.

[0075] S2, circuit analysis is performed on the equivalent circuit model of the low common-mode noise driver to obtain the time-domain waveform of the output signal common-mode noise under a plurality of different sets of to-be-optimized circuit parameters; wherein the to-be-optimized circuit parameters include the load resistance of the first-stage current-mode logic driver and the size of the tail current; the circuit analysis is specifically dynamic response analysis of the driver during the input signal flipping process and critical swing analysis of the current-mode logic driver, and more specifically, the dynamic response analysis of the driver during the input signal flipping process is input differential signal rising and falling edge response analysis.

[0076] Step S2 is specifically:

[0077] S2.1, set the values of the load resistance and the tail current of the second-stage current-mode logic driver, and the optimization range of the product of the load resistance and the tail current of the first-stage current-mode logic driver;

[0078] The load resistance of the second-stage current-mode logic driver is matched with the channel impedance of the output end of the low common-mode noise driver;

[0079] The product of the load resistance and the tail current of the second-stage current-mode logic driver is matched with the target output swing of the low common-mode noise driver;

[0080] The product of the load resistance and the tail current of the first-stage current-mode logic driver is greater than or equal to the critical swing of the second-stage current-mode logic driver.

[0081] S2.2, according to the circuit parameters set in step S2.1 and the optimization range of the to-be-optimized circuit parameters, perform dynamic response analysis of the driver during the input signal flipping process on the equivalent circuit model of the low common-mode noise driver under different values of the to-be-optimized circuit parameters, to obtain the time-domain response waveform of the output node voltage when the input signal flips;

[0082] In this process, the influence of all parasitic capacitances is considered, and the V op1 , V on1 , V s1 ,V op2 , V on2 , V s2 The Kirchhoff current law for the six output node voltages lists the equations for the dynamic analysis:

[0083] I p1 +I n1 =I gsp1 +I jsp1 +I gsn1 +I jsn1 +I ss1

[0084] I p2 +I n2 =I gsp2 +I jsp2 +I gsn2 +I jsn2 +I ss2

[0085] I op1 =I gdp1 +I p1 +I gdp2 +I gsp2 +I jdp1

[0086] I on1 =I gdn1 +I n1 +I gdn2 +I gsn2 +I jdn1

[0087] I op2 +I gdp2 =I jdp2 +Ip2

[0088] I on2 +I gdn2 =I jdn2 +I n2

[0089] wherein, I p1 and I n1 are the source-drain currents of two field effect transistors in the first stage current mode logic driver, I p2 and I n2 are the source-drain currents of two field effect transistors in the second stage current mode logic driver. The above field effect transistor source-drain currents are related to the output voltage sought as:

[0090] I p1 =I ds (V ip -V s1 ,V op1 -V s1 )

[0091] I n1 =I ds (V in -V s1 ,V on1 -V s1 )

[0092] I p2 =I ds (V op1 -V s2 ,V op2 -V s2 )

[0093] I n2=I ds (V on1 -V s2 ,V on2 -V s2 )

[0094] I op1 and I on1 is the current flowing through the load resistor in the first stage current mode logic driver, I op2 and I on2 is the current flowing through the load resistor in the second stage current mode logic driver, the relationship of the above currents with respect to the output voltage being solved is:

[0095] I op1 =(V DD -V op1 ) / R L1

[0096] I on1 =(V DD -V on1 ) / R L1

[0097] I op2 =(V DD -V op2 ) / R L2

[0098] I on2 =(V DD -V on2 ) / R L2

[0099] remaining I gsp1 , I gsp2 the current through the parasitic capacitance of the same subscript is the current through the capacitance C gsp1 the currentI gsp1 For example, the relationship with respect to the solved output voltage is:

[0100] I gsp1 =C gsp1 • d(V ip -V s1 ) / dt

[0101] The remaining current values can be obtained in the same way.

[0102] The above equation set is solved by a numerical method, and the output time domain waveform of the low common-mode noise driver proposed in the application, i.e., the time domain response waveform of the output node voltage when the input signal flips, is predicted, and the output time domain waveform of the low common-mode noise driver is obtained.

[0103] S2.3, according to the time domain response waveform of the output node voltage when the input signal flips under each set of circuit parameters to be optimized, the differential output signal (Vdiff) is obtained by taking the common-mode component of the differential output signal (Vdiff) and the output signal common-mode noise time domain waveform, i.e., the time domain variation waveform of the output signal common-mode noise. V op2 and V on2 ) to obtain the time domain waveform of the output signal common-mode noise, i.e., the time domain variation waveform of the output signal common-mode noise.

[0104] S3, according to the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized, the output common-mode noise is predicted, the relationship curve of the circuit parameters to be optimized and the output signal common-mode noise is obtained, the circuit parameters to be optimized corresponding to the minimum value of the output signal common-mode noise are obtained from the relationship curve as the optimal circuit parameters, and the low common-mode noise driver is manufactured according to the optimal circuit parameters.

[0105] In step S3, the process of output common-mode noise prediction is as follows: the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized is Fourier transformed to obtain the frequency spectrum of the output differential signal, and the maximum value of the alternating current component (i.e., the non-direct current part) in the common-mode part of the frequency spectrum of the output differential signal is taken as the output signal common-mode noise corresponding to the circuit parameters to be optimized, and the relationship curve of the circuit parameters to be optimized and the output signal common-mode noise is obtained.

[0106] In a specific implementation, it is also necessary to determine the size parameters according to the values of the circuit parameters, and the specific process is as follows:

[0107] First, the minimum length that can be achieved by the used process is taken as the length of the two current mode logic drivers, and the length can pass the required tail current of the second stage current mode logic driver I SS2The minimum width of the two current-mode logic drivers is used as the width of the low common-mode noise driver.

[0108] The principle of the low common-mode noise driver of the present invention is as follows:

[0109] The present invention proposes a low common-mode noise driver comprising two current-mode logic drivers in cascade. The basic schematic of the current-mode logic driver is shown in Figure 1 The current-mode logic driver comprises two N-type field effect transistors with common source, whose source is connected to a constant current source I SS through a load resistor with the same resistance R to the power supply V DD , and the gate of the two field effect transistors receives two differential input signals V ip , V in respectively.The design of the current-mode logic driver forms a push-pull structure. When the current-mode logic driver is working normally, one of the pair of differential input signals is at high level and the other is at low level, so that the two field effect transistors provide tail current alternately V ip . V in Assuming that I SS is at high level and V ip is at low level, then there is current V in flowing through the left field effect transistor and no current flowing through the right field effect transistor, and the corresponding output voltage I SS is the difference between the power supply voltage and the product of the load resistor and the tail current V op V DD -RI SS , V on V DD , and vice versa. Theoretically, the maximum swing of the output is the product of the load resistor and the tail current RI SS ​It is worth noting that the difference between the differential amplifier and the current mode logic driver based on the same push-pull structure lies in the working region of the field effect tubes. For the current mode logic driver, one field effect tube is in the saturation region and the other is in the cut-off region in normal working, which ensures that only one field effect tube supplies the tail current in the steady state and the other does not generate any current. In this normal working condition, the current mode logic driver must reach the maximum output swing, and the input swing requirement for the differential signal is the larger the better. For the differential amplifier, the DC working points of the two field effect tubes are required to be as stable as possible and close to each other in normal working, and in the ideal condition, each field effect tube supplies half of the tail current. In the balanced condition of the two field effect tubes, the differential amplifier has the best linearity and amplification effect. Therefore, the differential amplifier has a smaller requirement for the input swing than the current mode logic driver.

[0110] Figure 2 The design principle diagram of the low common-mode noise driver proposed in the application is shown. Due to the existence of the parasitic capacitance in the field effect tube, and the value of the parasitic capacitance has a great correlation with the working state of the field effect tube. Generally, the field effect tube in the saturation region will have a larger gate-source parasitic capacitance than the field effect tube in the cut-off region. This is because the field effect tube forms a conductive channel when it is turned on, and the extension of the conductive channel increases the area of the equivalent plate capacitance between the gate and the source. The mismatch of this parasitic capacitance will cause the inconsistent response speed of the field effect tube to the opening and closing of the high-speed signal, so that the common-mode voltage fluctuation occurs at the output end, which becomes a source of output common-mode noise. On the other hand, the parasitic capacitance at the common source end of the two field effect tubes in the current mode logic driver will also cause the output common-mode fluctuation when the signal flips. When the differential input signal is in the steady state, the DC working points of the two field effect tubes are at the zero current position and I SS current position of the transfer characteristic curve, respectively. When the differential input signal flips, the DC working points of the field effect tubes will exchange positions along the transfer characteristic curve. In the exchange process, if the common source end voltage of the two field effect tubes is unchanged, and the rising and falling rates of the gate input signal are the same, due to the nonlinear characteristic of the transfer characteristic curve of the field effect tube, the DC working point change process of the two field effect tubes will not be perfectly balanced. It can be analyzed from the actual transfer characteristic curve that in the initial stage of the input signal flip, the source-drain current of the field effect tube whose working point moves from the zero current position to the zero current position decreases faster than that of the field effect tube whose working point moves from the I SS current position to the zero current position. Therefore, the common-mode voltage at the output end will fluctuate, which is the source of the output common-mode noise. I SSThe source-drain current of the field effect transistor increases in speed of current position movement. At this time, the sum of the currents of the two field effect transistors will be less than the tail current size of the current mode logic driver, which does not conform to the Kirchhoff's current law at the source node of the field effect transistor, i.e. the sum of the source-drain currents of the two field effect transistors should be equal to the tail current size of the current mode logic driver. In the later period of the differential input signal flip, the situation is contrary to the initial period of the flip, at this time, the sum of the source-drain currents of the two field effect transistors will be greater than the tail current size of the current mode logic driver. Therefore, in the ideal case of no parasitic capacitance of the source-drain, the common source voltage of the two field effect transistors must respond to decrease in the initial period of the input signal flip to increase the gate-source voltage of the field effect transistor, so that the working point of the field effect transistor is shifted to the right on the transfer characteristic curve to increase the source-drain current of the field effect transistor, thereby ensuring that the sum of the source-drain currents of the two field effect transistors is equal to the tail current size at any time. Similarly, in the later period of the input signal flip, the common source voltage responds to increase so that the working point of the field effect transistor is shifted to the left on the transfer characteristic curve to decrease the source-drain current of the field effect transistor to achieve the same effect. However, the parasitic capacitance of the field effect transistor at the source end in the actual design will have a certain impact on the response of the source voltage of the field effect transistor: first, the parasitic capacitance will cause the response amplitude of the common source of the field effect transistor to attenuate, and the common source voltage after the response amplitude attenuation is not sufficient to make the sum of the source-drain currents of the two field effect transistors equal to the size of the tail current at any time, but less than the size of the tail current in the early period of the input signal flip and greater than the size of the tail current in the later period of the input signal flip. Second, the parasitic capacitance will cause the common source voltage of the field effect transistor to respond with a delay, which makes the source voltage unable to respond in time to the change of the gate input signal. The attenuation and delay of the parasitic capacitance on the response of the common source voltage cause the final output common mode voltage to fluctuate, and the output common mode voltage increases in the early period of the input signal flip and decreases in the later period of the input signal flip.

[0111] In Figure 2 the design principle diagram of the low common mode noise driver shown, the differential input signal V ip and V on are respectively input to the gate of the two field effect transistors of the first stage current mode logic driver (left) to control the current size flowing through the two field effect transistors. Then, the first stage differential output signal V op1 and V on1 are respectively input to the gate of the two field effect transistors of the second stage current mode logic driver (right) to control the current size flowing through the two field effect transistors. Finally, the second stage differential output signal V op2 and V on2The differential output signal of the whole low common mode noise driver is sent to the channel. The beneficial effect of this structure is that, from the whole, assuming the input signal V ip is at the rising edge, the input signal V on is at the falling edge, then the first stage output signal V op1 experiences a rising edge response of the first stage field effect transistor and, due to the output inversion characteristic of the current mode logic driver, itself is at the falling edge. The second stage output signal V op1 experiences a falling edge response of the second stage field effect transistor of the current mode logic driver and, finally, the second stage output signal V op2 experiences a rising edge response and a falling edge response and, itself, is at the rising edge. Conversely, the other side of the differential signal is also the same, the second stage output signal V on2 experiences a falling edge response and a rising edge response and, itself, is at the falling edge. At this point, the output signal experiences a rising edge and a falling edge response and the response mismatch problem of the field effect transistor is balanced. From the perspective of separation, the first stage current mode logic driver can be regarded as a signal preprocessing module. In the traditional current mode logic driver, when the input signal flips, due to the nonlinear characteristic of the field effect transistor transfer characteristic curve, the common source voltage of the field effect transistor used by the driver needs to respond so that the sum of the source-drain currents of the two field effect transistors is equal to the tail current. Here, the first stage current mode logic driver performs a targeted preprocessing on the ideal symmetric differential input signal, and the first stage differential output signal after preprocessing is used as the input signal of the second stage current mode logic driver, which can reduce the response required by the common source voltage of the field effect transistor of the second stage current mode logic driver, that is, the voltage at this point does not need to change too much, and the sum of the source-drain currents of the two field effect transistors is equal to the tail current, greatly reducing the influence of the source parasitic capacitance on the output common mode voltage.

[0112] Figure 2 The load resistance of the first stage current mode logic driver in the low common mode noise driver shown R L1 、 The load resistance of the second stage current mode logic driver R L2 、 The tail current of the first stage current mode logic driver I SS1 , the tail current of the second stage current mode logic driver I SS2are the circuit parameters that can be optimized. The optimization of the circuit parameters has the following constraints considering the channel impedance matching and the requirement of the driver output swing:

[0113] ① The output impedance of the low common-mode noise driver needs to match the channel impedance R 0 :

[0114] R L2 =R 0

[0115] where, R 0 is the channel impedance, R L2 is the load resistance of the second stage current-mode logic driver.

[0116] ② The output swing of the low common-mode noise driver needs to reach the target output swing of the design requirement V swing :

[0117] R L2 I SS2 =V swing

[0118] where, V swing is the target output swing, R L2 is the load resistance of the second stage current-mode logic driver, I SS2 is the tail current of the second stage current-mode logic driver.

[0119] ③ The output swing of the first stage current-mode logic driver must be such that the second stage current-mode logic driver can reach full swing:

[0120] R L1 I SS1 =V c

[0121] where, V C is the critical swing of the second stage current-mode logic driver, R L1 is the load resistance of the first stage current-mode logic driver, I SS1 is the tail current of the first stage current-mode logic driver.

[0122] Figure 4 Output swing of current mode logic driver is demonstrated V osw Regarding input swing V isw When the input swing of the second stage current mode logic driver (i.e. the output swing of the first stage current mode logic driver) is greater than or equal to the critical swing V C , the output swing can reach full swing, in which one field effect transistor current of the current mode logic driver is zero, and the tail current is provided by the other field effect transistor, and the driver works normally.

[0123] According to the above circuit parameter optimization limit analysis, the load resistance R L2 and the tail current I SS2 of the second stage current mode logic driver are limited to fixed values, and the product of the load resistance and the tail current of the first stage current mode logic driver R L1 I SS1 is required to be greater than or equal to the critical swing V C of the second stage current mode logic driver.

[0124] In addition to the circuit parameters, the size of the field effect transistor itself also has a great impact on the output common mode noise. On the one hand, the larger the size of the field effect transistor, the larger the area of the gate metal layer in its physical structure, and the larger the equivalent parasitic capacitance from the gate to the source and the drain. In order to achieve the effect of suppressing the output common mode noise, the size of the field effect transistor itself needs to be reduced to reduce the impact of the parasitic capacitance on the output common mode noise. On the other hand, the size of the current that can be passed through the field effect transistor is closely related to the width-length ratio of the field effect transistor, and increasing the width-length ratio of the field effect transistor can make the field effect transistor pass more current at the same DC operating point. In the normal working condition of the driver, a single field effect transistor needs to be able to pass the same amount of current as the tail current, which puts a certain limit on the width-length ratio of the field effect transistor. To achieve a larger width-length ratio with the smallest possible size of the field effect transistor, the length of the field effect transistor needs to be minimized. Under a certain process, the minimum length of the field effect transistor is fixed, so the size of the field effect transistor itself is also determined. That is, the length takes the minimum length that can be achieved by the used process, and the width takes the minimum length that can pass the required tail current under this length. The above analysis of the size of the field effect transistor is based on the single-stage current mode logic driver structure. For the driver composed of the cascaded current mode logic driver proposed by the present application, the size of the field effect transistor of the second-stage current mode logic driver is consistent with that of the single-stage current mode logic driver. For the first-stage current mode logic driver, in order to achieve the rise and fall edge response balance of the field effect transistor of the second-stage current mode logic driver, the same size of the field effect transistor as that of the second-stage current mode logic driver should also be used. Therefore, the low common mode noise driver proposed by the present application is consistent with the single-stage current mode logic driver in the selection of the size of the field effect transistor.

[0125] Figure 3 The precise equivalent circuit model containing parasitic capacitances established for the low common mode noise driver proposed by the present application is shown, and the extraction of these parasitic capacitance models is based on the physical structure and characteristics of the real device. Figure 3 In the middle, V DD For the power supply voltage, R L1 And R L2 R1 and R2 are the load resistances of the first-stage and second-stage current mode logic drivers respectively, and in the first-stage current mode logic driver, V op1 , V on1 Vd1 and Vd2 are the drain voltages of the two field effect transistors, which are also the differential output signals of the first-stage current mode logic driver, V s1 Vss is the voltage of the common source of the two field effect transistors, Ip1 and I n1 is the source-drain current of the two field effect transistors, V ip and V in is the gate voltage of the two field effect transistors, and is also the differential input signal of the first stage current-mode logic driver / low common-mode noise driver, I ss1 is the tail current source. Similarly, in the second stage current-mode logic driver, V op2 , V on2 is the drain voltage of the two field effect transistors, and is the differential output signal of the low common-mode noise driver, V s2 is the voltage of the common source of the two field effect transistors, I p2 and I n2 is the source-drain current of the two field effect transistors, the gates of the two field effect transistors are connected to the drains of the first stage current-mode logic driver, respectively, and the voltages are V op1 , V on1 , I ss1 is the tail current source. In this equivalent circuit model, each field effect transistor is equivalent to a voltage-controlled current source and four parasitic capacitances. Among them, the controlled current source I p1 , I n1 , I p2 , I n2 is used to equivalent the source-drain current of the field effect transistor, which is controlled by the gate-source voltage V GS and the source-drain voltage V DS of the corresponding field effect transistor, and the extracted field effect transistor voltage-controlled current function is I DS ( V GS , V DS ). In addition, the extracted parasitic capacitances of the field effect transistor are divided into gate-source capacitance, gate-drain capacitance, source junction capacitance, and drain junction capacitance according to the type, and the first two subscripts of their subscripts are gs , gd , js , jdThe third digit p or n of the parasitic capacitor subscript indicates whether the differential signal branch is p-branch or n-branch, and the fourth digit 1 or 2 indicates whether the current mode logic driver is the first or second level. Figure Three All capacitors listed, e.g. C gsp1 represents the gate-source parasitic capacitance of the FET under the p-branch of the first-stage current mode logic driver. In addition, Figure 3 In the figure, all currents are divided into different parts according to the nodes they are associated with. The blue part of the current is associated with the common source of each current mode logic driver stage; the orange part of the current is associated with the drain output of each current mode logic driver stage; and the green part of the current connects the output and input of the previous and next current mode logic drivers.

[0126] In the field-effect transistor (FET) equivalent circuit model used in the present invention, parasitic capacitance caused by the physical structure exists between either end of the FET. Because the gate metal layer and the oxide layer of the FET form a large parallel plate capacitor structure, the gate and source, as well as the gate and drain, of the FET have large parasitic capacitance values, and the magnitude of this type of parasitic capacitance will vary with the operating state of the FET. Taking an N-type FET as an example, when a negative voltage is applied between its gate metal layer and the substrate, the FET is in the cutoff region, the metal layer carries a negative charge, and the substrate induces a positive charge. At this time, the main contribution to the FET's parasitic capacitance is the oxide layer capacitance. When a smaller positive voltage is applied between the gate metal layer and the substrate, the direction of the electric field in the oxide layer is directed from the gate to the substrate. The carrier holes in the portion of the substrate below the oxide layer are repelled due to their positive charge, forming a space charge region in this portion of the substrate. At this time, the parasitic capacitance of the FET is mainly composed of the oxide layer capacitance and the space charge region capacitance in series, and the overall capacitance value decreases. When the positive voltage between the gate metal layer and the substrate increases, on the one hand, the space charge region gradually increases, resulting in a decrease in capacitance, and on the other hand, the inversion layer charge begins to gradually appear and increases the overall capacitance, so the overall capacitance value shows a trend of first decreasing and then increasing. Figure 3The physical structure of the parallel-plate capacitor affects the parasitic capacitances of the gate-source capacitance and the gate-drain capacitance. When the field effect transistor is in the cut-off region, both the gate-source capacitance and the gate-drain capacitance are contributed by the oxide layer capacitance of the field effect transistor. When the gate voltage of the field effect transistor begins to rise, the field effect transistor begins to change from the cut-off region to the saturation region. In this process, a conductive channel begins to form in the substrate of the field effect transistor. Although the source and the drain of the field effect transistor are symmetrical with respect to the gate in terms of the physical structure, the gate-drain voltage is often less than the gate-source voltage in the process of forming the conductive channel, and thus the charge of the conductive channel is often accumulated from the source to the drain. The increase of the channel charge capacitance causes the capacitance value between the gate and the source to continuously increase as the gate voltage increases. As for the gate-drain capacitance of the field effect transistor, due to the influence of the channel modulation effect, the pinch-off point of the conductive channel of the field effect transistor in the saturation region moves towards the source, and thus the channel will not be directly connected to the drain, and the gate-drain capacitance value is less affected by the channel charge and shows a relatively stable trend when the working region of the field effect transistor changes. In addition, different doping types at different positions of the field effect transistor can also cause PN junctions to form on the contact surface of the material (such as the N-doped source and the P-doped substrate in an N-type field effect transistor), resulting in junction capacitance. In the N-type field effect transistor used in the current-mode logic driver, the substrate is directly grounded, and thus both the two PN junctions at the source and the drain are in a reverse bias state. As the voltage of the source and the drain rises, the carriers are pulled away from the junction region. The decrease of the junction region charge will reduce the PN junction capacitance at the region.

[0127] The specific implementation of the present application is as follows:

[0128] First, the design requirements of the manufactured low common-mode noise driver are determined. The design requirements of the present embodiment are: (1) the channel impedance is 50 ohms, and the output impedance needs to be matched with the channel impedance; (2) the output swing reaches 0.4 volts. Therefore, under the design requirements, the size of the load resistance used by the second-stage current-mode logic driver is determined to be 50 ohms, and the size of the tail current is determined to be 8 milliamperes.

[0129] Second, the integrated circuit manufacturing process used to manufacture the low common-mode noise driver is selected. The manufacturing process used in the present embodiment is the TSMC 65 nanometer process. The field effect transistor devices under the selected process are parameter-extracted to obtain the five parameter models of the gate-source capacitance, the gate-drain capacitance, the source junction capacitance, the drain junction capacitance, and the source-drain current mentioned in the specification.

[0130] Based on the extracted field effect transistor parameter models and the equivalent model of the low common-mode noise driver mentioned in the foregoing specification, the circuit equation mentioned in the foregoing specification is established to solve a plurality of sets of to-be-optimized circuit parameters R L1 , I SS1) to predict the output common mode noise. The results are as follows Figure 5 As shown in the figure, it can be seen that the common mode noise of the low common mode noise driver proposed by the present invention is related to the circuit parameters to be optimized: the load resistance of the first stage current mode logic driver R L1 , the tail current of the first-stage current mode logic driver I SS1 Both are positively correlated. Figure 5 A set of circuit parameters corresponding to the minimum point of common mode noise ( R L1_min , I SS1_min ) as the optimization result of the driver circuit parameters. Figure 5 The functional relationship between the output common mode noise and the circuit parameters obtained in this embodiment shows that when the load resistance R L1 Take 178 ohms, tail current I ss1 At 4.04 mA, the driver's output common-mode noise reaches its minimum. Combined with the previously determined circuit parameters, the overall circuit parameters for the fabricated low common-mode noise driver are: the first-stage current-mode logic driver has a load resistor of 178 ohms and a tail current of 4.04 mA; the second-stage current-mode logic driver has a load circuit of 50 ohms and a tail current of 8 mA.

[0131] Figure 6 and Figure 7 The paper presents a comparison of the common-mode waveforms and spectra of the differential output signals of a low-common-mode noise driver and a single-stage current-mode logic driver (with a 50-ohm load resistor, 8-mA tail current, and the same field-effect transistor size and process as the low-common-mode noise driver). The input signal for this comparison is a 20-gigabit-per-second pseudo-random binary sequence (PRBS) signal. The time-domain common-mode waveforms of the differential output signals show that the fluctuations in the common-mode waveform of the proposed low-common-mode noise driver during input signal transitions (0-10 picoseconds) are significantly smaller than those of a conventional current-mode logic driver. A comparison of the common-mode spectra of the differential output signals shows that the proposed low-common-mode noise driver achieves approximately 16 decibels of noise reduction compared to a conventional current-mode logic driver at the primary signal frequency and its harmonic frequencies.

[0132] The above describes the preferred embodiments of the present application in detail in combination with the drawings. However, it is emphasized that the present application is not limited to the specific details of the above embodiments. Under the guidance of the technical concept and design idea of the present application, the technical solution of the present application has wide applicability and flexibility, and can be subjected to various simple and reasonable modifications. These modifications, although they may differ from the above embodiments in some aspects, are all based on the basic technical concept of the present application, and therefore should be considered as within the protection scope of the present application.

[0133] It is further explained that each technical feature mentioned in the above specific embodiments is an important part of the present application. These technical features can be combined in any suitable manner according to actual needs and specific application scenarios without violating the basic principles and functions of the present application. In order to save space and avoid unnecessary repetition, the present application does not describe each possible combination one by one. However, this does not mean that these combinations are not within the protection scope of the present application.

[0134] In addition, different embodiments of the present application also exhibit high compatibility and complementarity. On the basis of various embodiments, any combination and innovation can be carried out as long as they do not violate the core idea and goal of the present application. Such combinations and innovations not only enrich the technical content of the present application, but also expand its application field and improve its practical value. Therefore, these different embodiments and their combinations should also be considered as the disclosed technical content of the present application.

[0135] During the design and application of the present application, we encourage technicians to flexibly use and adjust the technical solution of the present application according to actual needs to achieve the best technical effect. At the same time, we also hope that technicians in the relevant field can continue to explore and research on the basis of the present application, and constantly promote technological progress to meet the needs of social development. The protection scope of the present application is not limited to the above embodiments, but also includes all modifications, combinations and innovations within the technical concept of the present application, which are all expected to be covered and protected by the present application.

Claims

1. A method for manufacturing a low common mode noise driver, characterized in that: The following steps are involved: S1. Establish a parasitic capacitance model of the field effect tube according to the performance parameters of the field effect tube, and establish an equivalent circuit model of the low common mode noise driver according to the parasitic capacitance model; The low common-mode noise driver includes two cascaded current-mode logic drivers; The input terminal of the first-stage current mode logic driver serves as the input terminal of the low common mode noise driver, the output terminal of the first-stage current mode logic driver is electrically connected to the input terminal of the second-stage current mode logic driver, and the output terminal of the second-stage current mode logic driver serves as the output terminal of the low common mode noise driver; The first-stage current mode logic driver receives a pair of differential input signals from the output end of the digital processing module at the high-speed interface transmitting end and pre-processes the differential input signals. The first-stage current mode logic driver outputs a first-stage differential output signal and serves as a differential input of the second-stage current mode logic driver. The second-stage current mode logic driver serves as an output driver and outputs a pair of differential output signals to the channel. Each current mode logic driver includes two N-type field effect transistors with a common source, the common source is grounded via a constant current source, the drains of the two field effect transistors are connected to a power supply via two load resistors of equal resistance, the gates of the two field effect transistors serve as input terminals of the current mode logic driver, and the drains of the two field effect transistors serve as output terminals of the current mode logic driver; The parasitic capacitance model includes the gate-drain parasitic capacitance, gate-source parasitic capacitance, drain junction capacitance and source junction capacitance of the field effect tube at each DC operating point; S2. Setting the values ​​of the load resistance and tail current of the second-stage current mode logic driver, and the optimization range of the product of the load resistance and tail current of the first-stage current mode logic driver; Under different values ​​of the circuit parameters to be optimized, the dynamic response of the driver during the input signal reversal process is analyzed for the equivalent circuit model of the low common-mode noise driver, and the time domain response waveform of the output node voltage to the input signal reversal is obtained; Considering the influence of all parasitic capacitances, based on V op1 、 V on1 、 V s1 、 V op2 、 V on2 、 V s2 Kirchhoff's current law for the six output node voltages gives the equations for dynamic analysis: List the equations for the source-drain current of the field-effect transistor with respect to the output voltage to be solved; V op1 、V on1 are the drain voltages of the two field-effect transistors in the first-stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first-stage current mode logic driver, V op2 、V on2 are the drain voltages of the two field-effect transistors in the second-stage current mode logic driver, V s2 is the voltage of the common source of the two field effect transistors in the second-stage current mode logic driver; List the set of equations for the current flowing through the load resistor and the output voltage to be solved; List the equations for the current flowing through the parasitic capacitance with respect to the output voltage to be solved; The above equations are solved numerically to predict the output time domain waveform of the low common-mode noise driver proposed in the present invention, thereby obtaining the output time domain waveform of the low common-mode noise driver. The output time domain waveform is the time domain response waveform of the output node voltage when the input signal is reversed. Based on the time domain response waveform of the output node voltage when the input signal is reversed under each set of circuit parameters to be optimized, the time domain waveform of the output signal common mode noise is obtained by taking the common mode component of the differential output signal; S3. Predict the output common-mode noise based on the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized, and obtain a relationship function between the circuit parameters to be optimized and the output signal common-mode noise. From the relationship function, obtain the circuit parameters to be optimized corresponding to the minimum value of the output signal common-mode noise as the optimal circuit parameters, and manufacture a low common-mode noise driver based on the optimal circuit parameters.

2. The method for manufacturing a low common mode noise driver according to claim 1, wherein: In step S1, the circuit equation of the equivalent circuit model is specifically: V op1 =V DD -R L1 I p1 V on1 =V DD -R L1 I n1 I p1 =I ds (V ip -V s1 ,V op1 -V s1 ) I n1 =I ds (V in -V s1 ,V on1 -V s1 ) I ss1 =I p1 + I n1 V op2 =V DD -R L2 I p2 V on2 =V DD -R L2 I n2 I p2 =I ds (V op1 -V s2 ,V op2 -V s2 ) I p2 =I ds (V on1 -V s2 ,V op2 -V s2 ) I ss2 =I p2 + I n2 Where V DD is the power supply voltage, R L1 、R L2 They are the load resistances of the first-stage current mode logic driver and the second-stage current mode logic driver, V op1 、V on1 are the drain voltages of the two field-effect transistors in the first-stage current mode logic driver, V s1 is the voltage of the common source of the two field effect transistors in the first-stage current mode logic driver, I p1 , I n1 are the source and drain currents of the two field effect transistors in the first-stage current mode logic driver, V ip 、V in are the gate voltages of the two field effect transistors in the first-stage current mode logic driver, I ss1 It is the tail current source of the first-stage current mode logic driver; V op2 、V on2 are the drain voltages of the two field-effect transistors in the second-stage current mode logic driver, V s2 is the voltage of the common source of the two field effect transistors in the second-stage current mode logic driver, I p2 and I n2 are the source and drain currents of the two field effect transistors in the second-stage current mode logic driver, I ss2 is the tail current source for the second-stage current mode logic driver, I ds (V gs ,V ds ) is the source leakage current of the field effect transistor with respect to the gate-source voltage V gs and source-drain voltage V ds Functional relationship.

3. The method for manufacturing a low common mode noise driver according to claim 1, wherein: In step S3, the process of predicting the output common-mode noise is specifically as follows: performing Fourier transform on the time domain waveform of the output signal common-mode noise under each set of circuit parameters to be optimized to obtain the frequency spectrum of the output signal common-mode noise, taking the maximum value of the AC component in the common-mode part frequency spectrum of the output signal common-mode noise as the output signal common-mode noise corresponding to the circuit parameters to be optimized, and obtaining the functional relationship between the circuit parameters to be optimized and the output signal common-mode noise.

4. The method for manufacturing a low common mode noise driver according to claim 1, wherein: The load resistance of the second-stage current mode logic driver is matched to the channel impedance; The product of the load resistance and tail current of the second-stage current mode logic driver matches the target output swing of the low common-mode noise driver; The product of the load resistance and the tail current of the first-stage current mode logic driver is greater than or equal to the critical swing of the second-stage current mode logic driver.

5. The method for manufacturing a low common mode noise driver according to claim 1, wherein: The drains of the two field effect transistors of the first-stage current mode logic driver are electrically connected to the gates of the two field effect transistors of the second-stage current mode logic driver respectively.

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