Flexible braille recognition processing circuit based on LTPO TFT

Abstract

The invention relates to a flexible braille recognition processing circuit based on LTPO TFT, belongs to the technical field of integrated circuits, and solves the problem of poor wearing performance of a braille recognition circuit in the prior art. Comprising six flexible touch sensors which correspond to six points of a braille unit respectively and are used for sensing external pressure signals and converting the pressure signals of braille to be recognized into current signals; the six voltage comparators are connected with the flexible tactile sensors in a one-to-one correspondence mode and used for converting current signals input by the flexible tactile sensors into six corresponding digital signals; wherein when the points in the braille units are salient points, the corresponding digital signal value is 1; when the point is a flat point, the corresponding digital signal value is 0; the conversion circuit is used for converting the six digital signals to obtain corresponding output signals; wherein the output signal represents a letter represented by the braille alphabet to be recognized by using a binary system. Flexible wearing of the braille recognition circuit is realized, and full output swing and low power consumption are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a flexible Braille recognition processing circuit based on LTPO TFT. Background Art

[0002] Unlike traditional semiconductor devices, flexible electronics utilize active thin-film semiconductor materials that can be fabricated on flexible substrates such as plastic, paper or metal foil. Flexible electronics have many advantages over crystalline silicon, including being thin, adaptable and low-cost to manufacture. Thin-film transistors (TFTs) can be fabricated on flexible substrates at much lower processing costs than metal oxide semiconductor field effect transistors (MOSFETs) fabricated on crystalline silicon wafers.

[0003] In today's society, blind people still face many difficulties in life and work, the most basic of which is the inability to distinguish visual information. Therefore, Braille recognition technology has become a research hotspot. Its main purpose is to convert paper Braille into speech through electronic devices to facilitate reading for blind people. In the Braille recognition system, the Braille recognition processing circuit is one of the core components. Its main task is to analyze and respond to the input tactile signals, and finally accurately recognize the Braille characters. At present, Braille recognition processing circuits have been widely used in Braille electronic readers and other auxiliary devices. However, most of these processing circuits are manufactured on rigid substrates, which brings great inconvenience to users in the process of wearing these electronic devices. Flexible electronics can solve this wearable problem very well. In the past 20 years, flexible electronics technology has developed to provide mature low-cost, highly flexible and adaptable devices, including sensors, memory and other circuits. CMOS circuits based on LTPO TFT are widely used in the field of Internet of Things due to their advantages such as full output swing, low power consumption, three-dimensional integration and low-cost manufacturing. There is currently no specialized flexible processing circuit for Braille recognition. Therefore, as an important part of the Braille recognition system, the research and development of Braille recognition processing circuits is of great significance to improving the quality of life and work of the blind. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a flexible Braille recognition processing circuit based on LTPO TFT to solve the problem of poor wearability of Braille recognition circuits in the prior art.

[0005] On the one hand, an embodiment of the present invention provides a flexible Braille recognition processing circuit based on LTPO TFT, including 6 flexible tactile sensors, 6 voltage comparators and a conversion circuit;

[0006] The six flexible tactile sensors correspond to the six points of the Braille unit respectively, and are used to sense the external pressure signal and convert the pressure signal of the Braille to be recognized into a current signal;

[0007] The six voltage comparators are connected to the flexible tactile sensors one by one, respectively, and are used to convert the current signal input by the flexible tactile sensor into six corresponding digital signals; wherein, when the dot in the Braille unit is a convex dot, the corresponding digital signal value is 1; when it is a flat dot, the corresponding digital signal value is 0;

[0008] The conversion circuit is used to convert the six digital signals into corresponding output signals; wherein the output signal uses binary to represent the letters represented by the Braille to be recognized.

[0009] Furthermore, the flexible tactile sensor is a thin film pressure sensor, and the thin film pressure sensor array is integrated on a flexible FPC board.

[0010] Furthermore, the conversion circuit includes 6 inverters, a plurality of AND gates and a plurality of XOR gates; wherein the 6 inverters invert the 6 digital signals respectively to obtain 6 inverted digital signals;

[0011] Based on 6 digital signals and 6 inverted digital signals, AND operations and XOR operations are performed using the AND gates and XOR gates to obtain 5 outputs, which are represented as OUT0, OUT1, OUT2, OUT3 and OUT4 in order from low to high binary bits.

[0012] Furthermore, the six digital signals are a, b, c, d, e, and f; the six inverted digital signals are !a, !b, !c, !d, !e, !f;

[0013] The process of obtaining OUT0 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes:

[0014] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the first AND result;

[0015] Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result;

[0016] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result;

[0017] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0018] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result;

[0019] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0020] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0021] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0022] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result;

[0023] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0024] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0025] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0026] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0027] An XOR gate is used to perform XOR operations on the first to thirteenth AND results in sequence to obtain an output result OUT0.

[0028] Furthermore, the process of obtaining the OUT1 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0029] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourteenth AND result;

[0030] Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result;

[0031] Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result;

[0032] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0033] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result;

[0034] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0035] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0036] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0037] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result;

[0038] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0039] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0040] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0041] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0042] The fourteenth, second, fifteenth, fourth, sixteenth, sixth, seventeenth, eighth, eighteenth, tenth, nineteenth, twelfth and twentieth AND results are sequentially XORed by an XOR gate to obtain an output result OUT1.

[0043] Furthermore, the process of obtaining OUT2 by performing AND operation and XOR operation on the plurality of AND gates and the plurality of XOR gates includes:

[0044] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-first AND result;

[0045] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result;

[0046] Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result;

[0047] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0048] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result;

[0049] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0050] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0051] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0052] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result;

[0053] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0054] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0055] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0056] The twenty-first, third, fifteenth, fourth, twenty-second, seventh, seventeenth, eighth, twenty-third, eleventh, nineteenth and twelfth numbers are XORed with the results in sequence using an XOR gate to obtain an output result OUT2.

[0057] Furthermore, the process of obtaining OUT3 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0058] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fourth AND result;

[0059] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result;

[0060] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result;

[0061] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0062] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result;

[0063] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0064] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0065] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0066] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result;

[0067] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0068] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0069] The twenty-fourth, fifth, sixteenth, sixth, twenty-second, seventh, seventeenth, eighth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT3.

[0070] Furthermore, the process of obtaining the OUT4 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0071] Use the AND gate to perform AND operations on a, b, c, !d, e, !f in sequence to obtain the twenty-sixth AND result;

[0072] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result;

[0073] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result;

[0074] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0075] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result;

[0076] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0077] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0078] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0079] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result;

[0080] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0081] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0082] The twenty-sixth, ninth, eighteenth, tenth, twenty-third, eleventh, nineteenth, twelfth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT4.

[0083] Furthermore, the basic building blocks of the voltage comparator, inverter, AND gate and XOR gate are all LTPOTFTs, which are integrated on the flexible FPC board; wherein the N-tube is an a-IGZO TFT manufactured with a back-channel etching structure, and the P-tube is a PTPSTFT manufactured with a coplanar structure.

[0084] Furthermore, the channel width-to-length ratio of the N-tube is W / L=5, and the channel width-to-length ratio of the P-tube is W / L=1 / 6.

[0085] Compared with the prior art, the present invention can at least achieve the following beneficial effects:

[0086] The present application uses components that can be realized with flexible materials. By using flexible materials for tactile sensors, voltage comparators and conversion circuits and manufacturing them on flexible substrates, the problem of poor wearability is solved. At the same time, thin-film transistors have lower processing costs than silicon-based chips, so they can be widely used in the fields of Internet of Things, medical health, wearable consumer electronics, etc.; through the combination of simple circuits of voltage comparators, inverters, AND gates and XOR gates, 6 digital signal inputs and 5 binary signal outputs of the Braille unit are realized. Compared with the existing Braille recognition circuit, the circuit in the present application is simpler and easier to implement; it can realize CMOS (Complementary Metal Oxide Semiconductor) circuits. The circuit designed by this method has the advantages of full output swing, low power consumption, high performance, etc. compared with other unipolar flexible integrated circuits.

[0087] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0089] Figure 1 This is a schematic diagram of the Braille recognition processing circuit for this application;

[0090] Figure 2 It is a schematic diagram of an XOR gate circuit of a flexible Braille recognition processing circuit based on LTPO TFT of the present invention;

[0091] Figure 3 It is a schematic diagram of an inverter circuit of a flexible Braille recognition processing circuit based on LTPO TFT of the present invention;

[0092] Figure 4 It is a schematic diagram of an AND gate circuit of a flexible Braille recognition processing circuit based on LTPO TFT of the present invention;

[0093] Figure 5 A schematic diagram of a comparator circuit of a flexible Braille recognition processing circuit based on LTPO TFT of the present invention;

[0094] Figure 6 is a schematic diagram of a Braille unit;

[0095] Figure 7 is the truth table for the 26-letter Braille unit;

[0096] Figure 8 This is a schematic diagram of an XOR gate circuit;

[0097] Fig. 9 This is a schematic diagram of an AND gate circuit;

[0098] Fig.10 is a schematic diagram of an inverter circuit;

[0099] Fig.11 This is the schematic diagram of the voltage comparator circuit;

[0100] Fig.12 This is the circuit simulation result diagram for this application. DETAILED DESCRIPTION

[0101] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0102] A specific embodiment of the present invention discloses a flexible Braille recognition processing circuit based on LTPO TFT, such as Figures 1 to 5 As shown. It includes 6 flexible tactile sensors, 6 voltage comparators and conversion circuits;

[0103] The six flexible tactile sensors correspond to the Braille units (such as Figure 6 The six points (as shown) are used to sense external pressure signals and convert the pressure signals of the Braille to be recognized into current signals;

[0104] The six voltage comparators are connected to the flexible tactile sensors one by one, respectively, and are used to convert the current signal input by the flexible tactile sensor into six corresponding digital signals, that is, Figure 7 The truth table shown in FIG. 1 ; wherein, when the dot in the Braille unit is a convex dot, the corresponding digital signal value is 1; when it is a flat dot, the corresponding digital signal value is 0;

[0105] The conversion circuit is used to convert the six digital signals into corresponding output signals; wherein the output signal uses binary to represent the letters represented by the Braille to be recognized.

[0106] Furthermore, the flexible tactile sensor is a thin film pressure sensor, and the thin film pressure sensor array is integrated on a flexible FPC board.

[0107] Specifically, according to the characteristics of the piezoresistive film on the thin film pressure sensor, the greater the pressure, the smaller the resistance. Taking the letter A as an example, the first dot of the Braille unit is a convex dot, the pressure is large, the resistance is small, and the output signal a through the voltage comparator is 1. The remaining five dots are flat dots, the pressure is small, the resistance is large, and the output signal b=c=d=e=f through the voltage comparator is 0.

[0108] Furthermore, the conversion circuit includes 6 inverters, a number of AND gates and a number of XOR gates; wherein,

[0109] The six inverters respectively invert the six digital signals to obtain six inverted digital signals;

[0110] Based on 6 digital signals and 6 inverted digital signals, AND operations and XOR operations are performed using the AND gates and XOR gates to obtain 5 outputs, which are represented as OUT0, OUT1, OUT2, OUT3 and OUT4 in order from low to high binary bits.

[0111] Furthermore, the six digital signals are a, b, c, d, e, and f; the six inverted digital signals are !a, !b, !c, !d, !e, !f;

[0112] Specifically, Figure 3 As shown, the output of a after the inverter is N107 is !a; the output of b after the inverter is N103 is !b, the output of c after the inverter is N1 is !c, the output of d after the inverter is N3 is !d, the output of e after the inverter is N5 is !e, and the output of f after the inverter is N6 is !f.

[0113] The process of obtaining OUT0 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes:

[0114] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the first AND result;

[0115] Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result;

[0116] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result;

[0117] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0118] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result;

[0119] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0120] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0121] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0122] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result;

[0123] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0124] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0125] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0126] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0127] An XOR gate is used to perform XOR operations on the first to thirteenth AND results in sequence to obtain an output result OUT0.

[0128] Furthermore, the process of obtaining the OUT1 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0129] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourteenth AND result;

[0130] Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result;

[0131] Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result;

[0132] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0133] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result;

[0134] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0135] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0136] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0137] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result;

[0138] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0139] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0140] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0141] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0142] The fourteenth, second, fifteenth, fourth, sixteenth, sixth, seventeenth, eighth, eighteenth, tenth, nineteenth, twelfth and twentieth AND results are sequentially XORed by an XOR gate to obtain an output result OUT1.

[0143] Furthermore, the process of obtaining OUT2 by performing AND operation and XOR operation on the plurality of AND gates and the plurality of XOR gates includes:

[0144] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-first AND result;

[0145] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result;

[0146] Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result;

[0147] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result;

[0148] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result;

[0149] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0150] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0151] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0152] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result;

[0153] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0154] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0155] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0156] The twenty-first, third, fifteenth, fourth, twenty-second, seventh, seventeenth, eighth, twenty-third, eleventh, nineteenth and twelfth numbers are XORed with the results in sequence using an XOR gate to obtain an output result OUT2.

[0157] Furthermore, the process of obtaining OUT3 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0158] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fourth AND result;

[0159] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result;

[0160] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result;

[0161] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result;

[0162] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result;

[0163] Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result;

[0164] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result;

[0165] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result;

[0166] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result;

[0167] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0168] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0169] The twenty-fourth, fifth, sixteenth, sixth, twenty-second, seventh, seventeenth, eighth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT3.

[0170] Furthermore, the process of obtaining the OUT4 by performing AND operations and XOR operations on the plurality of AND gates and the plurality of XOR gates includes:

[0171] Use the AND gate to perform AND operations on a, b, c, !d, e, !f in sequence to obtain the twenty-sixth AND result;

[0172] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result;

[0173] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result;

[0174] Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result;

[0175] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result;

[0176] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result;

[0177] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result;

[0178] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result;

[0179] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result;

[0180] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result;

[0181] Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result;

[0182] The twenty-sixth, ninth, eighteenth, tenth, twenty-third, eleventh, nineteenth, twelfth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT4.

[0183] like Figure 2 As shown, OUT0 is obtained by XOR operation of N59 and N33, which is expressed as:

[0184] OUT0=N59⊕N33=N58⊕N30⊕N33=N57⊕N27⊕N30⊕N33=……=N10 ⊕N48⊕N12⊕N15⊕N18⊕N20⊕N22⊕N24⊕N25⊕N26⊕N27⊕N30⊕N33

[0185] N10, N48, N12, N15, N18, N20, N22, N24, N25, N26, N27, N30, N33 correspond to the first to thirteenth results.

[0186] like Figure 4 As shown, taking N10 as an example: N10 = N104 & N6 = N9 & N5 & N6 = N8 & N3 & N5 & N6 = N7 & N1 & N3 & N5 & N6 = a & b & N1 & N3 & N5 & N6; and N1 is !c, N3 is !b, N5 is !e, N6 is !f; that is, the second AND result of a, b, !c, !d, !e, !f. The other AND results can be obtained in the same way.

[0187] Similarly, OUT1~OUT4 can be obtained.

[0188] Furthermore, the basic building blocks of the voltage comparator, inverter, AND gate and XOR gate are all LTPOTFTs, which are integrated on the flexible FPC board; wherein the N-tube is an a-IGZO TFT manufactured with a back-channel etching structure, and the P-tube is a PTPSTFT manufactured with a coplanar structure.

[0189] Specifically, Fig.11 , which is a circuit diagram of a voltage comparator, including: first to seventh P tubes, first to eighth N tubes;

[0190] The gate of the first P tube is connected to the gate of the first N tube, the drain of the first P tube is connected to the drain and gate of the first N tube, the gate of the second N tube is connected to the output end of the flexible tactile sensor as the input end of the voltage comparator, the drain of the second N tube is connected to the drain, gate of the second P tube and the gate of the third P tube, the source of the second N tube is connected to the drain of the third N tube and the source of the fourth N tube, the gate of the third N tube is connected to the drain of the first N tube, the gate of the fourth N tube and the gate of the fifth N tube, the drain of the fourth N tube is connected to the drain of the third P tube and the source of the fourth P tube The drain of the fourth P tube is connected to the drain of the fifth N tube, the gate of the fifth P tube and the gate of the sixth N tube, the drain of the fifth P tube is connected to the drain of the sixth N tube, the gate of the sixth P tube and the gate of the seventh N tube, the drain of the sixth P tube is connected to the drain of the seventh N tube, the gate of the seventh P tube and the gate of the eighth N tube, the drain of the seventh P tube is connected to the drain of the eighth N tube and serves as the output end of the voltage comparator, the source of the first P tube to the seventh P tube is connected to VDD, and the source of the first N tube, the third N tube, the fifth N tube to the eighth N tube is connected to GND.

[0191] Specifically, Fig.10 , which is a circuit diagram of an inverter, including an eighth P tube and a ninth N tube;

[0192] The gates of the eighth P tube and the ninth N tube are both connected to the output end of the voltage comparator, the source of the eighth P tube is connected to VDD, the source of the ninth N tube is grounded, the drain of the eighth P tube is connected to the drain of the ninth N tube, and serves as the output end of the inverter.

[0193] Specifically, Fig. 9 , which is a circuit diagram of an AND gate, including ninth to eleventh P tubes and tenth to twelfth N tubes;

[0194] The gate of the ninth P tube is connected to the gate of the tenth N tube as the first input end of the AND gate circuit, the drain of the ninth P tube is connected to the drain of the tenth P tube, the drain of the tenth N tube, the gate of the eleventh P tube and the gate of the twelfth N tube, the source of the tenth N tube is connected to the drain of the eleventh N tube, the gate of the tenth P tube is connected to the gate of the eleventh N tube as the second input end of the AND gate circuit, the drain of the eleventh P tube is connected to the drain of the twelfth N tube as the output end of the AND gate circuit, the sources of the ninth P tube to the tenth P tube are connected to VDD, and the sources of the eleventh N tube and the twelfth N tube are connected to GND.

[0195] Specifically, Figure 8 , which is a circuit diagram of an XOR gate, including 12th to 16th P tubes and 13th to 17th N tubes;

[0196] The gate of the thirteenth P tube is connected to the gates of the fourteenth N tube, the fifteenth N tube and the fifteenth P tube, serving as the first input terminal of the XOR gate; the source of the thirteenth P tube is connected to the drain of the twelfth P tube; the drain of the thirteenth P tube is connected to the drain of the thirteenth N tube, the drain of the fourteenth N tube, the sixteenth P tube and the gates of the seventeenth N tube; the source of the fifteenth N tube is connected to the drain of the sixteenth N tube; the drain of the fourteenth P tube is connected to the drain of the fifteenth P tube and the source of the sixteenth P tube;

[0197] The gate of the twelfth P tube is connected to the gate of the thirteenth N tube, the third stage of the fourteenth P tube and the gate of the sixteenth N tube as the second input end of the XOR gate, the drain of the fifteenth N tube is connected to the drain of the sixteenth P tube and the seventeenth N tube as the output end of the XOR gate, the source of the twelfth P tube, the fourteenth P tube and the fifteenth P tube is connected to VDD, and the source of the thirteenth N tube, the fourteenth N tube, the sixteenth N tube and the seventeenth N tube is connected to GND.

[0198] The basic building block of this circuit is the LTPO thin-film transistor, and whether the circuit function can be realized depends on the characteristics of the thin-film transistor. According to the device model provided by the process manufacturer, the functional simulation of the circuit of this application was completed. The simulation process is: adjust the resistance value of the front end of the voltage comparator, the low resistance value is 30kΩ, and the high resistance value is 900kΩ. This process simulates the actual resistance change of the pressure sensor when it contacts the Braille characters. Through the principle of series voltage division, the voltage comparator outputs the low resistance state as a high level and the high resistance state as a low level. After the response of the digital circuit, a binary value of 1-26 is finally obtained on the output port, representing the 26 English characters of AZ respectively.

[0199] Instance, Figure 5 The resistors R0-R5 are the resistance values ​​of the flexible tactile sensors used for each Braille unit pair, such as Fig.12As shown, it is the correct simulation result of the Braille unit output of the letter F, OUT4 = 2.4uV, OUT3 = 2.4uV, OUT2 = 10V, OUT1 = 10V, OUT0 = 2.4uV, corresponding to the binary 00110;

[0200] When the six points of the Braille unit recognized by the flexible tactile sensor are 111000 respectively, the resistance values ​​of the flexible tactile sensor are Ra=Rb=Rc=30kΩ, Rd=Re=Rf=900kΩ respectively. The digital signal 111000 is input into the flexible Braille recognition processing circuit for operation and calculation to obtain 00110, which corresponds to the decimal number 6, that is, the letter F, which is consistent with the simulation result output by the Braille unit, that is, the flexible Braille recognition processing circuit recognizes the letter F.

[0201] Specifically, the processing process of the digital circuit is the conversion of high and low levels. According to the circuit schematic diagram provided by the present invention, as long as the input signal is given, the digital logic circuit will give a specific response according to the connection relationship.

[0202] Furthermore, the channel width-to-length ratio of the N-tube is W / L=5, and the channel width-to-length ratio of the P-tube is W / L=1 / 6.

[0203] Specifically, by reasonably setting the width-to-length ratio of the N-tube and the P-tube, a symmetrical inverter voltage transfer characteristic curve (VTC) can be obtained, which can ensure that the low-level noise margin and the high-level noise margin of the inverter have the same value. In this design, the low-level noise margin is 3.15V, the high-level noise margin is 3.04V, and the power supply voltage is 10V.

[0204] Compared with the prior art, the flexible Braille recognition processing circuit based on LTPO TFT provided in this embodiment is composed of components that can be realized by flexible materials. By using flexible materials for tactile sensors, voltage comparators and conversion circuits and manufacturing them on flexible substrates, the problem of poor wearability is solved. At the same time, thin-film transistors have lower processing costs than silicon-based chips, so they can be widely used in the fields of Internet of Things, medical health, wearable consumer electronics, etc.; through the combination of simple circuits of voltage comparators, inverters, AND gates and XOR gates, 6 digital signal inputs and 5 binary signal outputs of the Braille unit are realized. Compared with the existing Braille recognition circuit, the circuit in this application is simpler and easier to implement; it can realize CMOS (Complementary Metal Oxide Semiconductor) circuits, and the circuit designed by this method has the advantages of full output swing, low power consumption, high performance, etc. compared with other unipolar flexible integrated circuits.

[0205] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0206] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A flexible Braille recognition processing circuit based on LTPO TFT, characterized in that: It includes 6 flexible tactile sensors, 6 voltage comparators and conversion circuits; The six flexible tactile sensors correspond to the six points of the Braille unit respectively, and are used to sense the external pressure signal and convert the pressure signal of the Braille to be recognized into a current signal; The six voltage comparators are connected to the flexible tactile sensors one by one, respectively, and are used to convert the current signal input by the flexible tactile sensor into six corresponding digital signals; wherein, when the dot in the Braille unit is a convex dot, the corresponding digital signal value is 1; when it is a flat dot, the corresponding digital signal value is 0; The conversion circuit is used to convert the six digital signals into corresponding output signals; wherein the output signal uses binary to represent the letters represented by the Braille to be recognized.

2. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 1, characterized in that: The flexible tactile sensor is a thin film pressure sensor, and the thin film pressure sensor array is integrated on a flexible FPC board.

3. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 2, characterized in that: The conversion circuit includes 6 inverters, a plurality of AND gates and a plurality of XOR gates; wherein the 6 inverters respectively invert the 6 digital signals to obtain 6 inverted digital signals; Based on 6 digital signals and 6 inverted digital signals, AND operations and XOR operations are performed using the AND gates and XOR gates to obtain 5 outputs, which are represented as OUT0, OUT1, OUT2, OUT3 and OUT4 in order from low to high binary bits.

4. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 3, characterized in that: The 6 digital signals are a, b, c, d, e, and f; the 6 inverted digital signals are !a, !b, !c, !d, !e, !f; The process of obtaining OUT0 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes: Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the first AND result; Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result; Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result; An XOR gate is used to perform XOR operations on the first to thirteenth AND results in sequence to obtain an output result OUT0.

5. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 4, characterized in that: The process of obtaining the OUT1 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes: Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourteenth AND result; Use the AND gate to perform AND operations on a, b, !c, !d, !e, !f in sequence to obtain the second AND result; Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result; The fourteenth, second, fifteenth, fourth, sixteenth, sixth, seventeenth, eighth, eighteenth, tenth, nineteenth, twelfth and twentieth AND results are sequentially XORed by an XOR gate to obtain an output result OUT1.

6. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 5, characterized in that: The process of obtaining OUT2 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes: Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-first AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the third AND result; Use the AND gate to perform AND operations on a, b, c, !d, !e, !f in sequence to obtain the fifteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the fourth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result; Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result; Use an XOR gate to perform XOR operations on the twenty-first, third, fifteenth, fourth, twenty-second, seventh, seventeenth, eighth, twenty-third, eleventh, nineteenth and twelfth numbers and the results in sequence to obtain an output result OUT2.

7. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 6, characterized in that: The process of obtaining OUT3 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes: Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fourth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the fifth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the sixteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the sixth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-second AND result; Use the AND gate to perform AND operations on a, b, !c, !d, e, !f in sequence to obtain the seventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the seventeenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result; The twenty-fourth, fifth, sixteenth, sixth, twenty-second, seventh, seventeenth, eighth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT3.

8. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 2, characterized in that: The process of obtaining the OUT4 by performing AND operation and XOR operation through the plurality of AND gates and the plurality of XOR gates includes: Use the AND gate to perform AND operations on a, b, c, !d, e, !f in sequence to obtain the twenty-sixth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the ninth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eighteenth AND result; Use the AND gate to perform AND operations on !a, !b, !c, !d, !e, !f in sequence to obtain the tenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-third AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the eleventh AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the nineteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twelfth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twenty-fifth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the thirteenth AND result; Use the AND gate to perform AND operations on a, b, c, d, e, and f in sequence to obtain the twentieth AND result; The twenty-sixth, ninth, eighteenth, tenth, twenty-third, eleventh, nineteenth, twelfth, twenty-fifth, thirteenth and twentieth AND results are XORed in sequence using an XOR gate to obtain an output result OUT4.

9. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 3, characterized in that: The basic building blocks of the voltage comparator, inverter, AND gate and XOR gate are all LTPO TFTs, which are integrated on the flexible FPC board; wherein the N-tube is an a-IGZO TFT manufactured with a back-etching structure, and the P-tube is a PTPS TFT manufactured with a coplanar structure.

10. The flexible Braille recognition processing circuit based on LTPO TFT according to claim 9, characterized in that: The channel width-to-length ratio of the N-tube is W / L=5, and the channel width-to-length ratio of the P-tube is W / L=1 / 6.

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