Phase-locked loop circuit and operating method thereof

Abstract

There is provided a phase-locked loop circuit including: a phase frequency detection circuit configured to receive a reference clock signal and a feedback clock signal having a first phase difference from each other, adjust a phase gain based on the first phase difference, and generate a first control signal and a second control signal based on the phase gain; a lock detection circuit configured to: generate a lock detection signal based on the first phase difference; a charge pump circuit configured to: generate a loop filter input signal based on the first control signal and the second control signal; a loop filter configured to: adjust an impedance based on the activated lock detection signal, and generate a loop filter output signal based on the adjusted impedance; an oscillator configured to: generate a clock signal based on the loop filter output signal; and a frequency divider configured to generate a feedback clock signal by dividing the clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0106419 filed in the Korean Intellectual Property Office on August 14, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a phase-locked loop circuit, and more particularly, to a phase-locked loop circuit that controls a loop filter based on a change in phase gain, and a method of operating the phase-locked loop circuit. Background Art

[0004] As the clock frequency of integrated circuits increases, methods of improving noise such as jitter have been studied. A phase-locked loop circuit using a time-amplified phase frequency detector can reduce in-band noise by increasing the gain of the phase frequency detector when the phase error is small and reducing the gain of the phase frequency detector when the phase error is large. Summary of the invention

[0005] The present disclosure relates to a phase-locked loop circuit for controlling a loop filter, and more particularly, to a phase-locked loop circuit for reducing a locking time required for a stable clock signal.

[0006] According to one aspect of the present disclosure, a phase-locked loop circuit is provided, comprising: a phase frequency detection circuit configured to receive a reference clock signal and a feedback clock signal, adjust a phase gain based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and generate a first control signal and a second control signal based on the phase gain; a lock detection circuit configured to generate a lock detection signal, which is activated based on the first phase difference being less than the reference value; a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on a first control signal and discharging the output node based on a second control signal; a loop filter comprising at least one resistor and at least one capacitor, the loop filter configured to adjust an impedance based on an activated lock detection signal, and generate a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance; an oscillator configured to generate a clock signal based on the loop filter output signal; and a frequency divider configured to generate a feedback clock signal by dividing the clock signal.

[0007] According to another aspect of the present disclosure, a method for operating a phase-locked loop circuit is provided, the method comprising: adjusting a phase gain based on a first phase difference between a reference clock signal and a feedback clock signal; generating a first control signal and a second control signal based on the adjusted phase gain; generating a lock detection signal based on the first phase difference, the lock detection signal being activated based on the first phase difference being less than or equal to a reference value, and the lock detection signal being deactivated based on the first phase difference exceeding the reference value; generating a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal; adjusting an impedance of the loop filter based on the lock detection signal; generating a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance; and generating a clock signal based on the loop filter output signal.

[0008] According to another aspect of the present disclosure, a phase-locked loop circuit is provided, comprising: a phase frequency detection circuit configured to receive a reference clock signal and a feedback clock signal, adjust a phase gain based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and generate a first control signal and a second control signal based on the phase gain; a lock detection circuit configured to generate a lock detection signal, which is activated based on the first phase difference being less than or equal to the reference value; a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on a first control signal and discharging the output node based on a second control signal; a loop filter comprising at least one resistor and at least one capacitor, the loop filter configured to adjust a resistance value of at least one resistor or a capacitance value of at least one capacitor based on an activated lock detection signal, and generate a loop filter output signal by filtering the loop filter input signal based on the adjusted resistance value or the adjusted capacitance value; and an oscillator configured to generate a clock signal based on the loop filter output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a phase-locked loop circuit according to an embodiment;

[0011] Figure 2 is a diagram for explaining a phase gain according to an embodiment;

[0012] Figure 3 is a circuit diagram showing a phase frequency detector according to an embodiment;

[0013] Figure 4 is a circuit diagram of a first time amplifier according to an embodiment;

[0014] Figure 5 is a detailed circuit diagram of a first time amplifier according to an embodiment;

[0015] Figure 6 is a timing chart for explaining the operation of the phase frequency detector according to the embodiment;

[0016] Fig. 7A and Figure 7B is a timing diagram for illustrating the relationship between the input phase difference and the output phase difference;

[0017] Figure 8 is a circuit diagram showing a lock detector according to an embodiment; and

[0018] Fig. 9 is a circuit diagram showing a charge pump and a loop filter according to an embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0020] The following detailed description is provided to help the reader obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to those order of operations set forth herein, but can be significantly changed after understanding the disclosure of the present application, except for operations that must be performed in a certain order. In addition, for greater clarity and brevity, the description of features known after understanding the disclosure of the present application may be omitted.

[0021] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0022] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, it may be directly "connected to" or "coupled to" the other component, or there may be one or more other components interposed therebetween. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements interposed therebetween. Likewise, similar expressions such as "between" and "directly between" and "adjacent to" and "immediately adjacent to" should also be interpreted in the same manner. As used herein, the term "and / or" includes any one of the items listed in the association and any combination of any two or more.

[0023] Although terms such as "first," "second," and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions should not be limited by these terms. Instead, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, component, region, layer, or portion mentioned in the examples may also be referred to as the second member, component, region, layer, or portion.

[0024] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "one", "an" and "the" are also intended to include plural forms. The terms "include", "comprise" and "have" represent the existence of the features, numbers, operations, components, elements and / or combinations thereof described, but do not exclude the existence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof. As used herein, the expression of "at least one of ......" modifies the entire element list after the element list rather than the individual elements in the modifying list. For example, the expression "at least one of a, b and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b and c.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by a person of ordinary skill in the art to which the present disclosure belongs based on an understanding of the disclosure of the present application. Terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the disclosure of the present application, and should not be interpreted as an ideal or overly formal meaning, unless explicitly defined as such herein. The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such a feature is included or implemented, and all example embodiments are not limited thereto.

[0026] The embodiments of the present disclosure are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. As is common in the art, embodiments may be described and illustrated according to blocks that perform one or more functions described as shown in the accompanying drawings. These blocks (which may be referred to herein as units or modules, etc., or named, for example, devices, logic, circuits, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and may be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein).

[0027] Figure 1 is a block diagram showing a phase locked loop circuit (PLL) 1 according to the embodiment.

[0028] The PLL circuit 1 may receive a reference clock signal REF_CK and a feedback clock signal FEED_CK, and output a clock signal CK having a locked phase or frequency.

[0029] The PLL circuit 1 may include a phase frequency detector 100, a charge pump 200, a loop filter 300, a voltage controlled oscillator 400, and a frequency divider 500. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, one or more other components may be included, combined, or omitted in the PLL circuit 1.

[0030] The phase frequency detector 100 may generate an up signal UP or a down signal DN, which is a pulse having a width proportional to the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK. For example, when the phase of the reference clock signal REF_CK is faster than the phase of the feedback clock signal FEED_CK, the up signal UP may be activated, and therefore, the phase frequency detector 100 may generate a pulse of the up signal UP. According to an embodiment, the term "faster than" may refer to the phase of the reference clock signal REF_CK occurring before the phase of the feedback clock signal FEED_CK. For example, the phase of the reference clock signal REF_CK leads the phase of the feedback clock signal FEED_CK. The pulse width of the up signal UP may be proportional to the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK. In the example case where the phase of the feedback clock signal FEED_CK is faster than the phase of the reference clock signal REF_CK, the down signal DN is activated, thereby generating a pulse of the down signal DN. The pulse width of the down signal DN may be proportional to a phase difference between the feedback clock signal FEED_CK and the reference clock signal REF_CK.

[0031] When the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK is greater than the reference value, the phase frequency detector 100 may generate an up signal UP and a down signal DN based on a first phase gain. The reference value may be a predetermined value. The phase gain may refer to a ratio of a phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK and a phase difference between the up signal UP and the down signal DN. The phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK may be referred to as an input phase difference. The phase difference between the up signal UP and the down signal DN may be referred to as an output phase difference. The phase gain may refer to a ratio of an input phase difference to an output phase difference.

[0032] When the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK is less than the reference value, the phase frequency detector 100 may generate an up signal UP and a down signal DN based on the second phase gain. The second phase gain may be greater than the first phase gain. That is, as the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK becomes smaller, the phase frequency detector 100 may generate an up signal UP and a down signal DN with an amplified output phase difference by amplifying the input phase difference more. Therefore, the in-band noise may be reduced.

[0033] The phase frequency detector 100 may be referred to as a time-amplified phase frequency detector.

[0034] The charge pump 200 may receive an up signal UP or a down signal DN and generate a loop filter input signal LFin. The charge pump 200 may increase the level of the loop filter input signal LFin in proportion to the pulse width of the up signal UP and reduce the level of the loop filter input signal LFin in proportion to the pulse width of the down signal DN. The term level may refer to a voltage level.

[0035] The loop filter 300 may receive a loop filter input signal LFin and generate a loop filter output signal LFout. The loop filter 300 may generate a loop filter output signal LFout by filtering the noise frequency of the loop filter input signal LFin. The loop filter 300 may be a second-order low-pass filter or a third-order low-pass filter. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the loop filter 300 may include at least one resistor or at least one capacitor. The loop filter impedance Z LF It may be determined according to the resistance value of at least one resistor and the capacitance value of at least one capacitor. According to another embodiment, other components (eg, passive components, active components, inductors, etc.) may be included in the loop filter 300 .

[0036] A voltage controlled oscillator (VCO) 400 may receive the loop filter output signal LFout and generate a clock signal CK having a frequency adjusted according to a voltage level of the loop filter output signal LFout.

[0037] The frequency divider 500 may generate a feedback clock signal FEED_CK by dividing the frequency of the clock signal CK.

[0038] In the example case where the reference clock signal REF_CK is faster than the feedback clock signal FEED_CK, the voltage level of the loop filter output signal LFout can be relatively high due to the up signal UP. With the relatively high loop filter output signal LFout, the voltage controlled oscillator 400 can generate a clock signal CK with a relatively high frequency. Therefore, the frequency of the feedback clock signal FEED_CK increases and the phase of the feedback clock signal FEED_CK becomes faster, so the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK can be corrected.

[0039] In the example case where the reference clock signal REF_CK is slower than the feedback clock signal FEED_CK, the voltage level of the loop filter output signal LFout can be relatively low due to the down signal DN. With the relatively low loop filter output signal LFout, the voltage controlled oscillator 400 can generate a clock signal CK with a relatively low frequency. Therefore, the frequency of the feedback clock signal FEED_CK is reduced and the phase of the feedback clock signal FEED_CK is slowed down, so the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK can be corrected.

[0040] According to an embodiment, the phase-locked loop circuit 1 may include a lock detector 110. The lock detector 110 may generate a lock detection signal LDS based on a phase difference between a reference clock signal REF_CK and a feedback clock signal FEED_CK. For example, the lock detector 110 may detect a time point when the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK is equal to a reference value, and activate the lock detection signal LDS at the detected time point. The loop filter 300 may control the loop filter impedance Z based on the lock detection signal LDS. LF .

[0041] In an embodiment, the phase frequency detector 100 can use different phase gains to generate the up signal UP and the down signal DN according to whether the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK is greater than the reference value. Therefore, as the phase gain of the phase frequency detector 100 changes, the spurious frequency components included in the loop filter input signal LFin can be different. For example, the spurious frequency components can be wrong frequency components or error frequency components.

[0042] According to an embodiment, when the loop filter impedance Z is controlled based on the lock detection signal LDS LF When the phase gain of the phase frequency detector 100 is changed by using the PWM signal, the loop filter 300 can improve the filtering performance for the spurious frequency.

[0043] Figure 2 is a diagram for explaining the phase gain according to the embodiment. Figure 1 To illustrate Figure 2 .

[0044] refer to Figure 2 , the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK may be referred to as an input phase difference Φ_error_in, and the phase difference between the up signal UP and the down signal DN may be referred to as an output phase difference Φ_error_out.

[0045] In the example case where the input phase difference Φ_error_in is a value between P_lock and 2π, the phase gain may be G1. In the example case where the input phase difference Φ_error_in is a value between -P_lock and P_lock, the phase gain may be G2. In the example case where the input phase difference Φ_error_in is a value between -P_lock and -2π, the phase gain may be G1. For example, G1 may be 1, and G2 may be K+1 (K is a natural number). As described above with reference to Figure 1 As described, in the example case where the phase gain is large, the voltage level of the loop filter output signal LFout also becomes large, so the frequency of the clock signal CK can be corrected quickly. That is, in the example case where the input phase difference Φ_error_in is a value between -P_lock and P_lock, the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK can be corrected relatively quickly. In the example case where the input phase difference Φ_error_in is a value between -2π and -P_lock or a value between P_lock and 2π, the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK can be corrected relatively slowly.

[0046] When correcting the phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK, the input phase difference Φ_error_in may gradually converge to 0 as the clock signal CK is repeatedly transmitted through the feedback path.

[0047] In the example case where the phase gain of the phase frequency detector 100 is changed while the phase difference is corrected, the open loop gain or the closed loop gain of the phase locked loop circuit 1 is changed, and thus the locking time of the stable clock signal CK may increase.

[0048] Lock detector 110 can detect when the phase gain changes, and can adjust the impedance Z of loop filter 300 based on the change in phase gain. LF For example, the lock detector 110 may detect a point in time when the phase gain changes, and adjust the impedance Z of the loop filter 300 at that point in time. LF The overall gain of the phase-locked loop circuit 1 is reset, thereby shortening the locking time.

[0049] Figure 3 is a circuit diagram showing a phase frequency detector 100 according to an embodiment.

[0050] refer to Figure 3The phase frequency detector 100 may include a lock detector 110 , a first flip-flop (DFF) 121 , a second flip-flop (DFF) 122 , a boost signal generating circuit 130 , a first time amplifier 141 , a second time amplifier 142 , and a reset signal generating circuit 150 .

[0051] The lock detector 110 may receive the first input signal Son1, the second input signal Son2, and the reset signal RST, and generate a lock detection signal LDS. Figure 5 The lock detector 110 is described in detail.

[0052] The first flip-flop 121 may receive a reference clock signal REF_CK and generate a first input signal Son1 based on the reference clock signal REF_CK. For example, the first flip-flop 121 may generate a first input signal Son1 synchronized with the reference clock signal REF_CK. The first flip-flop 121 may sample the power supply voltage VDD at a rising edge of the reference clock signal REF_CK. Therefore, the first input signal Son1 may have the same rising edge as the reference clock signal REF_CK. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the first flip-flop 121 may reset the first input signal Son1 to a deactivated state based on a reset signal RST.

[0053] The second flip-flop 122 may receive the feedback clock signal FEED_CK and generate a second input signal Son2 based on the feedback clock signal FEED_CK. For example, the second flip-flop 122 may generate a second input signal Son2 synchronized with the feedback clock signal FEED_CK. The second flip-flop 122 may sample the power supply voltage VDD at the rising edge of the feedback clock signal FEED_CK. Therefore, the second input signal Son2 may have the same rising edge as the feedback clock signal FEED_CK. However, the present disclosure is not limited thereto, and therefore, according to another embodiment, the second flip-flop 122 may reset the second input signal Son2 to a deactivated state based on the reset signal RST.

[0054] The boost signal generating circuit 130 may generate a boost signal Boost based on a first input signal Son1 and a second input signal Son2. The boost signal Boost may be activated based on the occurrence of a phase difference between the first input signal Son1 and the second input signal Son2. For example, the boost signal Boost may be activated in a phase error period, and may be deactivated during other periods. According to an embodiment, the phase error period may be a time period in which a phase difference occurs between the first input signal Son1 and the second input signal Son2, and other periods may be time periods in which no phase difference occurs between the first input signal Son1 and the second input signal. The boost signal generating circuit 130 may include a NAND circuit.

[0055] The first time amplifier 141 can generate an up signal UP based on the first input signal Son1, the boost signal Boost and the reset signal RST. For example, the first time amplifier 141 can discharge the internal node ( Figure 4 The node V_CAP1 in the circuit can be discharged, and the internal node ( Figure 4 According to an embodiment, the first time amplifier 141 can discharge the internal node ( V_CAP1 in the phase error period) at the first conversion rate SR1. Figure 4 The level of the node V_CAP1 in the circuit can be discharged, and the internal node ( Figure 4 The level of the node V_CAP1 in the circuit is discharged to activate the up signal UP. Figure 6 As shown in the embodiment of FIG. 1 , the first conversion rate SR1 may be greater than the second conversion rate SR2. According to an embodiment, the first time amplifier 141 may activate the up signal UP by using the first discharge current and the second discharge current to the internal node ( Figure 4 The node V_CAP1 in the middle is discharged, and the internal node ( Figure 4 The first time amplifier 141 may deactivate the up signal UP based on the reset signal RST.

[0056] The second time amplifier 142 can generate a down signal DN based on the second input signal Son2, the boost signal Boost, and the reset signal RST. The description of the first time amplifier 141 can be applied to the second time amplifier 142. For example, the second time amplifier 142 can discharge the internal node through the first discharge path and the second discharge path in the second time amplifier 142 during the phase error period, and can discharge the internal node through the first discharge path in the second time amplifier 142 during other periods to activate the down signal DN.

[0057] The reset signal generating circuit 150 receives the up signal UP and the down signal DN, and in the example case where both the up signal UP and the down signal DN are activated, the reset signal RST may be deactivated. In detail, the reset signal generating circuit 150 may include a NAND circuit 151 and a buffer circuit 152. The NAND circuit 151 may perform a NAND operation on the up signal UP and the down signal DN. The buffer circuit 152 may generate the reset signal RST by delaying the NAND operation result. Although Figure 3 One buffer circuit 152 is shown, but the present disclosure is not limited thereto, and therefore, according to another embodiment, the number of buffer circuits 152 may be more than one. The first and second input signals Son1 and Son2, the up signal UP, and the down signal DN may be reset to a deactivated state by a deactivated reset signal RST.

[0058] Figure 4 is a circuit diagram of the first time amplifier 141 according to an embodiment. Figure 3 To illustrate Figure 4 The description of the first time amplifier 141 may also be applied to the second time amplifier 142. For example, the second time amplifier 142 may include a node V_CAP2 corresponding to the node V_CAP1 of the first time amplifier 141. In addition, similar to the first phase error signal B_on1 of the first time amplifier 141, the second time amplifier 142 may generate a second phase error signal B_on2.

[0059] refer to Figure 4 The first time amplifier 141 includes an input terminal connected to the node V_CAP1 and may include an inverter INV outputting an up signal UP. The inverter INV may include an N-type transistor N1 and a P-type transistor P1.

[0060] The first time amplifier 141 may include a switch SW1 having one end connected to the power supply voltage VDD and the other end connected to the node V_CAP1. In the example case where the reset signal RST is activated, the switch SW1 is turned on, the node V_CAP1 may be precharged, and the up signal UP may be deactivated by the inverter INV. The voltage precharged at the node V_CAP1 may be charged to the capacitor cap. One end of the capacitor cap may be connected to the node V_CAP1, and the other end of the capacitor cap may be connected to the ground node.

[0061] The first time amplifier 141 may discharge the node V_CAP1 through the first discharge path P1 and the second discharge path P2. The switch SW2 located on the first discharge path P1 may have one end connected to the node V_CAP1 and the other end connected to the ground node. In the example case where the first input signal Son1 is activated, the switch SW2 is turned on, and the node V_CAP1 may be discharged through the first discharge current Idc1 on the first discharge path P1. The switch SW3 located on the second discharge path P2 may have one end connected to the node V_CAP1 and the other end connected to the ground node. In the example case where the first phase error signal B_on1 is activated, the switch SW3 may be turned on, and the node V_CAP1 may be discharged through the second discharge current Idc2 on the second discharge path P2. The ratio between the amplitude of the first discharge current Idc1 and the amplitude of the second discharge current Idc2 may be 1:K. That is, the node V_CAP1 may be discharged faster through the second discharge current Idc2 than through the first discharge current Idc1.

[0062] The first time amplifier 141 may include an AND circuit that generates a first phase error signal B_on1. The first phase error signal B_on1 may be generated by performing an AND operation between the first input signal Son1 and the boost signal Boost. Therefore, when the first input signal Son1 is activated but the second input signal Son2 is not activated, the first phase error signal B_on1 may be activated. That is, the first phase error signal B_on1 may be activated in a phase error period in which the first input signal Son1 is faster than the second input signal Son2. For example, the first phase error signal B_on1 may be activated in a phase error period in which the reference clock signal REF_CK is faster than the feedback clock signal FEED_CK. The second time amplifier 142 may include an AND circuit that generates a second phase error signal B_on2. The second phase error signal B_on2 may be activated by the AND circuit included in the second time amplifier 142 in a phase error period in which the second input signal Son2 (or the feedback clock signal FEED_CK) is faster than the first input signal Son1 (or the reference clock signal REF_CK).

[0063] Figure 5 is a detailed circuit diagram of the first time amplifier 141 according to an embodiment. Figure 4 To illustrate Figure 5 The description of the first time amplifier 141 can also be applied to the second time amplifier 142 .

[0064] refer to Figure 5 , the P-type transistor P2 can correspond to Figure 4 When the reset signal RST is disabled, the P-type transistor P2 may precharge the node V_CAP1. That is, in the example case where the reset signal RST is deactivated, the up signal UP may be reset to a deactivated state.

[0065] The bias voltage Vbias may be applied to gate terminals of the N-type transistors N2 and N3. A first discharge current Idc1 flowing through the N-type transistor N2 may discharge the node V_CAP1, and a second discharge current Idc2 flowing through the N-type transistor N3 may discharge the node V_CAP1.

[0066] The N-type transistor N4 may correspond to Figure 4 The first input signal Son1 may be provided to the gate terminal of the N-type transistor N4, and based on the first input signal Son1 being activated, the N-type transistor N4 may be turned on, thereby forming a first discharge path.

[0067] The N-type transistor N5 may correspond to Figure 4 The first phase error signal B_on1 may be provided to a gate terminal of the N-type transistor N5, and based on the first phase error signal B_on1 being activated, the N-type transistor N5 may be turned on, thereby forming a second discharge path.

[0068] According to an embodiment, the first time amplifier 141 may further include an N-type transistor N6 connected in parallel with the N-type transistor N4. A source terminal of the N-type transistor N6 may be connected to a source terminal of the N-type transistor N4, a drain terminal of the N-type transistor N6 may be connected to a power supply voltage VDD, and a gate terminal of the N-type transistor N6 may be connected to an output of the inverter 143. The inverter 143 may invert the first input signal Son1 and output the inverted first input signal Son1. That is, according to an embodiment, even if the first input signal Son1 is in an inactive state, the first discharge path may be formed by the N-type transistor N6.

[0069] Figure 6 is a timing chart for explaining the operation of the phase frequency detector 100 according to the embodiment. Figures 3 to 5To illustrate Figure 6 .exist Figure 6 , the voltages at the nodes V_CAP1 and V_CAP2 are initially shown to be precharged to the VDD level. However, the present disclosure is not limited thereto, and therefore, the initial voltage levels of the nodes V_CAP1 and V_CAP2 may vary according to the capacity of the capacitor Cap.

[0070] refer to Figure 6 , at the first time t1, the reference clock signal REF_CK may be converted to an active state. Figure 3 In the example case where the reference clock signal REF_CK is activated, the first flip-flop 121 may convert the first input signal Son1 into an activated state by sampling the power supply voltage VDD. For example, the first input signal Son1 may have the same activation timing as the reference clock signal REF_CK.

[0071] At the second time t2, the feedback clock signal FEED_CK may be switched to an active state. Figure 3 In the example case where the feedback clock signal FEED_CK is activated, the second flip-flop 122 may convert the second input signal Son2 into an activated state by sampling the power supply voltage VDD. For example, the second input signal Son2 may have the same activation timing as the feedback clock signal FEED_CK.

[0072] The phase of the reference clock signal REF_CK may be faster than the phase of the feedback clock signal FEED_CK, and an input phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK may be Φ_error_in. A time interval between the first time t1 and the second time t2 may be a phase error period.

[0073] refer to Figures 4 to 6 In the time interval between the first time t1 and the second time t2, the first input signal Son1 is in an active state and the second input signal Son2 is in an inactive state, so the first phase error signal B_on1 can be in an active state. Therefore, the first discharge current Idc1 and the second discharge current Idc2 can be discharged from the node V_CAP1. Figure 6 As shown, in the time interval between the first time t1 and the second time t2 , the node V_CAP1 may be discharged according to the first slew rate SR1 .

[0074] refer to Figure 4 and Figure 6, in the time interval between the first time t1 and the second time t2, the second input signal Son2 is in an inactive state, and thus, a discharge path for the node V_CAP2 may not be formed and the voltage level of the node V_CAP2 may be maintained at the power supply voltage VDD.

[0075] In the example case where the feedback clock signal FEED_CK is converted to an active state at the second time t2, the boost signal Boost may be Figure 3 The boost signal generating circuit 130 is switched to an inactive state. As the first phase error signal B_on1 passes Figure 4 The AND circuit of the switch SW3 is converted to an inactive state, and the switch SW3 is turned off, thereby blocking the second discharge path. Therefore, because the node V_CAP1 is discharged only by the first discharge current Idc1 on the first discharge path, the discharge speed (or the magnitude of the discharge) can be slower than the case where both the first discharge path and the second discharge path are turned on. Therefore, the node V_CAP1 can be discharged according to the second conversion rate SR2. The second conversion rate SR2 can be less than the first conversion rate SR1.

[0076] According to an embodiment, since the feedback clock signal FEED_CK is converted to an active state at the second time t2, the node V_CAP2 may be discharged by the first discharge current Idcl. That is, the node V_CAP2 may be discharged according to the second slew rate SR2.

[0077] At the third time t3, the voltage level of the node V_CAP1 may decrease by Figure 5 Therefore, in the first time amplifier 141, the P-type transistor P1 is turned on, and the up signal UP may be converted into an active state.

[0078] At the fourth time t4, the voltage level of the node V_CAP2 may decrease the threshold voltage Vth of the P-type transistor P1 included in the second time amplifier 142. Therefore, in the second time amplifier 142, the P-type transistor P1 is turned on and the down signal DN may be converted to an active state.

[0079] The phase of the up signal UP may be faster than the phase of the down signal DN, and a phase difference between the up signal UP and the down signal DN may be Φ_error_out.

[0080] According to an embodiment, in the case where both the up signal UP and the down signal DN are activated, when a certain delay time elapses after the down signal DN is activated, the reset signal RST may be activated. Figure 3The reset signal generating circuit 150 is deactivated. Therefore, the first input signal Son1, the second input signal Son2, the up signal UP and the down signal DN can all be reset to a deactivated state. In the time period between the fourth time t4 and the fifth time t5, the voltage levels of the nodes V_CAP1 and V_CAP2 can reach the power supply voltage VDD.

[0081] Fig. 7A and Figure 7B It is a timing diagram used to illustrate the relationship between the input phase difference and the output phase difference.

[0082] exist Fig. 7A and Figure 7B In the embodiment, the timing difference between the edge of the reference clock signal REF_CK and the edge of the feedback clock signal FEED_CK can be called the input error time T_error_in. The timing difference between the edge of the up signal UP and the edge of the down signal DN can be called the output error time T_error_out. Fig. 7A and Figure 7B In the input error time T_error_in, it can be longer than Figure 6 The voltage level of the midpoint node V_CAP1 drops by the time of the threshold voltage Vth.

[0083] Fig. 7A 1 shows that the phase of the reference clock signal REF_CK is faster than the phase of the feedback clock signal FEED_CK by more than the reference phase (eg, Figure 2 Timing diagram for the case of P_lock in .

[0084] Therefore, with Figure 6 The situation shown is different (in Figure 6 In the case described above, as the node V_CAP1 is discharged according to the first conversion rate SR1 between the first time t1 and the second time t2 and discharged according to the second conversion rate SR2 between the second time t2 and the third time t3, the level of the node V_CAP1 decreases by Vth. Fig. 7A As the node V_CAP1 is discharged according to the first slew rate SR1, the level of the node V_CAP1 may decrease by Vth. That is, in the example case where the node V_CAP1 is discharged only by the first discharge current Idc1 and the second discharge current Idc2 during the input error time T_error_in, the time Tup when the up signal UP is activated may be calculated as Equation 1.

[0085] [Equation 1]

[0086]

[0087] Here, Vth may represent a reduced voltage level of the node V_CAP1, C may represent a capacitance of the capacitor Cap, I may represent a magnitude of the first discharge current Idc1, and kI may represent a magnitude of the second discharge current Idc2. Here, kI may be derived by multiplying I by k.

[0088] In an example case where the feedback clock signal FEED_CK is activated, the node V_CAP2 may be discharged from T1+T_error_in and discharged only by the first discharge current Idc1 , and thus the time Tdn at which the down signal DN is activated may be calculated as in Equation 2.

[0089] [Equation 2]

[0090]

[0091] According to Equation 1 and Equation 2, the output error time T_error_out can be calculated as in Equation 3.

[0092] [Equation 3]

[0093]

[0094] According to Equation 3, since the output error time T_error_out is not amplified by the input error time T_error_in, the phase gain may be 1. That is, Figure 2 G1 in can be 1.

[0095] Figure 7B It shows that the phase of the reference clock signal REF_CK is faster than the feedback clock signal FEED_CK by less than or equal to the reference phase (for example, Figure 2 Timing diagram for the case of P_lock in .

[0096] That is, because the input error time T_error_in is short, even if the node V_CAP1 is discharged by the first discharge current Idc1 and the second discharge current Idc2 during the input error time T_error_in, the voltage level of the node V_CAP1 may only drop by a level Ve less than the threshold voltage Vth. Figure 6 and Figure 7B , at the first time t1 and the second time t2, the level of the node V_CAP1 may drop by Ve. After the voltage level of the node V_CAP1 drops by Ve, the node V_CAP1 is discharged by the first discharge current Idc1 in a time period Tm, thereby causing the voltage to drop by the total threshold voltage Vth. Tm may be Figure 6 Therefore, the time Tup at which the up signal UP is activated can be calculated by Equation 4 and Equation 5.

[0097] [Equation 4]

[0098]

[0099] [Equation 5]

[0100]

[0101] In an example case where the feedback clock signal FEED_CK is activated, the node V_CAP2 may be discharged starting from T1 + T_error_in, and because the node V_CAP2 is discharged only by the first discharge current Idc1 , the time when the down signal DN is activated may be calculated as in Equation 6.

[0102] [Equation 6]

[0103]

[0104] According to Equation 5 and Equation 6, the output error time T_error_out can be calculated as in Equation 7.

[0105] [Equation 7]

[0106]

[0107] Because the output error time T_error_out is amplified to (1+k) times the input error time T_error_in, the phase gain can be 1+k. In other words, Figure 2 G2 in can be 1+k.

[0108] refer to Fig. 7A and Figure 7B , in the example case where the voltage level of the node V_CAP1 dropped during the input error time T_error_in is greater than the threshold voltage Vth, the phase gain is 1, and the voltage level of the node V_CAP1 dropped during the input error time T_error_in is less than the threshold voltage, the phase gain may be K+1. That is, in the example case where the voltage level of the node V_CAP1 dropped during the input error time T_error_in is equal to the threshold voltage Vth, the phase gain may be changed, and the corresponding input error time T_error_in may be referred to as the gain change time Tgainchange.

[0109] As the phase-locked loop circuit 1 feeds back the clock signal CK, the phase error between the reference clock signal REF_CK and the feedback clock signal FEED_CK (ie, the input error time T_error_in) can gradually decrease, and when the input error time T_error_in reaches the gain change time Tgainchange calculated by Equations 8 and 9, the phase gain can be changed.

[0110] [Equation 8]

[0111]

[0112] [Equation 9]

[0113]

[0114] Figure 8 is a circuit diagram showing the lock detector 110 according to an embodiment. Figure 4 To describe Figure 8 .

[0115] refer to Figure 8 The lock detector 110 may include a time amplifier replica circuit 111 , an OR circuit 112 , a third flip-flop 113 , a fourth flip-flop 116 , a counter 114 , a comparison circuit 115 , and a buffer circuit 117 .

[0116] The time amplifier replica circuit 111 may have Figure 4 The first time amplifier 141 has the same structure. In detail, the time amplifier replica circuit 111 may include an inverter including an N-type transistor N2 and a P-type transistor P2. The input node of the inverter may be referred to as Nin, and the output node of the inverter may be referred to as Nout.

[0117] Similar to Figure 4 The switches SW1 and SW4 in the embodiment can precharge the node Nin by switching based on the reset signal RST. The precharge voltage can be charged to the capacitor cap. In the example case where the level of the node Nin is a logic high level, the level of the node Nout can have a logic low level indicating an inactive state of the inverter.

[0118] Figure 8 The third discharge current Idc3 may correspond to Figure 4 The third discharge current Idc3 may be (K+1)I. Fig. 7A and Figure 7BAs described, when the node Nin is discharged using a discharge current of (1+K)I, in the example case where the input error time T_error_in is shorter than the gain change time Tgainchange, because the node Nin is not discharged enough to turn on the P-type transistor P2, the level of the node Nout can be maintained at a logic low level. On the other hand, in the example case where the input error time T_error_in is longer than the gain change time Tgainchange, the node Nin is discharged enough to turn on the P-type transistor P2, so the level of the node Nout can be converted to a logic high level. That is, in the early stage of the operation of the phase-locked loop circuit 1, the input error time T_error_in can be longer than the gain change time Tgainchange, so the node Nout can be maintained at a logic low level. As the phase correction is repeatedly performed by the phase-locked loop circuit 1, the length of the input error time T_error_in gradually decreases, and the node Nout can be converted to a logic high level, which means that the input error time T_error_in reaches the gain change time Tgainchange.

[0119] Figure 4 The switches SW2 and SW3 in can be shown as Figure 8 . Unlike switches SW2 and SW3, switch SW5 can be turned on based on the result of the OR operation of the first input signal Son1 and the second input signal Son2. The OR circuit 112 can perform an OR operation on the first input signal Son1 and the second input signal Son2, and switch the switch SW5 based on the result of the OR operation. Therefore, in the example case where one of the first input signal Son1 and the second input signal Son2 is activated, the node Nin can be discharged by a discharge current corresponding to the magnitude of (K+1)I. That is, no matter which clock signal has a faster phase between the reference clock signal REF_CK and the feedback clock signal FEED_CK, in the phase error period, the node Nin can be discharged by a discharge current corresponding to the magnitude of (K+1)I.

[0120] The third flip-flop 113 may sample the level of the node Nout by being synchronized with a falling edge of an OR operation result of the first input signal Son1 and the second input signal Son2, and provide the sampled value to the counter 114.

[0121] When the phase-locked loop circuit 1 stabilizes the frequency of the clock signal CK, the input phase difference between the reference clock signal REF_CK and the feedback clock signal FEED_CK generally decreases, but the input phase difference may temporarily increase due to noise, etc. Therefore, the lock detector 110 can prevent the impedance of the loop filter 300 from changing when the level of the node Nout changes due to temporary noise by monitoring the level of the node Nout for more than a reference time.

[0122] In detail, the counter 114 may count the sampled value of the third flip-flop 113 by synchronizing with the reference clock signal REF_CK. The comparison circuit 115 may compare the count value and the reference value, and activate the output value when the count value exceeds the reference value.

[0123] The buffer circuit 117 may delay the activated output value and provide the delayed output value as a clock signal to the fourth flip-flop 116. The fourth flip-flop 116 may generate a lock detection signal LDS by sampling the corresponding output value.

[0124] Fig. 9 is a circuit diagram showing a charge pump 200 and a loop filter 300 according to an embodiment. Figure 3 and Figure 8 To illustrate Fig. 9 .

[0125] refer to Fig. 9 , the charge pump 200 may include a precharge circuit 210 and a discharge circuit 220. The precharge circuit 210 may increase the level of the loop filter input signal LFin by precharging the node m1 based on the up signal UP. The discharge circuit 220 may reduce the level of the loop filter input signal LFin by discharging the node m2 based on the down signal DN.

[0126] The loop filter 300 may generate a loop filter output signal LFout by filtering a loop filter input signal LFin.

[0127] The loop filter 300 may include resistors R1 and R2, capacitors C1 and C2, switches SW1 and SW2, and an inverter 310. One end of the capacitor C2 may be connected to a node m2, and the other end may be connected to a ground node. Figure 1 The impedance Z LF It can be determined by resistors R1 and R2 and capacitors C1 and C2.

[0128] The switch SW1 may be connected in series with the resistor R1 and may be switched between the node m2 and the capacitor C1. The switch SW2 may be connected in series with the resistor R2 and may be switched between the node m2 and the capacitor C1. One end of the capacitor C1 may be connected to the resistors R1 and R2, and the other end of the capacitor C1 may be connected to the ground node.

[0129] The switch SW1 may be switched by the lock detection signal LDS, and the switch SW2 may be switched by the inverted value of the lock detection signal LDS.

[0130] refer to Figure 2 and Fig. 9 , the loop filter 300 can change the impedance Z of the loop filter 300 based on the lock detection signal LDS LF In detail, in the example case where the phase gain is changed in the phase frequency detector 100, the open loop gain of the phase-locked loop circuit 1 is also changed, and thus the locking time for stabilizing the clock signal CK may increase. Therefore, when the phase gain of the phase frequency detector 100 is changed, the loop filter 300 may be configured to be stable by changing the impedance Z LF To keep the open-loop gain of the phase-locked loop circuit 1 constant.

[0131] According to the embodiment, reference Figure 2 , when the phase gain is G1, the total resistance value of the resistors R1 and R2 may be lower than the total resistance value of the resistors R1 and R2 when the phase gain is G2. For example, in the example case where the phase gain is G1, the lock detection signal LDS may be at a logic low level, the switch SW1 may be turned off, and the switch SW2 may be turned on. In the example case where the phase gain is G2, the lock detection signal LDS is at a logic high level, the switch SW1 may be turned on, and the switch S2 may be turned off. Therefore, in the example case where the phase gain is G1, the total resistance value of the loop filter 300 is equal to the resistance value of R1, and in the example case where the phase gain is G2, the total resistance value of the loop filter 300 is equal to the resistance value of R2. The resistance value of R1 may be less than the resistance value of R2.

[0132] However, the present disclosure is not limited thereto, and therefore, the number of resistors, the structure of the loop filter 300, the position of the switch, etc. may be different. For example, the number of resistors, the structure of the loop filter 300, the position of the switch, etc. may be varied or changed so that the total resistance value of the loop filter 300 when the phase gain is G1 is lower than the total resistance value of the loop filter 300 when the phase gain is G2.

[0133] In the present specification, the embodiments have been described using specific terms, but this is only for the purpose of explaining the technical idea of ​​the present disclosure and is not intended to limit the meaning or scope of the present disclosure set forth in the claims.

[0134] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A phase-locked loop circuit, comprising: The phase frequency detection circuit is configured as: Receive reference clock signal and feedback clock signal, adjusting a phase gain based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and Based on the phase gain, generating a first control signal and a second control signal; a lock detection circuit configured to: generate a lock detection signal, the lock detection signal being activated based on the first phase difference being less than the reference value; a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal; A loop filter, comprising at least one resistor and at least one capacitor, wherein the loop filter is configured to: Based on the activated lock detection signal, adjusting the impedance, and generating a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance; an oscillator configured to: generate a clock signal based on the loop filter output signal; as well as The frequency divider is configured to generate the feedback clock signal by dividing the frequency of the clock signal.

2. The phase-locked loop circuit according to claim 1, wherein: Based on the lock detection signal being in an inactive state, the resistance value of the at least one resistor has a first resistance value, wherein, based on the lock detection signal being in an activated state, the resistance value of the at least one resistor has a second resistance value, and Wherein, the first resistance value is greater than the second resistance value.

3. The phase-locked loop circuit according to claim 1, wherein: The phase frequency detection circuit comprises: A first flip-flop, configured to: generate a first input signal synchronously with the reference clock signal; A second flip-flop, configured to: generate a second input signal synchronously with the feedback clock signal; a first time amplifier configured to: discharge the first node based on a first discharge current and a second discharge current in a first period based on the reference clock signal leading the feedback clock signal, discharge the first node based on the first discharge current in a second period different from the first period, and generate the first control signal based on a voltage level of the first node; and The second time amplifier is configured to: discharge the second node based on the first discharge current and the second discharge current in the first time period based on the reference clock signal lagging behind the feedback clock signal, discharge the second node based on the first discharge current in the second time period, and generate the second control signal based on the voltage level of the second node.

4. The phase-locked loop circuit according to claim 3, wherein: The lock detection circuit is further configured to discharge a third node based on the first discharge current and the second discharge current, and generate the lock detection signal based on a voltage level of the third node.

5. The phase-locked loop circuit according to claim 4, wherein: The lock detection circuit also includes: an inverter configured to: invert the voltage level of the third node; a counter configured to: count an activation time of an output signal of the inverter; and The comparison circuit is configured to activate the lock detection signal based on a comparison between the activation time and a reference time.

6. The phase-locked loop circuit according to claim 5, wherein: The reference value is a phase value corresponding to a time in which the voltage level of the third node decreases by a threshold voltage of a transistor in the inverter.

7. The phase-locked loop circuit according to claim 3, wherein: The lock detection circuit has the same structure as the first time amplifier or the second time amplifier.

8. A method of operating a phase-locked loop circuit, the method comprising: adjusting a phase gain based on a first phase difference between a reference clock signal and a feedback clock signal; generating a first control signal and a second control signal based on the adjusted phase gain; generating a lock detection signal based on the first phase difference, the lock detection signal being activated based on the first phase difference being less than or equal to a reference value, and the lock detection signal being deactivated based on the first phase difference exceeding the reference value; generating a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal; adjusting an impedance of a loop filter based on the lock detection signal; generating a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance; and Based on the loop filter output signal, a clock signal is generated.

9. The method according to claim 8, wherein: Adjusting the impedance of the loop filter includes reducing a resistance value included in the loop filter based on the activated lock detection signal.

10. The method according to claim 8, further comprising: In a first period when the reference clock signal leads the feedback clock signal, discharging the first node through a first discharge path and a second discharge path; In a second time period different from the first time period, discharging the first node through the first discharge path; Based on the first node, generate a first control signal; In the first period when the reference clock signal lags behind the feedback clock signal, discharging the second node through the first discharge path and the second discharge path; In the second period, discharging the second node through the first discharge path; and Based on the second node, a second control signal is generated.

11. The method according to claim 10, wherein: Generating the lock detection signal further includes discharging a third node through the first discharge path and the second discharge path, and generating the lock detection signal based on a voltage level of the third node.

12. The method according to claim 11, wherein: Generating the lock detection signal comprises: generating an output signal by inverting the voltage level of the third node; calculating an activation time of the output signal; and Based on a comparison between the activation time and a reference time, the lock detection signal is activated.

13. The method according to claim 12, wherein: The reference value corresponds to a time when the voltage level of the third node is reduced by a threshold voltage of a transistor in an inverter, and the inverter inverts the voltage level of the third node.

14. The method according to claim 8, wherein: Generating the lock detection signal is performed based on a first circuit having the same structure as a second circuit that generates the first control signal and the second control signal.

15. A phase-locked loop circuit, comprising: The phase frequency detection circuit is configured as: Receive reference clock signal and feedback clock signal, adjusting a phase gain based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and Based on the phase gain, generating a first control signal and a second control signal; a lock detection circuit configured to: generate a lock detection signal, the lock detection signal being activated based on the first phase difference being less than or equal to the reference value; a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal; A loop filter, comprising at least one resistor and at least one capacitor, wherein the loop filter is configured to: adjusting a resistance value of the at least one resistor or a capacitance value of the at least one capacitor based on the activated lock detection signal, and generating a loop filter output signal by filtering the loop filter input signal based on the adjusted resistance value or the adjusted capacitance value; as well as The oscillator is configured to generate a clock signal based on the loop filter output signal.

16. The phase-locked loop circuit according to claim 15, wherein: Based on the lock detection signal being in an inactive state, the resistance value of the at least one resistor has a first resistance value, wherein, based on the lock detection signal being in an activated state, the resistance value of the at least one resistor has a second resistance value, and Wherein, the first resistance value is greater than the second resistance value.

17. The phase-locked loop circuit according to claim 15, wherein: The phase frequency detection circuit comprises: A first flip-flop, configured to: generate a first input signal synchronously with the reference clock signal; A second flip-flop, configured to: generate a second input signal synchronously with the feedback clock signal; a first time amplifier configured to: discharge the first node based on the first discharge current and the second discharge current in a first period, discharge the first node based on the first discharge current in a second period, and generate the first control signal based on a voltage level of the first node based on the reference clock signal leading the feedback clock signal; and The second time amplifier is configured to: discharge the second node based on the first discharge current and the second discharge current in the first time period based on the reference clock signal lagging behind the feedback clock signal, discharge the second node based on the first discharge current in the second time period, and generate the second control signal based on the voltage level of the second node.

18. The phase-locked loop circuit according to claim 17, wherein: The lock detection circuit is further configured to discharge a third node based on the first discharge current and the second discharge current, and generate the lock detection signal based on a voltage level of the third node.

19. The phase-locked loop circuit according to claim 18, wherein: The lock detection circuit also includes: an inverter configured to: invert the voltage level of the third node; a counter configured to: count an activation time of an output signal of the inverter; and The comparison circuit is configured to activate the lock detection signal based on a comparison between the activation time and a reference time.

20. The phase-locked loop circuit according to claim 19, wherein: The reference value is a phase value corresponding to a time at which the voltage level of the third node is reduced by a threshold voltage of a transistor in the inverter.

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