Sensor circuit

Abstract

The invention relates to a sensor circuit. The invention relates to a sensor circuit (300). The sensor circuit (300) includes an analog chopper circuit (110) configured to shift an analog input signal from an initial frequency to a chopping frequency to generate a chopped analog signal (112), a sigma delta modulator (320) coupled to an output of the analog chopper circuit (110) and configured to digitize the chopped analog signal (112) at a sampling frequency to generate a chopped digital signal (322), and a digital chopper circuit (310) coupled to an output of the sigma delta modulator (320) and configured to demodulate the chopped digital signal (322) to generate a demodulated chopped digital signal (328) having a signal component at the initial frequency.

Description

Technical Field

[0001] The present disclosure relates generally to analog-to-digital converters (ADCs), and more particularly, to ΣΔ analog-to-digital converters (ΣΔ ADCs) for chopper sensors. Background Art

[0002] Many modern devices (such as vehicles) include multiple sensors, for example. These sensors can "switch quickly" to provide information about the operation of the device to a digital control unit, which can act on the information. For example, the control unit of a vehicle can be configured to control a fuel injection component based on the position of a camshaft. To this end, a toothed wheel can be fixed to the camshaft, and a magnetic sensor (such as a Hall sensor) can be arranged to detect the teeth on the wheel. The sensor can output an analog signal indicating the presence (or absence) of a tooth. The analog signal of the sensor can be converted by an ADC into a digital signal to enable a digital processing component in the control unit to determine the position of the camshaft. Both the ADC and the digital-to-analog converter (DAC) can use ΣΔ modulation. The ΣΔADC can first encode the analog signal using high-frequency ΣΔ modulation, and then apply a digital filter to form a digital output with a higher resolution but a lower sampling frequency. The ΣΔDAC can encode a high-resolution digital input signal into a signal with a lower resolution but a higher sampling frequency that can be mapped to a voltage, and then smoothed using an analog filter. In the same case, the temporary use of a lower resolution signal can simplify the circuit design and improve efficiency.

[0003] ΣΔADC and ΣΔDC can be combined using chopping. Chopping refers to a technique that can be used to eliminate offset voltage and other low-frequency errors. A chopper circuit is an electrical circuit in which the signal to be amplified is modulated (chopped), amplified and demodulated again. By using this technique, the zero-point error (or offset error) and the so-called 1 / f noise of the amplifier can be shifted to a frequency band of no interest. Chopper circuits can be used, for example, in bandgap circuits that provide a defined reference voltage, but can also be used in other applications where signals need to be processed (such as in ΣΔADCs). The offsets generated in the various amplifiers of the ΣΔ modulator can generally be eliminated by local chopping or auto-zeroing amplifiers after filtering. However, other offset errors cannot be removed by these methods. A solution implemented on these ADCs can be to chop the entire analog signal chain within the ADC. This can remove any offset and low-frequency errors, giving extremely low offset errors and drift.

[0004] For a ΣΔ ADC used in a chopped sensor, it is desirable to reduce offset, noise, and loop complexity. Summary of the invention

[0005] This need is solved by an apparatus and a method according to the appended claims.

[0006] According to a first aspect, a sensor circuit is proposed. The sensor circuit includes an analog chopper circuit configured to shift an analog input (sensor) signal from an initial frequency to a chopping frequency to generate a chopped analog signal. The sensor circuit also includes a ΣΔ modulator coupled to the output of the analog chopper circuit. Therefore, the analog chopper circuit can be regarded as being outside the ΣΔ modulator. The ΣΔ modulator is configured to sample the chopped analog signal at a sampling frequency to generate a chopped digital signal. The sensor circuit further includes a digital chopper circuit coupled to the output of the ΣΔ modulator and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the initial frequency. Therefore, the digital chopper circuit can also be regarded as being outside the ΣΔ modulator. Demodulation (de-chopping) is made in the digital domain.

[0007] The present disclosure proposes a sensor circuit having an analog chopper circuit (for modulation) upstream of a ΣΔ modulator and a digital chopper circuit (for demodulation) downstream of the ΣΔ modulator. The ΣΔ modulator itself is configured without a chopper circuit, i.e., there is no chopper circuit in the feedforward path of the ΣΔ modulator and there is no chopper circuit in the feedback path of the ΣΔ modulator. Therefore, the present disclosure proposes a non-chopping ΣΔ ADC for a chopping sensor.

[0008] In some embodiments, the ratio between the sampling frequency and the chopping frequency of the ΣΔ modulator is greater than 50 or even greater than 100. In this way, the proposed sensor circuit can obtain broadband characteristics and a signal component at the chopping frequency and one or more harmonics of this signal component can pass through the ΣΔ modulator.

[0009] In some embodiments, the ΣΔ modulator includes an ADC and an analog loop filter coupled between the output of the analog chopper circuit and the ADC. That is, the analog loop filter (integrator) is upstream of the ADC.

[0010] In some embodiments, analog loop filter can be implemented as continuous time (CT) loop filter. In analog CT loop filter, both input signal and output signal of analog loop filter are continuous time signals. Analog loop filter processes input signal and produces continuous time output signal in its continuous time form, and the produced continuous time output signal can be converted into digital signal using ADC. In discrete time (DT) analog loop filter, on the other hand, input signal (chopped wave analog signal) will be sampled and processed in discrete time using clock signal, and output signal will be discrete time sampling sequence. DT analog loop filter usually includes sample and hold circuit (e.g., switch capacitor (SC) circuit) to capture input signal under clock rate.

[0011] In some embodiments, the ΣΔ modulator includes a multi-bit ADC coupled to the output of the analog loop filter (integrator), the multi-bit ADC configured to convert the chopped analog signal from analog to digital to generate a chopped digital signal. The multi-bit ADC may have a bit width greater than 2 bits, such as a bit width of 4 bits or 6 bits.

[0012] In some embodiments, the ΣΔ modulator includes a feedback path from the output of the ΣΔ modulator (the output of the ADC) to the input of the ΣΔ modulator (the input of the analog loop filter). The feedback path includes a multi-bit DAC configured to convert the chopped digital signal back to analog. The multi-bit DAC can have a bit width corresponding to the bit width of the multi-bit ADC in the feedback path. Therefore, the multi-bit DAC can have a bit width greater than 2 bits, such as a bit width of 4 bits or 6 bits.

[0013] In some embodiments, the ΣΔ modulator includes a single-bit ADC configured to convert the chopped analog signal from analog to digital to generate a chopped digital signal. The ΣΔ modulator may also include a feedback path from the output of the ΣΔ modulator to the input of the ΣΔ modulator, wherein the feedback path includes a single-bit DAC configured to convert the chopped digital signal back to analog.

[0014] In some embodiments, the sensor circuit may further include a digital filter coupled to the output of the digital chopper circuit. The digital filter is configured to suppress signal components at least at the chopping frequency. The digital filter may also be configured to suppress signal components at one or more harmonics of the chopping frequency.

[0015] In some embodiments, the digital filter comprises a notch filter having a notch at least at the chopping frequency. The notch filter may also have notches at one or more harmonics of the chopping frequency.

[0016] In some embodiments, the digital filter additionally or alternatively includes a low pass filter configured to allow signal components at the initial frequency to pass while attenuating signal components at the chopping frequency or higher.

[0017] In some embodiments, the digital filter comprises a combination of a low pass filter and a notch filter. This may be useful when the energy of the signal component at the chopping frequency is large.

[0018] In some embodiments, the sensor circuit may further include a digital filter coupled between the output of the ΣΔ modulator (the output of the ADC) and the input of the digital chopper circuit. The digital filter may be configured to suppress one or more harmonics of the chopping frequency. The digital filter may cause a filter delay. Therefore, the sensor circuit may further include a delay element coupled between the chopping clock signal and the digital chopper circuit that uses the chopping clock signal to demodulate. The delay element may be configured to cause a delay of the chopping clock signal corresponding to the filter delay.

[0019] In some embodiments, the sensor circuit may further include an amplifier coupled between the analog chopper circuit and the ΣΔ modulator and configured to amplify the chopped analog signal. The amplifier may be used in the case of a weak sensor signal. For example, the amplifier may include an operational transconductance amplifier (OTA).

[0020] In some embodiments, the digital chopper circuit is configured to multiply the chopped digital signal with a digital sinusoidal signal having a chopping frequency. The sinusoidal signal has only one frequency component and can therefore facilitate the generation of other harmonics and can therefore simplify filter design. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Some examples of apparatus and / or methods will be described below, by way of example only, and with reference to the accompanying drawings, in which:

[0022] Figure 1 illustrates a schematic block diagram of a sensor system including a chopped ΣΔ ADC for converting an analog input signal at an initial frequency into a digital output signal;

[0023] Figure 2 A block diagram showing an example implementation of a chopped ΣΔ ADC;

[0024] Figure 3 illustrates a schematic block diagram of a sensor circuit including a non-chopping ΣΔ ADC for converting an analog input signal at an initial frequency into a digital output signal;

[0025] Figure 4A Shows Figure 3 A first embodiment of the sensor circuit; and

[0026] Figure 4B Shows Figure 3 A second embodiment of the sensor circuit. DETAILED DESCRIPTION

[0027] Some examples are now described in more detail herein with reference to the accompanying drawings. However, other possible examples are not limited to the feature limitations of these embodiments described in detail. Other examples may include modifications to features and equivalents or substitutes of features. In addition, the terms used herein to describe certain examples should not limit other possible examples.

[0028] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be equivalent or implemented in a modified form while providing the same or similar functions. For clarity, the thickness of the lines, layers and / or regions in the drawings may also be exaggerated.

[0029] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e., only A, only B, and A and B, unless otherwise clearly defined in individual cases. As alternative words for the same combination, "at least one of A and B" or "A and / or B" may be used. This applies equally to combinations of more than two elements.

[0030] If singular forms, such as "a", "an", and "the" are used, and the use of only a single element is not explicitly or implicitly defined as mandatory, other examples may also use several elements to implement the same functionality. If a functionality is described below as being implemented using multiple elements, other examples may use a single element or a single processing entity to implement the same functionality. It should also be understood that when the terms "include", "including", "comprise" and / or "comprising" are used, the presence of specified features, integers, steps, operations, processes, elements, components and / or groups thereof is described, but the presence of one or more other features, integers, steps, operations, processes, elements, components and / or groups thereof is not excluded.

[0031] Sensors often introduce errors into the analog signals they output due to the inherent characteristics of the sensors themselves. For example, offset errors can be included in the analog signals output by Hall sensors. However, spin current technology can help distinguish between errors and sensor signals. Spin technology can convert the offset error component in the Hall sensor signal into a high-frequency error (also called offset ripple), while the sensor signal remains low frequency or DC.

[0032] The ADC may include an amplifier and / or an integrator, which may also introduce offset errors into the signal it processes. The amplifier or integrator offset error may be added to the offset error introduced by the Hall sensor. To compensate for the sensor offset error and / or amplifier offset error, some ADCs include a chopper. A chopper is a circuit that modulates the sensor signal to a higher frequency, which shifts the sensor output signal to a higher frequency range (i.e., the chopping frequency f). chop ) while the offset error component is maintained in the low frequency range, making the offset error component more easily distinguishable from the signal component. For the purposes of this description, the modulated sensor signal output by the chopper circuit at the chopping frequency will be referred to as being "chopped" or "at the chopping frequency", in contrast to a sensor signal that has not been modulated or remodulated to the original frequency of the sensor signal (which will be referred to as having the "original frequency").

[0033] Figure 1 A schematic block diagram of a sensor system including an ADC circuit 100 for converting an analog input signal VIN (eg, a sensor signal) at an initial frequency into a digital output signal DOUT is illustrated.

[0034] The analog input signal VIN can be assumed to be band-limited, and the signal bandwidth can be assumed to be much lower than the sampling frequency f of the ADC circuit 100. s The analog input signal VIN may include a signal component and an offset error component that may be introduced by a sensor (not shown) measuring a physical quantity (e.g., a Hall sensor measuring a magnetic field). To account for the offset error component in the analog input signal VIN, the ADC circuit 100 includes an analog chopper circuit 110 coupled between an input terminal 102 for the analog input signal VIN and an input terminal of a chopped ΣΔ ADC circuit 120. The analog chopper circuit (modulator) 110 may be considered to be external to the chopped ΣΔ ADC circuit 120 and include a modulator at the chopping frequency f chop The modulator circuit is clocked (switched) below. The chopping frequency f chop can be lower than the sampling frequency f of the ADC circuit 100 s At the chopping frequency f chop The chopping clock signal can be obtained by means of the timing circuit 130 from the sampling frequency f s The timing circuit 130 may be configured to implement a sampling frequency f s The frequency division is used to obtain the chopping frequency f chopThis can be accomplished, for example, via a counter that triggers a state transition (from low to high, or from high to low) of the chopping clock signal after j sampling clock pulses. The chopper or modulator circuit 110 is configured to convert the analog output signal VIN from a low to a high state at the chopping frequency f chop The chopped analog signal 112 is shifted to its original frequency at or near 100 Hz (which may be DC) to generate the chopped analog signal 112 at the input of the chopped ΣΔ ADC circuit 120 .

[0035] According to various example implementations, the chopped ΣΔ ADC circuit 120 may include an amplifier circuit and a demodulator circuit, wherein the amplifier circuit is used to chop the analog signal 112 to generate an amplified chopped analog signal, and the demodulator circuit is used to generate an amplified chopped analog signal at a chopping frequency f. chop The analog demodulator circuit 120 is clocked and configured to demodulate the amplified chopped analog signal to generate a demodulated analog signal having a signal component at the initial frequency. The analog demodulator circuit (which may also be referred to as an analog chopper circuit) is inside the chopped ΣΔADC circuit 120, and this is where the reference to the chopped ΣΔADC circuit 120 comes from. The ΣΔADC circuit 120 may further include a ΣΔ modulator and a digital / decimation filter to convert the analog input signal VIN into a digital output signal 122 (DOUT). The ΣΔ modulator may coarsely sample the analog input signal VIN into a 1-bit stream at a very high rate. The digital decimation filter may then take the sampled data and convert it into a high-resolution, slower digital code.

[0036] A block diagram of an example implementation of an ADC circuit 100 for converting an analog input signal VIN at an initial frequency into a digital output signal DOUT is shown in FIG. Figure 2 is shown in .

[0037] Figure 2 The chopped ΣΔ ADC includes an (oversampling) ΣΔ modulator 220. The ΣΔ modulator 220 includes a forward path 221 and a feedback path 225. The forward path 221 may include a pair of analog chopper circuits 110A / 110B (external chopper circuit 110A and internal chopper circuit 110B), a voltage-to-current converter (OTA) 222 including its own offset, a loop filter (integrator) 223, and a sampling frequency / rate f. s224 is clocked by a coarse ADC (e.g., a 1-bit comparator) 224. Integrator 223 has the function of shaping the quantization noise to a higher frequency. OTA 222 can convert the differential voltage VIN between its non-inverting and inverting inputs into a current as its output. OTA 222 can also be called a differential (or differential) amplifier. Recall that the sensor signal VIN from the Hall sensor (or other sensor type) can be a very small, nearly DC signal with an offset error caused by the inherent characteristics of the Hall sensor. The external analog chopper 110A combines the analog sensor signal VIN with a chopping frequency f chop The resulting chopped analog input signal 112 has a period T chop =1 / f chop The signal component corresponding to the square wave and the DC offset error component.

[0038] The OTA 222 may then be used to amplify the chopped analog input signal 112. The OTA 222 may also introduce a DC amplifier offset error that is added to the DC offset error of the Hall sensor. After the chopped analog input signal 112 is amplified, the amplified signal at the output of the OTA 222 may be demodulated by the second internal analog chopper circuit 110B to generate a signal in which the sensor component of the signal component has its original low frequency while the offset component (including both the Hall offset and the amplifier offset) is at the chopping frequency f chop The coarse ADC 224 converts the output of the integrator 223 into a digital value, which is the digital output signal DOUT of the ΣΔ modulator 220. The coarse ADC 224 may include a digital decimation filter.

[0039] The feedback path 225 of the ΣΔ modulator 220 may include a chopping DAC 226, which converts the digital output signal DOUT to analog in order to combine with the output signal of the OTA 222. The combination is the difference between the amplified signal at the output of the OTA 222 and the output signal of the chopping DAC 226. Therefore, the difference is obtained in the current domain at the output of the OTA 222. The chopped analog input signal 112 can therefore be processed differentially in the current domain at the output of the OTA 222. The differential signal (the difference between the amplified signal at the output of the OTA 222 and the output signal of the chopping DAC 226) can essentially correspond to the quantization error and is presented to the second analog chopper circuit 110B and the integrator 223, whose output is performed in the negative direction or the positive direction. The slope and direction of the output of the integrator 223 depend on the sign and magnitude of the differential signal. When the differential signal equals the reference voltage (of the comparator) of the coarse ADC 224, the output of the coarse ADC 224 switches from negative to positive, or from positive to negative, depending on its initial state. The output value DOUT of the coarse ADC 224 is clocked back into the 1-bit DAC 226 and is clocked out to the digital filter stage (not shown).

[0040] When the analog choppers 110A, 110B change states (change amplitude from 1 to -1, or from -1 to 1) at their half cycles (chopping phases), the chopped analog input signal 112 changes its polarity, causing a current peak due to the charging of the parasitic capacitor (not shown) at the input of the OTA 222. The differential chopped analog input signal is mainly generated by the OTA 222 via the integrating capacitor (C int ) is provided. However, the feedback signal is chopped again to make it independent of the chopping edge direction. The feedback signal is then fed to the integrating capacitor (C int ) is integrated over f to produce a cumulative error signal. Any parasitic capacitor will also produce chop Sampling of quantization noise under .

[0041] Those skilled in the art who have benefited from this disclosure will appreciate that the chopped ΣΔ ADC circuit design is not limited to Figure 2 .

[0042] with Figure 1 and Figure 2 Compared to the chopped ΣΔADC circuit illustrated in , the present disclosure proposes a circuit using a non-chopped ΣΔADC circuit. Here, the non-chopped ΣΔADC circuit should be understood as a ΣΔADC configured without any chopper circuit, i.e., there is no chopper circuit in the feedforward path and no chopper circuit in the feedback path. The non-chopped ΣΔADC circuit can provide low offset, low / medium noise, and / or low ripple loop complexity.

[0043] Figure 3 A schematic block diagram of a circuit 200 is illustrated, and a circuit 300 implements a non-chopping ΣΔ ADC circuit for converting an analog input signal VIN (eg, a sensor signal) at an initial frequency into a digital output signal DOUT.

[0044] Similar to ADC circuit 100, circuit 300 includes analog chopper circuit 110, which is configured to shift analog input signal VIN 102 from the original frequency of the signal to a chopping frequency f chop to generate a chopped analog signal 112 at the input of the non-chopped ΣΔ ADC circuit 320. Again, the analog input signal VIN can be assumed to be band-limited, and the signal bandwidth can be assumed to be much lower than the sampling frequency f of the non-chopped ΣΔ ADC circuit 320. s The analog input signal VIN may include a signal component and an offset error component, which may be introduced by a sensor (not shown) measuring a physical quantity (e.g., a Hall sensor measuring a magnetic field). The analog chopper circuit (modulator) 110 may be considered to be external to the non-chopping ΣΔ ADC circuit 320 and include a chopping frequency f chop The modulator circuit is controlled or switched by the clock. The chopping frequency f chop The sampling frequency f of the non-chopping ΣΔ ADC circuit 320 may be much lower than s For example, at sampling frequency f s and the chopping frequency f chop The ratio between them can be greater than 100. At the chopping frequency f chop The chopping clock signal can be obtained by means of the timing circuit 130 from the sampling frequency f s It is derived from the sampling clock signal below, which has been explained in the previous text.

[0045] According to various example implementations, the non-chopped ΣΔ ADC circuit 320 may include—similar to the chopped ΣΔ ADC circuit 120—an amplifier circuit (not shown) for chopping the analog signal 112 to generate an amplified chopped analog signal. The non-chopped ΣΔ ADC circuit 320 may further include a ΣΔ modulator to convert the chopped analog signal 112 to a chopped digital signal 322 (ADCOUT). The ΣΔ modulator may convert the (amplified) chopped analog signal 112 to a digital signal having a sampling frequency f s The digital signal 322 is obtained by converting the 1-bit ADC of the chopped ΣΔ ADC circuit 120 into a digital signal 322. Compared with the 1-bit ADC of the chopped ΣΔ ADC circuit 120, the proposed non-chopped ΣΔ ADC circuit 320 may include a single-bit ADC or a multi-bit ADC having a bit width greater than 2 bits.

[0046] Figure 3The circuit 300 also includes a digital chopper circuit 310 (digital demodulator) that is coupled to the output of the non-chopped ΣΔ ADC circuit 320 and is configured to demodulate the chopped digital signal 322 to generate a demodulated digital signal 328 having a signal component at the initial frequency. Similar to the analog chopper circuit 110, the digital chopper circuit (demodulator) 310 can be considered to be external to the non-chopped ΣΔ ADC circuit 320 and includes a demodulator that uses a chopped digital signal at the chopping frequency f. chop Therefore, both the analog chopper circuit (modulator) 110 and the digital chopper circuit (demodulator) 310 are outside (outside) the non-chopped ΣΔ ADC circuit 320. The non-chopped ΣΔ ADC circuit 320 itself does not include any chopper circuit.

[0047] Figure 4A An embodiment of a sensor circuit 300 including a non-chopped ΣΔ ADC circuit 320 is shown.

[0048] For example, the analog chopper circuit 110 combines the analog sensor signal VIN with a chopping frequency f chop And square waves with amplitudes of +1 and -1 are multiplied. In the example shown, the chopping frequency f chop is 312kHz. The generated chopped analog input signal 112 has a signal component with a period T chop =1 / f chop And the square wave corresponding to the offset error component of DC. An amplifier (not shown) coupled to the output of the analog chopper 110 can then be used to amplify the chopped analog input signal 112. The amplifier (e.g., OTA) can also introduce a DC amplifier offset error that is added to the DC offset error of the Hall sensor. The (amplified) chopped analog input signal 112 can then be fed into a non-chopped ΣΔ ADC circuit 320, which can also be referred to as a non-chopped ΣΔ modulator circuit. The non-chopped ΣΔ modulator circuit 320 includes a forward path 321 and a feedback path 325.

[0049] At its input, the non-chopped ΣΔ modulator circuit 320 includes a differentiator 327 for determining the difference between the chopped analog input signal 112 and the chopped digital signal 322, wherein the chopped digital signal 322 is sent back from the output of the non-chopped ΣΔ modulator circuit 320. This difference can be regarded as a quantization error. The quantization error is then further passed from the differentiator 327 to the analog loop filter (integrator) 323 in the feedforward path 321 of the non-chopped ΣΔ modulator circuit 320. The feedforward path 321 also includes a multi-bit ADC 324 coupled to the output of the analog loop filter 323. For example, the multi-bit ADC 324 can have a bit width of 2 to 4 bits and can utilize a sampling frequency fs In the example shown, the sampling frequency f s is 40MHz, that is, f s / f chop >100.

[0050] The function of the analog loop filter 323 is to shape the noise and attenuate the out-of-band signal before feeding it to the multi-bit ADC 324. This can also help to achieve high-order noise shaping. The analog loop filter 323 in the forward path 321 can be implemented in continuous time (CT) using a combination of analog components (such as operational amplifiers) and passive components. This means that the CT analog loop filter 323 operates on a continuous time signal without any discrete sampling or quantization. The CT analog loop filter 323 can provide high accuracy and is very suitable for high frequency applications. The latter can be a sampling frequency f s and the chopping frequency f chop There may be a case where the ratio between φ and φ is greater than 100. This larger ratio provides the non-chopping ΣΔ modulator circuit 320 with a wideband characteristic.

[0051] like Figure 4A As shown in the example of , for example, the order of the analog loop filter 323 can be second order or third order. The order refers to the number of integrators cascaded in the analog loop filter 323. It indicates the complexity and degree of filtering implemented by the analog loop filter 323. The order of the analog loop filter 323 is determined by the desired noise shaping characteristics and the specific requirements of the application. In general, higher order loop filters provide better noise shaping performance but may require more complex circuit devices and introduce additional challenges in terms of stability and implementation methods. The order of the loop filter is usually expressed as an integer value. For example, a first order loop filter includes one integrator or energy storage element, while a second order loop filter includes two integrators, and so on. The selection of the order of the loop filter depends on various factors, such as the desired noise shaping performance, the signal bandwidth of interest, the available resources, and the trade-off between complexity, stability and power consumption.

[0052] The analog loop filter 323 and the sampling frequency f s With the chopping frequency f chop The ratio between can be designed so that the non-chopping ΣΔ modulator circuit 320 allows the chopping frequency f chop For example, the analog loop filter 323 and the sampling frequency f s With the chopping frequency f chop The ratio between can be designed so that up to at least the third harmonic of the chopping frequency f chopThe non-chopped ΣΔ modulator circuit 320 can be used. For example, the analog loop filter 323 and the sampling frequency f s With the chopping frequency f chop The ratio between can be designed so that up to at least the fifth harmonic of the chopping frequency f chop The non-chopped ΣΔ modulator circuit 320 may be passed without attenuation.

[0053] The feedback path 325 of the non-chopped ΣΔ modulator circuit 320 may include a non-chopped multi-bit DAC (also referred to as a ΣΔ DAC) 326 to convert the chopped digital signal 322 (ADCOUT) to analog for combination with the chopped analog input signal 112. For example, the multi-bit DAC 326 may have a bit width of four to six bits and may be controlled by the sampling frequency f s Clock control. As described above, the combination at the differentiator 327 can be the difference between the (amplified) chopped analog input signal 112 and the output signal of the non-chopped multi-bit DAC 326. For example, the difference can be obtained in the current domain at the output of the selectable amplifier. The chopped analog input signal 112 can therefore be processed differentially in the current domain. The differential signal (the difference between the chopped analog input signal 112 and the output signal of the non-chopped DAC 326) is presented to the analog loop filter (integrator) 323, and the output of the analog loop filter 323 is performed in the negative direction or the positive direction. The slope and direction of the output of the integrator 323 depend on the sign and size of the differential signal. It will be understood by the technicians who benefit from this disclosure that in the case where the ADC 324 is implemented as a single-bit ADC, the DAC 326 can also be implemented as a single-bit DAC.

[0054] exist Figure 4A In the sensor circuit 300, the chopped digital signal 322 at the output of the multi-bit ADC 324 is then fed to a digital chopper circuit (demodulator) 310, which is configured to combine the chopped digital signal 322 with a chopped frequency f chop The digital demodulation signal 312 is multiplied by 312 to obtain the digital demodulation signal 328. Although the digital demodulation signal 312 can be a binary signal (e.g., ±1), it can also be preferred to use a sinusoidal digital demodulation signal 312 (e.g., sin(2πf chop t)). In this way, the generation of harmonics can be reduced. Therefore, the counterpart of the modulation performed by the analog chopper circuit 110 at the input of the non-chopped ΣΔ modulator circuit 320 is the digital chopper circuit 310 at the output of the non-chopped ΣΔ modulator circuit 320. Figure 4AIn the example of , reference numeral 312 also denotes a modulation signal for the analog chopper circuit 110. A skilled person having benefit of this disclosure will appreciate that the modulation signal and the demodulation signal may be different signals, and only the (digital) demodulation signal 312 may be sinusoidal.

[0055] The digital demodulated signal 328 may be fed to a digital filter 330 that is coupled to the output of the digital chopper circuit 310 and configured to reject signals having at least the chopping frequency f chop The digital filter 330 may be composed of a filter having a chopping frequency f chop The digital filter 330 may include a clock signal having at least a chopping frequency f chop The digital notch filter with a notch below the chopping frequency f chop Other notches at one or more harmonics of may be preferred. A digital notch filter is a digital filter designed to filter a signal typically at a specific frequency (here: f chop ) is centered to attenuate or reject a specific narrow range of frequencies while allowing other frequencies to pass unaffected. It can be used to remove or suppress unwanted interference or noise at specific frequencies in a digital signal. The main purpose of a digital notch filter is to attenuate or reject a specific narrow range of frequencies centered on f chop The invention relates to creating a "notch" or deep attenuation in the frequency response below the specified frequency (around 1000). This can be achieved using various filter design techniques such as infinite impulse response (IIR) or finite impulse response (FIR) filters. In an IIR digital notch filter, feedback is used to create a deep space or attenuation at a specified frequency. It is characterized by a recursive equation that refers to the previous output sample. IIR filters can provide high attenuation levels and are computationally efficient, but they may introduce phase distortion. On the other hand, FIR digital notch filters are distortionless filters that do not rely on feedback. They are designed using a finite number of coefficients and provide linear phase characteristics, which means that they do not introduce phase distortion. FIR filters can be designed to have sharp notches and provide precise control over the frequency response.

[0056] exist Figure 4A In the sensor circuit 300, the filtered digital signal 332 at the output of the digital filter 330 is then coupled to the digital decimation filter 340 to convert the filtered digital signal 332 to an output data rate f D <f s The digital output signal (DOUT) under the condition of f sThe filtered digital signal 332 is sampled at low frequencies and converted to a high resolution, lower digital code. While most converters have one sampling rate, the ΣΔ ADC has two—the input sampling rate / frequency f s and the output data rate f D . The decimation filter 340 is a digital filter that reduces the sampling rate of the filtered digital signal 332. The main purpose of the decimation filter 340 is to extract a lower rate representation of the filtered digital signal 332 while retaining the necessary information. This is achieved by filtering out unwanted high frequency components and then discarding or downsampling portions of the filtered signal. The decimation filter 340 can incorporate an anti-aliasing filter as its first stage. When the signal is subsequently downsampled, the anti-aliasing filter attenuates high frequency components above the desired signal bandwidth to prevent aliasing. The filter removes unwanted spectral components that may cause distortion or artifacts in the downsampled signal. After anti-aliasing filtering, the decimation filter 340 can reduce the sampling rate by discarding or selecting a subset of samples from the filtered signal. Downsampling reduces the number of samples in the signal while maintaining the desired frequency components within the reduced bandwidth. The digital decimation filter 340 can be implemented using various digital filter structures (such as finite impulse response (FIR) or infinite impulse response (IIR) filters).

[0057] Figure 4B Yet another embodiment of a sensor circuit 300 including a non-chopping ΣΔ ADC or ΣΔ modulator circuit 320 is shown.

[0058] exist Figure 4B In the sensor circuit of FIG. 1 , the chopped digital signal 322 at the output of the multi-bit ADC 324 is fed to a first digital notch filter 330-1 coupled between the multi-bit ADC 324 and the digital chopper circuit (demodulator) 310. The first digital notch filter 330-1 may have a frequency of at least 0.01 kHz at the chopping frequency f chop For example, the first digital notch filter 330-1 may be configured to remove the chopping frequency f chop In the case of an FIR filter, the first digital notch filter 330-1 may cause a filter delay. Therefore, Figure 4B The sensor circuit 300 further includes a delay element 334 coupled between the chopping clock signal and the digital chopper circuit 310. The delay element 334 is configured to cause a delay in the chopping signal corresponding to the filter delay of the first digital notch filter 330-1. The delayed (sinusoidal) chopping signal can then be multiplied with the digital output signal of the first digital notch filter 330-1 to obtain a filtered chopped digital signal 322'. The filtered chopped digital signal 322' can then be further processed as described in reference Figure 4A Process as explained. Figure 4B The two notch filters 330-1 and 330-2 in the embodiment can help to better reduce the chopping frequency f chop Instead of the first digital notch filter 330-1, or in addition to the first digital notch filter 330-1, a filter configured to allow the signal component at the initial frequency to pass through while attenuating the signal component at the chopping frequency f chop A low-pass filter of signal components at frequencies lower than 100 Hz or higher is also conceivable.

[0059] The present disclosure proposes a non-chopping wideband / bandpass CTΣΔADC to pass both the chopped signal and the offset. Instead of a conventional feedback loop for removing the offset, instead of chopping the integrator stage inside the ΣΔADC, the present disclosure proposes using an all-digital technique to remove the offset and reduce the noise folding associated with demodulating the quantization noise from the harmonics of the chopped signal.

[0060] The aspects and features described with respect to a specific one of the foregoing examples may also be combined with one or more of the other examples to replace equivalent or similar features of the other examples, or to additionally introduce features into the other examples.

[0061] The example may further be or relate to a (computer) program, which includes a program code that performs one or more of the above methods when the program is executed on a computer, a processor or other programmable hardware component. Therefore, the steps, operations or processes of the different methods described above may also be performed by a programmed computer, a processor or other programmable hardware component. The example may also cover a program storage device (such as a digital data storage medium), which is machine, processor or computer readable and encodes and / or includes machine executable, processor executable or computer executable programs and instructions. For example, the program storage device may include or may be a digital storage device, a magnetic storage medium (such as a disk and a tape), a hard drive or an optically readable digital data storage medium. Other examples may also include a computer, a processor, a control unit, a (field) programmable logic array ((F)PLA), a (field) programmable gate array ((F)PGA), a graphics processor unit (GPU), an application specific integrated circuit (ASIC), an integrated circuit (IC) or a system on a chip (SoC) that is programmed to perform the steps of the above method.

[0062] It is further understood that, unless explicitly stated in individual cases or necessary for technical reasons, the disclosure of several steps, processes, operations or functions disclosed in the specification or claims should not be interpreted as implying that these operations must rely on the described order. Therefore, the foregoing description does not limit the execution of several steps or functions to a certain order. In addition, in other examples, a single step, function, process or operation may include and / or be decomposed into several sub-steps, sub-functions, sub-processes or sub-operations.

[0063] If some aspects have been described with respect to a device or system, these aspects should also be understood as descriptions of the corresponding methods. For example, a block, device, or functional aspect of a device or system may correspond to a feature of a corresponding method, such as a method step. Therefore, aspects described with respect to a method should also be understood as descriptions of corresponding blocks, corresponding elements, attributes, or functional features of a corresponding device or system.

[0064] The following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. It should also be noted that although in the claims, a dependent claim refers to a specific combination with one or more other claims, other examples may also include a combination of a dependent claim with the subject matter of any other dependent claim or independent claim. Unless it is stated in individual cases that a specific combination is not intended, such a combination is hereby explicitly proposed. In addition, features of a claim should also be included with respect to any other independent claim, even if the claim is not directly defined as dependent on the other independent claim.

Claims

1. A sensor circuit (300), comprising: an analog chopper circuit (110) configured to shift an analog input signal from an initial frequency to a chopping frequency to generate a chopped analog signal (112); a ΣΔ modulator (320) coupled to the output of the analog chopper circuit (110) and configured to digitize the chopped analog signal (112) at a sampling frequency to generate a chopped digital signal (322); as well as A digital chopper circuit (310) is coupled to the output of the ΣΔ modulator (320) and is configured to demodulate the chopped digital signal (322) to generate a demodulated chopped digital signal (328) having a signal component at the initial frequency.

2. The sensor circuit (300) of claim 1, wherein the ΣΔ modulator (320) is configured without a chopper circuit.

3. The sensor circuit (300) according to claim 1 or 2, wherein a ratio between the sampling frequency and the chopping frequency of the ΣΔ modulator (320) is greater than 100.

4. The sensor circuit (300) according to any of the preceding claims, wherein the ΣΔ modulator (320) comprises an ADC (324) and an analog loop filter (323) coupled between the output of the analog chopper circuit (110) and the ADC (324).

5. The sensor circuit (300) of claim 4, wherein the analog loop filter (323) is implemented as a continuous-time loop filter.

6. The sensor circuit (300) of any one of the preceding claims, wherein the ΣΔ modulator (320) comprises a multi-bit ADC (324) configured to convert the chopped analog signal (112) from analog to digital to generate the chopped digital signal (322).

7. The sensor circuit (300) of claim 6, wherein the multi-bit ADC (324) has a bit width equal to or greater than two bits.

8. A sensor circuit (300) according to claim 6 or 7, wherein the ΣΔ modulator (320) includes a feedback path (325) from the output of the ΣΔ modulator to the input of the ΣΔ modulator, the feedback path including a multi-bit DAC (326) configured to convert the chopped digital signal (322) back to analog.

9. The sensor circuit (300) of claim 8, wherein the multi-bit DAC (326) has a bit width greater than or equal to 2 bits.

10. The sensor circuit (300) of any one of claims 1 to 5, wherein the ΣΔ modulator (320) comprises a single-bit ADC (324) configured to convert the chopped analog signal (112) from analog to digital to generate the chopped digital signal (322).

11. The sensor circuit (300) of claim 10, wherein the ΣΔ modulator (320) comprises a feedback path (325) from the output of the ΣΔ modulator to the input of the ΣΔ modulator, the feedback path comprising a single-bit DAC (326) configured to convert the chopped digital signal (322) back to analog.

12. The sensor circuit (300) according to any one of the preceding claims, further comprising: A digital filter (330) is coupled to the output of the digital chopper circuit (310) and is configured to suppress at least the chopping frequency f chop .

13. The sensor circuit (300) of claim 12, wherein the digital filter (330) comprises a notch filter having a notch at least at the chopping frequency.

14. The sensor circuit (300) of claim 12 or 13, wherein the digital filter (330) comprises a low-pass filter configured to allow the signal component at the initial frequency to pass while attenuating signal components at the chopping frequency or higher.

15. The sensor circuit (300) according to any one of claims 12 to 14, wherein the digital filter (330) comprises a combination of a low pass filter and a notch filter.

16. The sensor circuit (300) according to any one of the preceding claims, further comprising: A digital filter (330-1) is coupled between the ΣΔ modulator (320) and the digital chopper circuit (310) and is configured to suppress harmonics of the chopping frequency.

17. The sensor circuit (300) of claim 16, wherein the digital filter (330-1) causes a filter delay, and wherein the sensor circuit further comprises a delay element (334) coupled between a chopping clock signal and the digital chopper circuit (310), wherein the delay element (334) is configured to cause a delay in the chopping clock signal corresponding to the filter delay.

18. The sensor circuit (300) according to any one of the preceding claims, further comprising: An amplifier is coupled between the analog chopper circuit (110) and the ΣΔ modulator (320) and is configured to amplify the chopped analog signal (112).

19. The sensor circuit (300) of any one of the preceding claims, wherein the digital chopper circuit (310) is configured to multiply the chopped digital signal (322) with a digital sinusoidal signal having the chopping frequency.

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