Image processing apparatus

Abstract

The purpose of the present invention is to provide an image processing device capable of shortening the delay time of an output video signal relative to an input video signal. The present invention comprises: a memory which, when a video signal is input, reads out the written video signal at the timing of a read-out clock signal while writing the video signal, and outputs the read-out video signal as an output video signal; a horizontal synchronization detection circuit that detects a horizontal synchronization signal from the video signal; a phase comparator that generates a phase difference signal indicating a phase difference between a phase of the horizontal synchronization signal and a phase of the divided clock signal; a lock circuit that generates a reference clock signal in which the phase of the self-propelled clock signal is shifted by the amount of the phase difference indicated by the phase difference signal; a PLL that generates an oscillation signal having a dot frequency of the video signal, and generates a readout clock signal from a signal in which the phase of the oscillation signal and the phase of the reference clock signal are locked; and a frequency divider that supplies a clock signal obtained by dividing the readout clock signal as a divided clock signal to the phase comparator.

Description

Technical Field

[0001] The present invention relates to an image processing device for synchronously outputting video signals. Background Art

[0002] In recent years, a display system including a camera for capturing images outside the vehicle and a display device for displaying images based on a video signal captured by the camera is mounted on vehicles such as automobiles.

[0003] The display device is provided with an image processing device that adjusts the input video signal to a timing suitable for the display device (for example, see Patent Document 1). When performing such an adjustment, the image processing device uses a frame memory as a buffer memory. For example, while writing the video signal to the frame memory, the video signal is read from the frame memory at a predetermined timing, thereby adjusting the synchronization timing of the video signal.

[0004] Prior art literature Patent Literature Patent document 1: Japanese Patent Application Publication No. 2019-71066. Summary of the invention

[0005] Problems to be solved by the invention However, when the reading speed of the frame memory is faster than the writing speed, the frame memory may become empty. Therefore, in order to avoid this state, the image processing device reads out the input video signal after writing one or two frames of the input video signal. As a result, the output video signal is supplied to the display device after a delay time of one or two frames relative to the input video signal, which causes a large time lag in the image display of the input video signal.

[0006] Therefore, an object of the present invention is to provide an image processing device capable of shortening the delay time of an output video signal with respect to an input video signal.

[0007] Solutions to Solve Problems The image processing device of the present invention includes: a memory, which, when a video signal is input, writes the video signal while reading the written video signal at the timing of a read clock signal and outputs it as an output video signal; a horizontal synchronization detection circuit, which detects a horizontal synchronization signal from the video signal; a phase comparator, which generates a phase difference signal, wherein the phase difference signal shows the phase difference between the phase of the horizontal synchronization signal and the phase of a divided clock signal; a locking circuit, which receives a free-running clock signal and generates a reference clock signal by shifting the phase of the free-running clock signal by the amount of the phase difference shown by the phase difference signal; a PLL, which generates an oscillation signal with a dot frequency and generates a signal whose phase is locked with the phase of the reference clock signal as the read clock signal; and a frequency divider, which supplies a clock signal obtained by dividing the read clock signal to the phase comparator as the divided clock signal.

[0008] In addition, the image processing device of the present invention includes: a memory, which, when a video signal is input, writes the video signal while reading the written video signal at the timing of a read clock signal and outputs it as an output video signal; a horizontal synchronization detection circuit, which detects a horizontal synchronization signal from the video signal; a frequency multiplication circuit, which generates a signal that makes the frequency of the horizontal synchronization signal N times as a horizontal synchronization frequency multiplication signal, wherein N is a real number greater than 2; a phase comparator, which generates a phase difference signal, wherein the phase difference signal shows the phase difference between the phase of the horizontal synchronization frequency multiplication signal and the phase of the divided clock signal; a locking circuit, which receives a free-running clock signal and generates a reference clock signal that shifts the phase of the free-running clock signal by the amount of the phase difference shown by the phase difference signal; a PLL, which generates an oscillation signal with a dot frequency, and generates a signal whose phase is locked with the phase of the reference clock signal as the read clock signal; and a frequency divider, which supplies a clock signal obtained by dividing the read clock signal to the phase comparator as the divided clock signal.

[0009] Effects of the Invention In the present invention, when an input video signal is written into a memory and read out as an output video signal, a read clock signal synchronized in phase with a horizontal synchronization signal of the input video signal is generated, and the video signal is read out from the memory at the timing of the read clock signal.

[0010] This makes it possible to reduce the delay time of the output video signal with respect to the input video signal to less than the display period of one frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : is a block diagram showing the structure of a video system 100 including the image processing apparatus of the present invention. Figure 2It is a block diagram showing an example of the internal structure of the image processing device 20. Figure 3 2 is a timing chart showing an example of the waveforms of the horizontal synchronization signal HD and the divided clock signal CKd. Figure 4 1 is a timing chart showing how the output video signal VDX output by the image processing device 20 is delayed according to the input video signal VD. Figure 5 2 is a block diagram showing another example of the internal structure of the image processing device 20 . Figure 6 2 is a timing chart showing an example of the waveforms of the horizontal synchronization frequency-multiplied signal HDm and the frequency-divided clock signal CKe. DETAILED DESCRIPTION

[0012] Hereinafter, a mode for carrying out the present invention will be described in detail with reference to the drawings.

[0013] Figure 1 : is a block diagram showing the structure of a video system 100 including the image processing apparatus of the present invention.

[0014] like Figure 1 As shown, the video system 100 includes a video signal generating device 10 , an image processing device 20 and a display device 30 .

[0015] The video signal generating device 10 is constituted by, for example, a DVD or Blu-ray player (recorder), a TV tuner, a camera, etc., and supplies a video signal acquired or reproduced by itself as a video signal VD to the image processing device 20. In addition, the video signal VD includes a sequence of pixel data pieces, which shows the brightness level of each pixel constituting the screen of the display device 30.

[0016] When receiving the video signal VD from the video signal generating device 10, the image processing device 20 generates an output clock signal CLKX as a clock signal used on the display device 30 side and an output video signal VDX synchronized with the phase of the output clock signal CLKX based on the video signal VD. Then, the image processing device 20 outputs the output clock signal CLKX and the output video signal VDX to the display device 30.

[0017] The display device 30 is a display using, for example, liquid crystal or organic EL, and receives an output video signal VDX at a timing synchronized with the output clock signal CLKX to display an image based on the output video signal VDX.

[0018] Figure 2 It is a block diagram showing an example of the internal structure of the image processing device 20.

[0019] like Figure 2 As shown, the image processing device 20 includes a horizontal synchronization detection circuit 201, a phase comparator 202, an input sensing circuit 203, a locking circuit 204, a PLL (Phase Locked Loop) 205, a frequency divider 206, a frame memory 207 and a clock buffer 208.

[0020] The horizontal synchronization detection circuit 201 detects a horizontal synchronization signal from the video signal VD, and supplies it to the phase comparator 202 as a horizontal synchronization signal HD.

[0021] The phase comparator 202 compares the phase of the horizontal synchronization signal HD with the phase of the divided clock signal CKd supplied from the frequency divider 206 , and supplies a phase difference signal PH indicating the phase difference between the two to the lock circuit 204 .

[0022] For example, Figure 3 As shown, when the timing of the rising edge portion of the divided clock signal CKd (indicated by a white triangle mark) is delayed by dW relative to the timing of the rising edge portion of the horizontal synchronization signal HD (indicated by a white triangle mark) that appears in each horizontal synchronization period H, the phase comparator 202 supplies the phase difference signal PH as a phase difference indication (-dW) to the lock circuit 204. In addition, when the timing of the rising edge portion of the divided clock signal CKd is advanced by dW relative to the timing of the rising edge portion of the horizontal synchronization signal HD, the phase comparator 202 supplies the phase difference signal PH as a phase difference indication (dW) to the lock circuit 204.

[0023] The input sensing circuit 203 generates an input sensing signal ID which indicates "input is present" when the video signal VD is received, i.e., when the video signal is input, and indicates "no input" when the video signal VD is not input, i.e., when there is no input. The input sensing circuit 203 supplies the generated input sensing signal ID to the locking circuit 204.

[0024] The lock circuit 204 receives the phase difference signal PH, the input sensing signal ID, and the free-running clock signal CLKF. The free-running clock signal CLKF is a free-running clock signal generated by oscillation of an oscillation circuit (not shown) provided outside the image processing device 20, for example.

[0025] When the input sensing signal ID indicates “input present”, the locking circuit 204 generates a reference clock signal CKr phase-locked with the video signal VD by shifting the phase of the free-running clock signal CLKF by the phase difference indicated by the phase difference signal PH, and supplies it to the PLL 205 .

[0026] On the other hand, when the input sense signal ID indicates “no input”, the lock circuit 204 supplies the free-running clock signal CLKF as the reference clock signal CKr to the PLL 205 .

[0027] PLL 205 generates an oscillation signal having the dot frequency of the input video signal VD, and supplies a signal whose phase is locked with the phase of the reference clock signal CKr as a readout clock signal CKrd to the frequency divider 206 , the frame memory 207 , and the clock buffer 208 .

[0028] The frequency divider 206 generates a clock signal having a horizontal synchronization frequency by dividing the frequency of the read clock signal CKrd, and supplies the clock signal to the phase comparator 202 as the divided clock signal CKd.

[0029] When a video signal VD is input, the frame memory 207 sequentially imports and writes each of the pixel data slices included in the video signal VD, and outputs the pixel data slices read out in the order of writing at the timing of the read clock signal CKrd to the display device 30 as an output video signal VDX.

[0030] The clock buffer 208 outputs a signal obtained by amplifying the read clock signal CKrd to the display device 30 as the output clock signal CLKX.

[0031] According to such a configuration, when the video signal VD is input, the image processing device 20 writes the video signal VD into the frame memory 207, and outputs the output video signal VDX read out at a timing synchronized in phase with the horizontal synchronization signal HD of the input video signal VD to the display device 30. Furthermore, together with the output video signal VDX, the image processing device 20 outputs the output clock signal CLKX synchronized in phase with the horizontal synchronization signal HD of the video signal VD to the display device 30. On the other hand, when the video signal VD is not input, the image processing device 20 outputs the output clock signal CLKX synchronized in phase with the free-running clock signal CLKF to the display device 30.

[0032] Therefore, through the operation of the above-mentioned image processing device 20, as Figure 4 As shown, the delay time DL of the output video signal VDX supplied to the display device 30 with respect to the input video signal VD can be made shorter than the one-frame display period F.

[0033] However, in the case where the image processing device 20 adopts Figure 2 In the case of the structure shown, Figure 3As shown, the phase comparison between the horizontal synchronization signal HD of the video signal VD and the divided clock signal CKd is performed once in each horizontal scanning period H. At this time, the more times the phase comparison is performed per unit time, the higher the accuracy of the phase synchronization can be, so, for example, the dot frequency of the pixel data slice in the video signal VD, that is, the sampling frequency, is increased in frequency.

[0034] However, when a high-speed video signal conforming to a standard such as LVDS (Low Voltage Differential Signaling) or MIPI (Mobile Industry Processor Interface) is input, it is difficult to increase the sampling frequency without reducing the sampling accuracy.

[0035] Figure 5 1 is a block diagram showing another example of the internal structure of the image processing device 20 which can generate the output video signal VDX which is phase-synchronized with the input video signal VD with high accuracy even when such a high-speed video signal is input.

[0036] In addition, Figure 5 In the structure shown in FIG. 1 , a frequency multiplication circuit 210 is newly added, and a phase comparator 202a and a frequency divider 206a are used instead of the phase comparator 202 and the frequency divider 206. The other structures are the same as those of FIG. 1 . Figure 2 The structures shown are the same.

[0037] Therefore, the following describes the frequency multiplication circuit 210, the phase comparator 202a and the frequency divider 206a as the center. Figure 5 The operation of the image processing device 20 having the structure shown.

[0038] The frequency multiplication circuit 210 receives the horizontal synchronization signal HD detected by the horizontal synchronization detection circuit 201 , and supplies a signal obtained by multiplying the frequency of the horizontal synchronization signal HD by N (N is a positive real number other than 0) as a horizontal synchronization frequency multiplication signal HDm to the phase comparator 202 .

[0039] The frequency divider 206a supplies the divided clock signal CKe obtained by dividing the read clock signal CKrd output from the PLL 205 so that the divided frequency becomes N (N is a positive real number other than 0) times the horizontal synchronization frequency to the phase comparator 202a.

[0040] The phase comparator 202 compares the phase of the horizontal synchronization frequency-multiplied signal HDm with the phase of the divided clock signal CKe, and supplies a phase difference signal PH indicating the phase difference between the two to the lock circuit 204 .

[0041] That is, the phase comparator 202a supplies the phase difference signal PH to the locking circuit 204. Figure 6 The figure shows the phase difference of the rising edge portion (indicated by a white triangle mark) of the divided clock signal CKe with respect to the rising edge portion (indicated by a white triangle mark) of the horizontal synchronization signal HDm that appears N times in each horizontal synchronization period H.

[0042] Therefore, according to Figure 5 The structure shown in FIG. 1 is adopted because the number of phase comparisons performed during each horizontal scanning period H becomes Figure 2 The structure shown is N times that shown, so it is possible to generate an output video signal VDX that is phase-synchronized with a high-speed input video signal that complies with standards such as LVDS or MIPI with high precision.

[0043] In addition, Figure 2 or Figure 5 In the illustrated configuration, the read clock signal CKrd and the output clock signal CLKX are generated using the free-running clock signal CLKF supplied externally. However, an oscillation circuit that generates the free-running clock signal CLKF may be provided in the image processing device 20 .

[0044] Description of Reference Numerals 20: Image processing device 201: Horizontal synchronization detection circuit 202, 202a: Phase comparator 203: Input sensing circuit 204: Locking circuit 205: PLL 206, 206a: Divider 207: Frame memory 210: Frequency doubling circuit.

Claims

1. An image processing device, characterized in that: include: a memory that, when a video signal is input, writes the video signal while reading out the written video signal at the timing of a read clock signal and outputs it as an output video signal; A horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal; a phase comparator for generating a phase difference signal, wherein the phase difference signal indicates a phase difference between a phase of the horizontal synchronization signal and a phase of the divided clock signal; a locking circuit that receives a free-running clock signal and generates a reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal; PLL, generating an oscillation signal with a dot frequency, and generating a signal whose phase of the oscillation signal is locked with the phase of the reference clock signal as the readout clock signal; as well as The frequency divider supplies a clock signal obtained by frequency-dividing the read clock signal as the frequency-divided clock signal to the phase comparator.

2. An image processing device, characterized in that: include: a memory that, when a video signal is input, writes the video signal while reading out the written video signal at the timing of a read clock signal and outputs it as an output video signal; A horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal; A frequency multiplication circuit, generating a signal that makes the frequency of the horizontal synchronization signal N times as a horizontal synchronization frequency multiplication signal, wherein N is a real number greater than 2; a phase comparator, generating a phase difference signal, wherein the phase difference signal indicates a phase difference between a phase of the horizontal synchronization frequency-multiplied signal and a phase of the frequency-divided clock signal; a locking circuit that receives a free-running clock signal and generates a reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal; PLL, generating an oscillation signal with a dot frequency, and generating a signal whose phase of the oscillation signal is locked with the phase of the reference clock signal as the readout clock signal; as well as The frequency divider supplies a clock signal obtained by frequency-dividing the read clock signal as the frequency-divided clock signal to the phase comparator.

3. The image processing device according to claim 1 or 2, characterized in that: An input sensing circuit is included, wherein the input sensing circuit detects whether the video signal is input and generates an input sensing signal indicating whether there is input or no input, The locking circuit generates the reference clock signal by shifting the phase of the free-running clock signal by the amount of the phase difference indicated by the phase difference signal when the input sensing signal indicates that there is input, and uses the free-running clock signal as the reference clock signal when the input sensing signal indicates that there is no input.

4. The image processing device according to claim 1 or 2, characterized in that: The memory is a frame memory.

5. The image processing device according to claim 1 or 2, characterized in that: A clock buffer is included, and the clock buffer outputs the read clock signal externally as an output clock signal.

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