Graphene oxide circuit board and preparation method thereof
By setting graphene oxide in the line trench of the conductive line layer and reducing the graphene layer and setting the conductor layer, the problems of limited line fineness and complex electroplating layer in the production of thick copper circuit boards are solved, and the problem of the reduction of the graphene layer and complexity of the electroplating layer in the production of thick copper circuit boards is achieved. Efficient production and yield improvements, while improving the heat dissipation performance of the circuit board.
Patent Information
- Application Number
- CN202311028565.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-21
AI Technical Summary
During the production process, thick copper circuit boards have problems such as limited line fineness, complex electroplating layer and easy to lead to poor line, resulting in low production yield.
By providing graphene oxide in the line trench of the conductive line layer, reducing the surface graphene oxide to a graphene layer, and then setting a conductor layer for wiring production, the thickening of the conductive line layer is achieved.
The production of thick copper and thin circuits is realized, avoiding the burrs after etching caused by the metallization process, improving product yield and production efficiency, and improving the overall heat dissipation performance of the circuit board.
Smart Images
Figure CN119497308A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit boards, and in particular to a graphene oxide circuit board and a preparation method thereof. Background Art
[0002] With the rapid development of electronic and power communication technology, some high-current and high-power power products are increasingly widely used. The number of functional components integrated on the circuit board is increasing, and the requirements for the current conduction capacity and carrying capacity of the circuit are also getting higher and higher. Correspondingly, the copper thickness of the circuit board is getting thicker and thicker, so thick copper circuit boards have gradually become a type of circuit board with broad market prospects. However, thick copper circuit boards often have the following problems during use: the line width of the conventional printed circuit board (PCB) production process is limited by the thickness of the copper layer. The thinner the copper layer, the thinner the line, so the use of thick copper to make thin lines has its own limitations; when electroplating the layer, the metallization process must be realized within the line spacing, the processing is complicated, and it is easy to cause poor lines (such as burrs after etching, etc.), and the production yield is low. Summary of the invention
[0003] In view of this, the present application proposes a graphene oxide circuit board and a preparation method thereof to solve at least one of the above problems.
[0004] An embodiment of the present application provides a method for preparing a graphene oxide circuit board, comprising the following steps:
[0005] Prepare a substrate: the substrate comprises a first conductive circuit layer and a second conductive circuit layer formed on the surface of the first conductive circuit layer, the first conductive circuit layer has a first circuit groove, the second conductive circuit layer has a second circuit groove, the second circuit groove is arranged corresponding to the first circuit groove, and graphene oxide is arranged in the first circuit groove and the second circuit groove;
[0006] Reduction: reducing the graphene oxide on the surface into a graphene layer to obtain an intermediate;
[0007] Adding layers; disposing a conductor layer on the surface of the intermediate body, and manufacturing the conductor layer to form a third conductive circuit layer, wherein the third conductive circuit layer has a third circuit groove, and the third circuit groove is arranged corresponding to the second circuit groove;
[0008] Removing: removing the graphene layer;
[0009] Filling: Filling graphene oxide in the third circuit groove to obtain the graphene oxide circuit board.
[0010] In one embodiment, the steps of reducing, adding layers, removing and filling are repeated multiple times.
[0011] In one embodiment, the method of reducing the graphene oxide on the surface into a graphene layer includes a hydrogen plasma method, a water vapor method or an intense pulsed light method.
[0012] In one embodiment, the method of removing the graphene layer includes sandblasting or plasma cleaning.
[0013] In one embodiment, the step of preparing the substrate comprises:
[0014] Providing a metal layer, and manufacturing a first conductive circuit layer on the surface of the metal layer, wherein the first conductive circuit layer has a first circuit groove, and a portion of the surface of the metal layer is exposed from the first circuit groove;
[0015] Filling graphene oxide in the first line groove;
[0016] The metal layer is fabricated into a second conductive circuit layer, wherein the second conductive circuit layer has a second circuit groove;
[0017] Graphene oxide is filled in the second line groove, and the graphene oxide in the second line groove contacts the graphene oxide in the first line groove to form a dielectric layer.
[0018] In one embodiment, the thickness of the graphene oxide in the first circuit groove is 0.5 nm to 500 nm, and the thickness of the graphene oxide in the second circuit groove is 0.5 nm to 500 nm.
[0019] In one embodiment, the material of the metal layer includes copper, gold, and silver.
[0020] In one embodiment, the conductor layer is made of copper, gold or silver.
[0021] An embodiment of the present application provides a graphene oxide circuit board, which includes a conductive circuit layer and a dielectric layer. The conductive circuit layer has a circuit groove, the dielectric layer is arranged in the circuit groove, and the material of the dielectric layer is graphene oxide.
[0022] In one embodiment, the conductive circuit layer includes a first conductive circuit layer, a second conductive circuit layer formed on the surface of the first conductive circuit layer, and a third conductive circuit layer formed on the surface of the second conductive circuit layer. The first conductive circuit layer has a first circuit groove, the second conductive circuit layer has a second circuit groove, and the third conductive circuit layer has a third circuit groove. The third circuit groove is arranged corresponding to the second circuit groove and the first circuit groove to form the circuit groove.
[0023] The present application arranges graphene oxide in the circuit grooves of the conductive circuit layer, reduces the graphene oxide on the surface to a graphene layer, and then arranges a conductor layer and performs circuit production to thicken the conductive circuit layer, thereby achieving thick copper and thin circuits, and obtaining a graphene oxide circuit board with a conductive circuit layer of greater thickness. The preparation method described in the present application does not require a metallization process in the circuit grooves, so it can avoid the problem of burrs after etching caused by the metallization process, thereby improving product yield and production efficiency. In addition, the present application uses graphene oxide as a dielectric layer, and the overall heat dissipation performance of the circuit board is better. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figures 1 to 6 A cross-sectional view of a prepared substrate provided in accordance with one embodiment of the present application.
[0025] Figure 7 For the general Figure 6 A cross-sectional view of an intermediate obtained after graphene oxide on the surface of the substrate is reduced to a graphene layer.
[0026] Figure 8 For Figure 7 A cross-sectional view of an intermediate body with a conductor layer disposed on its surface is shown.
[0027] Fig. 9 For the general Figure 8 The conductor layer of the structure shown is a cross-sectional view of the third conductive circuit layer.
[0028] Fig.10 To remove Fig. 9 Cross-sectional view of a graphene layer of the illustrated structure.
[0029] Fig.11 For Fig.10 A cross-sectional view of a graphene oxide circuit board obtained after graphene oxide is filled in the third circuit groove of the structure shown in one embodiment.
[0030] Main component symbols
[0031] Graphene oxide circuit board 100
[0032] Substrate 10
[0033] The first conductive circuit layer 11
[0034] First line trench 110
[0035] The second conductive circuit layer 12
[0036] The second line trench 120
[0037] The third conductive circuit layer 13
[0038] The third line trench 130
[0039] Graphene oxide 20, 40, 60
[0040] Metal layer 30
[0041] Dry film 31
[0042] Gap 310
[0043] Dielectric layer 50
[0044] Graphene layer 70
[0045] Intermediate 80
[0046] Conductor layer 90
[0047] Conductive circuit layer 101
[0048] Line groove 140
[0049] The following specific implementation manner will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the present application. The terms used herein are only for the purpose of describing specific implementation methods and are not intended to limit the present application embodiments.
[0051] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0052] Here, the embodiments of the present application are described with reference to the cross-sectional views, which are schematic diagrams of the idealized embodiments (and intermediate configurations) of the present application. Thus, it is foreseeable that the shapes of the diagrams are different due to manufacturing processes and / or tolerances. Therefore, the embodiments of the present application should not be interpreted as being limited to the specific shapes of the regions illustrated here, but should include deviations in shapes such as those produced due to manufacturing. The regions shown in the figures are themselves only schematic, and their shapes are not intended to illustrate the actual shapes of the devices, and are not intended to limit the scope of the present application.
[0053] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0054] See also Figures 1 to 11In a first aspect, the present application provides a method for preparing a graphene oxide circuit board 100, which includes steps S10 to S50. It is understandable that the numbering of the steps is intended to clearly describe the specific preparation method, and is not intended to limit the order of the steps.
[0055] See also Figures 1 to 6 , step S10, preparing a substrate 10. The substrate 10 includes a first conductive circuit layer 11 and a second conductive circuit layer 12 formed on the surface of the first conductive circuit layer 11. The first conductive circuit layer 11 has a first circuit groove 110, and the second conductive circuit layer 12 has a second circuit groove 120. The second circuit groove 120 is arranged corresponding to the first circuit groove 110, and graphene oxide 20 is arranged in the first circuit groove 110 and the second circuit groove 120. The preparation method of the substrate 10 may include steps S11 to S15.
[0056] like Figure 1 As shown, step S11, providing a metal layer 30. The material of the metal layer 30 may be, but is not limited to, copper (Cu), gold (Au), silver (Ag), etc. In this embodiment, the metal layer 30 is copper. The thickness of the metal layer 30 can be adjusted according to actual needs, and this application does not limit it.
[0057] like Figure 2 and Figure 3 As shown, in step S12 , a first conductive circuit layer 11 is formed on the surface of the metal layer 30 .
[0058] Specifically, Figure 2 As shown, dry films 31 may be laminated on two opposite surfaces of the metal layer 30. Then, the dry film 31 on the upper surface of the metal layer may be exposed and developed (i.e., the exposed dry film 31 is removed), and a plurality of gaps 310 are formed after the exposed dry film 31 is removed. Figure 3 As shown, electroplating operations (e.g., copper plating) can be performed in the plurality of gaps 310 to form the first conductive circuit layer 11. The dry film 31 on the upper surface and the lower surface that has not been exposed can be removed using a strong base NaOH. The dry film 31 removed from the upper surface forms the first circuit groove 110 of the first conductive circuit layer 11, and a portion of the surface of the metal layer 30 close to the first conductive circuit layer 11 can be exposed from the first circuit groove 110, and the bottom wall of the first circuit groove 110 is the metal layer 30.
[0059] In some embodiments, the material of the first conductive circuit layer 11 may be, but is not limited to, copper, gold, silver, etc. In this embodiment, the material of the first conductive circuit layer 11 is copper.
[0060] like Figure 4 As shown, in step S13 , graphene oxide 20 is filled in the first line trench 110 .
[0061] Specifically, liquid graphene oxide may be first coated in the first circuit groove 110 and then dried. The upper surface of the dried graphene oxide 20 (i.e., the surface of the graphene oxide 20 facing away from the metal layer 30) may be flush with the upper surface of the first conductive circuit layer 11 (i.e., the surface of the first conductive circuit layer 11 facing away from the metal layer 30).
[0062] In some embodiments, the thickness of the graphene oxide 20 may range from 0.5 nm to 500 nm, but is not limited thereto. The graphene oxide (GO) 20 has insulating properties.
[0063] like Figure 5 As shown, in step S14, the metal layer 30 can be formed into the second conductive circuit layer 12 by lamination, exposure, development, etching, stripping and other steps. The lamination, exposure, development, etching, stripping and other steps are commonly used technical means in the art and will not be repeated here. Figure 5 As shown, the second conductive circuit layer 12 has a plurality of second circuit grooves 120, and the second circuit grooves 120 are arranged correspondingly to the first circuit grooves 110 of the first conductive circuit layer 11, that is, correspondingly to the graphene oxide 20. The corresponding arrangement means that in the thickness direction (i.e. Figure 5 In the vertical direction in FIG. 1 ), the orthographic projection of the graphene oxide 20 can just completely cover the second wiring groove 120 , and the first wiring groove 110 and the second wiring groove 120 can completely overlap.
[0064] like Figure 6 As shown, in step S15, graphene oxide 40 is filled in the second circuit groove 120 to obtain the substrate 10. The graphene oxide 40 in the second circuit groove 120 contacts the graphene oxide 20 in the first circuit groove 110, and the graphene oxide 40 also has insulating properties. The lower surface of the graphene oxide 40 (i.e., the surface of the graphene oxide 40 away from the graphene oxide 20 or the first conductive circuit layer 11) can be flush with the lower surface of the second conductive circuit layer 12 (i.e., the surface of the second conductive circuit layer 12 away from the first conductive circuit layer 11). The graphene oxide 20 and the graphene oxide 40 together form a dielectric layer 50. Graphene oxide has a higher thermal conductivity, so compared with general dielectric layers (such as polyimide PI, polyethylene naphthalate PEN, polyethylene terephthalate PET, polypropylene PP), graphene oxide has better heat dissipation performance.
[0065] See also Figure 7 , step S20, reduction: partially reducing the surface of the graphene oxide 20, 40 into a graphene layer 70 to obtain an intermediate 80.
[0066] Specifically, the graphene oxide 20, 40 can be reduced by, but not limited to, hydrogen plasma method (H2 Plasma), water vapor method (solvothermal) or intense pulsed light method (e.g., xenon lamp). The water vapor method, for example, treats the surface of the graphene oxide 20, 40 with water vapor at 100° C. for at least 20 minutes. The thickness of the graphene layer 70 can be one-third to one-tenth of the thickness of the graphene oxide 20 (40) before reduction, but is not limited thereto and can be adjusted according to actual needs.
[0067] See also Figure 8 and Fig. 9 Step S30 , adding layers: disposing a conductor layer 90 on the surface of the intermediate body 80 , and forming the conductor layer 90 into a third conductive circuit layer 13 .
[0068] like Figure 8 As shown, in this embodiment, a conductor layer 90 can be provided on both the upper and lower surfaces of the intermediate body 80 by electroplating, that is, a conductor layer 90 is provided on each of the surface of the first conductive circuit layer 11 away from the second conductive circuit layer 12 and the surface of the second conductive circuit layer 12 away from the first conductive circuit layer 11. The material of the conductor layer 90 can be, but is not limited to, copper, gold, silver, etc. In this embodiment, the material of the conductor layer 90 is copper.
[0069] In this embodiment, the third conductive circuit layer 13 can be formed by using an image transfer process and an etching process, and the third conductive circuit layer 13 has two layers. Fig. 9 As shown, the third conductive circuit layer 13 has a plurality of third circuit grooves 130, and the third circuit grooves 130 are arranged corresponding to the second circuit grooves 120, the first circuit grooves 110 and the graphene layer 70, and the bottom wall of the third circuit grooves 130 is the graphene layer 70. The corresponding arrangement means that in the thickness direction, the orthographic projection of the graphene layer 70 can just completely cover the third circuit grooves 130, and the third circuit grooves 130 can completely overlap with the first circuit grooves 110 and the second circuit grooves 120.
[0070] See also Fig.10 , step S40, removing: removing the graphene layer 70.
[0071] Specifically, the graphene layer 70 may be removed by sandblasting or plasma cleaning.
[0072] See also Fig.11Step S50, filling: filling the third circuit groove 130 with graphene oxide 60 to obtain the graphene oxide circuit board 100. The surface of the graphene oxide 60 away from the first conductive circuit layer 11 can be flush with the surface of the third conductive circuit layer 13 away from the first conductive circuit layer 11, and the surface of the graphene oxide 60 away from the second conductive circuit layer 12 can be flush with the surface of the third conductive circuit layer 13 away from the second conductive circuit layer 12. The graphene oxide 60 can contact the graphene oxide 20 filled in the first conductive circuit layer 11 and the graphene oxide 40 filled in the second conductive circuit layer 12 to form a thicker dielectric layer 50.
[0073] In some embodiments, steps S20 (reduction), S30 (layer addition), S40 (removal) and S50 (filling) may be repeated multiple times to obtain a graphene oxide circuit board 100 having a conductive circuit layer with a greater thickness.
[0074] See also Fig.11 In a second aspect, the present application provides a graphene oxide circuit board 100, which includes a conductive circuit layer 101 and a dielectric layer 50. The conductive circuit layer 101 has a circuit groove 140, and the dielectric layer 50 is disposed in the circuit groove 140. The material of the dielectric layer 50 is graphene oxide.
[0075] In this embodiment, the conductive circuit layer 101 includes a first conductive circuit layer 11, a second conductive circuit layer 12, and a third conductive circuit layer 13 that are bonded together. The circuit patterns of the first conductive circuit layer 11, the second conductive circuit layer 12, and the third conductive circuit layer 13 are the same. The second conductive circuit layer 12 is formed on one surface of the first conductive circuit layer 11, the third conductive circuit layer 13 is formed on the other surface of the first conductive circuit layer 11, and the third conductive circuit layer 13 is also formed on the surface of the second conductive circuit layer 12 away from the first conductive circuit layer 11. The first conductive circuit layer 11 has a first circuit groove 110, the second conductive circuit layer 12 has a second circuit groove 120, and the third conductive circuit layer 13 has a third circuit groove 130. The third circuit groove 130 is arranged corresponding to the second circuit groove 120 and the first circuit groove 110 to form a circuit groove 140 together.
[0076] In other embodiments, a fourth conductive circuit layer, a fifth conductive circuit layer, and the like may be further disposed on the surface of the third conductive circuit layer 13 to obtain a graphene oxide circuit board 100 having a conductive circuit layer 101 with a greater thickness.
[0077] The present application arranges graphene oxide 20, 40 in the circuit groove 140 of the conductive circuit layer 101, reduces the graphene oxide 20, 40 on the surface to a graphene layer 70, and then arranges a conductor layer 90 and performs circuit production to thicken the conductive circuit layer 101, thereby achieving thick copper and thin circuits, and obtaining a graphene oxide circuit board 100 with a conductive circuit layer 101 of greater thickness. The preparation method described in the present application does not require a metallization process in the circuit groove 140, so it can avoid the problem of burrs after etching caused by the metallization process, thereby improving product yield and production efficiency. In addition, the present application uses graphene oxide as the dielectric layer 50, and the overall heat dissipation performance of the circuit board is better.
[0078] The above descriptions are some specific implementations of the present application, but they are not limited to these implementations in actual application. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should all fall within the protection scope of the present application.
Claims
1. A method for preparing a graphene oxide circuit board, characterized in that: The steps include: Prepare a substrate: the substrate comprises a first conductive circuit layer and a second conductive circuit layer formed on the surface of the first conductive circuit layer, the first conductive circuit layer has a first circuit groove, the second conductive circuit layer has a second circuit groove, the second circuit groove is arranged corresponding to the first circuit groove, and graphene oxide is arranged in the first circuit groove and the second circuit groove; Reduction: reducing the graphene oxide on the surface into a graphene layer to obtain an intermediate; Add layers; Arranging a conductor layer on the surface of the intermediate body, manufacturing the conductor layer to form a third conductive circuit layer, wherein the third conductive circuit layer has a third circuit groove, and the third circuit groove is arranged corresponding to the second circuit groove; Removing: removing the graphene layer; Filling: Filling graphene oxide in the third circuit groove to obtain the graphene oxide circuit board.
2. The preparation method according to claim 1, characterized in that The steps of reducing, adding layers, removing and filling are repeated multiple times.
3. The preparation method according to claim 1, characterized in that: The method of reducing the graphene oxide on the surface into a graphene layer includes a hydrogen plasma method, a water vapor method or an intense pulsed light method.
4. The preparation method according to claim 1, characterized in that: Methods for removing the graphene layer include sandblasting or plasma cleaning.
5. The preparation method according to claim 1, characterized in that: The step of preparing the substrate comprises: Providing a metal layer, and manufacturing a first conductive circuit layer on the surface of the metal layer, wherein the first conductive circuit layer has a first circuit groove, and a portion of the surface of the metal layer is exposed from the first circuit groove; Filling graphene oxide in the first line groove; The metal layer is fabricated into a second conductive circuit layer, wherein the second conductive circuit layer has a second circuit groove; Graphene oxide is filled in the second line groove, and the graphene oxide in the second line groove contacts the graphene oxide in the first line groove to form a dielectric layer.
6. The preparation method according to claim 5, characterized in that: The thickness of the graphene oxide in the first line groove is 0.5 nm to 500 nm, and the thickness of the graphene oxide in the second line groove is 0.5 nm to 500 nm.
7. The preparation method according to claim 5, characterized in that: The material of the metal layer includes copper, gold and silver.
8. The preparation method according to claim 1, characterized in that: The material of the conductor layer includes copper, gold and silver.
9. A graphene oxide circuit board, characterized in that: It comprises a conductive circuit layer and a dielectric layer, wherein the conductive circuit layer has a circuit groove, the dielectric layer is arranged in the circuit groove, and the material of the dielectric layer is graphene oxide.
10. The graphene oxide circuit board according to claim 9, characterized in that: The conductive circuit layer includes a first conductive circuit layer, a second conductive circuit layer formed on the surface of the first conductive circuit layer, and a third conductive circuit layer formed on the surface of the second conductive circuit layer, the first conductive circuit layer has a first circuit groove, the second conductive circuit layer has a second circuit groove, and the third conductive circuit layer has a third circuit groove, and the third circuit groove is arranged corresponding to the second circuit groove and the first circuit groove to form the circuit groove.