Electronic memory device and method of modifying integrated circuit layout design

Abstract

An electronic memory device includes a memory cell circuit. The electronic memory device also includes a non-memory cell circuit. The non-memory cell circuit includes an active region. In a top view, the active region extends along a first direction. The active region includes a first section and a second section. The first section has a first dimension measured along a second direction in a top view. The second section has a second dimension measured in a top view along a second direction different from the first direction. The second dimension is different from the first dimension. The embodiment of the invention also provides a method for modifying the layout design of the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to electronic memory devices and methods of modifying integrated circuit layout designs. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more and more complex and advanced functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and reducing related costs. However, this scale also introduces increased complexity into the semiconductor manufacturing process. Therefore, the realization of the continued advancement of semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] As integrated circuit devices shrink in size, the geometric pattern of the active area may become more influential. If the active area has a substantially rectangular shape, certain device performance data records may not be optimized. Therefore, although IC layout designs for IC device designs are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, an electronic memory device is provided, comprising: a memory unit circuit; and a non-memory unit circuit, the non-memory unit circuit comprising an active area; wherein: in a top view, the active area extends along a first direction; the active area comprises a first segment and a second segment; the first segment has a first size measured along the second direction in the top view; the second segment has a second size measured along the second direction different from the first direction in the top view; and the second size is different from the first size.

[0005] According to another aspect of an embodiment of the present application, an electronic memory device is provided, which includes: a static random access memory cell array; and a non-static random access memory circuit, the non-static random access memory circuit including an active area extending along a first direction in a top view; wherein: the active area includes a first segment and a second segment directly adjacent to the first segment; the first segment is part of a first transistor and has a first size along a second direction in a top view, and the second direction is perpendicular to the first direction; the second segment is part of a second transistor and has a second size along the second direction in the top view; the first transistor is faster than the second transistor; and the first size is larger than the second size.

[0006] According to another aspect of an embodiment of the present application, a method for modifying an integrated circuit layout design is provided, comprising: accessing the integrated circuit layout design, wherein the integrated circuit layout design includes a memory cell circuit and a non-memory cell circuit, wherein the memory cell circuit includes a plurality of first active areas, wherein the non-memory cell circuit includes a plurality of second active areas, and wherein, in a top view, the first active areas and the second active areas each extend along a first direction; and modifying the integrated circuit layout design at least partially by adjusting the size of at least a subset of the second active areas along a second direction different from the first direction in the top view. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A is a schematic perspective view of a semiconductor device;

[0009] Figure 1B is a schematic top view of a semiconductor device;

[0010] Figure 1C is a schematic perspective view of a semiconductor device;

[0011] Figure 2 It is a circuit diagram of an SRAM cell;

[0012] Figure 3 is a top view block diagram of a memory device according to various aspects of the present invention;

[0013] Figure 4-Figure 11 is a top view of a portion of a memory device including an active region according to various aspects of the present invention;

[0014] Figure 12-14 Modification of an original IC layout design to generate a modified IC layout design according to various embodiments of the present invention is shown;

[0015] Fig.15 is a block diagram of a semiconductor manufacturing system;

[0016] Fig.16 is a flow chart illustrating a method of modifying an IC layout design. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following present invention, the formation of a feature on another feature, connected to and / or coupled to another feature may include an embodiment in which the feature is formed in a direct contact manner, and may also include an embodiment in which the additional feature is formed as an embedded feature so that the feature may not be in direct contact. In addition, spatial relative terms, such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "below", "upward", "downward", "top", "bottom", etc., and their derivatives (e.g., "horizontally", "downward", "upward", etc.), are used to simplify the relationship between one feature of the present invention and another feature. Spatial relative terms are intended to cover different directions of devices including features. Further, when "approximately", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to cover numbers included in a reasonable range of the described numbers, such as within + / -10% of the described numbers or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0019] The present invention generally relates to semiconductor devices, and more specifically, to field effect transistors (FETs), such as three-dimensional fin FETs (FinFETs) or gate-all-around (GAA) devices. In this regard, a FinFET device is a fin-shaped field effect transistor device, and a GAA device is a multi-channel field effect transistor device. Both FinFET devices and GAA devices have recently become increasingly popular in the semiconductor industry because they have some advantages over traditional metal oxide semiconductor field effect transistor (MOSFET) devices (e.g., "planar" transistor devices). These advantages can include better chip area efficiency, improved carrier mobility, and a manufacturing process that is compatible with the manufacturing process of planar devices. Therefore, it may be desirable to use FinFET devices or GAA devices to design a portion of an integrated circuit (IC) chip or the entire IC chip.

[0020] However, despite the advantages of FinFET devices and / or GAA devices, there may still be certain challenges in implementing FinFET or GAA devices in IC applications. For example, traditional semiconductor manufacturing does not take into account that transistors in different applications may have specific concerns and should be optimized differently based on their specific concerns. For example, in some IC circuits, the device speed of the transistor may be a greater concern, while in some other IC circuits, the leakage of the transistor may be a greater concern. Unfortunately, these concerns are not adequately addressed. For example, although the geometry of the active area may have a meaningful impact on device speed and / or leakage, the geometry of the active area in many different types of circuits is configured in a "one-size-fits-all" manner. Therefore, device performance is not fully optimized.

[0021] In order to solve the problems discussed above, the present invention configures the shape and / or size of the active area differently for implementation in transistors based on the type of IC circuit. For example, for IC circuits that place more emphasis on device speed, the corresponding active area can be enlarged to help achieve faster device speed. For IC circuits that place more emphasis on reducing leakage, the corresponding active area can be reduced to help reduce leakage. Therefore, even when different IC circuits are formed using the same set of manufacturing processes on the same wafer, their performance can be optimized individually to address their unique concerns.

[0022] Reference now Figure 1A-Figure 1C and Figure 2-Figure 16 , discusses various aspects of the present invention in more detail. In more detail, Figure 1A-Figure 1C The basic structures of exemplary FinFET and GAA devices will be described. Figure 2 An exemplary electronic memory device will be described. Figure 3 is a top view block diagram of a memory device according to various aspects of the present invention. Figure 4-Figure 11is a top view of a portion of a memory device including an active region according to various aspects of the present invention. Figure 12-14 Modification of an original IC layout design to generate a modified IC layout design is shown according to various embodiments of the present invention. Fig.15 is a block diagram of a semiconductor manufacturing system according to various embodiments of the present invention. Fig.16 is a flow chart illustrating a method of modifying an IC layout design according to various embodiments of the present invention.

[0023] Reference now Figure 1A and Figure 1B , respectively showing a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The IC device 90 may be an intermediate device manufactured during the processing of an IC or a portion thereof, which may include: static random access memory (SRAM) and / or other logic circuits; passive components such as resistors, capacitors, and inductors; and active components such as p-type FETs (PFETs), n-type FETs (NPFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other memory cells. Unless otherwise stated, the present invention is not limited to any particular number of devices or device areas, or any particular device configuration. For example, although the IC device 90 as shown is a three-dimensional FinFET device, the concepts of the present invention may also be applied to planar FET devices or GAA devices.

[0024] refer to Figure 1A, IC device 90 includes substrate 110. Substrate 110 may include: elemental (single element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 110 may be a single layer of material with a uniform composition. Alternatively, substrate 110 may include multiple material layers with similar or different compositions suitable for IC device manufacturing. In one example, substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions such as source / drain regions may be formed in or on substrate 110. According to design requirements, the doped region may be doped with an n-type dopant such as phosphorus or arsenic, and / or a p-type dopant such as boron. The doped region may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a double-well structure, or using a raised structure. The doped region may be formed by implantation of dopant atoms, epitaxial growth of in-situ doping, and / or other suitable techniques.

[0025] A three-dimensional active area 120 is formed on the substrate 110. The active area 120 is an elongated fin-shaped structure protruding upward from the substrate 110. In this way, the active area 120 may be interchangeably referred to as the fin structure 120 hereinafter. The fin structure 120 may be manufactured using a suitable process including a photolithography and an etching process. The photolithography process may include: forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element (not shown) including a resist. Then, using the mask element, etching is recessed into the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process may combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches than those obtainable using a single direct photolithography process, for example. For example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers may be formed next to the patterned layer using a self-aligned process. The layer may then be removed, and the remaining spacers or mandrels may then be used to pattern the fin structure 120.

[0026] The IC device 90 also includes a source / drain feature 122 formed above the fin structure 120. The source / drain feature 122 may include an epitaxial layer epitaxially grown on the fin structure 120. The IC device 90 also includes an isolation structure 130 formed above the substrate 110. The isolation structure 130 electrically separates the various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) feature. In one embodiment, the isolation structure 130 is formed by etching a trench in the substrate 110 during the formation of the fin structure 120. The trench may then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 130. Alternatively, the isolation structure 130 may include a multi-layer structure, for example, having one or more thermal oxide liner layers.

[0027] The IC device 90 also includes a gate structure 140 formed over the fin structure 120 on three sides in the channel region of each fin 120 and joined to the fin structure 120. The gate structure 140 may be a dummy gate structure (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or it may be an HKMG structure including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted herein, the gate structure 140 may include additional material layers, such as a capping layer, an interface layer over the fin structure 120, other suitable layers, or combinations thereof.

[0028] refer to Figure 1B , the plurality of fin structures 120 are oriented longitudinally along the X direction, and the plurality of gate structures 140 are oriented longitudinally along the Y direction, i.e., generally perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional components, such as gate spacers disposed along sidewalls of the gate structures 140, a hard mask layer disposed over the gate structures 140, and many other components.

[0029] It should also be understood that various aspects of the present invention discussed below may be applied to multi-channel devices such as full-all-around (GAA) devices. Figure 1C A three-dimensional perspective view of an exemplary GAA device 150 is shown. For consistency and clarity reasons, Figure 1C and Figure 1A-1B1 and 2. Similar components in the substrate 110 are labeled the same. For example, active areas such as fin structures 120 protrude vertically upward from the substrate 110 along the Z direction. Isolation structures 130 provide electrical separation between fin structures 120. Gate structures 140 are located above the fin structures 120 and above the isolation structures 130. Mask 155 is located above the gate structures 140, and gate spacers 160 are located on the sidewalls of the gate structures 140. A capping layer 165 is formed over the fin structures 120 to protect the fin structures 120 from oxidation during the formation of the isolation structures 130.

[0030] A plurality of nanostructures 170 are disposed above each fin structure 120. The nanostructure 170 may include nanosheets, nanotubes, or nanowires, or some other type of nanostructure extending horizontally along the X direction. The portion of the nanostructure 170 below the gate structure 140 may be used as a channel of the GAA device 150. A dielectric internal spacer 175 may be disposed between the nanostructures 170. In addition, although not shown for simplicity, each of the nanostructures 170 may be circumferentially surrounded by a gate dielectric and a gate electrode. In the illustrated embodiment, the portion of the nanostructure 170 outside the gate structure 140 may be used as a source / drain component of the GAA device 150. However, in some embodiments, a continuous source / drain component may be epitaxially grown above the portion of the fin structure 120 outside the gate structure 140. In any case, a conductive source / drain contact 180 may be formed above the source / drain component to provide an electrical connection thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source / drain contacts 180 .

[0031] Figure 2 Exemplary types of memory devices are shown in which transistors such as planar transistors, FinFET transistors, or gate-all-around (GAA) transistors may be implemented. In this regard, Figure 2A circuit schematic diagram of an exemplary static random access memory (SRAM) device, for example, as a single-port SRAM cell (e.g., a 1-bit SRAM cell) 200 is shown. The single-port SRAM cell 200 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and transmission gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, and transistors PG1, PG2, PD1, and PD2 are n-type transistors. According to various aspects of the present invention, the PG1, PG2, PD1, and PD2 transistors are implemented with thinner spacers than the PU1 and PU2 transistors. Since the SRAM cell 200 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell. In any case, transistors such as FinFETs or GAA transistors may be used to implement the PG1, PG2, PD1, PD2, PU1, and / or PU2 transistors.

[0032] The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are connected together, and the drains of the pull-up transistor PU2 and the pull-down transistor PD2 are connected together. Transistors PU1 and PD1 are cross-connected with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are connected together and connected to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are connected together and connected to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are connected to a power supply voltage Vcc (also called Vdd), and the sources of the pull-down transistors PD1 and PD2 are connected to a voltage Vss, which in some embodiments may be electrically grounded.

[0033] The first storage node SN1 of the first data latch is connected to the bit line BL through the transmission gate transistor PG1, and the complementary first storage node SNB1 is connected to the complementary bit line BLB through the transmission gate transistor PG2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of the transmission gate transistors PG1 and PG2 are connected to the word line WL. A SRAM device such as the SRAM cell 200 can be implemented using a "planar" transistor device with a FinFET device and / or a GAA device.

[0034] Figure 32 is a block diagram of a portion of an electronic memory device 300 in which the SRAM cell 200 may be implemented. The electronic memory device 300 may include an SRAM region 305. The SRAM region 305 includes an SRAM bit cell region 310. The SRAM bit cell region 310 is a portion of the SRAM region 305 in which a plurality of SRAM devices (e.g., Figure 2 SRAM cell 200). For example, multiple SRAM devices can be implemented as an SRAM array in the SRAM bit cell area 310. In some embodiments, the SRAM devices in the SRAM bit cell area 310 are implemented using FinFET transistors and / or GAA transistors discussed above, wherein the active areas of these transistors have substantially uniform widths. For example, if the active areas each extend in an elongated manner along the X direction in a top view, then their widths measured along the Y direction (perpendicular to the X direction) are substantially uniform. In other words, the width of each active area in the SRAM bit cell area 310 may not have a gentle bend or other artificial enlargement. The substantially uniform width of the active areas in the SRAM bit cell area 310 may not be the case for other circuits of the electronic memory device 300 as discussed in more detail later according to various aspects of the present invention.

[0035] The SRAM region 305 may also include various peripheral non-memory cell circuit regions surrounding the SRAM bit cell region 310, such as an IO (input / output) region 320, a WLD (word line driver) region 330, and a CNT (control circuit) region 340. In some embodiments, the IO region 320 includes circuits for processing input / output of the SRAM device for the SRAM bit cell region 310, the WLD region 330 includes circuits for driving word lines of the SRAM device for the SRAM bit cell region 310, and the CNT region 340 includes circuits for controlling the electrical operation of the SRAM device for the SRAM bit cell region 310. The IO region 320, the WLD region 330, and the CNT region 340 may be collectively referred to as peripheral regions. In some embodiments, the transistors of the IO region 320, the WLD region 330, and the CNT region 340 are also implemented using the FinFET transistors and / or GAA transistors discussed above, but the active areas of these transistors may have substantially non-uniform widths. For example, if the active areas each extend in an elongated manner along the X direction in a top view, their width measured along the Y direction may include a gentle bend or artificial enlargement. In this way, some transistors can have larger active areas than other transistors, where transistors with larger active areas are configured to achieve faster speeds, while transistors with smaller active areas are configured to achieve lower leakage, as discussed in more detail later in accordance with various aspects of the present invention.

[0036] The electronic memory device 300 may also include a Std cell (standard cell) region 350, an e-fuse region 360, and a GPIO (general purpose input / output) region 370. In some embodiments, the Std cell region 350 may include logic circuits for implementing Boolean logic operations, the e-fuse region 360 may include microscopic electronic fuses configured to implement dynamic real-time reprogramming of the chip, and the GPIO region 370 is configured to handle input / output between the electronic memory device 300 and devices external to the electronic memory device 300. A dummy fill region 380 may be implemented in the electronic memory device 300 between these regions 350-370, and between these regions 350-370 and the SRAM region 305. In some embodiments, the transistors of the Std cell region 350, the e-fuse region 360, and the GPIO region 370 are also implemented using the FinFET transistors and / or GAA transistors discussed above. In some embodiments, the active areas of transistors in the Std cell region 350 and the GPIO region 370 may also have substantially non-uniform widths, for example, including gentle bends or artificial enlargements. As discussed above, this helps achieve faster transistor speeds (with enlarged active areas) when speed is a more important concern, and reduces transistor leakage (with reduced active areas) when leakage is a more important concern.

[0037] exist Figure 4-Figure 11 The non-uniformity of the active area in certain circuits of the electronic memory device 300 is shown in more detail in FIG. , which is a simplified schematic top view of a portion of the electronic memory device 300. For reasons of consistency and clarity, Figure 3 and Figure 4-Figure 11 Similar components appearing in the same will be labeled the same.

[0038] Reference now Figure 4 , a top view of an exemplary embodiment of the SRAM region 305 and some of its components is shown in more detail. In this exemplary embodiment, the SRAM region 305 includes two SRAM bit cell regions 310 (e.g., including SRAM cell arrays) and two IO regions 320. The WLD region 330 and the CNT region 340 are disposed between the two SRAM bit cell regions 310 and between the two IO regions 320. It should be understood that the layout and / or configuration between the two SRAM bit cell regions 310 can be substantially the same as each other, and the layout or configuration between the two IO regions 320 can also be substantially the same as each other. The IO region 320, the WLD region 330, and the CNT region 340 can be referred to as a peripheral circuit region.

[0039] Figure 4Also shown is a portion 320A of the IO region 320. The portion 320A may span horizontally along the X direction in a top view, and may include an N region, a P region, and another N region. The P region is located between the two N regions along the Y direction. A sub-portion 320A-1 of the portion 320A is also shown in more detail. For example, the sub-portion 320A-1 is located in one of the N regions, and includes an active region 410, which also extends horizontally in an elongated manner along the X direction. The active region 410 may include the above combination. Figure 1A-Figure 1C The vertically protruding fin structure of the FinFET or GAA device in question.

[0040] A unique aspect of the present invention is that the active area 410 has artificial enlargement and / or reduction in certain areas. For example, the active area 410 of subsection 320A-1 has a segment 410A and a segment 410B that are directly adjacent to each other, and each of them extends horizontally along the X direction. However, segment 410A has a dimension 420A (also referred to as a width) measured along the Y direction, while segment 410B has a dimension 420B measured along the Y direction, wherein dimension 420A is greater than dimension 420B. In other words, segment 410A is enlarged compared to segment 410B. In some embodiments, dimension 420A is in a range between about 30 nanometers (nm) and about 39 nm, while dimension 420B is in a range between about 20 nm and about 29 nm. This enlargement of segment 410A can also be represented by a gentle bend 430 between segments 410A and 410B. The gentle bend 430 may correspond to a bulge of the edge of segment 410A beyond the edge of segment 410B, while the edges of segments 410A-410B on opposite sides are substantially flush with each other. In some embodiments, the gentle bend 430 may be in a range between about 8 nm and about 12 nm.

[0041] According to various aspects of the present invention, the enlargement of the section 410A is artificially performed (e.g., by modifying the original IC layout design of the SRAM region 305) to achieve certain device performance enhancements. For example, a larger active area can achieve faster transistor speeds. Since the IO region 320 can contain various types of circuits with different transistor speeds, it is desirable to optimize device performance by enlarging the portion of the active region 410 corresponding to the transistors that require faster speeds (e.g., transistors electrically connected to the bit lines of the SRAM cells). In other words, the present invention can determine which portions of the IO region 320 include circuits that require faster transistor speeds and which portions of the IO region 320 do not include circuits that require faster transistor speeds based on the original IC layout design of the electronic memory device 300. Based on such a determination, the present invention can modify the IC layout design by artificially enlarging the section of the active region corresponding to the circuit having the faster speed (e.g., section 410A). The size of the remaining portion of the active region 410 can remain the same (e.g., having the same size 420B as before the IC layout design modification). Alternatively, section 410B may correspond to a portion of IO region 320 where leakage is not a significant concern, rather than speed. Since a smaller active area may result in lower leakage, section 410B may correspond to a circuit of IO region 320 where it is desirable to reduce leakage. In other words, section 410B may have been shrunk along the Y direction to achieve a smaller dimension 420B along the Y direction (e.g., dimension 420B is smaller than the corresponding dimension in the original IC layout design). In this manner, the same active area 410 of the IO region may be configured differently based on different needs and / or considerations of its corresponding circuit.

[0042] It should be understood that while the above discussion regarding adjusting the size of the active area 410 specifically uses the IO region as an example, it is not intended to be limited to the IO region 320 unless otherwise stated. In other embodiments, such sizing of the active area 410 may also be applied to the WLD region 330 and / or the CNT region 340 of the SRAM region 305, or even the GPIO region 370. This is because these other regions of the electronic memory device 300 may also include some circuits where transistor speed is a more important concern (thus an enlarged active area width may be more advantageous), as well as some other circuits where leakage reduction is a more important concern (thus a reduced active area width may be more advantageous).

[0043] The SRAM bit cell region 310 itself may have an active region of substantially uniform thickness compared to the regions 320-340 of the SRAM region 305. For example, a portion of the SRAM bit cell region 310 may be Figure 4 In top view, portion 310A may span horizontally along the X direction, and may include a plurality of active regions 440 ( Figure 4 2 (two examples of which are shown in FIG. 1 ), each active region also extends horizontally in an elongated manner along the X direction. The active region 440 may include the above combination Figure 1A-Figure 1C The vertically protruding fin structure of the FinFET or GAA device discussed. However, unlike the active area 410 of the IO area 320 discussed above, the active area 440 of the SRAM bit cell area 310 may each have a substantially uniform size 450 along the Y direction. In other words, although each of the active areas 440 may experience slight variations in its overall size along the Y direction, contrary to the intentional design, such variations may be caused by manufacturing defects.

[0044] Because the SRAM bit cell region 310 may not include different circuits with different considerations (e.g., faster speed vs. lower leakage, etc.), there is no significant motivation to adjust the size of the active area of ​​the SRAM bit cell region 310. Therefore, while the active areas of the electronic memory device 300 may be manufactured on the same wafer using similar manufacturing processes, some regions of the electronic memory device 300 (e.g., IO region 320, WLD region 330, or CNT region 340) may have different active area sizes (e.g., widths along the Y direction) while other regions (e.g., SRAM bit cell region 310) may have more uniformly sized active areas.

[0045] Figure 5 Another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. For consistency and clarity reasons, Figure 4-Figure 5 Similar components appearing in the same manner will be labeled the same, and the above Figure 4 The discussion of these components in the embodiments will also apply to Figure 5 Embodiment of the invention.

[0046] Similar to Figure 4 In the embodiment of Figure 5 In the embodiment of FIG. 4 , the active area 410 of the IO region 320 is also sized to have a wider section 410A and a narrower section 410B. For example, along the Y direction, the section 410A has a dimension 420A that is larger than the dimension 420B of the section 410B. This results in a gentle bend 430 between the sections 410A and 410B. Although in Figure 4 In the embodiment of FIG. 4 , the slow bend is arranged “below” 410B along the Y direction, but in Figure 5 In the embodiment of the present invention, the gentle bend is arranged "above" 410B along the Y direction.

[0047] However, regardless of the relative position of the gentle bend 430, Figure 5The embodiments still allow for flexible configuration of the active area 410 based on design and / or operational goals. For example, the segment 410A of the active area 410 is configured to be larger because faster speed is more important for the transistor corresponding to the segment 410A. In contrast, the segment 410B of the active area 410 is configured to be smaller because reduced leakage is more important for the transistor corresponding to the segment 410B. At the same time, the active area 440 in the SRAM bit cell region 310 always maintains a relatively uniform overall size 450 (e.g., width measured along the Y direction).

[0048] Figure 6 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for reasons of consistency and clarity, Figure 4-Figure 6 Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 5 The discussion of these components in the embodiments of the present invention will also apply to Figure 6 Embodiment of the invention.

[0049] Similar to Figure 4-Figure 5 In the embodiment of Figure 6 In the embodiment of FIG. 4 , the size of the active area 410 of the IO region 320 is also adjusted to have a wider section 410A and a narrower section 410B. For example, along the Y direction, the section 410A has a dimension 420A that is larger than the dimension 420B of the section 410B. Although Figure 4-Figure 5 The embodiment of each has a gentle bend 430 along one direction, however Figure 6 In some embodiments, the two gentle bends 431 and 432 are arranged in opposite directions. For example, the gentle bend 431 exists between the segment 410A and the segment 410B and is located "above" the segment 410B along the Y direction, while the gentle bend 432 exists between the segment 410A and the segment 410B and is located "below" the segment 410B along the Y direction. In some embodiments, the gentle bends 431 and 432 may be smaller than Figure 4 or Figure 5 For example, while the slow bend 430 can be within a range between about 8 nm and about 12 nm, in some embodiments, the slow bends 431-432 can each be within a range between about 3 nm and about 7 nm. It should also be understood that in some embodiments, the slow bends 431 and 432 can be substantially equal to each other, or in other embodiments, they can be different from each other.

[0050] However, regardless of the relative positions and / or number of the gentle bends 431-432, Figure 6The embodiments still allow for flexible configuration of the active area 410 based on design and / or operational goals. For example, the segment 410A of the active area 410 is configured to be larger because faster speed is more important for the transistor corresponding to the segment 410A. In contrast, the segment 410B of the active area 410 is configured to be smaller because reduced leakage is more important for the transistor corresponding to the segment 410B. At the same time, the active area 440 in the SRAM bit cell region 310 always maintains a relatively uniform overall size 450 (e.g., width measured along the Y direction).

[0051] Figure 7 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for reasons of consistency and clarity, Figure 4-Figure 7 Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 6 The discussion of these components in the embodiments will also apply to Figure 7 Embodiment of the invention.

[0052] Similar to Figure 4-Figure 6 In the embodiment of Figure 7 In the embodiment of FIG. 4 , the size of the active area 410 of the IO region 320 is also adjusted to have a wider section 410A and a narrower section 410B. For example, along the Y direction, the section 410A has a dimension 420A that is larger than the dimension 420B of the section 410B. Although Figure 4-Figure 6 The embodiment shows that the active region 410 is implemented in the N region in the portion 320A of the IO region having an NPN configuration, however Figure 7 The embodiment of the present invention implements the active area 410 in the P region of the portion 320A of the IO region having a PNP configuration. In addition, it should be understood that the size adjustment of the active area 410 in the PNP configuration can also be applied to Figure 6 and Figure 7 In addition, it should be understood that the resizing of the active area 410 can be applied to the P region alone, or to the N region alone, or to both the N region and the P region, regardless of whether a PNP configuration or an NPN configuration is implemented. At the same time, the active area 440 of the SRAM bit cell region 310 can still maintain its relatively uniform size 450 along the Y direction.

[0053] Figure 8 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for reasons of consistency and clarity, Figure 4-Figure 8Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 7 The discussion of these components in the embodiments of the present invention will also apply to Figure 8 Embodiment of the invention.

[0054] Similar to Figure 4-Figure 7 In the embodiment, the size of the active area of ​​the IO region 320 is adjusted to have wider and narrower sections according to the needs of its corresponding circuit. For example, the portion 320A-2 of the IO region 320 is located in the P region, which can be wider than the N region along the Y direction. Figure 8 In the portion 320A-2 of the IO region 320, two exemplary active regions 410 and 510 are shown. For the active region 410, the size adjustment is similar to that of the above reference. Figure 6 The discussed embodiments are sized. For example, the active area 410 is sized to have a wider section 410A with two gentle bends 431 and 432 relative to a narrower section 410B on opposite sides along the Y direction. Additionally, the active area 510 is sized in a similar manner to have a wider section 510A connected to a narrower section 510B, wherein sections 510A and 510B have dimensions 520A and 520B, respectively. In some embodiments, the values ​​of dimensions 520A and 520B are substantially equal to the values ​​of dimensions 420A and 420B, respectively. The active area 510 also includes gentle bends 531 and 532 on opposite sides of the narrower section 510B. In some embodiments, the values ​​of gentle bends 531 and 532 are substantially equal to the values ​​of gentle bends 431 and 432, respectively. As discussed above, the wider sections 410A and 510A can be used to implement transistors for which faster speed is a more important concern, while the narrower sections 410B and 510B can be used to implement transistors for which reduced leakage is a more important concern. At the same time, the active area 440 of the SRAM bit cell area 310 can still maintain its relatively uniform size 450 along the Y direction.

[0055] Fig. 9 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for reasons of consistency and clarity, Figure 4-Figure 9 Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 8 The discussion of these components in the embodiments of the present invention will also apply to Fig. 9 Embodiment of the invention.

[0056] Similar to Figure 4-Figure 8In the embodiment of the present invention, the size of the active area of ​​the IO region 320 is adjusted to have wider and narrower sections according to the needs of its corresponding circuit. For example, the portion 320A-2 of the IO region 320 (which is located in the P region in this embodiment) includes the active region 610. The active region 610 includes: a segment 610A having a size 620A measured along the Y direction; a segment 610B having a size 620B measured along the Y direction; and two branch segments 610C and 610D having respective sizes 620C and 620D measured along the Y direction. Fig. 9 As clearly shown in FIG. 6 , segment 610B is wider than segment 610A, which means that dimension 620B is larger than dimension 620A. As a result, two gentle bends 631 and 632 are formed at the interface between segments 610A and 610B, wherein gentle bend 631 is located “above” segment 610A along the Y direction, and gentle bend 632 is located “below” segment 610A along the Y direction. The gentle bends 631 and 632 may be substantially equal to each other or may differ in value from each other.

[0057] At the same time, branch segments 610C and 610D are separated from segment 610B, wherein a distance 650 separates branch segments 610C and 610D. Branch segments 610C and 610D have corresponding dimensions 620C and 620D measured along the Y direction, wherein dimensions 620C and 620D are each smaller than dimension 620A. There are also gentle bends 633 and 634, respectively, between segment 610B and branch segments 610C and 610D. In more detail, gentle bend 633 is located "above" segment 610B along the Y direction, while gentle bend 634 is located "below" segment 610B along the Y direction. Segments 633 and 634 may be substantially equal to each other or may differ in value from each other. In some embodiments, gentle bends 633 and 634 may each be smaller than each of gentle bends 631 or 632.

[0058] In some embodiments, dimension 620A is within a range between about 50 nm and about 70 nm, dimension 620B is within a range between about 68 nm and about 88 nm, dimension 620C is within a range between about 20 nm and about 29 nm, dimension 620D is within a range between about 20 nm and about 29 nm, gentle bends 631 and 632 are each within a range between about 3 nm and about 7 nm, gentle bends 633 and 634 are each within a range between about 1 nm and about 5 nm, and distance 650 can be within a range between about 20 nm and about 40 nm.

[0059] Regardless of the specific values ​​of the various dimensions listed above, it can be seen that Fig. 9The active area 610 is also configured to achieve independent size adjustment. For example, segment 610A is relatively wide along the Y direction, so it can be used to implement a transistor with a relatively fast speed. Segment 610B is even wider than segment 610A along the Y direction, so segment 610B can be used to implement a transistor with a faster speed. At the same time, branch segments 610C and 610D are relatively narrow along the Y direction, so they can be used to implement transistors with relatively low leakage. The above configuration also ensures that there is a relatively smooth transition from segment 610A to branch segments 610C and 610D, wherein segment 610B is used as an intermediate segment or transition segment therebetween. Accordingly, the slow bends 631, 632, 633, and 634 can each be smaller, which is easier to handle than the case where there is a relatively large slow bend directly between segment 610A and branch segments 610C or 610D.

[0060] Fig.10 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for reasons of consistency and clarity, Figure 4-Figure 10 Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 9 The discussion of these components in the embodiments of the present invention will also apply to Fig.10 Embodiment of the invention.

[0061] Fig.10 Examples and Fig. 9 The embodiment of FIG. 3 shares some similarities, wherein the portion 320A-2 of the IO region 320 includes an active region having multiple segments with different widths, including branch segments 610C and 610D. However, unlike Fig. 9 Compared with the two branch sections 610C and 610D of the embodiment, Fig.10 The embodiment has three branch sections 610C, 610D, and 610E. Branches 610C and 610E are separated from each other by a distance 651, while branches 610E and 610D are separated from each other by a distance 652. Gentle bends 631, 632, 633, and 634 can still be similar to those in the above reference. Fig. 9 The discussed approach exists. In the present embodiment, the configuration of the "extra" branch section 610E provides even greater flexibility with respect to the implementation of circuits using transistors with reduced leakage.

[0062] It should be understood that although Figure 8-Figure 10 The active region in the embodiment is implemented in the P region in the NPN configuration, but the same concept can also be applied to the N region in the PNP configuration. Figure 8The two active regions 410 and 510 of can be implemented in the N region in the PNP configuration. As another example, the active region 610 having a relatively wide section 610A, two branch sections 610C / 610D, and an intermediate section 610B disposed between the sections 610A and 610C / 610D can be implemented in the N region in the PNP configuration. As another example, the active region 610 having a relatively wide section 610A, three branch sections 610C / 610D / 610E, and an intermediate section 610B disposed between the sections 610A and 610C / 610D / 610E can be implemented in the N region in the PNP configuration.

[0063] Fig.11 Still another embodiment of adjusting the active area size of certain components of the electronic memory device 300 (e.g., the IO region 320, the WLD region 330, and the CNT region 340 of the SRAM region 305) is shown. Again, for consistency and clarity reasons, Figure 4-Figure 11 Similar components appearing in the same manner will be labeled the same, and the above Figure 4-Figure 10 The discussion of these components in the embodiments of the present invention will also apply to Fig.11 Embodiment of the invention.

[0064] Fig.11 The embodiments can be used with Figure 4-Figure 5 and Fig. 9 For example, the active region 710 is implemented in one of the N regions, and another active region 711 is implemented in another of the N regions. Figure 4 The active region 410 is configured in a similar manner, while the active region 711 is configured in a similar manner to Figure 5 The active region 410 is configured in a similar manner. For example, similar to Figure 4 The active region 410 in FIG. 4 includes a wider section 710A and a narrower section 710B, wherein the wider section 710A has a size 720A and the narrower section 710B has a size 720B, wherein the size 720A is greater than the size 720B, which creates a gentle bend 730 between the section 710A and the section 710B. At the same time, similar to Figure 5 In the active region 410, the active region 711 includes a wider section 711A and a narrower section 711B, the wider section 711A has a size 721A, and the narrower section 711B has a size 721B, wherein the size 721A is greater than the size 721B, which creates a gentle bend 731 between the section 711A and the section 711B.

[0065] Fig.11 The embodiments are also Fig. 9The active region 610 is implemented in a substantially similar manner to the implementation of the active region 610 in the embodiment of FIG. For example, the active region 610 is located in the P region and includes a segment 610A, two branch segments 610C-610D, and a middle segment 610B (which is wider than the segment 610A). Note that in Fig.11 In the top view of FIG. 6 , a doped well 680 (eg, an N-well) is also shown, which surrounds the active region 610. It should be understood that the active region 610 can be formed vertically above the N-well along the Z direction (perpendicular to the plane defined by the X direction and the Y direction), as shown in FIG. Figure 1A or Figure 1C At the same time, the active area 440 of the SRAM bit cell area 310 still maintains a substantially uniform size 450.

[0066] It should be understood that although Fig.11 is implemented using an NPN configuration, but the concepts discussed above can also be applied to a PNP configuration. For example, active regions 710 and 711 can be implemented in two P regions on opposite sides of an N region, while active region 610 can be implemented in an N region. In any case, Fig.11 It is shown that the configuration of the active area herein can be flexible, and different portions of the peripheral circuitry can be configured differently to suit their specific design and / or manufacturing requirements.

[0067] Figure 12-13 1 and 2. In various embodiments of the present invention, the original IC layout design is modified to generate a modified (eg, new) IC layout design. In these embodiments, the original IC layout design may include an active region 800 located in a peripheral circuit, such as in the above reference Figure 3 In the IO area 320 discussed, in the WLD area 330, in the CNT area 340, and even in the GPIO area 370. In some embodiments, the original IC layout design can be in the format of a graphic data system (GDS) file, which includes solder masks, geometric shapes, layers, component labels, and the overall layout of the circuit. In some embodiments, the GDS file can have a binary format. The original IC layout design can be generated by an IC design company, and then the IC design company can send the original IC layout design to a manufacturing plant (e.g., an IC factory). The manufacturing plant can modify the original IC layout design to generate a modified IC layout design. Again, for consistency and clarity reasons, Figure 12-13 Similar components that appear in Figure 1A-Figure 11 The same markings are used in .

[0068] Reference now Fig.12, shows Example 1, Example 2, and Example 3 of the IC layout modification process. In each of Examples 1, 2, and 3, the active area 800 in the original IC layout design extends along the X direction and has a dimension (e.g., width) 810 measured along the Y direction. According to the original IC layout design in Examples 1-3, the active area 800 may be in the shape of a rectangle, wherein the dimension 810 is uniform along the entire length of the active area 800 along the X direction. However, in Example 1, in the modified IC layout design, the active area 800 may be converted into an active area 410 (similar to Figure 4 ), wherein, along the Y direction, the active area 410 includes a wider section 410A and a narrower section 410B, the wider section 410A having a dimension 420A, and the narrower section 410B having a dimension 420B, wherein the dimension 420A is greater than the dimension 420B. In some embodiments, the dimension 420A is greater than the dimension 810, while the dimension 420B is less than the dimension 810. In other embodiments, the dimension 420A is greater than the dimension 810, while the dimension 420B is approximately equal to the dimension 810. Due to the difference in size between the sections 410A and 410B, a gentle bend 430 is also created. It should be understood that when an IC wafer is manufactured using the modified IC layout design of Example 1, the resulting active area may look substantially similar to the above-discussed active area. Figure 4 The active area 410 is formed by a plurality of electrodes.

[0069] In the modified IC layout design in Example 2, the active area 800 may also be converted into the active area 410 (similar to Figure 5 ), wherein, along the Y direction, the active area 410 includes a wider section 410A and a narrower section 410B, the wider section 410A having a dimension 420A, and the narrower section 410B having a dimension 420B, wherein the dimension 420A is greater than the dimension 420B. In some embodiments, the dimension 420A is greater than the dimension 810, while the dimension 420B is less than the dimension 810. In other embodiments, the dimension 420A is greater than the dimension 810, while the dimension 420B is approximately equal to the dimension 810. Due to the size difference between the sections 410A and 410B, a gentle bend 430 is also created. One difference between Example 1 and Example 2 is the relative position of the gentle bend 430. In Example 1, the gentle bend 430 is located "below" the section 410B along the Y direction, while the gentle bend 430 is located "above" the section 410B along the Y direction. It should be understood that when an IC wafer is manufactured using the modified IC layout design of Example 2, the resulting active area may look substantially similar to that discussed above. Figure 5 The active area 410 is formed by a plurality of electrodes.

[0070] In the modified IC layout design, the active area 800 may also be converted into the active area 410 (similar to Figure 5 ), wherein, along the Y direction, the active area 410 includes a wider section 410A and a narrower section 410B, the wider section 410A having a dimension 420A, and the narrower section 410B having a dimension 420B, wherein the dimension 420A is greater than the dimension 420B. In some embodiments, the dimension 420A is greater than the dimension 810, and the dimension 420B is less than the dimension 810. In other embodiments, the dimension 420A is greater than the dimension 810, and the dimension 420B is approximately equal to the dimension 810. Although the active areas 410 in Examples 1 and 2 each have a single gentle bend 430, the active area 410 in Example 3 has two gentle bends 431 and 432, wherein the gentle bend 431 is located "above" the section 410B along the Y direction, and the gentle bend 432 is located "below" the section 410B along the Y direction. The gentle bend 430 is also generated due to the size difference between the sections 410A and 410B.

[0071] One difference between Embodiments 1 and 2 is the relative position of the gentle bend 430. In Embodiment 1, the gentle bend 430 is located "below" segment 410B along the Y direction, while the gentle bend 430 is located "above" segment 410B along the Y direction. In other words, Embodiments 1 and 2 each have a flush edge between segments 410A and 410B on one side, and the gentle bend 430 is located on the opposite side of the flush edge, but Embodiment 3 does not have a flush edge between segments 410A and 410B, resulting in two gentle bends 431 and 432. It should be understood that when the modified IC layout design of Embodiment 3 is used to manufacture an IC wafer, the resulting active area may look substantially similar to that discussed above. Figure 6 The active area 410 is formed by a plurality of electrodes.

[0072] Reference now Fig.13, shows Embodiment 4 and Embodiment 5 of the IC layout modification process. Similarly, in Embodiments 4 and 5, the active area 800 having a uniform size 810 in the original IC layout design will be modified. Specifically, in Embodiment 4, the active area 800 is modified to an active area 610 having two branches 610C and 610D, while in Embodiment 5, the active area 800 is modified to an active area 610 having three branches 610C, 610D, and 610E. In both Embodiments 4 and 5, due to the size difference between the branch segment 610A having a size 620A and the segment 610B having a larger size 620B, gentle bends 631 and 632 are generated. At the same time, in both of Examples 4-5, due to the positional offset between segment 610B and branch segments 610C and 610D, respectively, gentle bends 633 and 634 are also generated, even though the dimensions 620C and 620D of branch segments 610C and 610D are each smaller than the dimension 620B of segment 610B. In some embodiments, dimensions 620A and 620B are each larger than dimension 810, while dimensions 620C and 620D are smaller than or approximately equal to dimension 810.

[0073] like Fig.13 As shown, while in Embodiment 4 the distance 650 separates the branch segments 610C and 610D, in Embodiment 5 another branch segment 610E (having a dimension 620E) is implemented between the branch segments 610C and 610D along the Y direction. In addition, in Embodiment 5, a doped well 850 is also shown around the active region 800, wherein in the original IC layout design, a distance 860 separates the edge of the doped well 850 from the nearest edge of the active region 800. In the modified IC layout design, the doped well 850 is modified to a doped well 680, which also surrounds the active region 610. Note that the doped well 680 in the modified IC layout design also has non-flush edges in the modified IC layout design (e.g., due to the gentle bends 633 and 634). However, the same distance 860 is maintained between the edge of segment 610A and the nearest edge of doped well 680 , and between the edge of branch segments 610C / 610D and the nearest edge of doped well 680 .

[0074] It should be understood that when an IC wafer is manufactured using the modified IC layout design of Example 4, the resulting active area may look substantially similar to that discussed above. Fig. 9 When the modified IC layout design of Example 5 is used to manufacture an IC wafer, the resulting active area may look substantially similar to that discussed above. Fig.10 The active area 610 is formed by a plurality of electrodes.

[0075] As discussed above, the IC layout modification may be applied to the peripheral circuits of the SRAM bit cell region 310, but not to the SRAM bit cell region 310 itself. Fig.14 As shown, Fig.14 A plurality of exemplary active regions 880 in the SRAM bit cell region 310 are shown before and after implementing the IC layout modification process discussed above. In some embodiments, the active regions 880 in the SRAM bit cell region 310 may appear similar to the active regions 800 of the peripheral circuits. For example, the active regions 880 may each exhibit a substantially rectangular shape having substantially uniform dimensions 890 measured along the Y direction in the original IC layout design. Since the SRAM bit cell region 310 is not modified, the modified IC layout design also has the same active regions 880 having uniform dimensions 890. As discussed above, since the circuits in the SRAM bit cell region 310 may not need to simultaneously achieve faster speeds in some circuit portions and reduced leakage in other circuit portions, separate reconfiguration of the active regions 880 in the SRAM bit cell region 310 is not required.

[0076] Fig.15 An integrated circuit manufacturing system 900 is shown in accordance with an embodiment of the present invention. Manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916, ..., N connected by a communication network 918. Network 918 may be a single network, or may be a variety of different networks, such as an intranet and the Internet, and may include both wired and wireless communication channels.

[0077] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls a process and related recipes, or an equipment engineer who monitors or adjusts the conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool, such as an EUV tool for performing a lithography process to define an active area; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and additional other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0078] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control, and / or computing capabilities to other entities, and / or receive these capabilities from other entities. Each entity can also include one or more computer systems for implementing calculations and performing automation. For example, the high-level process control module of entity 914 can include a plurality of computer hardware with coded software instructions therein. The computer hardware can include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0079] Integrated circuit manufacturing system 900 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In one embodiment, advanced process control includes adjusting process conditions, settings, and / or recipes of a processing tool applied to an associated wafer based on metrology results.

[0080] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0081] One of the capabilities provided by the IC manufacturing system 900 can enable collaboration and information access in areas such as design, engineering, and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 900 can integrate systems between devices, such as systems between metrology tools and processing tools. This integration enables the devices to coordinate their activities. For example, integrating metrology tools with processing tools can enable manufacturing information to be more effectively incorporated into manufacturing processes or APC modules, and can enable wafer data to be obtained from online or on-site measurements using metrology tools integrated in related processing tools.

[0082] Fig.16 1 is a flow chart illustrating a method 1000 for modifying an IC layout design according to an embodiment of the present invention. The method 1000 includes step 1010 for accessing an integrated circuit (IC) layout design. For example, the IC layout design may be received from an IC design company. In some embodiments, the IC layout design is in the format of a graphic data system (GDS) file, which includes solder masks, geometric shapes, layers, component labels, and the overall layout of the circuit. The GDS file may have a binary format.

[0083] The IC layout design includes a memory unit circuit and a non-memory unit circuit. The memory unit circuit includes a plurality of first active regions. The non-memory unit circuit includes a plurality of second active regions. In a top view, the first active regions and the second active regions each extend along a first direction.

[0084] The method 1000 includes a step 1020 of modifying the IC layout design at least in part by adjusting a size of at least a subset of the second active regions along a second direction different from the first direction in top view.

[0085] The method 1000 includes step 1030 of manufacturing an IC device based on the modified IC layout design.

[0086] In some embodiments, the adjustment in step 1020 is implemented without adjusting the size of any first active region along the second direction.

[0087] In some embodiments, the non-memory cell circuit includes a first subset of transistors and a second subset of transistors, the first subset of transistors having a faster speed than the second subset of transistors, and the adjusting in step 1020 is implemented at least in part by enlarging a size of a second active area of ​​the first subset of transistors along a second direction.

[0088] In some embodiments, modifying the IC layout design of step 1020 further includes dividing at least a subset of the second active regions into two or more branches.

[0089] In some embodiments, the IC layout design also includes a plurality of well regions arranged around the second active region, and the modified IC layout design of step 1020 also includes adjusting the size of at least a subset of the well regions surrounding the subset of the second active region, and the distance between the edge of the subset of the well regions and the edge of the subset of the second active region remains the same before and after the modification.

[0090] In some embodiments, the non-memory cell circuit includes an input-output circuit, a driver circuit for a memory cell circuit, a control circuit, or a logic circuit.

[0091] It should be understood that method 1000 may include additional steps that are performed before, during, or after steps 1010-1030. For example, method 1000 may include steps for performing error checking, etc. For simplicity, these additional steps are not discussed in detail herein.

[0092] The advanced lithography processes, methods, and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, for which the above disclosure is well suited. In addition, spacers used to form the fins (also called mandrels) of FinFETs can be processed in accordance with the above disclosure. It should also be understood that the various aspects of the present invention discussed above can be applied to multi-channel devices, such as full-around-all-around (GAA) devices. To the extent that the present invention relates to fin structures or FinFET devices, such discussion can also be applied to GAA devices.

[0093] In summary, the present invention configures the size of the active area of ​​the non-memory cell area of ​​the electronic memory device differently according to design and / or manufacturing requirements. For example, some sections of the active area can be resized to be larger, while other sections of the active area can be resized to be smaller. For the non-memory cell area of ​​the memory device, different determinations of the size of the active area can provide certain advantages. However, it should be understood that not all advantages are discussed herein, different embodiments can provide different advantages, and no specific advantages are required for any embodiment. One advantage is that, based on its needs and applications, for circuit applications corresponding to the different adjustment of the active area size, the device performance is optimized. For example, for some circuits, faster speed is more important. In this case, the active area in these circuits is resized to have a larger width, which allows faster speed to be achieved. At the same time, for other circuits, reducing leakage is more important. In this case, the active area in these circuits is resized to have a smaller width, which reduces leakage. In this way, the non-memory cell circuits of the electronic memory device can achieve faster speed and reduced leakage at the same time, where these performance criteria can be considered more valuable. It should be understood that although these concepts of the present invention are discussed using electronic memory devices as examples, they are not intended to be limited to electronic memory devices unless otherwise stated. The concepts of adjusting the size of active areas on IC devices can also be applied to other suitable IC applications. Other advantages may include compatibility with existing manufacturing processes (including both FinFET and GAA processes) and ease and low cost of implementation.

[0094] One aspect of the present invention relates to an electronic memory device. The electronic memory device includes a memory cell circuit. The electronic memory device also includes a non-memory cell circuit. The non-memory cell circuit includes an active area. In a top view, the active area extends along a first direction. The active area includes a first section and a second section. The first section has a first size measured along a second direction in a top view. The second section has a second size measured along a second direction different from the first direction in a top view. The second size is different from the first size.

[0095] In some embodiments, the non-memory cell circuit includes an input-output circuit, a driver circuit for the memory cell circuit, a control circuit, or a logic circuit.

[0096] In some embodiments, the first section of the active area is part of a first transistor having a first speed; the second section of the active area is part of a second transistor having a second speed faster than the first speed; and the second size is larger than the first size.

[0097] In some embodiments, the active region is a first active region; the memory cell circuit has a plurality of second active regions; and the second active regions have substantially the same size along the second direction.

[0098] In some embodiments, the first segment has a first edge and a second edge, each extending along the first direction, and the first edge and the second edge are opposite to each other along the second direction; the second segment has a third edge and a fourth edge, each extending along the first direction, and the third edge and the fourth edge are opposite to each other along the second direction; the first edge and the third edge are substantially flush with each other; and there is a gentle bend between the second edge and the fourth edge along the second direction.

[0099] In some embodiments, the first segment has a first edge and a second edge each extending along the first direction, and the first edge and the second edge are opposite to each other along the second direction; the second segment has a third edge and a fourth edge each extending along the first direction, and the third edge and the fourth edge are opposite to each other along the second direction; there is a first gentle bend along the second direction between the first edge and the third edge; and there is a second gentle bend along the second direction between the second edge and the fourth edge.

[0100] In some embodiments, the active region includes two or more branches each extending along the first direction; and the first segment or the second segment is located in one of the branches.

[0101] In some embodiments, the first segment is located in one of the branches; the second segment directly adjoins the two or more branches along the first direction; and the active region further includes a third segment directly adjoining the second segment along the first direction.

[0102] In some embodiments, there are one or more first gentle bends between the first segment and the second segment along the second direction; and there are one or more second gentle bends between the second segment and the third segment along the second direction.

[0103] In some embodiments, the active region is part of a vertical protrusion structure of a FinFET device or a full-ring device.

[0104] One aspect of the present invention relates to an electronic memory device. The electronic memory device includes an array of static random access memory (SRAM) cells. The device also includes a non-SRAM circuit, which includes an active area extending along a first direction in a top view. The active area includes a first segment and a second segment directly adjacent to the first segment. The first segment is part of a first transistor and has a first dimension along a second direction in a top view. The second direction is perpendicular to the first direction. The second segment is part of a second transistor and has a second dimension along the second direction in a top view. The first transistor is faster than the second transistor. The first dimension is greater than the second dimension.

[0105] In some embodiments, the SRAM cell array includes a further active area extending along the first direction; and a size of the further active area along the second direction is different from the first size.

[0106] In some embodiments, the active region includes a plurality of branches; and the second segment is located in one of the branches.

[0107] In some embodiments, the active region is part of an input-output circuit, a driver circuit, a control circuit, or a logic circuit.

[0108] Another aspect of the present invention relates to a method for modifying an IC layout design. An integrated circuit (IC) layout design is accessed. The IC layout design includes a memory cell circuit and a non-memory cell circuit. The memory cell circuit includes a plurality of first active areas. The non-memory cell circuit includes a plurality of second active areas. In a top view, the first active area and the second active area each extend along a first direction. The IC layout design is modified at least in part by adjusting the size of at least a subset of the second active areas along a second direction in the top view that is different from the first direction.

[0109] In some embodiments, the adjusting is performed without adjusting a size of any of the first active regions along the second direction.

[0110] In some embodiments, the non-memory cell circuit includes a first subset of transistors and a second subset of transistors; the first subset of transistors has a faster speed than the second subset of transistors; and the adjustment is implemented at least in part by enlarging the size of the second active area of ​​the first subset of transistors along the second direction.

[0111] In some embodiments, modifying the integrated circuit layout design further comprises dividing at least a subset of the second active regions into two or more branches.

[0112] In some embodiments, the integrated circuit layout design also includes a plurality of well regions arranged around the second active region; the modifying the integrated circuit layout design also includes adjusting the size of at least a subset of the well regions surrounding the subset of the second active region; and before and after the modification, the distance between the edge of the subset of the well regions and the edge of the subset of the second active region remains the same.

[0113] In some embodiments, the non-memory cell circuit includes an input-output circuit, a driver circuit for the memory cell circuit, a control circuit, or a logic circuit.

[0114] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those of ordinary skill in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic memory device comprising: memory cell circuit; as well as a non-memory cell circuit, the non-memory cell circuit comprising an active region; in: In a top view, the active area extends along a first direction; The active region includes a first section and a second section; The first segment has a first dimension measured along a second direction in the top view; The second segment has a second dimension measured in the top view along a second direction different from the first direction; and The second size is different from the first size.

2. The electronic memory device of claim 1, wherein: The first section of the active area is part of a first transistor having a first speed; The second section of the active area is part of a second transistor having a second speed faster than the first speed; and The second size is greater than the first size.

3. The electronic memory device of claim 1 , wherein: The first section has a first edge and a second edge each extending along the first direction, the first edge and the second edge being opposite to each other along the second direction; The second section has a third edge and a fourth edge each extending along the first direction, the third edge and the fourth edge being opposite to each other along the second direction; the first edge and the third edge are substantially flush with each other; and There is a gentle bend between the second edge and the fourth edge along the second direction.

4. The electronic memory device of claim 1, wherein: The first section has a first edge and a second edge each extending along the first direction, the first edge and the second edge being opposite to each other along the second direction; The second section has a third edge and a fourth edge each extending along the first direction, the third edge and the fourth edge being opposite to each other along the second direction; There is a first gentle bend between the first edge and the third edge along the second direction; and There is a second gentle bend between the second edge and the fourth edge along the second direction.

5. The electronic memory device of claim 1 , wherein: The active region includes two or more branches each extending along the first direction; and The first section or the second section is located in one of the branches.

6. The electronic memory device of claim 1, wherein: The active region is part of a vertical protruding structure of a FinFET device or a full-ring device.

7. An electronic memory device comprising: static random access memory cell array; as well as a non-static random access memory circuit, the non-static random access memory circuit comprising an active region extending along a first direction in a top view; in: The active region includes a first section and a second section directly adjacent to the first section; The first section is a part of a first transistor and has a first dimension along a second direction in a top view, the second direction being perpendicular to the first direction; The second section is a part of a second transistor and has a second size along the second direction in the top view; The first transistor is faster than the second transistor; and The first size is greater than the second size.

8. The electronic memory device of claim 7, wherein: The SRAM cell array includes a further active region extending along the first direction; and The dimension of the further active area along the second direction is different from the first dimension.

9. The electronic memory device of claim 7, wherein: The active region includes a plurality of branches; and The second section is located in one of the branches.

10. A method for modifying an integrated circuit layout design, comprising: accessing an integrated circuit layout design, wherein the integrated circuit layout design includes a memory cell circuit and a non-memory cell circuit, wherein the memory cell circuit includes a plurality of first active regions, wherein the non-memory cell circuit includes a plurality of second active regions, and wherein, in a top view, the first active regions and the second active regions each extend along a first direction; and The integrated circuit layout design is modified at least in part by adjusting a dimension of at least a subset of the second active regions along a second direction in the top view that is different from the first direction.

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