Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises the steps: forming a hole which extends in a direction perpendicular to a substrate in a stacking structure of a storage unit region, and enabling the side wall of the hole to expose a conductive film and a first insulating film in the stacking structure; the holes in the conductive thin film are located in the conductive thin film; taking the hole in the conductive thin film as a mask, performing transverse etching on the first insulating thin film of the hole until a second insulating thin film is exposed out of the hole in the first insulating thin film, and transversely etching the second insulating thin film in the hole; and a step shape is formed between the groove bottom corresponding to the second groove in the second insulating film and the side wall of the second insulating film exposed on the side wall of the hole of the conductive film.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of dynamic random access memory (DRAM) technology, the planar 1T1C structure has reached its limit. In order to obtain higher storage capacitors, lower leakage, and higher integration, DRAM memory is gradually developing towards a three-dimensional (3D) structure. However, with the development of the 3D structure, various problems will be encountered. As the number of stacked layers increases, the array becomes larger and denser, and the presence of parasitic MOS tubes between different layers has a great impact on the retention of the capacitor storage charge and the overall stability of the device. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can reduce parasitic capacitors and improve device performance.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0006] Alternatingly depositing a first insulating film and a conductive film on a substrate to form a stacked structure; the conductive film comprises polysilicon;

[0007] Forming a plurality of first grooves penetrating the stacked structure by patterned etching, wherein the area between adjacent first grooves is a storage unit area;

[0008] Filling a second insulating film in the first grooves, the second insulating film covering the conductive film exposed in each first groove and the side wall of the first insulating film; the material of the second insulating film is different from the material of the first insulating film;

[0009] A hole extending in a direction perpendicular to the substrate is formed in the stacked structure of the memory cell region, wherein the sidewall of the hole exposes the conductive film and the first insulating film in the stacked structure; the hole on the conductive film is located in the conductive film;

[0010] Using the hole on the conductive film as a mask, laterally etching the first insulating film in the hole until the second insulating film located in the hole of the first insulating film is exposed, and laterally etching the second insulating film in the hole to form a second groove between two adjacent conductive films;

[0011] After forming the second groove, the conductive film is laterally etched to form a first electrode and a second electrode on the conductive film, exposing the second insulating film;

[0012] A step is formed between the bottom of the second insulating film corresponding to the second groove and the side wall of the second insulating film exposed by the side wall of the hole of the conductive film;

[0013] forming a semiconductor layer, a gate insulating layer and a gate electrode in sequence in the hole;

[0014] The parasitic semiconductor layer between each two adjacent conductive films is removed.

[0015] In one exemplary embodiment, removing the parasitic semiconductor layer includes:

[0016] The second insulating film between two adjacent holes is removed by dry etching, the second insulating film between the adjacent first grooves and the same layer as the conductive film is retained to expose the first insulating film, and the first insulating film is wet-etched to expose part of the side surface of the parasitic semiconductor layer between the adjacent transistors;

[0017] By patterned wet etching, the second insulating film on the same layer as the first insulating film is etched away to expose a portion of the side surface of the parasitic semiconductor layer between adjacent transistors, and a portion of the second insulating film on the same layer as the conductive film is retained to form an etching stop layer;

[0018] The exposed parasitic semiconductor layer is removed by patterned wet etching, and the semiconductor layer, the gate insulating layer and the gate electrode on the same layer as the conductive film are retained.

[0019] In an exemplary embodiment, forming a plurality of first grooves penetrating the stacked structure by patterned etching includes:

[0020] A plurality of first grooves penetrating the stacked structure are formed by patterned etching, so that the first insulating film in the stacked structure forms a first patterned structure; the conductive film in the stacked structure forms a second patterned structure; the second patterned structure includes a bit line and a branch connected to the bit line, the bit line extends along a second direction, the branch extends along a first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

[0021] In an exemplary embodiment, after filling the first groove with the second insulating film and before forming the hole, the method further includes:

[0022] The second insulating film corresponding to the end of the branch away from the bit line is etched away by patterned dry etching to form a groove extending in a direction perpendicular to the substrate, wherein the groove exposes the branch of the corresponding area and the side surface of the first insulating film;

[0023] The first insulating film exposed in the groove is etched away by wet selective etching to expose the side of the branch away from one end of the bit line;

[0024] By atomic layer deposition, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed at one end of the branch away from the bit line, wherein the first capacitor electrode and the second capacitor electrode form a capacitor.

[0025] In an exemplary embodiment, the memory further includes a lead region located at least on one side of the memory cell region. The method for manufacturing the semiconductor device, after removing the parasitic semiconductor layer, further includes:

[0026] The stacked structure of the lead area forms n steps; wherein the n steps are arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a first conductive film that are stacked, the first conductive film of each step is located on a side of the first insulating film away from the substrate, and the first conductive film of each step forms a lead layer connected to the bit line of the storage cell area, wherein n is a natural number greater than 2.

[0027] In an exemplary embodiment, forming the stacked structure of the lead region into n steps comprises:

[0028] forming a fifth insulating film on the first insulating film in the lead area;

[0029] forming a photoresist on the memory cell region and the lead region;

[0030] Etching the photoresist to form a first exposed area on the photoresist, wherein the first exposed area exposes the fifth insulating film at one end of the lead area;

[0031] Using a photolithography method, etching and removing the fifth insulating film and the first insulating film in the first exposed area, so that the nth layer of the first conductive film in the first exposed area is exposed;

[0032] Etching the photoresist along the edge of the first exposed area so that the photoresist forms a second exposed area connected to the first exposed area, wherein the second exposed area exposes the fifth insulating film of the lead area;

[0033] Through patterned dry etching, the n-th layer of the first conductive film and the first insulating film of the first exposed area are etched away to expose the n-1th layer of the first conductive film of the first exposed area; the fifth insulating film and the first insulating film of the second exposed area are etched away to expose the n-th layer of the first conductive film of the second exposed area, and the n-1th layer of the first conductive film of the first exposed area and the n-1th layer of the first conductive film of the second exposed area form a step.

[0034] The present disclosure also provides a semiconductor device manufactured by any of the above-mentioned methods for manufacturing a semiconductor device, including:

[0035] A plurality of memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; the memory cells at least include transistors;

[0036] The transistor comprises a gate electrode, a semiconductor layer surrounding the side wall of the gate electrode, and a gate insulating layer arranged between the side wall of the gate electrode and the semiconductor layer; semiconductor layers of memory cells of different layers are physically disconnected and arranged along a direction vertical to the substrate;

[0037] A word line, which penetrates through the different layers and extends in a direction perpendicular to the substrate, and is connected to the gate electrodes of the memory cells of the different layers;

[0038] A bit line extending in a direction parallel to the substrate and connected to at least one memory cell in the same layer;

[0039] The memory cell further comprises an etch stop layer, which is arranged on the side of the semiconductor layer of the transistor and between the first electrode and the second electrode of the transistor. The etch stop layer and the first electrode and the second electrode surround the semiconductor layer.

[0040] In an exemplary embodiment, it also includes a lead area located on at least one side of the storage cell area, the lead area includes n steps arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a conductive film stacked together, the conductive film of each step is located on the side of the first insulating film away from the substrate, the conductive film of each step forms a lead layer, and n is a natural number greater than 2.

[0041] In an exemplary embodiment, it includes a first storage cell area and a second storage cell area arranged along a first direction, and a first lead area and a second lead area arranged along the first direction, the first lead area is located on one side of the first storage cell area in the second direction and is connected to the first storage cell area, the second lead area is located on one side of the second storage cell area in the second direction and is connected to the second storage cell area, the n steps in the first lead area are arranged in sequence along the first direction, the n steps in the second lead area are arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

[0042] In an exemplary embodiment, a first memory cell region and a second memory cell region are arranged along a first direction, the first memory cell region and the second memory cell region share a lead region, and n steps of the lead region are sequentially arranged along the first direction.

[0043] In an exemplary embodiment, a first storage cell area and a second storage cell area are arranged along a first direction, the first storage cell area and the second storage cell area share a lead area, the lead area includes a first step row and a second step row, the first step row and the second step row are arranged along the second direction, the first step row includes an even-numbered step, and the even-numbered step is arranged in sequence along the opposite direction of the first direction; the second step row includes an odd-numbered step, and the odd-numbered step is arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

[0044] An embodiment of the present disclosure also provides an electronic device, comprising any of the semiconductor devices described above.

[0045] The semiconductor device of the disclosed embodiment can eliminate parasitic MOS capacitors between adjacent storage structure layers and improve device stability by spacing semiconductor layers of storage units of different layers in a direction perpendicular to the substrate.

[0046] The manufacturing process of the semiconductor device of the embodiment of the present disclosure forms a stacked structure by using silicon oxide and polysilicon. Both silicon oxide and polysilicon are silicon-based materials. A single etching process can be used to simultaneously etch silicon oxide and polysilicon to form holes. The process is simple, and the uniformity of silicon oxide and polysilicon is good. The sidewall morphology of the hole formed by etching is smooth. In the subsequent process, there is no need to use conductive materials to replace polysilicon. Polysilicon can be etched to form two electrodes and bit lines of the transistor, which simplifies the process steps and reduces production costs.

[0047] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped second insulating film, so that after the second insulating film located in the film layer where the first insulating film is located is etched away, the second insulating film located corresponding to the holes in the conductive film is retained to form an etching barrier layer. The etching barrier layer can protect the semiconductor layer located in the film layer where the first conductive film is located when the semiconductor layer located in the film layer where the first insulating film is located is subsequently etched away to prevent it from being corroded by the etching solution.

[0048] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped hole, and when the semiconductor layer located in the film layer where the first insulating film is located is subsequently etched away, the semiconductor layer located in the film layer where the first conductive film is located is protected to prevent it from being corroded by the etching solution.

[0049] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0050] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0052] Figure 1 A cross-sectional view of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment;

[0053] Figure 2 for Figure 1 A cross-sectional view along the a-a' direction;

[0054] Figure 3 A schematic diagram of a semiconductor device after a stacked structure is formed in a manufacturing process according to an exemplary embodiment;

[0055] Figure 4a A perspective view of a semiconductor device after a first patterned structure and a second patterned structure are formed in a manufacturing process provided for an exemplary embodiment;

[0056] Figure 4b A schematic diagram in a direction parallel to a substrate after a first patterned structure and a second patterned structure are formed in a manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0057] Figure 5a A schematic diagram of a semiconductor device after forming a first trench and a second trench in a manufacturing process provided by an exemplary embodiment;

[0058] Figure 5b A schematic diagram of a semiconductor device after a third trench and a fourth trench are formed in a manufacturing process provided by an exemplary embodiment;

[0059] Figure 5c A schematic diagram of a semiconductor device after a capacitor is formed in a manufacturing process provided by an exemplary embodiment;

[0060] Figure 6a A schematic diagram of a semiconductor device in a manufacturing process provided by an exemplary embodiment after a hole is formed in a direction parallel to a substrate;

[0061] Figure 6b A schematic diagram of a semiconductor device in a manufacturing process provided by an exemplary embodiment after a hole is formed in a direction perpendicular to a substrate;

[0062] Figure 7a A schematic diagram of forming a step-like shape between a hole sidewall located in a first insulating film and a hole sidewall located in a first conductive film in a manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0063] Figure 7b A schematic diagram of etching a second insulating film in a manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0064] Figure 7c A schematic diagram of forming a second insulating film into a step shape in a manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0065] Figure 8 A schematic diagram of a semiconductor device after a semiconductor layer, a gate insulating layer and a gate electrode are formed in a manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0066] Figure 9a A schematic diagram of a semiconductor device manufacturing process in which the side walls of a first insulating film and a first conductive film are exposed according to an exemplary embodiment;

[0067] Figure 9b A schematic diagram of a semiconductor device after a first insulating film is removed during manufacturing of the semiconductor device according to an exemplary embodiment;

[0068] Fig.9c A schematic diagram of a semiconductor device after an etching stop layer is formed in a manufacturing process provided by an exemplary embodiment;

[0069] Figure 9d A schematic diagram of a semiconductor device manufacturing process provided by an exemplary embodiment after removing a semiconductor layer, a gate insulating layer and a gate electrode located in a hole of a first insulating film;

[0070] Fig.10a A schematic diagram of a semiconductor device after a fifth insulating film is formed in a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0071] Fig.10b A schematic diagram of a semiconductor device manufacturing process provided by an exemplary embodiment after removing a fifth insulating film and a first insulating film from a first exposed area;

[0072] Fig.10c A schematic diagram of a semiconductor device after forming a second exposure region and a third exposure region in a manufacturing process provided by an exemplary embodiment;

[0073] Fig.10d A schematic diagram of a semiconductor device after a step is formed in a manufacturing process provided by an exemplary embodiment;

[0074] Fig.10e A schematic diagram of a semiconductor device after n steps are formed in a manufacturing process provided by an exemplary embodiment;

[0075] Fig.11 A schematic diagram of a semiconductor device provided for an exemplary embodiment;

[0076] Fig.12 A schematic diagram of a semiconductor device provided for yet another exemplary embodiment;

[0077] Fig.13 A schematic diagram of a semiconductor device is provided for yet another exemplary embodiment. DETAILED DESCRIPTION

[0078] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0079] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0080] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0081] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0082] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0083] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0084] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0085] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0086] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0087] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0088] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0089] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0090] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0091] Figure 1 A cross-sectional view of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment; Figure 2 for Figure 1 The cross-sectional view along the a-a' direction. Figure 1 and Figure 2 As shown, in a direction parallel to the substrate, the semiconductor device provided in this embodiment may include: a memory cell region 100 and a peripheral circuit region 200 located on at least one side of the memory cell region 100. The memory cell region 100 may include a memory structure layer 102 and an insulating structure layer 101, as well as a word line 40 and a bit line 30, which are sequentially overlapped and arranged along a direction perpendicular to the substrate.

[0092] In an exemplary embodiment, in a direction parallel to the substrate, the memory structure layer 102 includes a plurality of memory cells arranged at intervals and a first insulating layer 71 separating the memory cells. The material of the first insulating layer 71 may be silicon nitride.

[0093] In an exemplary embodiment, the insulating structure layer 101 includes a second insulating layer 72 , and the second insulating layer 72 separates adjacent memory cells in a direction perpendicular to the substrate.

[0094] In an exemplary embodiment, the word line 40 extends in a direction perpendicular to the substrate and penetrates through different layers of the memory structure layer 102 , and is connected to memory cells of different layers of the memory structure layer 102 .

[0095] In an exemplary embodiment, the bit line 30 extends in a direction parallel to the substrate and is located in each memory structure layer 102 . The bit line 30 is connected to at least one memory cell in the memory structure layer 102 of the same layer.

[0096] In an exemplary embodiment, the peripheral circuit area 200 includes a shared electrode area 201 and a lead area 202 which are sequentially arranged away from the memory cell area 100, and the lead area 202 is connected to the memory cell area 100 through the shared electrode area 201. The shared electrode area 201 may include a plurality of shared electrodes spaced apart in a direction perpendicular to the substrate. The lead area 202 may include a plurality of lead layers spaced apart in a direction perpendicular to the substrate. A first end of a shared electrode is connected to a bit line 30 in a corresponding memory structure layer 102, and a second end of the shared electrode is connected to a corresponding lead layer, that is, a lead layer may be connected to a bit line 30 in a corresponding memory structure layer 102 through a corresponding shared electrode to achieve signal transmission.

[0097] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0098] In an exemplary embodiment, the storage unit may include: a transistor, the transistor including a first electrode 51, a second electrode 52, a gate electrode 26, and a semiconductor layer 23 surrounding the gate electrode 26 and insulated from the gate electrode 26 by a gate insulating layer 24, the semiconductor layer 23 extending on the side wall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; wherein the channel between the first electrode 51 and the second electrode 52 is a horizontal channel; the gate electrode 26 is connected to the word line 40.

[0099] A horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. The present application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0100] In an exemplary embodiment, the semiconductor device provided in this embodiment may further include: a hole 60 (via), the hole 60 extending in a direction perpendicular to the substrate. The hole 60 penetrates the storage structure layer 102 and the insulating structure layer 101 which are sequentially overlapped, and the hole 60 exposes the sidewalls of the first electrode 51 and the second electrode 52 in the storage structure layer 102, and the sidewalls of the insulating structure layer 101.

[0101] In an exemplary embodiment, a semiconductor layer 23 , a gate insulating layer 24 , and a gate electrode 26 are sequentially disposed on the sidewall of the hole 60 corresponding to the storage structure layer 102 .

[0102] In an exemplary embodiment, the semiconductor layer 23 of the transistor of the storage unit of at least some adjacent storage structure layers 102 is spaced apart in a direction perpendicular to the substrate, that is, the semiconductor layer 23 is arranged on the side wall of the hole 60 corresponding to the storage structure layer 102, and the side wall of the hole 60 corresponding to the insulating structure layer 101 is the side of the insulating structure layer 101, and the semiconductor layer 23 thereon is etched away, and in the direction perpendicular to the substrate, the semiconductor layer 23 of the transistor of the storage unit of the adjacent storage structure layer 102 is disconnected at the insulating structure layer 101.

[0103] In an exemplary embodiment, the semiconductor layers 23 of the transistors of the memory cells of different memory structure layers 102 are physically disconnected in a direction perpendicular to the substrate. That is, the semiconductor layers 23 of the transistors of the memory cells of all adjacent memory structure layers 102 are physically disconnected in a direction perpendicular to the substrate, thereby eliminating the parasitic MOS capacitors between all adjacent memory structure layers 102 and improving the device stability.

[0104] The semiconductor device provided in this embodiment has at least partially adjacent semiconductor layers of the transistors of the storage structure layer 102 spaced apart, which can reduce or eliminate at least partially the parasitic MOS capacitors between the layers and improve the stability of the device.

[0105] In an exemplary embodiment, the semiconductor layer 23 surrounds the sidewall of the gate electrode 26. The sidewall surround of the semiconductor layer 23 can be understood as partially or completely surrounding the gate electrode 26. In some embodiments, the surround can be completely surrounded as a whole, and the cross section of the semiconductor layer 23 after the surround is a closed ring. The interception direction of the cross section is intercepted along a direction parallel to the substrate. In some embodiments, the surround can be partially surrounded, and the cross section after the surround is not closed, but presents a ring shape. For example, a ring with an opening.

[0106] In an exemplary embodiment, the semiconductor layer 23 extends on the side wall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate. The semiconductor layer 23 may extend only in a direction perpendicular to the substrate, or the main body extends in a direction perpendicular to the substrate, and there may be a horizontal portion at the end extending in a horizontal direction and toward the gate electrode 26.

[0107] In an exemplary embodiment, the material of the semiconductor layer 23 may be a metal oxide, and the material of the metal oxide may be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, a metal oxide containing In and / or Sn, etc. When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power ampere, and 1E-10A refers to 10 to the negative 10th power ampere, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and the like, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0108] In an exemplary embodiment, the gate insulating layer 24 surrounds the sidewall of the gate electrode 26 . The gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23 . The semiconductor layer 23 is connected to the gate electrode 26 through the gate insulating layer 24 .

[0109] In an exemplary embodiment, the gate insulating layer 24 may be made of a high-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The high-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0110] In an exemplary embodiment, the gate insulating layers 24 of transistors of at least some adjacent storage structure layers 102 are spaced apart in a direction perpendicular to the substrate. That is, the gate insulating layer 24 is disposed on the sidewalls of the holes 60 corresponding to the storage structure layer 102, and the sidewalls of the holes 60 corresponding to the insulating structure layer 101 are the side surfaces of the insulating structure layer 101, on which the gate insulating layer 24 is etched away, and in a direction perpendicular to the substrate, the gate insulating layers 24 of the transistors of the storage units of the adjacent storage structure layers 102 are disconnected at the insulating structure layer 101.

[0111] In an exemplary embodiment, transistors in different memory structure layers 102 may share a word line 40 extending in a direction perpendicular to the substrate.

[0112] In an exemplary embodiment, the word line 40 is filled in the hole 60. The word line 40 is a line extending in a direction perpendicular to the substrate. The word line 40 is connected to the gate electrode 26 as a whole. The gate electrode 26 of the transistor in the storage structure layer 102 of different layers can be a part of the word line 40.

[0113] In an exemplary embodiment, the material composition of different regions of the word line 40 extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process. The same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.

[0114] In an exemplary embodiment, along a direction perpendicular to the substrate, the gate electrode 26 includes two end portions (a first end portion 261 and a second end portion 262) and a middle portion 263 located between the two end portions, and the first end portion 261 and the second end portion 262 are located on opposite sides of the middle portion 263 in the direction perpendicular to the substrate. The orthographic projections of the first end portion 261 and the second end portion 262 on the substrate are both located within the orthographic projection of the middle portion 263 on the substrate, and the side surfaces of the middle portion 263 protrude from the side surfaces of the first end portion 261 and the second end portion 262, and the gate electrode 26 presents a shape with small ends and a large middle, that is, the orthographic projection areas of the first end portion 261 and the second end portion 262 on the substrate are both smaller than the orthographic projection area of ​​the middle portion 263 on the substrate.

[0115] In an exemplary embodiment, the first electrode 51 and the second electrode 52 of the same transistor may be located in the same storage structure layer 102. The first electrode 51 and the second electrode 52 are formed by patterning a conductive film layer, and the conductive film layer is approximately parallel to the upper surface of the substrate. The first electrode 51 and the second electrode 52 may be arranged in the same layer. That is, the first electrode 51 and the second electrode 52 may be formed simultaneously by the same patterning process, but the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be manufactured separately by different patterning processes.

[0116] In an exemplary embodiment, at least part of the memory cells of the same memory structure layer 102 form an array distributed along the first direction D1 and the second direction D2, respectively. The bit line 30 extends along the second direction D2, and the memory cells arranged along the second direction D2 form a column of transistors. The bit line 30 is located on one side of the column of transistors in the first direction D1, and the bit lines 30 are all connected to the second electrodes 52 of the transistors in the adjacent columns of the memory structure layer 102 of the same layer. Figure 1 It is shown that each storage structure layer 102 includes at least three rows and two columns of storage cells, but the embodiments of the present disclosure are not limited thereto. Each storage structure layer 102 may include storage cells of other numbers of rows and columns, for example, may include only one storage cell. The first direction D1 may be parallel to the substrate, the second direction D2 may be parallel to the substrate, and the first direction D1 and the second direction D2 may intersect. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0117] In an exemplary embodiment, the bit line 30 is located between two adjacent columns of transistors in the same storage structure layer 102, and the second electrodes 52 of the transistors in the two adjacent columns are connected to the same bit line 30. The second electrodes 52 of the transistors in the two adjacent columns and the bit line 30 may be an integrated structure.

[0118] In an exemplary embodiment, at least one memory cell is disposed between an end portion of the bit line 30 and the peripheral circuit region 200 .

[0119] In an exemplary embodiment, the second electrode 52 of the transistor may be a portion of the bit line 30 connected to the second electrode 52. The second electrode 52 and the bit line 30 may both be made of polysilicon.

[0120] In an exemplary embodiment, the semiconductor device may further include a data storage element.

[0121] In an exemplary embodiment, the data storage element is, for example, a capacitor, which forms a 1T1C storage structure with a transistor. However, the disclosed embodiment is not limited thereto, and can form a 2T0C storage structure with other transistors, and so on.

[0122] In an exemplary embodiment, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode 51 .

[0123] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 51 may be an integrated structure, wherein the first capacitor electrode 41 and the first electrode 51 may both be made of polysilicon (poly-Si).

[0124] The polycrystalline silicon mentioned in the embodiments of the present application that performs a conductive role or is used as a conductor or electrode means that the main material is polycrystalline silicon. In order to ensure its conductivity, it may be doped polycrystalline silicon, or polycrystalline silicon containing metal silicide, or polycrystalline silicon with a metal layer deposited on the surface.

[0125] In an exemplary embodiment, the second capacitor electrodes 42 of the capacitors of different layers of the storage structure layer 102 may be connected into an integrated structure, that is, the capacitors of the same column of different layers share the same electrode as the second capacitor electrode 42 .

[0126] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer 43 disposed between the first capacitor electrode 41 and the second capacitor electrode 42. The capacitor dielectric layer 43 serves as a medium between the first capacitor electrode 41 and the second capacitor electrode 42.

[0127] In an exemplary embodiment, the memory cell further includes an etch stop layer 25, which is disposed in the memory structure layer 102. The etch stop layer 25 is disposed on the side of the semiconductor layer 23 of the transistor and between the first electrode and the second electrode of the transistor. The etch stop layer 25 and the first electrode and the second electrode surround the semiconductor layer. The etch stop layer 25 is used to stop the etching liquid from corroding the semiconductor material in the memory structure layer 102 during the process of etching and removing the semiconductor material in the insulating structure layer, so as to prevent the semiconductor layer 23 in the memory structure layer 102 from being corroded by the etching liquid, and ensure the quality of the semiconductor layer 23. The material of the etch stop layer 25 can be silicon nitride.

[0128] Fig.11 FIG. 1 is a schematic diagram of a semiconductor device provided by an exemplary embodiment. Fig.11 As shown, the lead area includes n steps 70 arranged in sequence along a direction perpendicular to the substrate, each step 70 includes a first insulating film 10 and a first conductive film 11 stacked, the first conductive film 11 of each step is located on the side of the first insulating film 10 away from the substrate, so that the first conductive film 11 of each step is exposed, and the first conductive film 11 of each step forms a lead layer. Wherein, n is a natural number greater than 2, such as 3, 4, 5, 6, etc.

[0129] In an exemplary embodiment, the lead region further includes a signal line 80 extending in a direction perpendicular to the substrate, and the signal line 80 is connected to each step 70 in a one-to-one correspondence.

[0130] In an exemplary embodiment, the semiconductor device includes a first storage cell region 110 and a second storage cell region 120 arranged along a first direction D1, and a first lead region 2021 and a second lead region 2022 arranged along the first direction D1, the first lead region 2021 is located on one side of the first storage cell region 110 in the second direction D2 and is connected to the first storage cell region 110, and the second lead region 2022 is located on one side of the second storage cell region 120 in the second direction D2 and is connected to the second storage cell region 120. The n steps 70 in the first lead area 2021 are arranged in sequence along the first direction D1, that is, the n-th step 70 in the first lead area 2021 is located on the side close to the second lead area 2022, and the n-1-th step 70 in the first lead area 2021 is located on the side away from the second lead area 2022; the n steps 70 in the second lead area 2022 are arranged in sequence along the opposite direction of the first direction D1, that is, the n-th step 70 in the second lead area 2022 is located on the side close to the first lead area 2021, and the n-1-th step 70 in the second lead area 2022 is located on the side away from the first lead area 2021.

[0131] Fig.12A schematic diagram of a semiconductor device is provided as another exemplary embodiment. Fig.12 As shown, the semiconductor device of this embodiment is Fig.11 The semiconductor devices shown are substantially the same, except that the first memory cell region 110 and the second memory cell region 120 share a wiring region 202. The n steps 70 in the wiring region 202 are arranged in sequence along the first direction D1.

[0132] Fig.13 A schematic diagram of a semiconductor device is provided as another exemplary embodiment. Fig.13 As shown, the semiconductor device of this embodiment is Fig.11 The semiconductor devices shown are substantially the same, except that the first memory cell region 110 and the second memory cell region 120 share a lead region 202. The lead region 202 includes a first step row 210 and a second step row 220, and the first step row 210 and the second step row 220 are arranged along the second direction D2. The first step row 210 includes even-numbered steps 70, such as the second step 70, the fourth step 70, the sixth step 70, etc., and the even-numbered steps 70 are arranged in sequence in the opposite direction of the first direction D1; the second step row 220 includes odd-numbered steps 70, such as the first step 70, the third step 70, the fifth step 70, etc., and the odd-numbered steps 70 are arranged in sequence in the opposite direction of the first direction D1.

[0133] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0134] In this embodiment, each storage structure layer 102 may include multiple storage units, but the embodiments of the present disclosure are not limited thereto, and each storage structure layer 102 may include one storage unit.

[0135] In an exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0136] S101) forming a stacking structure.

[0137] Forming the stack structure includes: alternately depositing a first insulating film 10 and a first conductive film 11 on a substrate to form a stack structure, wherein the film layer close to the substrate and the film layer away from the substrate in the stack structure are both the first insulating film 10, such as Figure 3 As shown ( Figure 3 The substrate is not shown in FIG. 1 ). Figure 3 A schematic diagram of a semiconductor device in a manufacturing process according to an exemplary embodiment after a stacked structure is formed in a direction perpendicular to a substrate is provided.

[0138] In an exemplary embodiment, the material of the first insulating film 10 may be a low-K material, such as silicon oxide, and the material of the first conductive film 11 may include polysilicon.

[0139] The embodiment of the present application forms a stacked structure by using silicon oxide and conductive polysilicon. Both silicon oxide and polysilicon are silicon-based materials. A single etching process can be used to simultaneously etch silicon oxide and polysilicon to form holes. The process is simple, and the uniformity of silicon oxide and polysilicon is good. The sidewall morphology of the hole formed by etching is smooth. In the subsequent process, there is no need to use metal conductive materials to replace polysilicon. Polysilicon can be etched to form two electrodes and bit lines of the transistor, which simplifies the process steps and reduces production costs.

[0140] In an exemplary embodiment, the first insulating film 10 and the first conductive film 11 may be deposited by using a chemical vapor deposition method or an atomic layer deposition method.

[0141] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0142] Figure 3 The stacked structure shown in the figure includes 5 layers of first insulating films 10 and 4 layers of first conductive films 11, which is only an example. In other embodiments, the stacked structure may include more or fewer layers of first insulating films 10 and first conductive films 11 that are alternately arranged.

[0143] S102) forming a first patterned structure and a second patterned structure.

[0144] The first patterned structure and the second patterned structure are formed by: etching the stacked structure of the memory cell region 100 in a patterned manner through a mask on the basis of the substrate on which the aforementioned pattern is formed, so as to form a plurality of first grooves (which can be understood as trenches, with the bottom of the first grooves facing the substrate) penetrating the stacked structure, and the area between adjacent first grooves is the memory cell region; making the first insulating films 10 of each layer in the stacked structure of the memory cell region 100 form first patterned structures that are stacked on each other and distributed cyclically in sequence, and making the first conductive films 11 of each layer in the stacked structure of the memory cell region 100 form second patterned structures that are stacked on each other and distributed cyclically in sequence; and retaining the stacked structure of the peripheral circuit region 200;

[0145] Then, the second insulating film 12 is filled in the first grooves, and the second insulating film 12 covers the sidewalls of the first conductive film 11 and the first insulating film 10 exposed in each first groove to isolate different devices, such as Figure 4a and Figure 4b As shown. Among them, Figure 4a A perspective view of a semiconductor device after a first patterned structure and a second patterned structure are formed in a manufacturing process provided for an exemplary embodiment; Figure 4b A schematic diagram in a direction parallel to a substrate after a first patterned structure and a second patterned structure are formed in a manufacturing process of a semiconductor device according to an exemplary embodiment is provided.

[0146] In an exemplary embodiment, the material of the second insulating film 12 may be silicon nitride having an etching selectivity ratio with the first insulating film.

[0147] In an exemplary embodiment, each layer of the second patterned structure includes a bit line 30, a plurality of first branches 21, and a plurality of second branches 22. The bit line 30 is in the shape of a long strip and extends along the second direction D2. The plurality of first branches 21 and the plurality of second branches 22 are both in the shape of a long strip and extend along the first direction D1. The plurality of first branches 21 and the plurality of second branches 22 are respectively located on opposite sides of the bit line 30 in the first direction D1. The plurality of first branches 21 are arranged at intervals along the second direction D2. The first ends of the plurality of first branches 21 are vertically connected to the bit line 30, and the second ends of the plurality of first branches 21 extend in the opposite direction of the first direction D1. The first ends of the plurality of second branches 22 are vertically connected to the bit line 30, and the second ends of the plurality of second branches 22 extend along the first direction D1. The first branches 21 subsequently form the first electrode 51 and the second electrode 52 of a transistor, and the second branches 22 subsequently form the first electrode 51 and the second electrode 52 of another adjacent transistor.

[0148] S103) forming a capacitor before forming a semiconductor layer.

[0149] The formation of the capacitor includes: on the basis of the substrate formed with the aforementioned pattern, etching and removing the second insulating film 12 corresponding to the end of the plurality of first branches 21 away from the bit line 30 by patterned dry etching to form a first groove 13 extending in a direction perpendicular to the substrate, the first groove 13 exposes the plurality of first branches 21 in the corresponding area and the side of the multi-layer first insulating film 10, and retains the second insulating film 12 on the side of the plurality of first branches 21 away from the bit line 30, the second insulating film 12 can support the plurality of first branches 21 to prevent the plurality of first branches 21 from collapsing; etching and removing the second insulating film 12 corresponding to the end of the plurality of second branches 22 away from the bit line 30 to form a second groove 14 extending in a direction perpendicular to the substrate, the second groove 14 exposes the plurality of second branches 22 in the corresponding area and the side of the multi-layer first insulating film 10, retains the second insulating film 12 on the side of the plurality of second branches 22 away from the bit line 30, the second insulating film 12 can support the plurality of second branches 22 to prevent the plurality of second branches 22 from collapsing, such as Figure 5a As shown;

[0150] Subsequently, the first insulating film 10 exposed by the first trench 13 is etched away by wet selective etching, and a third trench extending in a direction parallel to the substrate is formed in the region where the first insulating film 10 is etched away, the third trench and the first trench 13 surround the side surfaces of the plurality of first branches 21 away from one end of the bit line 30, and the side surfaces of the plurality of first branches 21 away from one end of the bit line 30 are exposed; the first insulating film 10 exposed by the second trench 14 is etched away, and a fourth trench extending in a direction parallel to the substrate is formed in the region where the first insulating film 10 is etched away, the fourth trench and the second trench 14 surround the side surfaces of the plurality of second branches 22 away from one end of the bit line 30, and the side surfaces of the plurality of second branches 22 away from one end of the bit line 30 are exposed, as shown in FIG. Figure 5b As shown;

[0151] Subsequently, through the atomic layer deposition method, the multiple first branches 21 away from the end of the bit line 30 and the multiple second branches 22 away from the end of the bit line 30 can be used as the first capacitor electrode and the capacitor dielectric layer; or, a first electrode film and a capacitor dielectric layer are sequentially formed on the side of the multiple first branches 21 away from the end of the bit line 30 and the side of the multiple second branches 22 away from the end of the bit line 30, so that the first electrode film forms a first capacitor electrode, and the material of the first electrode film can be TIN; subsequently, the second electrode film is deposited to form the second capacitor electrode, and the material of the second electrode film can be TIN, and the first trench 13 and the second trench 14 are filled with polysilicon; finally, the surface of the stacked structure is smoothed by chemical mechanical polishing, such as Figure 5c As shown, the first capacitor electrode and the second capacitor electrode form a capacitor 15.

[0152] In an exemplary embodiment, the material of the capacitor dielectric layer may be a high-k dielectric, such as hafnium oxide.

[0153] S104) forming holes.

[0154] The hole formation includes: on the basis of the substrate formed with the aforementioned pattern, etching the stacked structure by patterned dry etching to form a hole K1 penetrating the first insulating film 10 and the first conductive film 11 of the stacked structure respectively, the hole K1 is located in the first insulating film 10 and the first conductive film 11, and is not located on the second insulating film. The side wall of the hole K1 exposes the side wall of each first insulating film 10 and the first conductive film 11 in the stacked structure, the side wall of the first conductive film 11 is a closed ring, and the side wall on the first conductive film does not expose the second insulating film. Figure 6a and Figure 6b As shown. The plurality of first branches 21, the plurality of second branches 22 and the bit line 30 are all provided with the hole K1. The hole K1 may extend in a direction perpendicular to the substrate. The hole K1 may expose or not expose the substrate.

[0155] In an exemplary embodiment, the orthographic projection of the hole K1 on a plane parallel to the substrate may be a square or the like.

[0156] In an exemplary embodiment, the orthographic projection of the hole K1 on the substrate is located within the orthographic projection of the conductive layer 12 on the substrate. For example, the orthographic projection of the hole K1 passing through the first branch 21 on the substrate is located within the orthographic projection of the first branch 21 on the substrate, and the orthographic projection of the hole K1 passing through the second branch 22 on the substrate is located within the orthographic projection of the second branch 22 on the substrate.

[0157] S105) The sidewall of the hole is etched to form a step shape.

[0158] The step of etching the sidewall of the hole to form a step shape includes: based on the substrate formed with the aforementioned pattern, using the hole of the first conductive film 11 in the aforementioned step as a mask, etching the first insulating film 10 exposed by the hole K1 in a direction away from the hole K1 through patterned wet etching, and in a second direction D2, etching away the first insulating film 10 (silicon oxide), so that the hole K1 located in the first insulating film 10 exposes the second insulating film 12 (silicon nitride), so that on a plane parallel to the substrate, the orthographic projection of the hole K1 located in the first conductive film 11 on the substrate falls within the orthographic projection of the hole K1 located in the first conductive film 10 on the substrate, and the area of ​​the orthographic projection of the hole K1 located in the first conductive film 10 on the substrate is larger than the area of ​​the orthographic projection of the hole K1 located in the first conductive film 11 on the substrate, so that the sidewall of the hole K1 located in the first insulating film 10 and the sidewall of the hole K1 located in the first conductive film 11 form a step shape, as shown in FIG. Figure 7a In this step, the second insulating film around the first conductive film 11 is blocked by the first conductive film and is not etched.

[0159] Subsequently, the second insulating film 12 (silicon nitride) exposed by the hole K1 in the first insulating film 10 is etched away from the hole K1 by patterned wet etching, so that the second insulating film exposed by the hole K1 in the first insulating film 10 is etched back to form a second groove, and the hole K1 in the first insulating film 10 is expanded along the second direction D2. The thickness of the bottom of the second groove is less than the thickness of the second insulating film 12 in the film layer where the first conductive film 11 is located. Figure 7b shown.

[0160] Subsequently, the first conductive film 11 exposed by the hole K1 is etched in a direction away from the hole K1 by patterned wet etching, and the first conductive film 11 is removed by etching in a second direction D2, so that the second insulating film located in the hole K1 of the first conductive film 11 is exposed, so that the first branches, the second branches and the bit line of the first conductive film 11 form a first electrode and a second electrode separated from each other. Since the thickness of the bottom of the second groove is less than the thickness of the second insulating film 12 located in the film layer where the first conductive film 11 is located, the bottom of the second groove and the side wall of the second insulating film 12 exposed by the side wall of the hole K1 of the first conductive film 11 form a step shape, as shown in FIG. Figure 7c As shown, the etching amount of the first conductive film 11 is less than the etching amount of the first insulating film 10, so that the area of ​​the positive projection of the hole K1 located in the first insulating film 10 on the substrate is larger than the area of ​​the positive projection of the hole K1 located in the first conductive film 11 on the substrate, so as to ensure that the side wall of the hole K1 located in the first insulating film 10 and the side wall of the hole K1 located in the first conductive film 11 form a step shape.

[0161] S106) forming a semiconductor layer, a gate insulating layer and a gate electrode.

[0162] The forming of the semiconductor film comprises: on the basis of the substrate formed with the aforementioned pattern, by means of an atomic layer deposition method, sequentially depositing a semiconductor film, a gate insulating film and a second conductive film on the side wall of the hole K1 in the stacked structure to form a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 26; due to the step-like structure of the side wall of the hole K1, the area of ​​the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 located in the hole K1 of the first insulating film 10, which is projected on the substrate, is larger than the area of ​​the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 located in the hole K1 of the first conductive film 11, which is projected on the substrate; and then, by means of chemical polishing, the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 are ground flat, such as Figure 8 shown.

[0163] S107) removing the parasitic semiconductor layer between each two adjacent conductive films.

[0164] Removing the parasitic semiconductor layer between each adjacent two conductive films comprises: on the basis of the substrate formed with the aforementioned pattern, etching and removing the second insulating film between the two adjacent holes in the storage unit area by patterned dry etching, retaining the second insulating film 12 in the same layer as the first conductive film between the adjacent first grooves, and etching and removing the area of ​​the second insulating film 12 to expose the side walls of the first insulating film 10 and the first conductive film 11 in the stacked structure, such as Figure 9a As shown; wherein, during this etching process, the peripheral circuit area can be protected from being etched by photoresist.

[0165] Subsequently, the sidewalls of the exposed first insulating film 10 are patterned wet-etched to remove the first insulating film 10 in the stacked structure, exposing the upper and lower surfaces of the first conductive film 11, and exposing the parasitic semiconductor layer in the first direction D1, which is a semiconductor layer located between adjacent first conductive films 11. Figure 9b As shown; wherein, during this etching process, the peripheral circuit area can be protected from being etched by photoresist.

[0166] Subsequently, the stepped second insulating film 12 corresponding to the hole K1 is slowly etched by patterned wet etching. Due to the stepped structure of the second insulating film 12 corresponding to the hole K1, that is, the thickness of the second insulating film 12 located in the film layer where the first insulating film 10 is located (the thickness of the bottom of the second groove) is less than the thickness of the second insulating film 12 located in the film layer where the first conductive film 11 is located, in the second direction D2, after the parasitic semiconductor layer on the first insulating film 10 is exposed, a portion of the second insulating film in the same layer as the first conductive film 11 is still retained, and the retained second insulating film 12 forms an etching stopper 25, that is, the second insulating film 12 located in the film layer where the first insulating film 10 is located is completely etched away, and a portion of the second insulating film 12 located in the film layer where the first conductive film 11 is located is etched away, and a portion of the second insulating film 12 located in the film layer where the first conductive film 11 is located is retained, and the retained second insulating film 12 forms an etching stopper 25, as shown in FIG. Fig.9c shown.

[0167] Subsequently, the exposed parasitic semiconductor layer is removed by patterned wet etching. In some embodiments, the gate insulating layer exposed by the removed semiconductor layer can be further removed. Due to the step-like structure of the hole K1 and the blocking of the etching barrier layer 25, during the above etching process, the etching liquid will not etch the semiconductor layer 23, the gate insulating layer and the gate electrode located in the hole K1 of the first conductive film 11, so that the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 in the same layer as the first conductive film 11 are completely retained, such as Figure 9d As shown. Among them, Figure 9d Only the semiconductor layer 23 is shown. Figure 9d The gate insulating layer and the gate electrode are not shown.

[0168] The solution provided in this embodiment can effectively reduce or eliminate parasitic MOS by etching away the parasitic semiconductor layer, thereby increasing device stability without affecting the effective channel length (the length of the semiconductor layer between the first electrode 51 and the second electrode 52 ).

[0169] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped second insulating film, so that after the second insulating film located in the film layer where the first insulating film is located is etched and removed, the second insulating film located corresponding to the holes in the conductive film is retained to form an etching barrier layer. The etching barrier layer can protect the semiconductor layer located in the film layer where the first conductive film is located when the parasitic semiconductor layer is subsequently etched and removed, and prevent it from being corroded by the etching solution.

[0170] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped hole, and when the parasitic semiconductor layer is subsequently etched away, the semiconductor layer located in the film layer where the first conductive film is located is protected to prevent it from being corroded by the etching solution.

[0171] S108) Filling the insulating film.

[0172] Filling the insulating film includes: on the basis of the substrate formed with the aforementioned pattern, using the atomic layer deposition method, depositing a third insulating film on the surface of the first conductive film 11 and the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26, the third insulating film filling the area where the first insulating film is etched away; then, using the atomic layer deposition method, using a fourth insulating film to fill the area where the second insulating film is etched away, and covering the surface of the lead area and the shared electrode area; finally, using chemical mechanical polishing to grind the fourth insulating film flat. The material of the third insulating film can be silicon oxide, and the material of the fourth insulating film can be silicon nitride.

[0173] S109) forming n steps in the lead region.

[0174] The n steps forming the lead region include:

[0175] S1091) Based on the substrate formed with the aforementioned pattern, a photolithography method is used to expose and etch the lead area, and the fourth insulating film of the lead area 202 is etched away to expose the first insulating film of the lead area 202; then, a fifth insulating film 16 is used to fill the area of ​​the lead area 202 where the fourth insulating film is etched away, and the fifth insulating film 16 is polished flat by chemical mechanical polishing, as shown in FIG. Fig.10a The material of the fifth insulating film may be silicon oxide.

[0176] S1092) forming a photoresist 17 on the memory cell region 100 and the peripheral circuit region 200, the photoresist 17 forming a rectangular first exposed region 181, the first exposed region 181 exposing the fifth insulating film at one end of the lead region 202; using a photolithography method, etching away the fifth insulating film and the first insulating film of the first exposed region 181, so that the n-th layer of the first conductive film 11 of the first exposed region 181 is exposed, as shown in FIG. Fig.10b shown.

[0177] S1093) etching the photoresist 17. When the photoresist 17 is thinned, the photoresist 17 is etched along the edge of the first exposure area 181. The etching amount is controlled so that the photoresist 17 is etched along a direction parallel to the substrate to form a rectangular second exposure area 182 and a rectangular third exposure area 183. The second exposure area 182 is located on a side of the first exposure area 181 in the opposite direction of the first direction D1 and is connected to the first exposure area 181. The second exposure area 182 exposes the fifth insulating film 192 of the lead area 202. The third exposure area 183 is located on a side of the first exposure area 181 in the opposite direction of the second direction D2 and is connected to the first exposure area 181. The third exposure area 183 exposes the fourth insulating film 191 of the shared electrode area 201. Fig.10c shown.

[0178] S1094) The first conductive film 11 and the first insulating film of the nth layer of the first exposed area 181 are etched away through patterned dry etching to expose the first conductive film 11 of the n-1th layer of the first exposed area 181; the fifth insulating film 192 and the first insulating film of the second exposed area 182 are etched away to expose the first conductive film 11 of the nth layer of the second exposed area 182, and the first conductive film 11 of the n-1th layer of the first exposed area 181 and the first conductive film 11 of the nth layer of the second exposed area 182 form a step; due to the blocking of the fourth insulating film 191 of the shared electrode area 201, the shared electrode area 201 is not etched during the above etching process, such as Fig.10d As shown in FIG. 1 , n is a natural number greater than 2, such as 3, 4, 5, 6, etc.

[0179] In an exemplary embodiment, a polymer deposition and etching method may be used to protect the exposed sidewalls of the film layer.

[0180] S1095) repeat step S1094) to form n steps 70 in the lead area 202, wherein the n steps 70 are sequentially arranged along a direction perpendicular to the substrate, and each step 70 includes a first insulating film 10 and a first conductive film 11 which are stacked, and the first conductive film 11 of each step is located on a side of the first insulating film 10 away from the substrate, so that the first conductive film 11 of each step is exposed, and the first conductive film 11 of each step forms a lead layer connected to a bit line of a corresponding storage structure layer in the memory cell area, such as Fig.10e shown.

[0181] S1096) using a sixth insulating layer to fill the n steps of the lead area, and using chemical mechanical polishing to grind the sixth insulating film flat. The sixth insulating film may be made of silicon nitride.

[0182] The manufacturing method of this embodiment can be realized by using existing mature preparation equipment and can be well compatible with existing preparation processes. Therefore, the process is simple to realize, easy to implement, and has high production efficiency. It has the advantages of easy process realization, low production cost and high yield rate.

[0183] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0184] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Alternatingly depositing a first insulating film and a conductive film on a substrate to form a stacked structure; The material of the conductive film includes polysilicon; Forming a plurality of first grooves penetrating the stacked structure by patterned etching, wherein the area between adjacent first grooves is a storage unit area; Filling a second insulating film in the first grooves, the second insulating film covering the conductive film exposed in each first groove and the side wall of the first insulating film; the material of the second insulating film is different from the material of the first insulating film; Forming a hole extending in a direction perpendicular to the substrate in the stacked structure of the memory cell region, wherein the sidewall of the hole exposes the conductive film and the first insulating film in the stacked structure; The hole on the conductive film is located in the conductive film; Using the hole on the conductive film as a mask, laterally etching the first insulating film in the hole until the second insulating film located in the hole of the first insulating film is exposed, and laterally etching the second insulating film in the hole to form a second groove between two adjacent conductive films; After forming the second groove, the conductive film is laterally etched to form a first electrode and a second electrode on the conductive film, exposing the second insulating film; A step is formed between the bottom of the second insulating film corresponding to the second groove and the side wall of the second insulating film exposed by the side wall of the hole of the conductive film; forming a semiconductor layer, a gate insulating layer and a gate electrode in sequence in the hole; The parasitic semiconductor layer between each two adjacent conductive films is removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Removing the parasitic semiconductor layer between two adjacent conductive films comprises: The second insulating film between two adjacent holes is removed by dry etching, the second insulating film between the adjacent first grooves and the same layer as the conductive film is retained to expose the first insulating film, and the first insulating film is wet-etched to expose part of the side surface of the parasitic semiconductor layer between the adjacent transistors; By patterned wet etching, the second insulating film on the same layer as the first insulating film is etched away to expose a portion of the side surface of the parasitic semiconductor layer between adjacent transistors, and a portion of the second insulating film on the same layer as the conductive film is retained to form an etching stop layer; The exposed parasitic semiconductor layer is removed by patterned wet etching.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a plurality of first grooves penetrating the stacked structure by patterned etching comprises: A plurality of first grooves penetrating the stacked structure are formed by patterned etching, so that the first insulating film in the stacked structure forms a first patterned structure; the conductive film in the stacked structure forms a second patterned structure; the second patterned structure includes a bit line and a branch connected to the bit line, the bit line extends along a second direction, the branch extends along a first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After the first groove is filled with a second insulating film and before the hole is formed, the method further includes: The second insulating film corresponding to the end of the branch away from the bit line is etched away by patterned dry etching to form a groove extending in a direction perpendicular to the substrate, wherein the groove exposes the branch of the corresponding area and the side surface of the first insulating film; The first insulating film exposed in the groove is etched away by wet selective etching to expose the side of the branch away from one end of the bit line; By atomic layer deposition, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed at one end of the branch away from the bit line, wherein the first capacitor electrode and the second capacitor electrode form a capacitor.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: The memory further includes a lead region located at at least one side of the memory cell region. The method for manufacturing the semiconductor device further includes, after removing the parasitic semiconductor layer: The stacked structure of the lead area forms n steps; wherein the n steps are arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a first conductive film that are stacked, the first conductive film of each step is located on a side of the first insulating film away from the substrate, and the first conductive film of each step forms a lead layer connected to the bit line of the storage cell area, wherein n is a natural number greater than 2.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of forming n steps in the stacked structure of the lead region comprises: forming a fifth insulating film on the first insulating film in the lead area; forming a photoresist on the memory cell region and the lead region; Etching the photoresist to form a first exposed area on the photoresist, wherein the first exposed area exposes the fifth insulating film at one end of the lead area; Using a photolithography method, etching and removing the fifth insulating film and the first insulating film in the first exposed area, so that the nth layer of the first conductive film in the first exposed area is exposed; Etching the photoresist along the edge of the first exposed area so that the photoresist forms a second exposed area connected to the first exposed area, wherein the second exposed area exposes the fifth insulating film of the lead area; Through patterned dry etching, the n-th layer of the first conductive film and the first insulating film of the first exposed area are etched away to expose the n-1th layer of the first conductive film of the first exposed area; the fifth insulating film and the first insulating film of the second exposed area are etched away to expose the n-th layer of the first conductive film of the second exposed area, and the n-1th layer of the first conductive film of the first exposed area and the n-1th layer of the first conductive film of the second exposed area form a step.

7. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising: A plurality of memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; the memory cells at least include transistors; The transistor comprises a gate electrode, a semiconductor layer surrounding the side wall of the gate electrode, and a gate insulating layer arranged between the side wall of the gate electrode and the semiconductor layer; semiconductor layers of memory cells of different layers are physically disconnected and arranged along a direction vertical to the substrate; A word line, which penetrates through the different layers and extends in a direction perpendicular to the substrate, and is connected to the gate electrodes of the memory cells of the different layers; A bit line extending in a direction parallel to the substrate and connected to at least one memory cell in the same layer; The memory cell further comprises an etch stop layer, which is arranged on the side of the semiconductor layer of the transistor and between the first electrode and the second electrode of the transistor. The etch stop layer and the first electrode and the second electrode surround the semiconductor layer.

8. The semiconductor device according to claim 7, characterized in that It also includes a lead area located on at least one side of the storage cell area, the lead area includes n steps arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a conductive film stacked, the conductive film of each step is located on the side of the first insulating film away from the substrate, the conductive film of each step forms a lead layer, and n is a natural number greater than 2.

9. The semiconductor device according to claim 8, characterized in that It includes a first storage cell area and a second storage cell area arranged along a first direction, and a first lead area and a second lead area arranged along the first direction, the first lead area is located on one side of the first storage cell area in the second direction and is connected to the first storage cell area, the second lead area is located on one side of the second storage cell area in the second direction and is connected to the second storage cell area, n steps in the first lead area are arranged in sequence along the first direction, n steps in the second lead area are arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

10. The semiconductor device according to claim 8, characterized in that It comprises a first storage cell region and a second storage cell region arranged along a first direction, the first storage cell region and the second storage cell region share a lead region, and n steps of the lead region are arranged in sequence along the first direction.

11. The semiconductor device according to claim 8, characterized in that It includes a first storage cell area and a second storage cell area arranged along a first direction, the first storage cell area and the second storage cell area share a lead area, the lead area includes a first step row and a second step row, the first step row and the second step row are arranged along a second direction, the first step row includes an even-numbered step, and the even-numbered step is arranged in sequence along the opposite direction of the first direction; the second step row includes an odd-numbered step, and the odd-numbered step is arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

12. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 7 to 11.

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