Semiconductor structure and method of manufacturing the same

Abstract

This application relates to a semiconductor structure and its fabrication method. The fabrication method includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including sacrificial portions and initial semiconductor pillars alternately stacked along the thickness direction of the substrate, the sacrificial portions being adjacent to the substrate; using a first preset process to remove the sacrificial portions, forming an interface layer on the outer surface of the initial semiconductor pillars extending along a first direction, the remaining initial semiconductor pillars being used to form intermediate semiconductor pillars; using a second preset process to remove the interface layer and an etching layer formed by part of the intermediate semiconductor pillars; wherein the remaining intermediate semiconductor pillars are used to form target semiconductor pillars, the first preset process differs from the second preset process, the first direction being perpendicular to the thickness direction. The above method can improve the crystal quality of the single-crystal silicon on the surface of the target semiconductor pillar, thereby increasing the carrier mobility of the channel, and thus improving the performance of the gate-all-around device, while also increasing the device integration density.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design and manufacturing technology, specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] In integrated circuit manufacturing, with the continuous improvement of memory integration and performance, the use of gate all-around transistors (GAA transistors) can effectively reduce the size of memory cells. The channels in GAA devices are mainly located in the nanometer range within a single-crystal silicon thin film, resulting in a small size. Therefore, the overall performance of the device places extremely high demands on the quality of the single-crystal silicon thin film.

[0003] However, during the fabrication of semiconductor structures, etching of adjacent structures can lead to deformation and surface damage in single-crystal silicon thin films, affecting the performance and reliability of gate-all-around transistors. Therefore, there is an urgent need to provide a semiconductor structure and its fabrication method to improve the morphology and surface damage of single-crystal silicon thin films. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its preparation method to address issues such as the morphology and surface damage of single-crystal silicon thin films, so as to improve the morphology of single-crystal silicon thin films used to form channels and reduce or eliminate their surface damage, thereby improving the overall performance of gate-all-around transistors.

[0005] This application provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure including sacrificial portions and initial semiconductor pillars alternately stacked along the thickness direction of the substrate, the sacrificial portions being adjacent to the substrate; using a first preset process to remove the sacrificial portions, forming an interface layer on the outer surface of the initial semiconductor pillars extending along a first direction, the remaining initial semiconductor pillars being used to form intermediate semiconductor pillars; using a second preset process to remove the interface layer and an etching layer formed by part of the intermediate semiconductor pillars; wherein the remaining intermediate semiconductor pillars are used to form target semiconductor pillars, the first preset process differs from the second preset process, and the first direction is perpendicular to the thickness direction.

[0006] In the above-described semiconductor structure fabrication method, the stacked structure includes sacrificial portions and initial semiconductor pillars alternately stacked along the thickness direction of the substrate. The initial semiconductor pillars are used to form the channel portion in the all-around gate transistor, and the sacrificial portions are the portions that need to be etched and removed subsequently. In the process of removing the sacrificial portions, firstly, after removing the sacrificial portions using a first preset process, the outer surface of the initial semiconductor pillars extending along the first direction is eroded by the etching reactants in the first preset process, resulting in morphological changes or surface damage, thus forming an interface layer. Then, the interface layer is removed using a second preset process, and the size of the intermediate semiconductor pillars is further controlled, thereby exposing the ultra-high crystal quality single-crystal silicon on the surface of the target semiconductor pillars for use in forming the channel of the all-around gate transistor. This improves the carrier mobility of the channel, thereby improving the performance of the all-around gate device. Therefore, by improving the surface morphology of the target semiconductor pillar, the channel diameter can be further reduced to decrease dark current. Since the initial semiconductor pillar includes an etched layer and the target semiconductor pillar, and the interface layer is removed, the thickness of the target semiconductor pillar is less than the thickness of the initial semiconductor pillar. This reduced thickness of the target semiconductor pillar can replace part of the thickness of the initially formed sacrificial layer. Therefore, during the fabrication of the stacked structure, while the overall thickness of the single-cycle sacrificial portion and the initial semiconductor pillar remains unchanged, the thickness of the sacrificial layer can be reduced accordingly. This process method can significantly increase the achievable maximum number of cycles for the stacked structure, thereby increasing the number of 3D stacked layers in the device and improving device integration. The above semiconductor structure fabrication method can mitigate the damage and morphology impact on the surface of the initial semiconductor pillar caused by etching to remove the sacrificial layer in related technologies, thereby reducing the impact of the process on the device carrier mobility and increasing the number of 3D stacked layers in the device structure to improve device integration.

[0007] In some of these embodiments, the first preset process includes a dry etching process, and the second preset process includes a quasi-atomic layer wet etching process.

[0008] In some embodiments, the second preset process has at least one process cycle to remove the etched layer, including: in one process cycle, providing a first etchant on an interface layer to remove the exposed oxide surface on the etched layer; providing a second etchant on the etched layer to oxidize the remaining etched layer; repeating the process cycle until the etched layer is completely removed and the thickness of the target semiconductor pillar reaches the preset channel thickness.

[0009] In some embodiments, the first etching solution includes a buffered oxide etching solution, and the second etching solution includes a hydrogen peroxide solution.

[0010] In some embodiments, the initial semiconductor pillar has a first preset thickness; wherein the first preset thickness is greater than a preset channel thickness.

[0011] In some embodiments, the first preset thickness is greater than or equal to 1 nm and less than or equal to 100 nm; the thickness of the interface layer is greater than or equal to 1 nm; wherein, the first preset thickness is the sum of the preset channel thickness and the thickness of the etching layer on the two outer surfaces of the target semiconductor pillar along the thickness direction.

[0012] In some embodiments, in the dry etching process, the etching selectivity ratio of the sacrificial portion to the initial semiconductor pillar is greater than 100.

[0013] In some embodiments, the sacrificial part is made of a silicon-germanium alloy, wherein the germanium content in the silicon-germanium alloy is 5%-40%.

[0014] In some embodiments, a stacked structure is formed on a substrate, including: forming a sacrificial layer and a semiconductor layer alternately stacked sequentially along the thickness direction of the substrate, the sacrificial layer being adjacent to the substrate; forming a plurality of stacked structures spaced apart along a second direction based on the sacrificial layer and the semiconductor layer, the sacrificial layer being used to form a sacrificial portion, and the semiconductor layer being used to form an initial semiconductor pillar; wherein the second direction, the first direction, and the thickness direction are perpendicular to each other.

[0015] In some embodiments, after removing the etched layer, the method further includes: performing ion doping on the target semiconductor pillar to form a first contact region, a channel region, a second contact region, and a capacitor region arranged sequentially along a first direction; wherein the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

[0016] In some embodiments, after forming the first contact area, the method further includes: forming a bit line structure extending in a second direction on the side of the first contact area away from the channel area along a first direction, wherein the first contact areas arranged in the same column along the second direction share a bit line structure.

[0017] In some embodiments, after forming the bit line structure, the method further includes: forming a word line structure that extends along the thickness direction and contacts the outer surface of a portion of the channel region, wherein the same column of channel regions arranged along the thickness direction shares a word line structure.

[0018] In some embodiments, after forming the word line structure, the method further includes: forming a capacitor structure that circumferentially surrounds the outer surface of the capacitor region extending along a first direction, the capacitor structure extending along the first direction.

[0019] In some embodiments, forming a capacitor structure includes: forming a first electrode that circumferentially surrounds the capacitor region and extends along a first direction; forming an intermediate dielectric layer on the outer surface of the first electrode extending along the first direction; and forming a second electrode on the outer surface of the intermediate dielectric layer extending along the first direction, wherein the first electrode, the intermediate dielectric layer, and the second electrode together constitute the capacitor structure.

[0020] This application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in any one of the embodiments of this application.

[0021] In the aforementioned semiconductor structure, the crystal quality of the single-crystal silicon on the surface of the target semiconductor pillar can be improved, thereby enhancing the channel for forming the gate-all-around transistor. This improves the carrier mobility of the channel, thus enhancing the performance of the gate-all-around device. Furthermore, the channel diameter can be further reduced to decrease dark current. Additionally, during the stacked structure fabrication process, while maintaining the same overall thickness of the single-cycle sacrificial portion and the initial semiconductor pillar, the thickness of the sacrificial layer can be correspondingly reduced. This process significantly increases the achievable maximum number of cycles for the stacked structure, thereby increasing the number of 3D stacked layers and improving device integration. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0024] Figure 2 (a) is a top view schematic diagram of a method for fabricating a semiconductor structure according to an embodiment of this application, in which a sacrificial layer and a semiconductor layer are formed on a substrate;

[0025] Figure 2 (b) in the middle is Figure 2 (a) A cross-sectional view along the AA' direction in the diagram;

[0026] Figure 3 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 2 (a) shows a top view of the structure forming a stacked structure.

[0027] Figure 3 (b) in the middle is Figure 3 (a) A cross-sectional view along the AA' direction in the diagram;

[0028] Figure 4 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 3 A top view of the structure shown in (a) above, showing the formation of an interface layer and a target semiconductor pillar.

[0029] Figure 4 (b) in the middle is Figure 4 (a) A cross-sectional view along the AA' direction in the diagram;

[0030] Figure 5 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 4 (a) shows a top view of the structure with the interface layer removed;

[0031] Figure 5 (b) in the middle is Figure 5 (a) A cross-sectional view along the AA' direction in the diagram;

[0032] Figure 6 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 5 The top view of the structure shown in (a) above, which forms a first contact area, a channel area, a second contact area, and a capacitor area.

[0033] Figure 6 (b) in the middle is Figure 6 (a) A cross-sectional view along the AA' direction in the diagram;

[0034] Figure 7 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 6 (a) is a top view of the structure on which the bitline structure is formed;

[0035] Figure 7 (b) in the middle is Figure 7 (a) A cross-sectional view along the AA' direction in the diagram;

[0036] Figure 8 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 7 (a) shows a top view of the structure forming the character line structure.

[0037] Figure 8 (b) in the middle is Figure 8 (a) A cross-sectional view along the AA' direction in the diagram;

[0038] Figure 9 (a) in this application refers to a method for fabricating a semiconductor structure provided in one embodiment of the present application. Figure 8 (a) is a top view of the structure on which a capacitor structure is formed.

[0039] Figure 9 (b) in the middle is Figure 9 (a) A cross-sectional view along the AA' direction in the diagram;

[0040] Figure 10 (a) is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this application;

[0041] Figure 10 (b) in the middle is Figure 10 A three-dimensional structural diagram of part of the structure in (a) is shown.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10. Substrate; 11. Sacrificial layer; 12. Semiconductor layer; 13. Stacked structure; 131. Sacrificial part; 132. Initial semiconductor pillar; 1320. Interface layer; 1321. Intermediate semiconductor pillar; 1321'. Etching layer; 1322. Target semiconductor pillar; 1322a. First contact region; 1322b. Channel region; 1322c. Second contact region; 1322d. Capacitor region; 14. Bit line structure; 15. Word line structure; 16. Capacitor structure; 161. First electrode; 162. Intermediate dielectric layer; 163. Second electrode; 17. Stacked isolation structure; 18. Bit line isolation structure; 19. Word line isolation structure; 20. Fixing structure; 21. Filling dielectric layer. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the content of this application more thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0047] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" can be used here to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of devices in use and operation.

[0048] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “composes” and / or “comprises” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. In the use of “comprises,” “has,” and “includes” as described herein, another part may be added unless explicit qualifying terms such as “only,” “composes of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0049] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shape of the area shown herein, but rather include shape deviations due to, for example, manufacturing techniques.

[0050] Please see Figures 1-10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] In integrated circuit manufacturing, with the integration and miniaturization of memories such as DRAM (Dynamic Random Access Memory), the density of the internal circuit structure of the memory is gradually increasing. As the integration and performance of memories continue to improve, the use of Gate All Around Transistors (GAA transistors) can effectively reduce the size of memory cells, providing the possibility to further reduce memory size without compromising performance. The channels in GAA devices are mainly located in the nanometer range within a single-crystal silicon thin film, making them very small. Therefore, the overall performance of the device places extremely high demands on the quality of the single-crystal silicon thin film.

[0052] However, in multilayer horizontal cell DRAM structures based on stacked structures, single-crystal silicon in the stacked structure is used to form channels and is stacked alternately with sacrificial layers. In the etching process of sacrificial layers, the two common etching methods are wet etching and dry etching. Wet etching changes the edge morphology of the silicon film, forming rounded corners and poor verticality. Dry etching, on the other hand, has high selectivity and can obtain relatively steep edge morphologies. However, the plasma used in dry etching can damage the surface of the silicon film, thereby affecting the channel quality and the overall performance of the device.

[0053] Based on the morphology and surface damage issues of single-crystal silicon thin films in gate-all-around transistors, the following embodiments of this application provide a semiconductor structure and its fabrication method to improve the morphology of the single-crystal silicon thin film used to form the channel and reduce or eliminate its surface damage, thereby improving the overall performance of the gate-all-around transistor.

[0054] It should be noted that in the embodiments of this application, the thickness direction can be the oy direction, the first direction can be the ox direction, and the second direction can be the oz direction.

[0055] For example, please refer to Figure 1 This application provides a method for fabricating a semiconductor structure, comprising:

[0056] Step S2: Provide a substrate;

[0057] Step S4: Form a stacked structure on the substrate. The stacked structure includes sacrificial portions and initial semiconductor pillars that are alternately stacked along the thickness direction of the substrate. The sacrificial portions are adjacent to the substrate.

[0058] Step S6: Using the first preset process, the sacrificial part is removed, and an interface layer is formed on the outer surface of the initial semiconductor pillar extending along the first direction. The remaining initial semiconductor pillar is used to form an intermediate semiconductor pillar.

[0059] Step S8: Using the second preset process, remove the etched layer consisting of the interface layer and part of the intermediate semiconductor pillars; wherein, the remaining intermediate semiconductor pillars are used to form the target semiconductor pillars. The first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction.

[0060] In the above-described semiconductor structure fabrication method, the stacked structure includes sacrificial portions and initial semiconductor pillars alternately stacked along the thickness direction of the substrate. The initial semiconductor pillars are used to form the channel portion in the all-around gate transistor, and the sacrificial portions are the portions that need to be etched and removed subsequently. In the process of removing the sacrificial portions, firstly, after removing the sacrificial portions using a first preset process, the outer surface of the initial semiconductor pillars extending along the first direction is eroded by the etching reactants in the first preset process, resulting in morphological changes or surface damage, thus forming an interface layer. Then, the interface layer is removed using a second preset process, and the size of the intermediate semiconductor pillars is further controlled, thereby exposing the ultra-high crystal quality single-crystal silicon on the surface of the target semiconductor pillars for use in forming the channel of the all-around gate transistor. This improves the carrier mobility of the channel, thereby improving the performance of the all-around gate device. Therefore, by improving the surface morphology of the target semiconductor pillar, the channel diameter can be further reduced to decrease dark current. Since the initial semiconductor pillar includes an etched layer and the target semiconductor pillar, and the interface layer is removed, the thickness of the target semiconductor pillar is less than the thickness of the initial semiconductor pillar. This reduced thickness of the target semiconductor pillar can replace part of the thickness of the initially formed sacrificial layer. Therefore, during the fabrication of the stacked structure, while the overall thickness of the single-cycle sacrificial portion and the initial semiconductor pillar remains unchanged, the thickness of the sacrificial layer can be reduced accordingly. This process method can significantly increase the achievable maximum number of cycles for the stacked structure, thereby increasing the number of 3D stacked layers in the device and improving device integration. The above semiconductor structure fabrication method can mitigate the damage and morphology impact on the surface of the initial semiconductor pillar caused by etching to remove the sacrificial layer in related technologies, thereby reducing the impact of the process on the device carrier mobility and increasing the number of 3D stacked layers in the device structure to improve device integration.

[0061] As an example, the first preset process includes a dry etching process, and the second preset process includes a quasi-atomic layer wet etching process, i.e., qALE (quasi-atomic layer etching). The dry etching process has a high selectivity, enabling the etched target semiconductor pillars to have very high conformability, thus facilitating the formation of high-quality channel regions. The quasi-atomic layer wet etching process utilizes its self-limiting and self-saturating adsorption reactions to achieve surface control. The fabricated structures exhibit excellent three-dimensional conformity and large-area uniformity, while also producing smooth surface morphologies to reduce stress generated in subsequent deposition processes. Furthermore, it allows for precise control of the etching thickness, ensuring the target semiconductor pillars are controlled within the preset channel thickness while simultaneously improving surface uniformity.

[0062] As an example, the initial semiconductor pillar has a first preset thickness, and the target semiconductor pillar has a preset channel thickness; wherein the first preset thickness is greater than the preset channel thickness. Quasi-atomic layer wet etching can precisely control the etching thickness, ensuring the target semiconductor pillar has the preset channel thickness while simultaneously improving its surface uniformity. Since the thickness of the target semiconductor pillar is less than the thickness of the initial semiconductor pillar, this reduced thickness can replace part of the initially formed sacrificial layer thickness. Therefore, the thickness of the sacrificial layer can be correspondingly reduced, further increasing the number of stacked layers.

[0063] As an example, the first preset thickness is greater than or equal to 1 nm and less than or equal to 100 nm; the thickness of the interface layer is greater than or equal to 1 nm; wherein, the first preset thickness is the sum of the preset channel thickness and the thickness of the etching layer on the two outer surfaces of the target semiconductor pillar along the thickness direction. Specifically, the first preset thickness can be 1 nm, 10 nm, 30 nm, 50 nm, or 100 nm, etc.; the thickness of the interface layer can be equal to 1 nm, 2 nm, 5 nm, or 10 nm, etc.

[0064] For example, please refer to Figure 1 Step S2 in Figure 2In steps S2, as shown in (a) and (b), the substrate 10 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate 10 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the type of substrate 10 based on the type of transistors formed on it; therefore, the type of substrate 10 should not limit the scope of protection of this application.

[0065] For example, please refer to Figure 1 Step S4, in which a stacked structure is formed on the substrate, includes:

[0066] Step S41: A sacrificial layer and a semiconductor layer are formed on the substrate, which are alternately stacked along the thickness direction of the substrate, with the sacrificial layer adjacent to the substrate;

[0067] Step S42: Based on the sacrificial layer and the semiconductor layer, a plurality of stacked structures are arranged at intervals along the second direction. The sacrificial layer is used to form the sacrificial part, and the semiconductor layer is used to form the initial semiconductor pillar. The second direction, the first direction, and the thickness direction are perpendicular to each other.

[0068] As an example, in step S41, please refer to Figure 2 In (a) and (b), a sacrificial layer 11 and a semiconductor layer 12 are formed alternately along the thickness direction (e.g., the oy direction) of the substrate 10, with the sacrificial layer 11 adjacent to the substrate 10; wherein, the specific formation process includes, but is not limited to, reduced pressure chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE), etc., and the precursor for preparing the sacrificial layer 11 includes, but is not limited to, materials such as silane (SiH4) and germanium hydride (GeH4).

[0069] In the above embodiments, the substrate 10 is made of single-crystal silicon, and the sacrificial layer 11 is made of a silicon-germanium alloy. The germanium content in the silicon-germanium alloy is 5%-40%, and the thickness of the sacrificial layer 11 is greater than or equal to 1 nm and less than or equal to 100 nm. Specifically, the germanium content in the silicon-germanium alloy can be 5%, 10%, 20%, 30%, or 40%, etc.; the thickness of the sacrificial layer 11 can be 1 nm, 10 nm, 30 nm, 50 nm, or 100 nm, etc.

[0070] As an example, in step S42, please refer to Figure 3 In (a) and (b), multiple stacked structures 13 are formed at intervals along a second direction (e.g., the oz direction) based on the sacrificial layer 11 and the semiconductor layer 12. The sacrificial layer 11 is used to form the sacrificial portion 131, and the semiconductor layer 12 is used to form the initial semiconductor pillar 132, so as to form the active region in the semiconductor structure. Specifically, the active region can be defined using a photolithography process.

[0071] As an example, please continue reading Figure 3 In (a) and (b) above, the steps of defining the active region using photolithography may include: providing a mask substrate (not shown); coating a layer of photoresist (not shown) on the mask substrate; exposing and developing the photoresist to form a photoresist pattern; transferring the photoresist layer onto the sacrificial layer 11 and the semiconductor layer 12 to define the active region; etching the sacrificial layer 11 and the semiconductor layer 12 in the thickness direction (e.g., the oy direction) to form a plurality of stacked structures 13 spaced apart along a first direction (e.g., the ox direction), wherein the sacrificial layer 11 is used to form the sacrificial portion 131 and the semiconductor layer 12 is used to form the initial semiconductor pillar 132 to form the active region in the semiconductor structure.

[0072] For example, please refer to Figure 1 Step S6 in Figure 3 (a), (b), Figure 4 In steps (a) and (b), in step S6, under the first preset process, the sacrificial portion 131 is removed, and an interface layer 1320 is formed on the outer surface of the initial semiconductor pillar 132 extending along the first direction (e.g., the ox direction). The remaining initial semiconductor pillar 132 is used to form the intermediate semiconductor pillar 1321. During the removal of the sacrificial portion 131, the surface crystal structure of the initial semiconductor pillar 132 is damaged due to the participation of plasma during the etching process. Therefore, an interface layer 1320 is formed on its outer surface extending along the first direction (e.g., the ox direction), and in some embodiments, the thickness of the interface layer 1320 is greater than or equal to 1 nm.

[0073] As an example, please continue reading Figure 3 (a), (b), Figure 4In (a) and (b), before removing the sacrificial part 131, a fixing structure 20 is formed on the outer surface of the stacked structure 13 to fix the initial semiconductor pillar 132 in its original position and provide support for the semiconductor structure in subsequent process steps.

[0074] The steps for removing the sacrificial portion 131 under the first preset process may specifically include: first, defining the etching area using photolithography, and then performing dry lateral selective etching to achieve a high selectivity ratio between the sacrificial portion 131 and the initial semiconductor pillar 132, thereby achieving conformal integrity of the channel formed in the initial semiconductor pillar 132.

[0075] As an example, in the above-described dry etching process, the etching selectivity ratio of the sacrificial portion 131 to the initial semiconductor pillar 132 is greater than 100. Specifically, the etching selectivity ratio of the sacrificial portion 131 to the initial semiconductor pillar 132 can be 140, 145, 150, 155, or 160, etc.

[0076] For example, please refer to Figure 1 In step S8, the second preset process has at least one process cycle. Step S8, removing the etched layer, includes:

[0077] Step S81: In one process cycle, a first etching solution is provided on the etched layer to remove the exposed oxide surface on the etched layer;

[0078] Step S82: Apply a second etching solution to the etched layer to oxidize the remaining etched layer;

[0079] Step S83: Repeat the process cycle until the etched layer is completely removed and the thickness of the target semiconductor pillar reaches the preset channel thickness.

[0080] As an example, in step S81, please refer to Figure 4 (a), (b) and Figure 5 In (a) and (b), the etched layer 1321' is the part to be removed in the second preset process. The etched layer 1321' consists of the entirety of the interface layer 1320 and a portion of the intermediate semiconductor pillar 1321. After removing the etched layer 1321', the remaining intermediate semiconductor pillar is used to form the target semiconductor pillar. The exposed surface of the etched layer 1321' has a natural oxide layer. Therefore, a first etching solution is used to remove the exposed oxide surface on the etched layer 1321'. The first etching solution includes a buffered oxide etching solution. Specifically, the buffered oxide etching solution can be a diluted buffered oxide etching solution, i.e., dBOE (dilute buffered oxide etch), which can be made by mixing hydrofluoric acid and water or ammonium fluoride and water.

[0081] As an example, in step S82, please refer to... Figure 4 (a), (b) and Figure 5 In steps (a) and (b), a second etching solution is provided on the etched layer 1321'. After the first etching solution etches away a portion of the etched layer 1321', the remaining etched layer 1321' is oxidized. The second etching solution includes a hydrogen peroxide solution. In one process cycle, the etched layer 1321' may not be completely removed; only a portion of the etched layer 1321' is removed at a time to protect the surface of the target semiconductor pillar 1322 from damage, thereby obtaining a high-quality crystal surface.

[0082] As an example, after step S81 and / or step S82, the surface of the structure after the reaction can be cleaned with a cleaning solution to remove impurities from the surface of the corrosion layer 1321'. The cleaning solution includes deionized water.

[0083] As an example, in step S83, please refer to... Figure 4 (a), (b) and Figure 5 In (a) and (b), the quasi-atomic layer wet etching process can precisely control the etching thickness of the etching layer 1321' through multiple etching process cycles. By controlling the etching cycle, the etching layer 1321' can be completely removed to expose the high-quality target semiconductor pillar 1322 surface, i.e., the silicon single crystal surface, thereby improving the carrier mobility of the channel. In addition, due to the improved quality of the silicon single crystal surface, a smaller channel width can be achieved with the same device size to reduce leakage current; it is also possible to appropriately reduce the thickness of the sacrificial layer 11 under the same channel spacing and stack size conditions, thereby increasing the stack density.

[0084] As an example, the difference between the first preset thickness and the preset channel thickness is greater than or equal to 1 nm and less than or equal to 60 nm. Specifically, the difference between the first preset thickness and the preset channel thickness can be 1 nm, 10 nm, 30 nm, 50 nm, or 60 nm, etc.

[0085] As an example, after step S8 removes the etched layer, the process also includes:

[0086] Step S91: Form a filling dielectric layer between adjacent target semiconductor pillars along the thickness direction and the second direction;

[0087] Step S92: Ion doping is performed on the target semiconductor pillar to form a first contact region, a channel region, a second contact region, and a capacitor region arranged sequentially along a first direction; wherein, the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

[0088] As an example, in step S92, please refer to Figure 6In (a) and (b), a filling dielectric layer 21 is formed between adjacent target semiconductor pillars along the thickness direction (e.g., the oy direction) and the second direction (e.g., the oz direction) to fill the gaps inside the semiconductor structure. Specifically, the material of the filling dielectric layer 21 can be selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0089] As an example, in step S92, please refer to... Figure 6 In (a) and (b), photolithography is used again to define the first contact region 1322a, the channel region 1322b, the second contact region 1322c, and the capacitor region 1322d, and ion doping is performed on the corresponding regions. The first contact region 1322a, the channel region 1322b, and the second contact region 1322c in the same target semiconductor pillar 1322 are used to form the same transistor. Specifically, the type of doped ions can be either a first doping type or a second doping type. The first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type. The specific photolithography process is a conventional technique that can be used by those skilled in the art and will not be described in detail here.

[0090] As an example, P-type impurity ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. N-type impurity ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0091] As an example, after step S9 forms the first contact area, it also includes:

[0092] Step S10: A bit line structure extending in the second direction is formed on the side of the first contact area away from the channel area along the first direction, and the first contact areas in the same column arranged along the second direction share a bit line structure.

[0093] As an example, in step S10, please refer to Figure 7 In (a) and (b), a bit line structure 14 extending along a second direction (e.g., the oz direction) is formed on the side of the first contact area 1322a away from the channel area 1322b along a first direction (e.g., the ox direction). Specifically, the position of the bit line structure 14 can be defined first by photolithography, and the first contact area 1322a can be etched by high aspect ratio dry etching to form a bit line contact plug (not shown) and a bit line structure 14; wherein the first contact area 1322a is connected to the bit line structure 14, and the first contact areas 1322a in the same column arranged along the second direction (e.g., the oz direction) share a bit line structure 14.

[0094] As an example, after step S10 forms the bitline structure, it also includes:

[0095] Step S11: Form a letter line structure that extends along the thickness direction and contacts the outer surface of the channel area. The same column of channel areas arranged along the thickness direction share a letter line structure.

[0096] As an example, in step S11, please refer to Figure 8 In (a) and (b), a word line structure 15 is formed that extends along the thickness direction (e.g., the oy direction) and contacts a portion of the outer surface of the channel region 1322b. Channel regions 1322b arranged in the same column along the thickness direction (e.g., the oy direction) share a single word line structure 15. Specifically, the position of the word line structure 15 can be defined first using a photolithography process. The word line structure 15 is formed on a portion of the outer surface of the channel region 1322b and circumferentially surrounds the channel region 1322b, meaning the word line structure 15 at least covers a portion of the outer surface of the channel region 1322b. The material of the word line structure 15 may include a metal with a high dielectric constant to form a corresponding gate structure.

[0097] For example, please refer to Figure 9 In (a) and (b), after step S11 forms the word line structure, it also includes:

[0098] Step S12: Form a capacitor structure 16 that circumferentially surrounds the outer surface of the capacitor region 1322d and extends along a first direction (e.g., the ox direction). The capacitor structure 16 extends along the first direction (e.g., the ox direction).

[0099] As an example, step S12 forms the capacitor structure, including:

[0100] Step S121: Form a first electrode on the outer surface of the capacitor region extending circumferentially in the first direction;

[0101] Step S122: Form an intermediate dielectric layer on the outer surface of the first electrode extending along the first direction;

[0102] Step S123: A second electrode is formed on the outer surface of the intermediate dielectric layer extending along the first direction. The first electrode, the intermediate dielectric layer, and the second electrode together constitute a capacitor structure.

[0103] As an example, in step S121, please refer to... Figure 9 In (a) and (b), the position of the capacitor region 1322d is first defined by photolithography, and a first electrode 161 is formed on the outer surface of the capacitor region 1322d extending circumferentially along a first direction (e.g., the ox direction). Specifically, the material of the first electrode 161 is selected from doped silicon, polycrystalline silicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, nitride, and combinations thereof.

[0104] As an example, please refer to step S122. Figure 9In (a) and (b) above, the same photolithography process is used to form an intermediate dielectric layer 162 on the outer surface of the first electrode 161 extending along a first direction (e.g., the ox direction). Specifically, the material of the intermediate dielectric layer 162 is selected from alumina, zirconium oxide, and combinations thereof. The intermediate dielectric layer 162 may also include other insulating materials with high dielectric constants (high-k), such as materials with a dielectric constant greater than 3.9.

[0105] As an example, in step S123, a second electrode 163 is formed on the outer surface of the intermediate dielectric layer 162 extending along a first direction (e.g., the ox direction). The first electrode 161, the intermediate dielectric layer 162, and the second electrode 163 together constitute the capacitor structure 16. Specifically, the material of the second electrode 163 is selected from doped silicon, polycrystalline silicon, copper, tungsten, aluminum, copper alloys, titanium, titanium nitride, nitride, and combinations thereof.

[0106] Although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be executed in other sequences. Moreover, although Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0107] As an example, please continue reading Figure 9 In addition to (a) and (b) in the present application, this application also provides a semiconductor structure prepared by the semiconductor structure preparation method described in any one of the embodiments of this application.

[0108] In the aforementioned semiconductor structure, the crystal quality of the single-crystal silicon on the surface of the target semiconductor pillar 1322 can be improved, thereby enhancing the channel for forming the gate-all-around transistor. This improves the carrier mobility of the channel, thus enhancing the performance of the gate-all-around device. Furthermore, the channel length can be further reduced to decrease dark current. Additionally, while maintaining the overall thickness of the stacked structure, the number of stacked cycles can be further increased, thereby further increasing the transistor density and improving device integration.

[0109] For example, please refer to Figure 10 (a) and (b) in the text, Figure 10This 3D DRAM device is fabricated using the semiconductor structure fabrication method provided in any embodiment of this application. It is formed by stacking multiple stacked units, ultimately resulting in a DRAM device with horizontally stacked units. The device includes target semiconductor pillars 1322 extending along a first direction (e.g., the ox direction) and arranged in an array along the thickness direction (e.g., the oy direction) and a second direction (e.g., the oz direction) of the substrate (not shown). Adjacent target semiconductor pillars 1322 along the thickness direction (e.g., the oy direction) have a stacked isolation structure 17 to insulate adjacent horizontal units along the thickness direction (e.g., the oy direction). The device also includes bit line structures 14 extending along the second direction (e.g., the oz direction) and spaced apart along the thickness direction (e.g., the oy direction). Adjacent bit line structures 14 along the thickness direction (e.g., the oy direction) have a bit line isolation structure 18 to insulate adjacent bit line structures 14. The device further includes word line structures 15 extending along a thickness direction (e.g., the oy direction) and spaced apart along a second direction (e.g., the oz direction). Adjacent word line structures 15 along the second direction (e.g., the oz direction) also have word line isolation structures 19 for insulating adjacent word line structures 15. The device also includes capacitor structures 16 extending along a first direction (e.g., the ox direction) and arranged in an array along the thickness direction (e.g., the oy direction) and the second direction (e.g., the oz direction) of the substrate 10. The capacitor structures 16 are formed on corresponding target semiconductor pillars 1322. Additionally, the capacitor structure 16 has a fixing structure 20 on the side of the capacitor structure 16 away from the bit line structure 14 along the first direction (e.g., the ox direction). The above semiconductor structure can improve the carrier mobility of the channel, thereby improving the performance of the gate-all-around device. It can also further reduce the channel length to reduce dark current and further increase transistor density.

[0110] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A stacked structure is formed on the substrate, the stacked structure including sacrificial portions and initial semiconductor pillars that are alternately stacked along the thickness direction of the substrate, the sacrificial portions being adjacent to the substrate; Using a first preset process, the sacrificial portion is removed, and an interface layer is formed on the outer surface of the initial semiconductor pillar extending along the first direction. The remaining initial semiconductor pillar is used to form an intermediate semiconductor pillar. A second preset process is used to remove the interface layer and part of the etching layer formed by the intermediate semiconductor pillars; wherein, the remaining intermediate semiconductor pillars are used to form the target semiconductor pillars. The first preset process is different from the second preset process, and the first direction is perpendicular to the thickness direction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first preset process includes a dry etching process, and the second preset process includes a quasi-atomic layer wet etching process.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The second preset process has at least one process cycle to remove the etched layer, including: During one of the process cycles, a first etching solution is provided on the interface layer to remove the exposed oxide surface in the etched layer; A second etching solution is provided on the interface layer to oxidize the remaining etched layer; Repeat the process cycle until the etched layer is completely removed and the thickness of the target semiconductor pillar reaches the preset channel thickness.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first etching solution includes a buffered oxide etching solution, and the second etching solution includes a hydrogen peroxide solution.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The initial semiconductor pillar has a first preset thickness; wherein the first preset thickness is greater than the preset channel thickness.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first preset thickness is greater than or equal to 1 nm and less than or equal to 100 nm; the thickness of the interface layer is greater than or equal to 1 nm. Wherein, the first preset thickness is the sum of the preset channel thickness and the thickness of the etched layer on the two outer surfaces of the target semiconductor pillar along the thickness direction.

7. The method for preparing a semiconductor structure according to any one of claims 2-6, characterized in that, In the dry etching process, the etching selectivity ratio between the sacrificial portion and the initial semiconductor pillar is greater than 100.

8. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, The material of the sacrificial part includes a silicon-germanium alloy, wherein the germanium content in the silicon-germanium alloy is 5%-40%.

9. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, A stacked structure is formed on the substrate, comprising: A sacrificial layer and a semiconductor layer are formed on the substrate, which are alternately stacked along the thickness direction of the substrate, and the sacrificial layer is adjacent to the substrate; Multiple stacked structures are formed based on the sacrificial layer and the semiconductor layer, which are spaced apart along the second direction. The sacrificial layer is used to form the sacrificial portion, and the semiconductor layer is used to form the initial semiconductor pillar. The second direction, the first direction, and the thickness direction are perpendicular to each other.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, After removing the etched layer, the process further includes: Ion doping is performed on the target semiconductor pillar to form a first contact region, a channel region, a second contact region, and a capacitor region arranged sequentially along the first direction; wherein, the first contact region is a source contact region or a drain contact region, and the second contact region is a drain contact region or a source contact region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, After the first contact area is formed, the process further includes: A bit line structure extending in the second direction is formed on the side of the first contact area away from the channel area along the first direction, and the first contact areas in the same column arranged along the second direction share one bit line structure.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, After forming the bitline structure, the method further includes: A word line structure is formed that extends along the thickness direction and contacts the outer surface of the channel area, and the same column of channel areas arranged along the thickness direction shares one word line structure.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, After forming the character line structure, the method further includes: A capacitor structure is formed that circumferentially surrounds the outer surface of the capacitor region and extends along the first direction, the capacitor structure extending along the first direction.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming the capacitor structure includes: A first electrode is formed circumferentially surrounding the outer surface of the capacitor region, extending along the first direction; An intermediate dielectric layer is formed on the outer surface of the first electrode extending along the first direction; A second electrode is formed on the outer surface of the intermediate dielectric layer extending along the first direction, and the first electrode, the intermediate dielectric layer, and the second electrode together constitute the capacitor structure.

15. A semiconductor structure, characterized in that, It is prepared by the method of any one of claims 1-14.

Images