Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of storage units which are distributed in different layers, are stacked in a direction perpendicular to a substrate, and are periodically distributed; each layer comprises a plurality of columns of storage units, and each storage unit comprises a transistor; the transistor comprises a semiconductor layer, a gate electrode and a gate insulating layer arranged between the side wall of the gate electrode and the semiconductor layer; the semiconductor layer extends along a first direction parallel to the substrate; the gate electrode comprises a vertical part and a horizontal part, the vertical part extends in the direction perpendicular to the substrate, the horizontal part intersects with the vertical part, the vertical part surrounds the side wall of the semiconductor layer, and the horizontal part surrounds at least part of the side wall of the semiconductor layer. The gate electrode of the transistor of the semiconductor device has more areas surrounding the semiconductor layer, the control capability of the gate electrode on the semiconductor layer is relatively high, and the performance of the transistor is relatively excellent.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (Random Access Memory, RAM) and non-volatile memory based on application. RAM includes dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random-Access Memory, SRAM). Non-volatile memory includes read-only memory (Read-Only Memory, ROM) and non-ROM.

[0003] Taking DRAM as an example, the conventional DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device. The gate electrode of the transistor of the semiconductor device has a larger area surrounding the semiconductor layer, the gate electrode has a stronger control capability over the semiconductor layer, and the transistor has better performance.

[0007] An embodiment of the present application provides a semiconductor device, the semiconductor device comprising:

[0008] A plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to a substrate and distributed periodically; each layer comprises a plurality of columns of memory cells, wherein the memory cells comprise transistors; the transistors comprise a semiconductor layer, a gate electrode and a gate insulating layer arranged between the sidewall of the gate electrode and the semiconductor layer; the semiconductor layer extends along a first direction parallel to the substrate; the gate electrode comprises a vertical portion extending along a direction perpendicular to the substrate and a horizontal portion intersecting the vertical portion, wherein the vertical portion surrounds the sidewall of the semiconductor layer, and the horizontal portion surrounds at least a portion of the sidewall of the semiconductor layer.

[0009] In an exemplary embodiment of the present application, the vertical portion and the horizontal portion of the same gate electrode may be connected to form a closed ring, and the sidewall of the semiconductor layer is completely surrounded by the gate electrode.

[0010] In an exemplary embodiment of the present application, the semiconductor device may further include a word line, wherein the word line runs through the memory cells of different layers and extends in a direction perpendicular to the substrate; and the gate electrode is a part of the word line.

[0011] In an exemplary embodiment of the present application, the word line may have a plurality of openings spaced apart in a direction perpendicular to the substrate, the openings are fully surrounded by the gate electrode, and the semiconductor layer is located in the openings.

[0012] In an exemplary embodiment of the present application, the horizontal portions of two adjacent layers of the gate electrodes may be an integrated structure.

[0013] In an exemplary embodiment of the present application, the transistor may further include a first electrode and a second electrode extending along the first direction, and a channel between the first electrode and the second electrode is a horizontal channel.

[0014] In an exemplary embodiment of the present application, the semiconductor device may further include a bit line extending along a second direction parallel to the substrate, wherein the second direction intersects the first direction; the first electrodes of the transistors of a plurality of the memory cells located in the same layer and spaced apart along the second direction may be connected to the same bit line.

[0015] In an exemplary embodiment of the present application, the storage unit may further include a capacitor, the capacitor including a third electrode, a fourth electrode and a dielectric layer located between the third electrode and the fourth electrode, the third electrode of the capacitor located in the same storage unit is connected to the second electrode of the transistor, and the third electrode and the second electrode connected thereto are an integrated structure.

[0016] The embodiment of the present application provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to a substrate, and periodically distributed; each layer comprises a plurality of columns of memory cells, and the memory cells comprise transistors; the transistors comprise a semiconductor layer, a gate electrode, and a gate insulating layer disposed between a side wall of the gate electrode and the semiconductor layer; the semiconductor layer extends in a first direction parallel to the substrate; the gate electrode comprises a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion intersecting the vertical portion, the vertical portion surrounds the side wall of the semiconductor layer, and the horizontal portion surrounds at least a portion of the side wall of the semiconductor layer;

[0017] The manufacturing method comprises:

[0018] Alternately depositing sacrificial layers and semiconductor layers on a substrate to obtain a stacked structure, wherein the stacked structure includes an electrode region, a channel region, and a capacitor region;

[0019] Using a second insulating layer to replace the sacrificial layer located in the electrode region and the sacrificial layer located in the capacitor region close to the electrode region;

[0020] replacing the remaining sacrificial layer with the first insulating layer;

[0021] Etching a through hole penetrating each of the semiconductor layers in the first insulating layer in the channel region, and making the sidewall of the through hole covered by the first insulating layer;

[0022] Filling the through hole with the second insulating layer;

[0023] removing the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers;

[0024] The gate electrode is formed in a gap vacated by removing the first insulating layer.

[0025] In an exemplary embodiment of the present application, replacing the sacrificial layer located in the electrode region with a second insulating layer may include:

[0026] Etching the stacked structure along a direction toward the substrate, so that a groove penetrating each of the semiconductor layers and extending along a first direction parallel to the substrate is formed in a storage region of the stacked structure;

[0027] Filling a first insulating layer in the trench;

[0028] Etching and removing the first insulating layer in the groove in the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers;

[0029] Performing lateral etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located in the electrode region;

[0030] The second insulating layer is filled in the space vacated after the sacrificial layer in the electrode region is removed.

[0031] In an exemplary embodiment of the present application, replacing the sacrificial layer located on one side of the capacitor region close to the electrode region with the second insulating layer may include:

[0032] Etching and removing the first insulating layer in the groove located in the capacitor region near the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers;

[0033] Performing transverse etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located on a side of the capacitor region close to the electrode region;

[0034] The second insulating layer is filled in the space vacated after removing the sacrificial layer on the side of the capacitor region close to the electrode region.

[0035] In an exemplary embodiment of the present application, etching in the first insulating layer in the channel region to form a through hole penetrating each of the semiconductor layers, and making the sidewall of the through hole covered by the first insulating layer may include:

[0036] The first insulating layer in the trench in the channel region is etched along a direction toward the substrate to form the through hole in the first insulating layer, and the first insulating layer is exposed on the entire circumferential sidewall of the through hole.

[0037] In an exemplary embodiment of the present application, the removing of the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers may include:

[0038] The remaining first insulating layer in the trench in the channel region and the first insulating layer in the channel region between the semiconductor layers are removed by etching.

[0039] In an exemplary embodiment of the present application, gate electrodes of a plurality of transistors spaced apart and distributed in a direction perpendicular to the substrate are connected together to form a word line;

[0040] The manufacturing method may further include, after forming a gate electrode that completely surrounds the sidewall of the semiconductor layer located in the channel region,

[0041] The gate electrode material on the upper surface of the substrate in the channel region is removed by etching to expose the top of the second insulating layer between two adjacent word lines, and the second insulating layer is deposited on the surface of the region between the two adjacent word lines. The two adjacent word lines are isolated by the second insulating layer.

[0042] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0043] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0045] Figure 1 A schematic top view of a semiconductor device according to an exemplary embodiment of the present application;

[0046] Figure 2A for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the a-a' direction;

[0047] Figure 2B for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0048] Figure 2C for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0049] Figure 2D for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0050] Figure 2E for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0051] Figure 2F for Figure 2C A partial enlarged view of

[0052] Figure 3 A process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0053] Figure 4A A schematic diagram of a longitudinal cross-sectional structure in the bb' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a stacked structure is formed;

[0054] Figure 4B for Figure 4A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0055] Figure 5A A schematic diagram of a longitudinal cross-sectional structure in the a-a' direction after forming a trench in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0056] Figure 5B for Figure 5A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0057] Figure 5C for Figure 5A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0058] Figure 5D for Figure 5A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0059] Figure 5E for Figure 5A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0060] Figure 6 A schematic diagram of a longitudinal cross-sectional structure in the c-c' direction after a first insulating layer is filled in a trench according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present application;

[0061] Fig. 7A A schematic diagram of a longitudinal cross-sectional structure in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after removing a sacrificial layer in an electrode region;

[0062] Figure 7B for Fig. 7A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0063] Figure 7C for Fig. 7A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0064] Fig.7D for Fig. 7A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0065] Fig. 7E for Fig. 7A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0066] Fig. 8AA schematic diagram of a longitudinal cross-sectional structure in the bb' direction after a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application uses a second insulating layer to fill the space vacated by the sacrificial layer in the electrode region;

[0067] Figure 8B for Fig. 8A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0068] Fig. 9 A schematic diagram of a longitudinal cross-sectional structure in the bb' direction after removing the first insulating layer in the trench on one side of the capacitor region according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present application;

[0069] Fig.10 A schematic diagram of a longitudinal cross-sectional structure in the bb' direction after removing a sacrificial layer on one side of a capacitor region in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0070] Fig.11A A schematic diagram of a longitudinal cross-sectional structure in the bb' direction after a second insulating layer is filled in a space vacated by removing a sacrificial layer on one side of a capacitor region according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present application;

[0071] Fig. 11B for Fig.11A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0072] Fig. 12A A schematic diagram of a longitudinal cross-sectional structure in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after all first insulating layers are removed;

[0073] Fig. 12B for Fig. 12A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0074] Fig. 12C for Fig. 12A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0075] Fig.12D for Fig. 12A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0076] Fig.12E for Fig. 12A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0077] Fig.13AA schematic diagram of a longitudinal cross-sectional structure in the a-a' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after all sacrificial layers are removed;

[0078] Fig. 13B for Fig.13A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0079] Fig. 13C for Fig.13A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0080] Fig.13D for Fig.13A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0081] Fig.13E for Fig.13A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0082] Fig.14A A schematic diagram of a longitudinal cross-sectional structure in the aa' direction after a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application fills a space vacated by removing the first insulating layer and the sacrificial layer with the first insulating layer;

[0083] Fig. 14B for Fig.14A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0084] Fig. 14C for Fig.14A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0085] Fig.14D for Fig.14A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0086] Fig.14E for Fig.14A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0087] Fig.15A It is a schematic diagram of a longitudinal cross-sectional structure in the c-c' direction after forming a through hole K1 in a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;

[0088] Fig. 15B for Fig.15A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0089] Fig.16AA schematic diagram of a longitudinal cross-sectional structure in the aa' direction after a second insulating layer is filled in a through hole K1 according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present application;

[0090] Fig. 16B for Fig.16A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction;

[0091] Fig. 16C for Fig.16A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction;

[0092] Fig.16D for Fig.16A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0093] Fig.16E for Fig.16A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction;

[0094] Fig.17A A schematic diagram of a longitudinal cross-sectional structure in the c-c' direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after removing the remaining first insulating layer in the trench located in the channel region;

[0095] Fig. 17B for Fig.17A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction;

[0096] Fig.18 It is a schematic diagram of the longitudinal cross-sectional structure in the bb' direction after removing the first insulating layer located in the channel region between the semiconductor layers according to the manufacturing method of a semiconductor device of the exemplary embodiment of the present application. DETAILED DESCRIPTION

[0097] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0098] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0099] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0100] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0101] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0102] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0103] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0104] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0105] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0106] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced by "semiconductor film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0107] The term "A and B are arranged in the same layer" in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface. In one embodiment, A and B are formed simultaneously by subjecting the same film layer to the same patterning process.

[0108] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0109] In the various embodiments of the present application, the spacing can be understood as being separated, and can be achieved by a physical structural disconnection or an electrical characteristic disconnection. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0110] The gate electrode of the horizontal channel transistor in the current DRAM is generally a double gate structure, that is, only two opposite side walls of the transistor channel are surrounded by the gate electrode. As the core size of semiconductor devices gradually decreases, for horizontal channel transistors, the reduction in channel size weakens the control ability of the gate electrode over the channel. The contact area between the gate electrode surrounded on both sides and the horizontal channel is small, and the gate electrode has poor control over the horizontal channel. Therefore, the performance of DRAM using horizontal channel transistors is poor.

[0111] An embodiment of the present application provides a semiconductor device.

[0112] Figure 1 A schematic top view of a semiconductor device according to an exemplary embodiment of the present application; Figure 2A for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the a-a' direction; Figure 2B for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the bb' direction; Figure 2C for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the c-c' direction; Figure 2D for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the d-d' direction; Figure 2E for Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in the ee' direction; Figure 2F for Figure 2C A partial enlarged view of .

[0113] like Figures 1 to 2F As shown, the semiconductor device may include: a plurality of memory cells 20 located on a substrate 10;

[0114] A plurality of memory cells 20 are distributed in different layers, stacked along a direction perpendicular to the substrate 10 and distributed periodically; each layer includes a plurality of columns of memory cells 20, and each memory cell 20 includes a transistor 30;

[0115] The transistor 30 includes a semiconductor layer 40, a gate electrode 50, and a gate insulating layer 60 disposed between the sidewall of the gate electrode 50 and the semiconductor layer 40; the semiconductor layer 40 extends along a first direction parallel to the substrate 10; the semiconductor layer 40 can be understood as a semiconductor material, and its shape and structure are not emphasized here, only its function is emphasized; the first direction parallel to the substrate can be understood as a lateral direction, for example, the first direction can be as follows Figure 1 b-b' direction shown;

[0116] The gate electrode 50 includes a vertical portion 51 extending in a direction perpendicular to the substrate 10 and a horizontal portion 52 crossing the vertical portion 51 . The vertical portion 51 surrounds a sidewall of the semiconductor layer 40 , and the horizontal portion 52 surrounds at least a portion of the sidewall of the semiconductor layer 40 .

[0117] The semiconductor device of the embodiment of the present application enables the horizontal portion 52 of the gate electrode 50 to surround at least part of the sidewall of the semiconductor layer 40, that is, the gate electrode 50 extends between two adjacent semiconductor layers 40 and surrounds the sidewalls of the upper and lower surfaces of the semiconductor layer. Compared with a double gate structure transistor (where only the vertical portion of the gate electrode surrounds the sidewall of the semiconductor layer), the contact area between the gate electrode and the semiconductor layer in the semiconductor device of the embodiment of the present application is larger, so the gate electrode has a stronger control capability over the semiconductor layer, and the performance of the semiconductor device is better.

[0118] In an exemplary embodiment of the present application, Figure 2C As shown, the vertical portion 51 and the horizontal portion 52 of the same gate electrode 50 can be connected to form a closed ring, and the sidewall of the semiconductor layer 40 is completely surrounded by the gate electrode 50 .

[0119] Here, “all around” means completely around the circumference, and does not limit the extension degree of the gate electrode 50 in the extension direction of the semiconductor layer 40 .

[0120] When the vertical portion 51 and the horizontal portion 52 of the same gate electrode 50 can be connected to form a closed ring, the side wall of the semiconductor layer 40 is completely surrounded by the gate electrode 50, that is, the gate electrode 50 contacts the entire circumferential side wall of the semiconductor layer 40, the contact area between the gate electrode 50 and the semiconductor layer 40 is the largest, and the gate electrode has the strongest control ability over the semiconductor layer.

[0121] In an exemplary embodiment of the present application, FIG. 2B to FIG. 2F As shown, the longitudinal cross-sectional profile of the semiconductor layer 40 can be a rectangle, where the longitudinal cross-sectional profile refers to a cross-sectional profile perpendicular to the substrate 10; the semiconductor layer 40 has two end faces and four side faces located between the two end faces, the two end faces of the semiconductor layer 40 are respectively connected to the source electrode and the drain electrode of the transistor, the two opposite side faces of the semiconductor layer 40 are fully surrounded by the vertical portion 51 of the gate electrode 50, and the other two opposite side faces of the semiconductor layer 40 are fully surrounded by the horizontal portion 52 of the gate electrode 50, so that the four side faces of the semiconductor layer 40 (constituting the entire side wall) are fully surrounded by the gate electrode 50.

[0122] In an exemplary embodiment of the present application, the horizontal portion 52 of the gate electrode 50 may extend in a direction parallel to the substrate.

[0123] In an exemplary embodiment of the present application, Figure 1 and Figure 2C As shown, the semiconductor device may further include a word line 70 , which runs through the memory cells of different layers and extends in a direction perpendicular to the substrate 10 ; the gate electrode 50 is a part of the word line 70 .

[0124] In an exemplary embodiment of the present application, Figure 2C As shown, the word line 70 may have a plurality of openings 71 spaced apart and distributed along a direction perpendicular to the substrate 10 . The openings 71 are completely surrounded by the gate electrode 50 , and the semiconductor layer 40 is located in the openings 71 .

[0125] In an exemplary embodiment of the present application, Figure 2C As shown, the horizontal portions of two adjacent layers of gate electrodes 50 may be an integrated structure.

[0126] In an exemplary embodiment of the present application, Figure 1 and Figure 2BAs shown, the transistor structure may further include a first electrode 41 and a second electrode 42 extending along the first direction, and a channel between the first electrode 41 and the second electrode 42 is a horizontal channel.

[0127] In an exemplary embodiment of the present application, the first electrode 41 may be a drain electrode of a transistor, and the second electrode 42 may be a source electrode of the transistor; or, the first electrode 41 may be a source electrode of a transistor, and the second electrode 42 may be a drain electrode of the transistor.

[0128] In an exemplary embodiment of the present application, Figure 2B As shown, the first electrode 41, the second electrode 42 and the semiconductor layer 40 therebetween may be arranged in the same layer or in an integrated structure. For example, the first electrode 41, the second electrode 42 and the semiconductor layer 40 therebetween may be formed by the same semiconductor film layer, and different regions in the semiconductor film layer serve as the first electrode 41, the second electrode 42 and the semiconductor layer 40 (i.e., the channel) of the transistor, respectively.

[0129] In an exemplary embodiment of the present application, Figure 1 As shown, the semiconductor device may further include a bit line 80 extending along a second direction parallel to the substrate 10, wherein the second direction intersects the first direction, and the second direction may be as follows: Figure 1 The first electrodes 41 of the transistors 30 of the plurality of memory cells 20 located in the same layer and spaced apart along the second direction may be connected to the same bit line 80 .

[0130] In an exemplary embodiment of the present application, the memory cell may be a memory cell including a transistor, the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C or 2T1C memory cell, or a read transistor and a storage node in a 1T0C or 2T0C memory cell.

[0131] In an exemplary embodiment of the present application, Figure 1 As shown, the storage unit may further include a capacitor 90, the capacitor including a third electrode 91, a fourth electrode 92 and a dielectric layer located between the third electrode 91 and the fourth electrode 92 (not shown in the figure, and Figure 1 The third electrode is covered by the fourth electrode), the third electrode 91 of the capacitor located in the same storage unit is connected to the second electrode 42 of the transistor; the third electrode may extend along the first direction.

[0132] In an exemplary embodiment of the present application, Figure 1As shown, the second electrode 42 of the transistor included in the same storage unit and the third electrode 91 of the capacitor 90 connected thereto may be an integrated structure. For example, different regions of the same semiconductor film layer may be used as the second electrode 42 and the third electrode 91 respectively.

[0133] The substrate in the embodiment of the present application may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the main surface of the supporting structure.

[0134] In an exemplary embodiment of the present application, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap less than 1.65 eV, or a wide band gap material such as a metal oxide material with a band gap greater than 1.65 eV.

[0135] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0136] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0137] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0138] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0139] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0140] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0141] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0142] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0143] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0144] Low-K materials, such as silicon oxide.

[0145] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplarily, for example, at least one of the following may be included but is not limited to: high-K materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0146] In an exemplary embodiment of the present application, the material of the dielectric layer may be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al2O3) and hafnium oxide.

[0147] In an exemplary embodiment of the present application, the semiconductor device may be a 3D memory, such as a 3D DRAM, etc. The 3D memory may have a 1T1C or 2T1C structure, or may have a 1T0C or 2T0C structure including a read transistor and a write transistor.

[0148] The embodiment of the present application also provides a method for manufacturing a semiconductor device. The semiconductor device includes a plurality of memory cells distributed in different layers, stacked in a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells, and the memory cells include transistors; the transistors include a semiconductor layer, a gate electrode, and a gate insulating layer disposed between the sidewall of the gate electrode and the semiconductor layer; the semiconductor layer extends in a first direction parallel to the substrate; the gate electrode includes a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion intersecting the vertical portion, the vertical portion surrounds the sidewall of the semiconductor layer, and the horizontal portion surrounds at least part of the sidewall of the semiconductor layer.

[0149] Figure 3 FIG. 1 is a process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application. Figure 3 As shown, the manufacturing method comprises:

[0150] Alternately depositing sacrificial layers and semiconductor layers on a substrate to obtain a stacked structure, wherein the stacked structure includes an electrode region, a channel region, and a capacitor region;

[0151] Using a second insulating layer to replace the sacrificial layer located in the electrode region and the sacrificial layer located in the capacitor region close to the electrode region;

[0152] replacing the remaining sacrificial layer with the first insulating layer;

[0153] Etching a through hole penetrating each of the semiconductor layers in the first insulating layer in the channel region, and making the sidewall of the through hole covered by the first insulating layer;

[0154] Filling the through hole with the second insulating layer;

[0155] removing the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers;

[0156] The gate electrode is formed in a gap vacated by removing the first insulating layer.

[0157] In an exemplary embodiment of the present application, replacing the sacrificial layer located in the electrode region with a second insulating layer may include:

[0158] Etching the stacked structure along a direction toward the substrate, so that a groove penetrating each of the semiconductor layers and extending along a first direction parallel to the substrate is formed in a storage region of the stacked structure;

[0159] Filling a first insulating layer in the trench;

[0160] Etching and removing the first insulating layer in the groove in the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers;

[0161] Performing lateral etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located in the electrode region;

[0162] The second insulating layer is filled in the space vacated after the sacrificial layer in the electrode region is removed.

[0163] In an exemplary embodiment of the present application, replacing the sacrificial layer located on one side of the capacitor region close to the electrode region with the second insulating layer may include:

[0164] Etching and removing the first insulating layer in the groove located in the capacitor region near the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers;

[0165] Performing transverse etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located on a side of the capacitor region close to the electrode region;

[0166] The second insulating layer is filled in the space vacated after removing the sacrificial layer on the side of the capacitor region close to the electrode region.

[0167] In an exemplary embodiment of the present application, etching in the first insulating layer in the channel region to form a through hole penetrating each of the semiconductor layers, and making the sidewall of the through hole covered by the first insulating layer may include:

[0168] The first insulating layer in the trench in the channel region is etched along a direction toward the substrate to form the through hole in the first insulating layer, and the first insulating layer is exposed on the entire circumferential sidewall of the through hole.

[0169] In an exemplary embodiment of the present application, the removing of the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers may include:

[0170] The remaining first insulating layer in the trench in the channel region and the first insulating layer in the channel region between the semiconductor layers are removed by etching.

[0171] In an exemplary embodiment of the present application, gate electrodes of a plurality of transistors spaced apart and distributed in a direction perpendicular to the substrate are connected together to form a word line;

[0172] The manufacturing method may further include, after forming a gate electrode that completely surrounds the sidewall of the semiconductor layer located in the channel region,

[0173] The gate electrode material on the upper surface of the substrate in the channel region is removed by etching to expose the top of the second insulating layer between two adjacent word lines, and the second insulating layer is deposited on the surface of the region between the two adjacent word lines. The two adjacent word lines are isolated by the second insulating layer.

[0174] Illustratively, the semiconductor device provided in the embodiment of the present application can be obtained by the method for manufacturing the semiconductor device provided in the embodiment of the present application described above.

[0175] The following is an example of the manufacturing process of a DRAM device with a 1T1C structure to further illustrate the technical solution of the embodiment of the present application. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping a photoresist, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0176] FIG. 4A to FIG. 18 A schematic diagram of the longitudinal cross-sectional structure of a device structure in the a-a', b-b', c-c', d-d' and e-e' directions obtained in each step of a method for manufacturing a semiconductor device of an exemplary embodiment of the present application.

[0177] Among them, if the longitudinal cross-sectional structural schematic diagrams of the semiconductor structure obtained in a certain step in the a-a', b-b', c-c', d-d' and e-e' directions are not fully given, it means that the longitudinal cross-sectional structural schematic diagram of the semiconductor structure obtained in this step and the previous step in the same direction is the same.

[0178] like FIG. 4A to FIG. 18 and FIG. 2A to FIG. 2F As shown, in an exemplary embodiment of the present application, the method for manufacturing the semiconductor device includes the following steps.

[0179] S10: A stacking structure in which semiconductor layers 40 and sacrificial layers 11 are alternately stacked is formed on a substrate 10, wherein the stacking structure includes a storage area for forming the storage unit, and the storage area includes an electrode area for forming a first electrode and a second electrode (i.e., a source electrode and a drain electrode) of the transistor, a channel area for forming a semiconductor layer (i.e., a channel) of the transistor, and a capacitance area for forming the capacitor.

[0180] By way of example, the substrate 10 may be a silicon substrate, the material of the semiconductor layer 40 may be silicon, and the material of the sacrificial layer 11 may be silicon germanium (SiGe).

[0181] Exemplarily, step S10 may include: using epitaxial technology to alternately and cyclically deposit SiGe / Si on the surface of the silicon wafer to form a superlattice epitaxial structure, and then sequentially depositing a first insulating layer 12 and a second insulating layer 13 as protective layers, such as Figure 4A and Figure 4B As shown; Figure 4A The longitudinal cross-sectional structure diagram of the structure shown in the a-a', d-d' and e-e' directions is Figure 4A same.

[0182] The materials of the first insulating layer and the second insulating layer can be independently selected from any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the materials of the first insulating layer and the second insulating layer are different, so that when one of the insulating layers is subsequently etched and removed, the first insulating layer and the second insulating layer can have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.

[0183] Illustratively, under the same etching conditions, the etching rate of the sacrificial layer 11 is significantly different from the etching rates of the semiconductor layer 40, the first insulating layer 12, and the second insulating layer 13, so that the semiconductor layer 40, the first insulating layer 12, and the second insulating layer 13 will not be affected when etching and removing the sacrificial layer 11 in subsequent steps. For example, the material of the sacrificial layer 11 may include but is not limited to silicon germanium (SiGe).

[0184] Figure 4A The stacked structure shown in the figure includes three sacrificial layers 11 and three semiconductor layers 40 , which is only an example. In other embodiments, the stacked structure may include more or fewer sacrificial layers 11 and semiconductor layers 40 that are alternately arranged.

[0185] S20: Etching the stacked structure in a direction toward the substrate 10, so that a groove 14 penetrating each semiconductor layer 40 and extending in a first direction parallel to the substrate 10 is formed in the storage region of the stacked structure. The groove 14 may not penetrate both sides of the stacked structure in the first reverse direction, and the groove 14 is only required to be formed in the storage region. FIG. 5A to FIG. 5E shown.

[0186] For example, a patterned etching process may be used to form the groove 14 in the stacked structure, including using photolithography to define a pattern and using dry etching to etch the groove 14 in the stacked structure. The groove 14 may also extend in a direction perpendicular to the substrate 10 and pass through the upper and lower surfaces of the stacked structure, and may also extend into the substrate 10.

[0187] S30: depositing a first insulating layer 12 filling the trench 14 on the substrate 10, and then planarizing it by chemical mechanical polishing (CMP), and the second insulating layer on the surface of the stacked structure is used as a stop layer, such as Figure 6 shown.

[0188] S40: Etching and removing the first insulating layer 12 in the groove 14 in the electrode region (including the region where the first electrode and the second electrode of the transistor are to be formed), exposing the staggered stacked semiconductor layer 40 and the sacrificial layer 11. The longitudinal cross-sectional structure schematic diagram of the structure obtained in this step in the directions a-a', b-b', c-c' and e-e' is the same as that in step S30, and the longitudinal cross-sectional structure schematic diagram in the direction d-d' is the same as that in step S40. Figure 5D same.

[0189] For example, in step S40 , a pattern may be defined by photolithography, and the first insulating layer 12 in the trench 14 may be removed by dry etching.

[0190] S50: Laterally etching the sacrificial layer exposed in the groove 14 to remove the sacrificial layer 11 located in the electrode region. 7A to 7E shown.

[0191] S60: filling the second insulating layer 13 in the space vacated after removing the sacrificial layer in the electrode region.

[0192] Exemplarily, step S60 may include: depositing a second insulating layer 13 on the surface of the substrate 10 obtained in step S50, and allowing the deposited second insulating layer 13 to fill the space vacated after removing the sacrificial layer in the electrode region, and then planarizing the surface of the substrate 10 using a CMP process, and then dry etching the second insulating layer 13 on the surface of the stacked structure to expose the first insulating layer in the groove 14 in the channel region, such as Fig. 8A and Figure 8B shown.

[0193] S70: etching and removing the second insulating layer in the groove 14 located in the capacitor region near the electrode region, exposing the staggered stacked semiconductor layer 40 and the sacrificial layer 11, as shown in FIG. Fig. 9 shown.

[0194] S80: performing lateral etching on the sacrificial layer 11 exposed in the groove 14, for example, a wet etching process may be used to remove the sacrificial layer 11 located in the capacitor region near the electrode region, such as Fig.10 shown.

[0195] S90: filling the second insulating layer 13 in the space vacated after removing the sacrificial layer 11 on the side of the capacitor region close to the electrode region.

[0196] Exemplarily, step S90 may include: depositing a second insulating layer 13 on the surface of the substrate 10 obtained in step S80, and allowing the deposited second insulating layer 13 to fill the space vacated after removing the sacrificial layer in the capacitor region, and then planarizing the surface of the substrate 10 using a CMP process, and then dry etching the second insulating layer 13 on the surface of the stacked structure to expose the first insulating layer in the groove 14 in the channel region, such as Fig.11A and Fig. 11B shown.

[0197] The purpose of depositing the second insulating layer 13 in step S90 is to prepare for the subsequent formation of capacitors. The fourth electrodes of multiple capacitors are formed by the same film layer, so the obtained fourth electrodes will be connected together. Removing the second insulating layer 13 deposited in step S90 can disconnect the fourth electrodes of each capacitor.

[0198] S100: etching and removing all the first insulating layer 12 in the substrate 10 obtained in step S90, including the first insulating layer 12 on the upper surface of the stacked structure and the first insulating layer 12 in the groove 14; for example, the first insulating layer 12 may be removed by a wet etching process, such as FIG. 12A to FIG. 12E shown.

[0199] S110: etching and removing all the sacrificial layer 11 in the substrate 10 obtained in step S90. For example, a wet etching process may be used to remove the sacrificial layer 11. FIG. 13A to FIG. 13E shown.

[0200] S120: Fill the space vacated by removing the first insulating layer 12 and the sacrificial layer 11 with the first insulating layer 12, and perform planarization using a CMP process until the second insulating layer on the surface of the substrate 10 is exposed, such as FIG. 14A to FIG. 14E shown.

[0201] S130: the first insulating layer 12 in the groove 14 in the channel region is etched along the direction toward the substrate 10, and a through hole K1 is formed in the first insulating layer 12, and the entire circumferential side wall of K1 exposes the first insulating layer 12, that is, the first insulating layer 12 in the groove 14 in the channel region is not completely etched away, and a certain thickness of the first insulating layer 12 is retained on the side wall of the groove 14 in the channel region, such as Fig.15A and Fig. 15B shown.

[0202] S140: depositing a second insulating layer 13 filling the through hole K1 on the substrate 10 obtained in step S130, and then planarizing the surface of the substrate 10 using a CMP process. After the planarization, the surface of the substrate 10 still has a second insulating layer 13 of a certain thickness, such as FIG. 16A to FIG. 16E shown.

[0203] S150: etching and removing the remaining first insulating layer 12 in the trench 14 in the channel region. For example, a dry etching process may be used to remove the remaining first insulating layer 12. Fig.17A and Fig. 17B shown.

[0204] S160: etching and removing the first insulating layer 12 located in the channel region between the semiconductor layers 40. For example, a wet etching process may be used to remove the first insulating layer 12 between the semiconductor layers 40. Fig.18 shown.

[0205] S170: A gate insulating layer 60 is deposited on the inner wall of the gap between the semiconductor layers 40 located in the channel region, and the gap is filled with a gate electrode material to form a gate electrode 50 surrounding the entire circumferential side wall of the semiconductor layer 40 located in the channel region, that is, the gate electrode 50 completely surrounds the semiconductor layer 40 located in the channel region; the semiconductor layer 40 located in the channel region serves as the channel of the transistor, and the semiconductor layer 40 located in the electrode region serves as the first electrode and the second electrode of the transistor respectively, and the first electrode, the second electrode, the channel and the gate electrode completely surrounding the channel constitute a transistor; the gate electrodes of multiple transistors spaced apart and distributed in a direction perpendicular to the substrate 10 are connected together to form a word line 70.

[0206] For example, step S170 may use an in-situ steam generation (ISSG) process to oxidize the exposed surface of the silicon semiconductor layer to form a layer of silicon oxide as a gate insulating layer, or directly deposit a High K material to form a gate insulating layer; the gate electrode 50 may be a multilayer structure of TiN / W or Ti / TiN / W. Figure 2F In the embodiment, the gate electrode 50 may be a double-layer structure including a TiN layer 53 and a W layer 54 .

[0207] Exemplarily, step S170 may further include using a dry etching process to remove the gate electrode material on the upper surface of the substrate located in the channel region, or removing the gate electrode material on the entire upper surface of the substrate, so that the top of the second insulating layer 13 used to isolate the two adjacent word lines between the two adjacent word lines is exposed, and then the second insulating layer 13 is deposited on the surface of the substrate 10, and the CMP process is used to planarize it, so that the second insulating layer 13 on the surface of the substrate 10 can be used to isolate the tops of the two adjacent word lines 70, and the following is obtained: FIG. 2A to FIG. 2F The semiconductor device shown.

[0208] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0209] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0210] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to a substrate and distributed periodically; each layer comprises a plurality of columns of memory cells, wherein the memory cells comprise transistors; the transistors comprise a semiconductor layer, a gate electrode and a gate insulating layer arranged between the sidewall of the gate electrode and the semiconductor layer; the semiconductor layer extends along a first direction parallel to the substrate; the gate electrode comprises a vertical portion extending along a direction perpendicular to the substrate and a horizontal portion intersecting the vertical portion, wherein the vertical portion surrounds the sidewall of the semiconductor layer, and the horizontal portion surrounds at least a portion of the sidewall of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein: The vertical portion and the horizontal portion of the same gate electrode are connected to form a closed ring, and the side wall of the semiconductor layer is completely surrounded by the gate electrode.

3. The semiconductor device according to claim 2, characterized in that It also includes a word line, which runs through the memory cells of different layers and extends in a direction perpendicular to the substrate; the gate electrode is a part of the word line.

4. The semiconductor device according to claim 3, characterized in that The word line has a plurality of openings spaced apart from each other in a direction perpendicular to the substrate, the openings are completely surrounded by the gate electrodes, and the semiconductor layer is located in the openings.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The horizontal parts of the gate electrodes of two adjacent layers are an integrated structure.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that The transistor further includes a first electrode and a second electrode extending along the first direction, and a channel between the first electrode and the second electrode is a horizontal channel; and / or, The semiconductor device also includes a bit line extending along a second direction parallel to the substrate, the second direction intersecting the first direction; the first electrodes of the transistors of the plurality of storage cells located in the same layer and spaced apart along the second direction are connected to the same bit line.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The storage unit also includes a capacitor, which includes a third electrode, a fourth electrode and a dielectric layer located between the third electrode and the fourth electrode. The third electrode of the capacitor located in the same storage unit is connected to the second electrode of the transistor, and the third electrode and the second electrode connected thereto are an integrated structure.

8. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a plurality of memory cells which are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically; each layer comprises a plurality of columns of memory cells, and the memory cells comprise transistors; the transistors comprise a semiconductor layer, a gate electrode, and a gate insulating layer disposed between a side wall of the gate electrode and the semiconductor layer; the semiconductor layer extends in a first direction parallel to the substrate; the gate electrode comprises a vertical portion extending in a direction perpendicular to the substrate and a horizontal portion intersecting the vertical portion, the vertical portion surrounds a side wall of the semiconductor layer, and the horizontal portion surrounds at least a portion of the side wall of the semiconductor layer; The manufacturing method comprises: Alternately depositing sacrificial layers and semiconductor layers on a substrate to obtain a stacked structure, wherein the stacked structure includes an electrode region, a channel region, and a capacitor region; A second insulating layer is used to replace the sacrificial layer located in the electrode region and the sacrificial layer located in the capacitor region close to the electrode region; replacing the remaining sacrificial layer with the first insulating layer; Etching a through hole penetrating each of the semiconductor layers in the first insulating layer in the channel region, and making the sidewall of the through hole covered by the first insulating layer; Filling the through hole with the second insulating layer; removing the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers; The gate electrode is formed in a gap vacated by removing the first insulating layer.

9. The manufacturing method according to claim 8, characterized in that: The using the second insulating layer to replace the sacrificial layer located in the electrode region comprises: Etching the stacked structure along a direction toward the substrate, so that a groove penetrating each of the semiconductor layers and extending along a first direction parallel to the substrate is formed in a storage region of the stacked structure; Filling a first insulating layer in the trench; Etching and removing the first insulating layer in the groove in the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers; Performing lateral etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located in the electrode region; The second insulating layer is filled in the space vacated after the sacrificial layer in the electrode region is removed.

10. The manufacturing method according to claim 9, characterized in that: The step of using the second insulating layer to replace the sacrificial layer located on a side of the capacitor region close to the electrode region comprises: Etching and removing the first insulating layer in the groove located in the capacitor region near the electrode region to expose the staggered stacked semiconductor layers and sacrificial layers; Performing transverse etching on the sacrificial layer exposed in the groove, so as to remove the sacrificial layer located on a side of the capacitor region close to the electrode region; The second insulating layer is filled in the space vacated after removing the sacrificial layer on the side of the capacitor region close to the electrode region.

11. The manufacturing method according to claim 10, characterized in that: The etching along a direction toward the substrate to form a through hole penetrating each of the semiconductor layers, and making the sidewalls of the through hole covered by the first insulating layer comprises: The first insulating layer in the trench in the channel region is etched along a direction toward the substrate to form the through hole in the first insulating layer, and the first insulating layer is exposed on the entire circumferential sidewall of the through hole.

12. The manufacturing method according to claim 11, characterized in that: The removing of the first insulating layer on the sidewall of the through hole and the first insulating layer located in the channel region between the semiconductor layers comprises: The remaining first insulating layer in the trench in the channel region and the first insulating layer in the channel region between the semiconductor layers are removed by etching.

13. The manufacturing method according to any one of claims 8 to 12, characterized in that: The gate electrodes of a plurality of transistors spaced apart and distributed in a direction perpendicular to the substrate are connected together to form a word line; The manufacturing method further comprises, after forming a gate electrode that completely surrounds the sidewall of the semiconductor layer located in the channel region, The gate electrode material on the upper surface of the substrate in the channel region is removed by etching to expose the top of the second insulating layer between two adjacent word lines, and the second insulating layer is deposited on the surface of the region between the two adjacent word lines. The two adjacent word lines are isolated by the second insulating layer.

14. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 7.

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