Semiconductor device

Abstract

The semiconductor device may include a channel structure, a gate insulating layer, a work function adjustment layer, and a word line. The channel structure may include an oxide semiconductor material. A gate insulating layer, a work function adjustment layer, and a word line may be sequentially formed on the channel structure.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical channel structure. Background Art

[0002] Advances in electronic technology have led to a rapid reduction in the size of semiconductor devices, which in turn has led to a reduction in the size of DRAM devices. In a DRAM device having a 1T-1C structure in which one capacitor is connected to one transistor, as the device becomes smaller, the leakage current through the channel region gradually increases. In order to reduce the leakage current, a transistor using an oxide semiconductor material as a channel layer has been proposed. Summary of the invention

[0003] The inventive concept provides a semiconductor device in which electrical reliability of a transistor having a channel structure is improved due to the use of an oxide semiconductor material.

[0004] In addition, disadvantages to be solved by the present inventive concept are not limited to the above-mentioned disadvantages, and other disadvantages may be clearly understood by those skilled in the art through the following description.

[0005] The present inventive concept provides the following semiconductor device.

[0006] According to an aspect of the inventive concept, a semiconductor device is provided, which includes: a substrate; a bit line extending in a first horizontal direction on the substrate; a channel layer disposed on the bit line and including a first portion and a second portion, the first portion extending in the first horizontal direction, the second portion connected to the first portion, the second portion including a first sidewall and a second sidewall opposite to the first sidewall and extending in a vertical direction perpendicular to an upper surface of the substrate; a gate insulating layer formed to conformally cover the first portion on an upper surface of the first portion of the channel layer and conformally cover the second portion on the first sidewall of the second portion of the channel layer; a work function adjustment layer conformally formed on the gate insulating layer; and a word line disposed on a sidewall of the work function adjustment layer and extending in a second horizontal direction perpendicular to the first horizontal direction. The channel layer may include an oxide semiconductor material.

[0007] According to another aspect of the inventive concept, a semiconductor device is provided, comprising: a substrate; a bit line extending in a first horizontal direction on the substrate; a molded insulating layer covering the bit line on the substrate and comprising a molded opening; a first cell transistor disposed on a first sidewall of the molded opening; and a second cell transistor disposed on a second sidewall of the molded opening, wherein each of the first cell transistor and the second cell transistor comprises: a channel layer disposed on the bit line and comprising a first portion and a second portion, the first portion extending in the first horizontal direction, the second portion connected to the first portion and extending in a vertical direction perpendicular to an upper surface of the substrate; a work function adjustment layer disposed on the first portion and the second portion of the channel layer; a gate insulating layer between the channel layer and the work function adjustment layer; a word line disposed on a sidewall of the work function adjustment layer and extending in a second horizontal direction perpendicular to the first horizontal direction; a contact disposed on the second portion of the channel layer; and a positioning pad disposed on the contact. The channel layer may include an oxide semiconductor material.

[0008] According to another aspect of the inventive concept, a semiconductor device is provided, comprising: a substrate; a peripheral circuit region, the peripheral circuit region being arranged on the substrate; a plurality of peripheral circuits, the plurality of peripheral circuits being arranged in the peripheral circuit region; a plurality of lower conductive lines, the plurality of lower conductive lines being arranged in parallel with each other and respectively connected to the plurality of peripheral circuits; a mold insulating pattern, the mold insulating pattern being arranged on the plurality of lower conductive lines and defining a transistor region extending lengthwise in a first horizontal direction; a plurality of channel structures, the plurality of channel structures being arranged in rows in the first horizontal direction in the transistor region, and each of the channel structures comprising a A vertical channel portion of a sidewall; a work function adjustment layer having a thickness of about 1 nm to 20 nm, located in the transistor region and covering the plurality of channel structures; a gate insulating layer, the gate insulating layer being located between the plurality of channel structures and the work function adjustment layer; an upper conductive line, the upper conductive line being arranged on the plurality of channel structures in the transistor region, having a sidewall of the vertical channel portion facing each of the plurality of channel structures, and extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of conductive contact patterns, the plurality of conductive contact patterns being respectively connected to the vertical channel portions of the plurality of channel structures. The plurality of channel structures may include an oxide semiconductor material. The work function adjustment layer may include a material having a work function of about 4.9 eV or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram showing a semiconductor device according to an example embodiment;

[0011] Figure 2 According to an example embodiment Figure 1 An enlarged layout diagram of a cell array region portion;

[0012] Figure 3 According to an example embodiment, Figure 2 A cross-sectional view of the semiconductor device taken along line A1-A1' in FIG.

[0013] Figures 4 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and their redundant descriptions are omitted.

[0015] The embodiments may be modified in various forms and various embodiments may be provided, therefore, some embodiments are shown in the drawings and some embodiments are described in detail. However, it should be understood that the embodiments are not limited in scope and include all modifications, equivalents and substitutes that belong to the concept and technical scope of the present invention. When describing the embodiments, if it is considered that the detailed description of the relevant known technology will unnecessarily distract the main points of the present invention, the detailed description will be omitted, but the description will be understood by those skilled in the art.

[0016] Figure 1 is a layout diagram illustrating a semiconductor device 100 according to example embodiments. Figure 2 According to an example embodiment Figure 1 An enlarged layout diagram of the cell array area MCA portion. Figure 3 According to an example embodiment, Figure 2 1 is a cross-sectional view of the semiconductor device 100 taken along line A1 - A1 ′.

[0017] refer to Figures 1 to 3 , the semiconductor device 100 may include a substrate 110, the substrate 110 including a cell array area MCA and a peripheral circuit area PCA. In some embodiments, the cell array area MCA may be a memory cell area of ​​a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of ​​the DRAM device. For example, the peripheral circuit area PCA may include a plurality of peripheral circuit transistors (not shown) for sending signals and / or power to a memory cell array included in the cell array area MCA. In an embodiment, the peripheral circuit transistors (not shown) may form various circuits such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output (I / O) circuit.

[0018] like Figure 2 As shown, on the cell array area MCA of the substrate 110, a plurality of word lines WL extending in a first horizontal direction X and a plurality of bit lines BL extending in a second horizontal direction Y perpendicular to the first horizontal direction X may be arranged. The plurality of word lines WL extending in the first horizontal direction X may be arranged in parallel with each other. The plurality of bit lines BL extending in the second horizontal direction Y may be arranged in parallel with each other. A plurality of cell transistors CTR may be arranged at intersections of the word lines WL and the bit lines BL, respectively. A plurality of cell capacitors CAP may be arranged on the cell transistors CTR, respectively.

[0019] The word lines WL may include first and second word lines WL1 and WL2 alternately arranged in the second horizontal direction Y, and the cell transistors CTR may include first and second cell transistors CTR1 and CTR2 alternately arranged in the second horizontal direction Y. The first cell transistor CTR1 may be disposed on the first word line WL1, and the second cell transistor CTR2 may be disposed on the second word line WL2.

[0020] The first cell transistor CTR1 and the second cell transistor CTR2 may have mirror-symmetric structures with respect to each other. For example, the first cell transistor CTR1 and the second cell transistor CTR2 may have mirror-symmetric structures on a center line extending in the first horizontal direction X between the first cell transistor CTR1 and the second cell transistor CTR2.

[0021] like Figure 3 As shown, the lower insulating layer 112 may be disposed on the substrate 110. The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. The lower insulating layer 112 may include an oxide film, a nitride film, or a combination thereof.

[0022] The bit line BL extending in the second horizontal direction Y may be disposed on the lower insulating layer 112. In an embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. For example, the bit line BL may include a conductive layer 122 and a conductive barrier layer 124 disposed on the upper and lower surfaces of the conductive layer 122. A bit line insulating layer (not shown) extending in the second horizontal direction Y may be disposed on a sidewall of the bit line BL. For example, the bit line insulating layer may fill a space between two adjacent bit lines BL and may be formed at the same height as that of the bit line BL.

[0023] The mold insulating layer 130 may be disposed on the bit line BL and the bit line insulating layer. The mold insulating layer 130 may include a plurality of mold openings 130H. Each mold opening 130H may include a first sidewall 130H1 and a second sidewall 130H2, and the first sidewall 130H1 and the second sidewall 130H2 may be separated from each other and extend in a first horizontal direction. The upper surface of the bit line BL may be exposed from the bottom of each mold opening 130H. The mold insulating layer 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0024] A plurality of channel layers 140 may be disposed on the inner wall of the mold opening 130H. Each channel layer 140 may include a first portion 140P1 extending in the second horizontal direction Y at the bottom of each mold opening 130H and a second portion 140P2 connected to the first portion 140P1 and disposed on the first sidewall 130H1 and the second sidewall 130H2 of each mold opening 130H. For example, each channel layer 140 may have a U-shaped vertical cross section. The second portion 140P2 of each channel layer 140 may include a first sidewall and a second sidewall opposite to each other, and the second sidewall may contact the mold insulating layer 130. The second portion 140P2 may include two vertical portions within one mold opening 130H. At the same time, the upper surface of each channel layer 140 may be disposed at a level higher than the level of the upper surface of the mold insulating layer 130, and the upper portion of the second sidewall may not be surrounded by the mold insulating layer 130.

[0025] It will be understood that when an element is referred to as being "connected," "coupled" or "on" another element, it may be directly connected or coupled to or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "in contact with" or "in contact with" another element, there are no intervening elements at the point of contact.

[0026] In an embodiment, the channel layer 140 may include an oxide semiconductor material. For example, the oxide semiconductor material may be formed of or include indium, and may include, for example, InGaZnO. x (IGZO), Sn-doped IGZO, W-doped IGZO and InZnO x At least one of (IZO).

[0027] The gate insulating layer 150, the work function adjustment layer 155, and the word line WL may be sequentially disposed on the first sidewall of the second portion 140P2 of each channel layer 140. In an embodiment, each of the gate insulating layer 150 and the work function adjustment layer 155 may include a horizontal portion and two vertical portions within one mold opening 130H. For example, the gate insulating layer 150 may be conformally disposed on the upper surface of the first portion 140P1 of each channel layer 140 and on the first sidewall of the second portion 140P2. For example, the horizontal portion of the gate insulating layer 150 may contact the upper surface of the first portion 140P1. The work function adjustment layer 155 may be disposed on the upper surface of the first portion 140P1 of each channel layer 140 and on the first sidewall of the second portion 140P2, and the gate insulating layer 150 may be located between the work function adjustment layer 155 and the channel layer 140. For example, the upper surface of the horizontal portion of the gate insulating layer 150 may contact the lower surface of the horizontal portion of the work function adjustment layer 155. The word lines WL may be disposed on sidewalls of the work function adjusting layer 155 .

[0028] The work function adjusting layer 155 may contact the gate insulating layer 150 and the word line WL. For example, the work function adjusting layer 155 may be disposed between the gate insulating layer 150 and the word line WL on the first sidewall of the second portion 140P2 of each channel layer 140 within one mold opening 130H.

[0029] For example, each channel layer 140 having a U-shaped vertical cross section may be disposed within one mold opening 130H, and two word lines WL may be positioned apart from each other within one mold opening 130H on each channel layer 140. One word line WL may be disposed to face one second portion 140P2 of each channel layer 140, and the other word line WL may be disposed to face the other second portion 140P2 of each channel layer 140. One word line WL, one second portion 140P2 of each channel layer 140, and the gate insulating layer 150 and the work function adjustment layer 155 between the one second portion 140P2 of each channel layer 140 and the one word line WL may constitute a first cell transistor CTR1, and another word line WL, another second portion 140P2 of each channel layer 140, and the gate insulating layer 150 and the work function adjustment layer 155 between the another word line WL and the another second portion 140P2 of each channel layer 140 may constitute a second cell transistor CTR2. Therefore, the first cell transistor CTR1 and the second cell transistor CTR2 may be arranged in a mirror-symmetrical shape within one mold opening 130H.

[0030] In an embodiment, the gate insulating layer 150 may include at least one selected from a high-k material having a dielectric constant higher than that of silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 includes at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0031] In an embodiment, the work function adjustment layer 155 may include a material having a work function of about 4.9 eV or more. The work function adjustment layer 155 may be made of, for example, indium oxide (In 2 O 3 ), titanium dioxide (TiO 2 ), molybdenum trioxide (MoO 3 ) or tungsten trioxide (WO 3 ) or includes at least one selected from, for example, indium oxide (In 2 O 3 ), titanium dioxide (TiO 2 ), molybdenum trioxide (MoO 3 ) or tungsten trioxide (WO 3 In an embodiment, the work function adjusting layer 155 may be formed to have a thickness of about 1 nm to about 20 nm.

[0032] In embodiments, the word lines WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0033] A contact formation region (not shown) may be disposed on an upper surface of the second portion 140P2 of each channel layer 140. A contact layer 170 may be disposed on the contact formation region. The contact layer 170 may cover the contact formation region and may extend onto the mold insulation layer 130. For example, the contact layer 170 may have an inverted L-shaped vertical cross section. In an embodiment, the contact layer 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0034] The insulating liner 182A and the first insulating layer 182B may be disposed between the two word lines WL in each mold opening 130H, and the second insulating layer 184 may be disposed on the two word lines WL. In addition, the third insulating layer 186 may be disposed on both sidewalls of the contact layer 170. For example, the insulating liner 182A may include silicon nitride, and the first insulating layer 182B may include silicon oxide. The second insulating layer 184 and the third insulating layer 186 may include silicon nitride.

[0035] A bottom surface of the insulating liner 182A may contact the work function adjusting layer 155 within one mold opening 130H. For example, the work function adjusting layer 155 may be disposed on an upper surface of the first portion 140P1 of each channel layer 140 between the gate insulating layer 150 and the insulating liner 182A.

[0036] An etch stop layer 188 may be disposed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 may include an opening 188H, and an upper surface of the contact layer 170 may be exposed to a bottom of the opening 188H.

[0037] The capacitor structure 190 may be disposed on the etch stop layer 188. The capacitor structure 190 may include a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196. The sidewall of the bottom of the lower electrode 192 may be disposed within the opening 188H of the etch stop layer 188, and the lower electrode 192 may extend in the vertical direction (Z direction). The capacitor dielectric layer 194 may be disposed on the sidewall of the lower electrode 192, and the upper electrode 196 may cover the lower electrode 192 on the capacitor dielectric layer 194.

[0038] The semiconductor device 100 having a vertical channel structure according to the present inventive concept can improve the electrical reliability of the semiconductor device by inserting a work function adjustment layer 155 between the word line WL and the gate insulating layer 150. The threshold voltage of the cell transistor in the semiconductor device 100 can be positively shifted by the insertion of the work function adjustment layer 155. For example, by inserting the work function adjustment layer 155 in the cell transistor, the off-cell current Ioff of the cell transistor and the voltage VBB2 applied to the gate of the cell transistor can be reduced. Therefore, the reliability of the semiconductor device can be improved by reducing the applied voltage VBB2.

[0039] Figures 4 to 16 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device 100 according to an example embodiment. Figures 4 to 16 In, with Figures 1 to 3 The same reference numerals as shown indicate the same components.

[0040] refer to Figure 4, a lower insulating layer 112 is formed on the substrate 110. Thereafter, bit lines BL extending in the second horizontal direction (Y direction) and a bit line insulating layer (not shown) filling spaces between the bit lines BL may be formed on the lower insulating layer 112.

[0041] In an embodiment, each bit line BL may include a conductive barrier layer 124, a conductive layer 122, and a conductive barrier layer 124 arranged sequentially. For example, a bit line insulating layer may be formed on the lower insulating layer 112 and the bit line insulating layer may be patterned using a mask pattern (not shown) to form a bit line forming space (not shown), and a conductive barrier layer 124, a conductive layer 122, and a conductive barrier layer 124 may be sequentially formed in the bit line forming space. Thereafter, the bit line BL may be formed by removing the upper sides of the conductive barrier layer 124, the conductive layer 122, and the conductive barrier layer 124 until the upper surface of the bit line insulating layer is exposed.

[0042] refer to Figure 5 , a mold insulating layer 130 may be formed on the bit line BL and the bit line insulating layer. The mold insulating layer 130 having a relatively large height in a vertical direction (Z direction) may be formed using at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0043] Thereafter, a mask pattern (not shown) may be formed on the mold insulating layer 130, and the mask pattern may be used as an etching mask to form a mold opening 130H. The upper surface of the bit line BL may be exposed from the bottom of each mold opening 130H. Each mold opening 130H may include a first sidewall 130H1 and a second sidewall 130H2 opposite to each other. In an embodiment, one mold opening 130H may be defined as a transistor region. For example, Figure 2 The first cell transistor CTR1 and the second cell transistor CTR2 may be disposed in one mold opening 130H.

[0044] refer to Figure 6 , a preliminary channel layer 140L may be formed on the mold insulation layer 130 to conformally cover an inner wall of each mold opening 130H. The preliminary channel layer 140L may be formed in a row in the second horizontal direction Y.

[0045] In an embodiment, the preliminary channel layer 140L may be formed using an oxide semiconductor material. For example, the oxide semiconductor material may be formed of or include indium, and may include, for example, InGaZnO. x At least one of (IGZO), Sn-doped IGZO, W-doped IGZO and IZO.

[0046] In embodiments, the preliminary channel layer 140L may be formed using at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition process.

[0047] refer to Figure 7 , Figure 8 and Fig. 9 , you can Figure 6 A gate insulating layer 150, a work function adjusting layer 155, and a gate electrode layer 160L are sequentially formed on the preliminary channel layer 140L.

[0048] The gate insulating layer 150 may be disposed on the channel layer 140. For example, each horizontal portion of the channel layer 140 (ie, the first portion 140P1) may include an upper surface coplanar with a lower surface of the horizontal portion of the gate insulating layer 150 within one mold opening 130H.

[0049] The gate insulating layer 150 may include at least one selected from a high-k material having a dielectric constant higher than that of silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 includes at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0050] In an embodiment, the work function adjustment layer 155 may include a material having a work function of 4.9 eV or more. The work function adjustment layer 155 may be made of, for example, indium oxide (In 2 O 3 ), titanium dioxide (TiO 2 ), molybdenum trioxide (MoO 3 ) and tungsten trioxide (WO 3 ) or includes at least one selected from, for example, indium oxide (In 2 O 3 ), titanium dioxide (TiO 2 ), molybdenum trioxide (MoO 3 ) and tungsten trioxide (WO 3In an embodiment, the work function adjusting layer 155 may be formed to have a thickness of about 1 nm to about 20 nm.

[0051] In embodiments, the gate electrode layer 160L may be formed using Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0052] refer to Fig.10 , an anisotropic etching process may be performed on the gate electrode layer 160L to remove a portion of the gate electrode layer 160L disposed on the bottom of each mold opening 130H and a portion of the gate electrode layer 160L disposed on the work function adjustment layer 155 within each mold opening 130H, and a portion of the gate electrode layer 160L may remain on the first sidewall 130H1 and the second sidewall 130H2 of each mold opening 130H. At the same time, a portion of the gate electrode layer 160L disposed on the upper surface of the mold insulation layer 130 may also be removed by the anisotropic etching process.

[0053] For example, the gate electrode layer 160L may be separated into two word lines WL respectively disposed on the first sidewall 130H1 and the second sidewall 130H2 of each mold opening 130H.

[0054] Although not shown, the work function adjustment layer 155 may also be etched in the above process. For example, when the portion of the gate electrode layer 160L disposed on the upper surface of the mold insulating layer 130 is removed, the portion of the work function adjustment layer 155 disposed at the bottom of each mold opening 130H and on the gate insulating layer 150 within each mold opening 130H may be removed, and a portion of the work function adjustment layer 155 may remain on the first sidewall 130H1 and the second sidewall 130H2 of each mold opening 130H. In this case, within each mold opening 130H, the upper surface of the work function adjustment layer 155 may be coplanar with the upper surface of the word line WL, and the lower surface of the work function adjustment layer 155 may be coplanar with the lower surface of the word line WL. However, the inventive concept is not limited thereto, and the work function adjustment layer 155 may not be etched during the above process but may remain.

[0055] refer to Fig.11, portions of the gate insulating layer 150 and the work function adjustment layer 155 disposed on the upper surface of the mold insulating layer 130 may be removed by an etch-back process or a planarization process. In an embodiment, the uppermost surface of the second portion 140P2 of each channel layer 140 and the uppermost surface of the vertical portion of the gate insulating layer 150 may be disposed at the same horizontal height. An insulating liner 182A and a first insulating layer 182B may be formed within one mold opening 130H. The insulating liner 182A and the first insulating layer 182B may be disposed between two adjacent word lines WL, and the insulating liner 182A may be disposed on the upper surface of the channel layer 140 and the upper surface of the mold insulating layer 130. For example, the insulating liner 182A may be disposed on the upper surface of the second portion 140P2 of each channel layer 140.

[0056] refer to Fig.12 , a portion of the insulating liner 182A disposed on the upper surface of the mold insulating layer 130 may be removed by an etch-back process or a planarization process, leaving the channel layer 140 within the mold opening 130H.

[0057] Each channel layer 140 having a U-shaped vertical cross-section may be formed within one mold opening 130H through an etch-back process or a planarization process. In addition, an upper surface of the mold insulation layer 130 may be exposed.

[0058] In an embodiment, each channel layer 140 may include a first portion 140P1 extending in a second horizontal direction (Y direction) and a second portion 140P2 connected to both ends of the first portion 140P1 and extending in a vertical direction (Z direction). A first sidewall of the second portion 140P2 may be surrounded by the gate insulating layer 150, and a second sidewall of the second portion 140P2 may be surrounded by the mold insulating layer 130. In addition, an upper surface of each channel layer 140 may be disposed at the same level as that of an upper surface of the mold insulating layer 130.

[0059] Thereafter, the upper portion of the word line WL disposed in one mold opening 130H may be removed by an etch-back process. During the etch-back process, the upper portion of the insulating liner 182A and the upper portion of the first insulating layer 182B may also be removed. During the etch-back process, a portion of the work function adjustment layer 155 may also be removed, but the inventive concept is not limited thereto. For example, when the upper portion of the insulating liner 182A and the upper portion of the first insulating layer 182B are removed, the work function adjustment layer 155 may not be removed.

[0060] Thereafter, a second insulating layer 184 may be formed to fill an entrance of each mold opening 130H. The second insulating layer 184 may be disposed on upper surfaces of the word lines WL, the insulating liner 182A, and the first insulating layer 182B, and have a flat bottom surface.

[0061] Therefore, the first cell transistor CTR1 and the second cell transistor CTR2 may be formed within one mold opening 130H. The first cell transistor CTR1 and the second cell transistor CTR2 may be arranged to have mirror symmetry with respect to each other.

[0062] refer to Fig.13 , a recess process may be performed on the upper surface of the mold insulation layer 130 to remove the upper portion of the mold insulation layer 130. As a result of the recess process, the upper surface of the mold insulation layer 130 may be disposed at a lower level than the upper surface of each channel layer 140, and the upper portion of the second sidewall of the second portion 140P2 of each channel layer 140 may be exposed to the outside of the mold insulation layer 130.

[0063] refer to Fig.14 A surface treatment process may be performed on the exposed second side wall of the second portion 140P2 of each channel layer 140 and / or the upper surface of the first portion 140P1 of each channel layer 140 to form a contact forming region (not shown), and a contact conductive layer 170L may be formed on the contact forming region, the molded insulating layer 130, and the second insulating layer 184.

[0064] In embodiments, the contact conductive layer 170L may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0065] refer to Fig.15 , a mask pattern (not shown) may be formed on the contact conductive layer 170L, a portion of the contact conductive layer 170L may be removed using the mask pattern to form the contact layer 170, and a third insulating layer 186 may be formed in the region where the contact conductive layer 170L is removed.

[0066] In an embodiment, the third insulating layer 186 may be formed using silicon nitride. In addition, the sidewalls of the contact layer 170 may be surrounded by the third insulating layer 186, and the bottom surface of the contact layer 170 may cover the contact formation region and extend onto the mold insulating layer 130.

[0067] refer to Fig.16 , an etch stop layer 188 may be formed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 may include an opening 188H, and an upper surface of the contact layer 170 may be exposed to a bottom of the opening 188H.

[0068] Thereafter, a lower electrode 192 , a capacitor dielectric layer 194 , and an upper electrode 196 may be sequentially formed on the etch stop layer 188 .

[0069] The semiconductor device 100 may be completed by performing the above-described processes.

[0070] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: substrate; a bit line extending in a first horizontal direction on the substrate; a channel layer disposed on the bit line and comprising: a first portion extending in the first horizontal direction; and a second portion connected to the first portion, comprising a first sidewall and a second sidewall opposite to the first sidewall, and extending in a vertical direction perpendicular to an upper surface of the substrate; a gate insulating layer formed to conformally cover the first portion of the channel layer on an upper surface of the first portion and to conformally cover the second portion of the channel layer on the first sidewall thereof; a work function adjustment layer, the work function adjustment layer being conformally formed on the gate insulating layer; and a word line, the word line being disposed on a sidewall of the work function adjustment layer and extending in a second horizontal direction perpendicular to the first horizontal direction, Wherein, the channel layer includes oxide semiconductor material.

2. The semiconductor device according to claim 1, wherein The work function adjusting layer includes a material having a work function of 4.9 eV or more.

3. The semiconductor device according to claim 1, wherein: The work function adjustment layer includes at least one of indium oxide, titanium dioxide, molybdenum trioxide and tungsten trioxide, and The oxide semiconductor material includes InGaZnO x .

4. The semiconductor device according to claim 1, wherein: The work function adjusting layer is formed to have a thickness of 1 nm to 20 nm.

5. The semiconductor device according to claim 1, wherein: An upper surface of the first portion of the channel layer is coplanar with a lower surface of the horizontal portion of the gate insulating layer, and An upper surface of the word line is coplanar with an upper surface of the work function adjusting layer, and a lower surface of the word line is coplanar with a lower surface of the work function adjusting layer.

6. The semiconductor device according to claim 1, wherein An uppermost surface of the second portion of the channel layer and an uppermost surface of the vertical portion of the gate insulating layer are disposed at the same level.

7. The semiconductor device according to claim 1, wherein An upper surface of the vertical portion of the work function adjusting layer is disposed at the same level as that of an upper surface of the word line.

8. The semiconductor device according to claim 1, wherein An upper surface of the gate insulating layer is disposed at a higher level than an upper surface of the word line.

9. The semiconductor device according to claim 1, further comprising: A mold insulating layer is disposed on the bit line and covers the second side wall of the channel layer.

10. The semiconductor device according to claim 1, further comprising: a conductive contact pattern connected to the second portion of the channel layer; as well as A capacitor structure is connected to the conductive contact pattern.

11. A semiconductor device, comprising: substrate; a bit line extending in a first horizontal direction on the substrate; a molded insulating layer covering the bit line on the substrate and including a molded opening; a first unit transistor disposed on a first sidewall of the mold opening; as well as a second unit transistor, the second unit transistor being disposed on a second sidewall of the mold opening, Wherein each of the first unit transistor and the second unit transistor comprises: a channel layer disposed on the bit line and comprising: a first portion extending in the first horizontal direction; and a second portion connected to the first portion and extending in a vertical direction perpendicular to an upper surface of the substrate; a work function adjustment layer, the work function adjustment layer being disposed on the first portion and the second portion of the channel layer; a gate insulating layer, the gate insulating layer being located between the channel layer and the work function adjustment layer; a word line disposed on a sidewall of the work function adjustment layer and extending in a second horizontal direction perpendicular to the first horizontal direction; and a contact disposed on the second portion of the channel layer, Wherein, the channel layer includes oxide semiconductor material.

12. The semiconductor device according to claim 11, wherein The channel layer of the first cell transistor and the channel layer of the second cell transistor have mirror-symmetrical shapes with respect to each other.

13. The semiconductor device according to claim 11, wherein The work function adjusting layer is formed to have a thickness of 1 nm to 20 nm.

14. The semiconductor device according to claim 11, wherein The work function adjusting layer includes a material having a work function of 4.9 eV or more.

15. The semiconductor device according to claim 11, wherein: The work function adjustment layer includes at least one of indium oxide, titanium dioxide, molybdenum trioxide and tungsten trioxide, and The oxide semiconductor material includes InGaZnO x .

16. The semiconductor device according to claim 11, wherein: An upper surface of the first portion of the channel layer is coplanar with a lower surface of the horizontal portion of the gate insulating layer, and An upper surface of the word line is coplanar with an upper surface of the work function adjusting layer, and a lower surface of the word line is coplanar with a lower surface of the work function adjusting layer.

17. A semiconductor device, comprising: substrate; a peripheral circuit region, the peripheral circuit region being located on the substrate; a plurality of peripheral circuits, the plurality of peripheral circuits being arranged in the peripheral circuit area; a plurality of lower conductive lines, the plurality of lower conductive lines being arranged in parallel with each other and respectively connected to the plurality of peripheral circuits; a mold insulating pattern disposed on the plurality of lower conductive lines and defining a transistor region elongated in a first horizontal direction; a plurality of channel structures arranged in a row in the first horizontal direction in the transistor region, and each of the channel structures including a vertical channel portion facing a sidewall of the mold insulation pattern; a work function adjustment layer, the work function adjustment layer having a thickness of 1 nm to 20 nm, being located in the transistor region and covering the plurality of channel structures; a gate insulating layer, the gate insulating layer being located between the plurality of channel structures and the work function adjustment layer; an upper conductive line, the upper conductive line being disposed on the plurality of channel structures in the transistor region, having a sidewall facing the vertical channel portion of each of the plurality of channel structures, and extending in a second horizontal direction perpendicular to the first horizontal direction; as well as a plurality of conductive contact patterns, the plurality of conductive contact patterns being respectively connected to the vertical channel portions of the plurality of channel structures, wherein each of the plurality of channel structures comprises an oxide semiconductor material, and Wherein, the work function adjustment layer includes a material having a work function of 4.9 eV or greater.

18. The semiconductor device according to claim 17, wherein: The transistor region includes a plurality of transistors, and the plurality of transistors include the plurality of channel structures, The plurality of transistors include two transistors facing each other in the first horizontal direction, and The two transistors share one channel structure selected from the plurality of channel structures.

19. The semiconductor device according to claim 17, wherein: The uppermost surface of the upper conductive line is closer to the substrate than the uppermost surface of the gate insulating layer, and An upper surface of a horizontal portion of one of the plurality of channel structures is coplanar with a lower surface of a horizontal portion of the gate insulating layer.

20. The semiconductor device according to claim 17, wherein The work function adjustment layer includes at least one of indium oxide, titanium dioxide, molybdenum trioxide and tungsten trioxide, and Wherein, the oxide semiconductor material includes InGaZnO x .

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