Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: forming a stack by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack; forming a cap layer by exposing an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the edges of the cap layer and the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element coupled to the third layer pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0106199, filed on August 14, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor devices, and more particularly, to semiconductor devices including three-dimensional memory cells, and methods for manufacturing the semiconductor devices. Background Art

[0004] Recently, in order to cope with demands for large capacity and miniaturization of memory devices, a technology for providing a 3D memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack by sequentially forming a first layer, a second layer, a third layer, a fourth layer and a fifth layer on a lower structure; forming an opening in the stack; forming a capping layer by horizontally recessing the second layer and the fourth layer from the opening to expose an edge of the third layer; forming a pad structure on the edges of the capping layer and the third layer; forming a sacrificial pad material on the pad structure; recessing the sacrificial pad material and the pad structure to expose an edge of the third layer; forming a third layer pattern by recessing the exposed edge of the third layer; and forming a data storage element coupled to the third layer pattern.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack by sequentially forming a first layer, a second layer, a third layer, a fourth layer and a fifth layer on a lower structure; forming a first opening in the stack; replacing a portion of the second layer and a portion of the fourth layer with a horizontal conductive line through the first opening; forming a vertical conductive line when filling the first opening, the vertical conductive line coupled to a first edge of the third layer; forming a second opening in the stack; forming a capping layer by horizontally recessing the second layer and the fourth layer from the second opening to expose a second edge of the third layer; forming a pad structure over the capping layer and the second edge of the third layer; forming a sacrificial pad material over the pad structure; recessing the sacrificial pad material and the pad structure to expose the second edge of the third layer; forming a third layer pattern by recessing the exposed second edge of the third layer; and forming a data storage element coupled to the third layer pattern.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a cell isolation layer, which is vertically oriented in a first direction; a horizontal layer, which is horizontally oriented in a second direction intersecting the first direction and vertically stacked between the cell isolation layers in the first direction; a vertical wire, which is vertically oriented in the first direction and coupled to a first edge of the horizontal layer; a horizontal wire, which crosses each horizontal layer in a third direction intersecting the first direction and the second direction; and a data storage element, which is respectively coupled to the second edge of the horizontal layer. The semiconductor device may also include a cap layer between the data storage element and the horizontal wire; and a pad layer between the cap layer and the data storage element. The pad layer may include: a first pad layer, which is disposed on the upper surface and the lower surface of the second edge of the horizontal layer; a second pad layer, which is disposed between the cap layer and the data storage element above the first pad layer; and a third pad layer, which is disposed inside the second pad layer. Each data storage element may include a first electrode stacked in the first direction, a dielectric layer above the first electrode, and a second electrode above the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0010] Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in .

[0011] Figure 2 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0012] Figures 3 to 18 An example of a method for manufacturing a semiconductor device according to another embodiment of the present invention is shown.

[0013] Fig.19A is a schematic perspective view showing a storage unit according to another embodiment of the present invention.

[0014] Fig.19B It is shown Fig.19A Schematic cross-sectional view of a memory cell shown in .

[0015] Fig.19C It is shown Fig.19A A plan view of the switching element shown.

[0016] Fig. 20 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention.

[0017] Fig.21 It is shown Fig. 20 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown in FIG.

[0018] Fig. 22 is along Fig. 20 A cross-sectional view taken along line AA' in FIG. DETAILED DESCRIPTION

[0019] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to convey the scope of the present invention to those skilled in the art. Throughout the disclosure, the same reference numerals in the multiple drawings and embodiments of the present invention refer to the same parts.

[0020] The drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first and second layers or between the substrates.

[0021] The following embodiments of the present invention relate to three-dimensional memory cells, and memory cells can be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0022] Figure 1A is a schematic perspective view showing a storage unit according to another embodiment of the present invention. Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in .

[0023] refer to Figure 1A and Figure 1B , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0024] The first wire BL may be vertically oriented in the first direction D1. The first wire BL may include a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0025] The switching element TR may have a function of controlling the voltage (or current) supply to the data storage element AP in the data write operation and the data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0026] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in a first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in a second horizontal direction (e.g., the third direction D3).

[0027] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include one or more of polycrystalline silicon, single crystal silicon, germanium, or silicon germanium or a combination thereof. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0028] The upper surface and the lower surface of the horizontal layer HL may have flat surfaces. In other words, the upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0029] The horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0030] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as a first source / drain region and a second source / drain electrode region.

[0031] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first conductive line BL.

[0032] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other, with a horizontal layer HL interposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed above the horizontal layer HL, and the lower horizontal wire G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair and may be coupled to one memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire. In this case, one of the upper horizontal wire G1 and the lower horizontal wire G2 may be used as a back gate or a shielding gate.

[0033] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of, for example, about 4.5 eV or less, while the P-type work function material may have a high work function of, for example, about 4.5 eV or greater. The second wire DWL may include a stack of a low work function material and a high work function material.

[0034] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include one or more of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0035] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally arranged from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN, which extends horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be arranged in the inner space of the first electrode SN on the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0036] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a 3D structure, and the first electrode SN of the 3D structure may have a horizontal 3D structure oriented in the second direction D2. As an example of a 3D structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0037] According to another embodiment of the present invention, the first electrode SN may have a columnar shape or a cylindrical barrel shape. The cylindrical barrel shape refers to a structure in which a columnar shape and a cylindrical shape are combined.

[0038] The first electrode SN and the second electrode PN may include one or more of a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, and titanium nitride (TiN) may be used as a second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0039] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include one or more of silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3), or a combination thereof. According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer including two or more layers of the above-mentioned high-k materials.

[0040] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacking structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide (ZrO2)-based layer. According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacking structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide are stacked in sequence. The HA stack and the HAH stack may be referred to as hafnium oxide (HfO2) based layers. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a dielectric constant lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material, the band gap energy of the high-band gap material being greater than the band gap energy of the high-k material. The dielectric layer DE may include silicon oxide (SiO2) as a high-band gap material instead of aluminum oxide (Al2O3). Since the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacking structure in which high-k materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacking structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0041] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material, and may include a stacked structure in which multiple high-k materials and multiple high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0042] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0043] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0044] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include one or more of titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0045] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0046] For example, the memory cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced by an anode wire. Therefore, the horizontal layer HL may include four semiconductor layers stacked horizontally in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a relatively large amount of current flows or a low conductance state in which a relatively small amount of current flows or no current flows. Each memory cell MC may have a "1" state or a "0" state based on the high conductance state and the low conductance state of the thyristor, respectively.

[0047] Return to reference Figure 1B , the first capping layer BC may be disposed between the first wire BL and the second wire DWL. The second capping layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first capping layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first capping layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second capping layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP.

[0048] The first cap layer BC and the second cap layer CC may include a dielectric material. The first cap layer BC and the second cap layer CC may include one or more of silicon oxide, silicon nitride, silicon oxycarbide, an air gap, or a combination thereof. The first cap layer BC may include silicon oxide, and the second cap layer CC may include a stack of silicon oxide and silicon nitride.

[0049] A plurality of pad layers L1, L2, and L3 may be disposed between the first electrode SN of the data storage element and the second cap layer CC. The pad layers L1, L2, and L3 may include a first pad layer L1, a second pad layer L2, and a third pad layer L3. The first pad layer L1 may be disposed on the upper and lower surfaces of the edge of the horizontal layer HL. The second pad layer L2 may contact the second cap layer CC, and the third pad layer L3 may be disposed in the second pad layer L2. The first pad layer L1 and the second pad layer L2 may include silicon oxide, and the third pad layer L3 may include silicon nitride.

[0050] Figure 2 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0051] refer to Figure 2 , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. Each memory cell MC may be used with Figure 1A and Figure 1B Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0052] In the following, reference will be made to Figure 1A , Figure 1B and Figure 2 The semiconductor device 100 will be described.

[0053] The memory cell array MCA may include a three-dimensional array of memory cells MC. The 3D array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may include a plurality of memory cells MC horizontally arranged in a second direction D2. The memory cell array MCA may have a mirror-type structure in which two memory cells MC share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 100 may also include a mirror-type memory cell array in which two memory cells MC share a second electrode PN of a data storage element CAP.

[0054] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer.

[0055] The memory cell array MCA may be disposed on the lower structure LS.

[0056] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0057] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second wire DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0058] The first capping layer BC may be disposed between the second wire DWL and the first wire BL. The second capping layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first capping layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first capping layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second capping layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first capping layers BC and a pair of second capping layers CC.

[0059] The first cap layer BC and the second cap layer CC may include a dielectric material. The first cap layer BC and the second cap layer CC may include one or more of silicon oxide, silicon nitride, silicon oxycarbide, an air gap, or a combination thereof. The first cap layer BC may include silicon oxide, and the second cap layer CC may include a stack of silicon oxide and silicon nitride. According to another embodiment of the present invention, the first cap layer BC may include a stack of silicon oxide and silicon nitride.

[0060] A plurality of pad layers L1, L2, and L3 may be disposed between the first electrode SN of the data storage element and the second cap layer CC. The pad layers L1, L2, and L3 may include a first pad layer L1, a second pad layer L2, and a third pad layer L3. The first pad layer L1 may be disposed on the surface (ie, the upper surface and the lower surface) of the edge of the horizontal layer HL.

[0061] The second liner layer L2 may contact the second capping layer CC, and the third liner layer L3 may be disposed in the second liner layer L2.

[0062] The first and second liner layers L1 and L2 may include silicon oxide, and the third liner layer L3 may include silicon nitride.

[0063] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0064] The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0065] The lower structure LS may include a semiconductor substrate, a metal interconnection structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit unit.

[0066] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnection structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be coupled by wafer bonding.

[0067] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may be referred to as a peripheral upper unit (COP) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc.

[0068] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The second conductive line DWL may be coupled to the sub word line driver. The first conductive line BL may be coupled to the sense amplifier.

[0069] According to another embodiment of the present invention, the peripheral circuit unit may be arranged at a higher level than the memory cell array MCA. This may be referred to as a periphery on cell (POC) structure. The lower structure LS may include a first semiconductor substrate, and the peripheral circuit unit may include a second semiconductor substrate.

[0070] According to another embodiment of the present invention, the memory cell array MCA may include one or more of dynamic random access memory (DRAM), embedded DRAM, NAND memory, ferroelectric RAM (FeRAM), spin transfer torque RAM (STTRAM), phase change RAM (PCRAM) or resistive RAM (ReRAM).

[0071] Figures 3 to 18 An example of a method for manufacturing a semiconductor device according to various embodiments of the present invention is shown.

[0072] refer to Figure 3 , the stack SB may be formed on the lower structure 11. The lower structure 11 may be a material suitable for semiconductor processing. The lower structure 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. A variety of materials may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a silicon-containing material. The lower structure 11 may include one or more of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials such as germanium. The lower structure 11 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate. According to another embodiment of the present invention, the lower structure 11 may include one or more of a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory or a peripheral circuit unit.

[0073] For example, the lower structure 11 may include a structure in which a peripheral circuit unit, a metal interconnect structure, and a bonding pad structure are sequentially stacked. The peripheral circuit unit may include at least one or more control circuits. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc. For example, the peripheral circuit unit may include a sub-word line driver and a sense amplifier.

[0074] In the stack SB, a plurality of sub-stacks may be alternately stacked. The formation of an individual sub-stack may include sequentially stacking a first layer 12, a second layer 13, a third layer 14, a fourth layer 15, and a fifth layer 12. The third layer 14 may be referred to as a preliminary horizontal layer 14, and the second layer 13 may be referred to as a first sacrificial layer 13. The fourth layer 15 may be referred to as a second sacrificial layer 15, and the first layer 12 and the fifth layer 12 may be referred to as an inter-cell dielectric layer 12. Therefore, each sub-stack may include an inter-cell dielectric layer 12, a first sacrificial layer 13, a second sacrificial layer 15, and a preliminary horizontal layer 14. The preliminary horizontal layer 14 may be disposed between the inter-cell dielectric layers 12, and the first sacrificial layer 13 may be disposed between the lower inter-cell dielectric layer 12 and the preliminary horizontal layer 14. The second sacrificial layer 15 may be disposed between the upper inter-cell dielectric layer 12 and the preliminary horizontal layer 14. The inter-cell dielectric layer 12 may include silicon oxide, and the first sacrificial layer 13 and the second sacrificial layer 15 may include silicon nitride. The preliminary horizontal layer 14 may include a single crystal silicon layer, a polycrystalline silicon layer, or an oxide semiconductor layer. Among the inter-cell dielectric layers 12, the lower inter-cell dielectric layer 12 may be referred to as a first layer, and the upper inter-cell dielectric layer 12 may be referred to as a fifth layer.

[0075] refer to Figure 4 , the first opening 16 may be formed by etching a portion of the stacked body SB.

[0076] Subsequently, the first sacrificial layer 13 and the second sacrificial layer 15 may be horizontally recessed from the first opening 16. As a result, a first sacrificial level recess 17 may be formed. A portion of the preliminary horizontal layer 14 may be exposed by the first sacrificial level recess 17. In order to recess the first sacrificial layer 13 and the second sacrificial layer 15, a wet etching process or a dry etching process may be used. The first opening 16 may be a hole-type opening.

[0077] refer to Figure 5 , an interlayer dielectric layer 18 may be formed on the exposed portion of the preliminary horizontal layer 14. The interlayer dielectric layer 18 may be formed by oxidizing the surface of the preliminary horizontal layer 14. According to another embodiment of the present invention, the interlayer dielectric layer 18 may be formed by a deposition process of silicon oxide.

[0078] The interlayer dielectric layer 18 may be formed of one or more of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 18 may include one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON or a combination thereof.

[0079] Subsequently, a horizontal conductor 19 filling the first sacrificial level recess 17 may be formed on the interlayer dielectric layer 18. Forming the horizontal conductor 19 may include depositing a conductive material filling the first sacrificial level recess 17 on the interlayer dielectric layer 18 and performing an etch-back process on the conductive material. The horizontal conductor 19 may include a pair of first horizontal conductors 19A and second horizontal conductors 19B facing each other, with the preliminary horizontal layer 14 interposed therebetween. The first horizontal conductor 19A and the second horizontal conductor 19B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductor 19A and the second horizontal conductor 19B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductor 19A and the second horizontal conductor 19B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductor 19A and the second horizontal conductor 19B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of, for example, about 4.5 eV or less, and the P-type work function material may have a high work function of, for example, about 4.5 eV or more. The horizontal conductor 19 may correspond to Figure 1A , Figure 1B and Figure 2 , and the first horizontal wire 19A and the second horizontal wire 19B may correspond to the upper horizontal line G1 and the lower horizontal line G2.

[0080] refer to Figure 6 , a first capping layer 20 may be formed on one side surface of the horizontal conductive line 19. The first capping layer 20 may include silicon oxide, silicon nitride, or a combination thereof. A capping material may be deposited and etched back to form the first capping layer 20. When or after forming the first capping layer 20, a portion of the interlayer dielectric layer 18 may be removed to expose a first edge portion of each preliminary horizontal layer 14. The first capping layer 20 may correspond to Figure 1A , Figure 1B and Figure 2 The first cover layer BC shown in FIG.

[0081] Then, if Figure 6 As shown, a vertical conductive line 21 coupled to a first edge portion of each preliminary horizontal layer 14 may be formed. The vertical conductive line 21 may fill the first opening 16. The vertical conductive line 21 may be commonly coupled to the preliminary horizontal layer 14. The vertical conductive line 21 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive line 21 may include a bit line. The vertical conductive line 21 may correspond to Figure 1A , Figure 1B and Figure 2 The first wire BL is shown in FIG.

[0082] refer to Figure 7 , the second opening 22 may be formed by etching another portion of the stacked body SB. The second opening 22 may be a hole-type opening.

[0083] Subsequently, the first sacrificial layer 13 and the second sacrificial layer 15 may be horizontally recessed from the second opening 22. As a result, second sacrificial level recesses 13R and 15R may be formed.

[0084] After forming the second sacrificial level recesses 13R and 15R, the remaining first and second sacrificial layers 13 and 15 may become second capping layers 13S and 15S.

[0085] refer to Figure 8 , a first liner material 23A may be formed on the exposed surface of the preliminary horizontal layer 14. The first liner material 23A may be formed by an oxidation process. The vertical thickness of the second edge portion of the preliminary horizontal layer 14 may be reduced by the first liner material 23A. The first liner material 23A may include silicon oxide.

[0086] refer to Fig. 9 , the second liner material 24A and the sacrificial liner material 25A may be sequentially formed on the first liner material 23A. The second liner material 24A and the sacrificial liner material 25A may be formed by a deposition process such as chemical vapor deposition (CVD). The second liner material 24A may include silicon oxide, and the sacrificial liner material 25A may include silicon nitride. The sacrificial liner material 25A may include a gap 25S or a void. The first liner material 23A and the second liner material 24A may be referred to as a liner structure.

[0087] refer to Fig.10 , the sacrificial liner material 25A may be selectively recessed. Subsequently, the second liner material 24A and the first liner material 23A may be selectively recessed. As a result, the first liner layer 23, the second liner layer 24, and the sacrificial liner layer 25 may be formed. The sacrificial liner layer 25 may include a slit 25S. The slit 25S of the sacrificial liner material 25A may not be exposed to the recessing process.

[0088] The second edge of the preliminary horizontal layer 14 may be exposed or protruded by a recess process of the liner material. The first liner layer 23 , the second liner layer 24 , and the sacrificial liner layer 25 may be disposed between the inter-cell dielectric layer 12 and the preliminary horizontal layer 14 .

[0089] The second liner layer 24 may cover the upper and lower surfaces of the inter-cell dielectric layer 12 (refer to reference numeral '12A'). That is, when the sacrificial liner layer 25 is formed, the upper and lower surfaces of the inter-cell dielectric layer 12 may be prevented from being lost.

[0090] refer to Fig.11, a sacrificial cover layer 26 may be formed to cover the upper and lower surfaces of the second edge of the preliminary horizontal layer 14. Forming the sacrificial cover layer 26 may include deposition and etching of silicon nitride. The sacrificial cover layer 26 may cover the first liner layer 23 and the second liner layer 24, and may expose the sacrificial liner layer 25. The sacrificial cover layer 26 may not include a gap. The sacrificial cover layer 26 may be referred to as a pocket layer. The sacrificial cover layer 26 may include a silicon nitride pocket layer.

[0091] refer to Fig.12 , the second edge of the preliminary horizontal layer 14 may be selectively recessed horizontally. In the recessing process of the preliminary horizontal layer 14, the sacrificial capping layer 26 may be used as an etching barrier. As a result, a horizontal layer HL having a short horizontal length may be formed. The horizontal layer HL may be Figure 3 The pattern of the third layer 14 is shown (referred to as a third layer pattern). After forming the horizontal layer HL, the sacrificial liner layer 25 having the slits 25S may be exposed.

[0092] After the recess process for forming the horizontal layer HL is performed, the first liner layer 23 and the second liner layer 24 may be partially etched. As a result, the preliminary storage opening 27 may be formed. The first liner layer 23 may cover the upper and lower surfaces of the second edge of the horizontal layer HL. The second liner layer 24 may partially cover the sacrificial liner layer 25.

[0093] refer to Fig.13 , the sacrificial cover layer 26 and the sacrificial liner layer 25 may be removed to expose the second liner layer 24. As the sacrificial cover layer 26 and the sacrificial liner layer 25 are removed, a storage opening 29A may be formed between the inter-cell dielectric layers 12. The storage opening 29A may be defined by an extension of the preliminary storage opening 27. The first liner layer 23 may cover the upper and lower surfaces of the second edge of the horizontal layer HL, and the side surface of the second edge of the horizontal layer HL may be exposed through the storage opening 29A. The second liner layer 24 may remain inside each storage opening 29A.

[0094] As described above, the sacrificial liner layer 25 having the slit 25S may be removed through the full recess process.

[0095] refer to Fig.14 , an additional liner material, such as a third liner material, may be formed on the second edge side of the second liner layer 24, the first liner layer 23, and the horizontal layer HL. The third liner material 28A may include silicon nitride. The third liner material 28A may be conformally formed on the surface of the storage opening 29A. The third liner material 28A may not include a gap.

[0096] After the sacrificial liner layer 25 having the slit 25S is removed through a series of processes as described above, a third liner material 28A without a gap may be formed.

[0097] refer to Fig.15 , a third liner layer 28 may be formed by etching back the third liner material 28A. The third liner layer 28 may fill the inner surface of the second liner layer 24. The volume of the storage opening indicated by reference numeral '29B' may be reduced due to the third liner layer 28. The storage opening 29B may be referred to as a capacitor opening. The first liner layer 23 may cover the upper and lower surfaces of the second edge of the horizontal layer HL, and the side surface of the second edge of the horizontal layer HL may be exposed through the storage opening 29B.

[0098] The first and second liner layers 23 and 24 may include silicon oxide, and the third liner layer 28 may include silicon nitride.

[0099] As described above, after forming the third liner layer 28, the second liner layer 24 may cover the upper and lower surfaces of the inter-cell dielectric layer 12 (refer to reference numeral '12A'). The upper and lower surfaces of the inter-cell dielectric layer 12 may be prevented from being lost by the third liner layer 28. As a result, since thinning of the inter-cell dielectric layer 12 is prevented or reduced, a space where a second electrode is to be formed in a subsequent process may be ensured to be sufficiently wide.

[0100] refer to Figures 7 to 15 The series of processes shown may be performed in sequence as follows: forming the second sacrificial level recesses 13R and 15R, sequentially forming the first liner material 23A, the second liner material 24A, and the sacrificial liner material 25A, recessing the sacrificial liner material 25A to form a sacrificial liner layer 25, recessing the first liner material 23A and the second liner material 24A to form the first liner layer 23 and the second liner layer 24, forming the sacrificial capping layer 26, recessing the preliminary horizontal layer 14, removing the sacrificial liner layer 25, and forming the third liner material 28A. This series of processes may be referred to as a "channel-later recess scheme".

[0101] As a comparative example, the channel pre-recessing scheme may include sequentially performing the following after horizontally recessing the preliminary horizontal layer 14: forming second sacrificial level recesses 13R and 15R, sequentially forming a first liner material 23A, a second liner material 24A, and a third liner material 28A, recessing the third liner material 28A, and recessing the first liner material 23A and the second liner material 24A. In the channel recessing pre-recessing scheme similar to the comparative example, thinning of the inter-cell dielectric layer 12 may occur during the recessing of the first liner material 23A and the second liner material 24A, and therefore, in a subsequent process, a space where the second electrode will be formed may be insufficient.

[0102] refer to Fig.16, a first electrode 29 of the data storage element may be formed on a side surface of the second edge of the horizontal layer HL. The first electrode 29 may be formed in the storage opening 29B. The first electrode 29 may have a horizontally oriented cylindrical shape.

[0103] refer to Fig.17 The inter-cell dielectric layer-level recess 30 exposing the outer wall of the first electrode 29 may be formed by horizontally recessing the inter-cell dielectric layer 12 and the second liner layer 24. The recessed inter-cell dielectric layer 12 may correspond to Figure 2 The inter-cell dielectric layer IL is shown.

[0104] refer to Fig.18 , a dielectric layer 31 and a second electrode 32 may be sequentially formed on the first electrode 29. The first electrode 29, the dielectric layer 31 and the second electrode 32 may become a data storage element CAP.

[0105] Return to reference Fig.17 and Fig.18 , the inter-cell dielectric layer-level recess 30 may have a vertical height 12B. The vertical height 12B may be the interval between vertically adjacent first electrodes 29. In this way, the vertical height 12B of the inter-cell dielectric layer-level recess 30 can provide a sufficiently wide space in which a subsequent dielectric layer 31 and a second electrode 32 will be formed.

[0106] In a comparative example such as the channel pre-recess scheme, the gap between the first electrodes 29 may be narrowed due to the thinning of the inter-cell dielectric layer 12, and thus the vertical height 12B of the inter-cell dielectric level recess 30 may be reduced. As a result, after forming the dielectric layer 31 in the inter-cell dielectric level recess 30, the space where the second electrode 32 is to be formed may be insufficient.

[0107] Return to reference Fig.18 , each first electrode 29 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 29 may include a plurality of inner surfaces. The outer surface of the first electrode 29 may include a vertical outer surface and a plurality of horizontal outer surfaces. The inner space of the first electrode 29 may be a three-dimensional space. The dielectric layer 31 may conformally cover the inner and outer surfaces of the first electrode 29. The second electrode 32 may be disposed in the inner space of the first electrode 29 on the dielectric layer 31.

[0108] The first electrode 29 may have a cylindrical shape. The cylindrical shape of the first electrode 29 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surface of the first electrode 29 may be electrically connected to the horizontal layer HL. The dielectric layer 31 and the second electrode 32 may be disposed on the cylindrical inner surface of the first electrode 29.

[0109] The first electrode 29 and the second electrode 32 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 29 and the second electrode 32 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. One or more. The second electrode 32 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 32 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inner space of the first electrode 29, and titanium nitride (TiN) may be used as the second electrode 32 of the data storage element CAP, while tungsten nitride may be a low resistance material.

[0110] The dielectric layer 31 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 31 may include one or more of silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The high-k material of the dielectric layer 31 may include one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanium oxide (SrTiO3) or a combination thereof. The dielectric layer 31 may include one or more of a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O2 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack or a combination thereof.

[0111] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode 29 and the dielectric layer 31. The interface control layer may include one or more of titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode 32 and the dielectric layer 31.

[0112] Since the third liner material 28A is Figures 3 to 18 The sacrificial liner material 25A having the gap 25S therein is re-deposited after being completely recessed, so that a third liner layer 28 without a gap can be formed. Therefore, thinning of the inter-cell dielectric layer 12 can be prevented or reduced. Since the thinning of the inter-cell dielectric layer 12 is prevented, sufficient space for forming the second electrode 32 can be ensured. As a result, the capacitance of the data storage element CAP can be increased.

[0113] Fig.19A is a schematic perspective view showing a storage unit according to another embodiment of the present invention. Fig.19B It is shown Fig.19A Schematic cross-sectional view of a memory cell shown in FIG. Fig.19C It is shown Fig.19A A plan view of the switching element shown. Fig.19A and 19B The memory cell MC1 can be similar to Figure 1A and 1B In the following, regarding the memory cell MC that also appears Figure 1A and Figure 1B For a detailed description of the components in Figure 1A and Figure 1B .

[0114] refer to FIG. 19A to FIG. 19C , the memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0115] The first wire BL may be vertically oriented in the first direction D1. The first wire BL may include a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include one or more of polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0116] The switching element TR may have a function of controlling the voltage (or current) supply to the data storage element CAP in the data write operation and the data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0117] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in a first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in a second horizontal direction (e.g., the third direction D3).

[0118] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include one or more of polycrystalline silicon, single crystal silicon, germanium, or silicon germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0119] The upper surface and the lower surface of the horizontal layer HL may have flat surfaces. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0120] The horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0121] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as a first source / drain region and a second source / drain region.

[0122] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first conductive line BL.

[0123] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other, with a horizontal layer HL interposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed above the horizontal layer HL, and the lower horizontal wire G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair and may be coupled to one memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire. In this case, one of the upper horizontal wire G1 and the lower horizontal wire G2 may be used as a back gate or a shielding gate.

[0124] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of, for example, about 4.5 eV or less, while the P-type work function material may have a high work function of, for example, about 4.5 eV or greater. The second wire DWL may include a stack of a low work function material and a high work function material.

[0125] Each of the upper horizontal line G1 and the lower horizontal line G2 may have a varying width in the second direction D2. For example, the width of the upper horizontal line G1 and the lower horizontal line G2 may be greater at an overlapping portion where the upper horizontal line G1 and the lower horizontal line G2 overlap the horizontal layer HL than at a non-overlapping portion where the upper horizontal line G1 and the lower horizontal line G2 do not overlap the horizontal layer HL. Due to the difference in width, the sidewall of the second conductive line DWL extending in the third direction D3 may have a notch-shaped sidewall.

[0126] Return to reference Fig.19C , the second conductive line DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlap portion NOL may refer to a portion not overlapping with the horizontal layer HL. The channel overlap portion WLP may have a cross shape or an orthogonal shape. According to another embodiment of the present invention, the side surface of the channel overlap portion WLP may have a curved shape or a rounded shape.

[0127] The channel CH and the channel overlap portion WLP of the second conductive line DWL may overlap each other. The channel CH may have a cross shape or an orthogonal shape. The size of the channel overlap portion WLP of the second conductive line DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0128] From the perspective of a top view, the horizontal layer HL may have a cross shape or an orthogonal shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0129] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include one or more of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include one or more of SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0130] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN extending horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN on the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The second electrode PN may be coupled to the common plate PL.

[0131] The first capping layer BC may be disposed between the first wire BL and the second wire DWL. The second capping layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first capping layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first capping layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second capping layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP.

[0132] The first cap layer BC and the second cap layer CC may include a dielectric material. The first cap layer BC and the second cap layer CC may include one or more of silicon oxide, silicon nitride, silicon oxycarbide, an air gap, or a combination thereof. The first cap layer BC may include silicon oxide, and the second cap layer CC may include a stack of silicon oxide and silicon nitride.

[0133] A plurality of pad layers L1, L2, and L3 may be disposed between the first electrode SN of the data storage element and the second cap layer CC. The pad layers L1, L2, and L3 may include a first pad layer L1, a second pad layer L2, and a third pad layer L3. The first pad layer L1 may be disposed on the upper and lower surfaces of the edge of the horizontal layer HL. The second pad layer L2 may contact the second cap layer CC, and the third pad layer L3 may be disposed in the second pad layer L2. The first pad layer L1 and the second pad layer L2 may include silicon oxide, and the third pad layer L3 may include silicon nitride.

[0134] Fig. 20 is a schematic plan view showing a semiconductor device according to another embodiment of the present invention. Fig.21 It is shown Fig. 20 Schematic three-dimensional diagram of a first memory cell array MCA1. Fig. 22 is along Fig. 20 A cross-sectional view taken along line AA' in FIG.

[0135] refer to Fig. 20 , Fig.21 and Fig. 22 , the semiconductor device 200 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC1. For individual memory cells MC1, reference may be made to Fig.19A and Fig.19B Each memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0136] The memory cell array MCA may include a three-dimensional array of memory cells MC1. The 3D array of memory cells MC1 may include a column array of memory cells MC1 and a row array of memory cells MC1. The column array of memory cells MC1 may include a plurality of memory cells MC1 stacked in a first direction D1, and the row array of memory cells MC1 may include a plurality of memory cells MC1 horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include sub-memory cell arrays MCA1 adjacent to each other in the second direction D2. The sub-memory cell arrays MCA1 may have a mirror-type structure in which two memory cells MC1 share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 200 may further include a sub-memory cell array having a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which memory cells MC1 are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 horizontally arranged in the third direction D3.

[0137] According to another embodiment of the present invention, in the memory cell array MCA, a plurality of sub-memory cell arrays MCA1 may be arranged in the second direction D2. For example, the data storage element CAP, the switch element TR, the first wire BL and the switch element TR may be alternately arranged in the second direction D2 in the above order.

[0138] The inter-cell dielectric layer IL may be disposed between the memory cells MC1 stacked along the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer.

[0139] The cell isolation layers ISOA and ISOB may be disposed between the memory cells MC1 adjacent to each other in the third direction D3. The cell isolation layers ISOA and ISOB may be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include one or more of silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a columnar structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB may include a stack of a cell isolation liner layer and a cell isolation gap-filling layer. The cell isolation liner layer may include silicon oxide, and the cell isolation gap-filling layer may include silicon oxycarbide.

[0140] The memory cell array MCA may be disposed on the lower structure LS.

[0141] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0142] like Fig.19C As shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or an orthogonal shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portion WLP and the channel non-overlap portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notch-shaped sidewall.

[0143] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second wire DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0144] From the perspective of a top view, the horizontal layer HL may have a cross shape or an orthogonal shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a circular shape. Fig.19B and Fig.19C , the horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP.

[0145] The first capping layer BC may be disposed between the second wire DWL and the first wire BL. The second capping layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first capping layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first capping layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second capping layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second capping layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first capping layers BC and a pair of second capping layers CC.

[0146] The first cap layer BC and the second cap layer CC may include a dielectric material. The first cap layer BC and the second cap layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cap layer BC may include silicon oxide, and the second cap layer CC may include a stack of silicon oxide and silicon nitride. According to another embodiment of the present invention, the first cap layer BC may include a stack of silicon oxide and silicon nitride.

[0147] A plurality of pad layers L1, L2, and L3 may be disposed between the first electrode SN of the data storage element and the second cap layer CC. The pad layers L1, L2, and L3 may include a first pad layer L1, a second pad layer L2, and a third pad layer L3. The first pad layer L1 may be disposed on the upper and lower surfaces of the edge of the horizontal layer HL. The second pad layer L2 may contact the second cap layer CC, and the third pad layer L3 may be disposed in the second pad layer L2. The first pad layer L1 and the second pad layer L2 may include silicon oxide, and the third pad layer L3 may include silicon nitride.

[0148] The memory cell MC1 may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include one or more of titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BL and the second contact node SNC, respectively.

[0149] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0150] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP in the third direction D3. The first electrodes SN may be isolated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0151] The lower structure LS may include one or more of a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit unit.

[0152] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnection structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be coupled by wafer bonding.

[0153] The peripheral circuit unit of the lower structure LS can be set at a level lower than the memory cell array MCA. This can be referred to as the above-mentioned COP structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc.

[0154] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The second conductive line DWL may be coupled to the sub word line driver. The first conductive line BL may be coupled to the sense amplifier.

[0155] According to another embodiment of the present invention, the peripheral circuit unit may be arranged at a higher level than the memory cell array MCA. This may be referred to as the above-mentioned POC structure. In this case, the lower structure LS may include a first semiconductor substrate, and the peripheral circuit unit may include a second semiconductor substrate.

[0156] According to another embodiment of the present invention, the memory cell array MCA may include one or more of dynamic random access memory (DRAM), embedded DRAM, NAND memory, ferroelectric RAM (FeRAM), spin transfer torque RAM (STTRAM), phase change RAM (PCRAM) or resistive RAM (ReRAM).

[0157] According to an embodiment of the present invention, the capacitance of a data storage element can be increased by preventing an inter-cell dielectric layer from being thinned.

[0158] According to the embodiments of the present invention, the yield of 3D memory cells can be improved.

[0159] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention disclosed herein. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stack by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer on the lower structure; forming an opening in the stack; forming a capping layer by horizontally recessing the second layer and the fourth layer from the opening to expose an edge of the third layer; forming a liner structure on edges of the cover layer and the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; as well as A data storage element coupled to the third layer pattern is formed.

2. The method according to claim 1, further comprising: Before forming the third layer pattern, An additional liner material is formed covering the recessed sacrificial liner material and the recessed liner structure.

3. The method according to claim 1, wherein: Forming the pad structure includes: forming a first liner material on an edge of the third layer by an oxidation process; and A second liner material is conformally deposited over the first liner material.

4. The method according to claim 1, wherein: The pad structure includes silicon oxide.

5. The method according to claim 1, wherein: The sacrificial liner material includes silicon nitride.

6. The method according to claim 1, wherein: Forming the data storage element includes: forming a first electrode coupled to the third layer pattern; exposing an outer wall of the first electrode by selectively recessing a portion of the first layer, the fifth layer, and the pad structure; forming a dielectric layer over the first electrode; and A second electrode is formed over the dielectric layer.

7. The method according to claim 1, wherein: The data storage element includes a capacitor.

8. The method according to claim 1, wherein: The third layer includes a semiconductor material or an oxide semiconductor material.

9. The method according to claim 1, wherein: The third layer includes a single crystal silicon layer.

10. The method according to claim 1, wherein: The first layer and the fifth layer include silicon oxide, and the second layer and the fourth layer include silicon nitride.

11. A method for manufacturing a semiconductor device, the method comprising: forming a stack by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer on the lower structure; forming a first opening in the stack; replacing a portion of the second layer and a portion of the fourth layer with a horizontal conductive line through the first opening; forming a vertical conductive line when filling the first opening, the vertical conductive line being coupled to a first edge of the third layer; forming a second opening in the stack; forming a capping layer by horizontally recessing the second layer and the fourth layer from the second opening to expose a second edge of the third layer; forming a liner structure over the cover layer and the second edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose a second edge of the third layer; forming a third layer pattern by recessing an exposed second edge of the third layer; as well as A data storage element coupled to the third layer pattern is formed.

12. The method according to claim 11, further comprising: Before forming the third layer pattern, An additional liner material is formed covering the recessed sacrificial liner material and the recessed liner structure.

13. The method according to claim 11, wherein: Forming the pad structure includes: forming a first liner material over the second edge of the third layer by an oxidation process; and A second liner material is conformally deposited over the first liner material.

14. The method according to claim 11, wherein: The pad structure includes silicon oxide.

15. The method according to claim 11, wherein: The sacrificial liner material includes silicon nitride.

16. The method according to claim 11, wherein: Forming the data storage element includes: forming a first electrode coupled to the third layer pattern; exposing an outer wall of the first electrode by selectively recessing a portion of the first layer, the fifth layer, and the pad structure; forming a dielectric layer over the first electrode; and A second electrode is formed over the dielectric layer.

17. The method according to claim 11, wherein: The data storage element includes a capacitor.

18. The method according to claim 11, wherein: The third layer includes a semiconductor material or an oxide semiconductor material.

19. The method according to claim 11, wherein: The third layer includes a single crystal silicon layer.

20. The method according to claim 11, wherein: The first layer and the fifth layer include silicon oxide, and The second layer and the fourth layer include silicon nitride.

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