Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes forming a stack including a plurality of recessed target layers over a lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers, the bottom surface of the sacrificial vertical opening being disposed at a lower level than the bottom surface of the sacrificial isolation opening; forming a preliminary horizontal layer by recessing the recessing target layer through the sacrificial vertical opening; forming a sacrificial column structure filling the sacrificial vertical opening; forming a cell isolation opening by removing the sacrificial isolation layer; forming a horizontal layer by trimming the preliminary horizontal layer through the cell isolation opening; and forming a cell isolation layer filling the cell isolation opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0109068, filed on August 21, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including memory cells arranged in a three-dimensional manner and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, in order to cope with demands for large capacity and miniaturization of memory devices, a technology for providing a three-dimensional (3D) memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including a plurality of recessed target layers above a lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers, the bottom surface of which is set at a horizontal height lower than the bottom surface of the sacrificial isolation opening; forming a preliminary horizontal layer by recessing the recessed target layer through the sacrificial vertical opening; forming a sacrificial column structure filling the sacrificial vertical opening; forming a cell isolation opening by removing the sacrificial isolation layer; forming a horizontal layer by trimming the preliminary horizontal layer through the cell isolation opening; and forming a cell isolation layer filling the cell isolation opening.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack body including a plurality of sub-stacks above a lower structure; forming a sacrificial isolation opening in the stack body; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack body between the sacrificial isolation layers, the bottom surface of which is set at a horizontal height lower than the sacrificial isolation opening; forming a sacrificial column structure filling the sacrificial vertical opening; forming a unit isolation opening by removing the sacrificial isolation layer; expanding the unit isolation opening to form a support member supporting the sacrificial column structure; and forming a unit isolation layer filling the expanded unit isolation opening.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a unit isolation layer, which is vertically oriented in a first direction; a horizontal layer, which is horizontally oriented in a second direction intersecting the first direction and is vertically stacked in the first direction between the unit isolation layers; a vertical wire, which is vertically oriented in the first direction and coupled to a first edge of the horizontal layer; a horizontal wire, which crosses each horizontal layer in a third direction intersecting the first direction and the second direction; a data storage element, which is respectively coupled to the second edge of the horizontal layer; and a support member, which is arranged below the vertical wire and the data storage element. The bottom surface of the unit isolation layer is arranged at a lower level than the bottom surface of the vertical wire. Each unit isolation layer includes: a lower isolation region arranged between the supports; and an upper isolation region arranged between the vertical wires, and the horizontal width of the lower isolation region is greater than the horizontal width of the upper isolation region. The supports and the horizontal layers include single crystal silicon. Each horizontal wire includes a double structure horizontal line facing each other, and the horizontal layers are respectively placed therebetween.

[0009] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including multiple sub-stacks above a lower structure; forming a sacrificial isolation opening including a bottom surface of a first level in the stack; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening including a bottom surface of a second level higher than the first level in the stack between the sacrificial isolation layers; extending the sacrificial vertical opening to have a bottom surface of a third level lower than the second level; forming a sacrificial column structure filling the extended sacrificial vertical opening; forming a unit isolation opening by removing the sacrificial isolation layer; extending the unit isolation opening to have a bottom surface of a fourth level lower than the third level; forming a support member between the extended unit isolation openings; and forming a unit isolation layer filling the extended unit isolation opening.

[0010] These and other features and advantages of the present invention will be better understood from the following drawings and detailed description of specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0012] Figure 1B It is shown Figure 1A A schematic cross-sectional view of a memory cell is shown.

[0013] Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0014] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention.

[0015] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0016] Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown.

[0017] Figure 3B is along Figure 2 A cross-sectional view taken along line AA' is shown.

[0018] Figure 3C is along Figure 2 A cross-sectional view taken along line BB' is shown.

[0019] Figure 3D is along Figure 2 A cross-sectional view taken along line B1-B1' is shown.

[0020] Figure 3E is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0021] FIG. 4A to FIG. 26B A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0022] FIG. 27A to FIG. 27C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0023] Figures 28 to 30 is a perspective view showing a memory cell array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in each of the drawings and embodiments of the present invention.

[0025] The drawings are not necessarily drawn to scale, and in some cases, proportions may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate. In addition, unless otherwise specified, "overlap" as used herein may refer to complete overlap or partial overlap. Complete overlap means that two structures completely cover each other or completely share the same space, and no part of either structure is separated from the other structure. Partial overlap means that only a portion of one structure or object overlaps with another structure or object.

[0026] The following embodiments of the present invention relate to three-dimensional memory cells, and memory cells may be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0027] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention. Figure 1B It is shown Figure 1A A schematic cross-sectional view of a memory cell is shown. Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0028] Reference Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0029] The first wire BL may be vertically oriented in the first direction D1. The first wire BL may include a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0030] The switching element TR may have a function of controlling the voltage (or current) supply to the data storage element CAP in the data write operation and the data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire or a word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0031] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in a first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in a second horizontal direction (i.e., the third direction D3).

[0032] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first wire BL. The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other and with the horizontal layer HL disposed therebetween. The interlayer dielectric layer GD may be formed on the upper surface and the bottom surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed above the horizontal layer HL, and the lower horizontal wire G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair to be coupled to one memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. In this case, one of the upper horizontal wire G1 and the lower horizontal wire G2 may be used as a back gate or a shielding gate.

[0033] Return to reference Figure 1C, each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping with the horizontal layer HL, which is greater than a width of a portion not overlapping with the horizontal layer HL. Due to this difference in width, the second wire DWL may have a notch-shaped sidewall. The second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlapping portion NOL may refer to a portion not overlapping with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or an orthogonal shape.

[0034] From a top view perspective, the horizontal layer HL may have a cross shape or an orthogonal shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0035] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon-germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0036] The upper surface and the bottom surface of the horizontal layer HL may have flat surfaces. The upper surface and the bottom surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0037] The horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body. The channel overlap portion WLP of the channel CH and the second conductive line DWL may overlap each other. The channel CH may have a cross shape or an orthogonal shape. The size of the channel overlap portion WLP of the second conductive line DWL may be greater than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap the channel CH.

[0038] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as first and second source / drain regions.

[0039] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0040] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second wire DWL may include a stack of a low work function material and a high work function material.

[0041] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally arranged in the second direction D2 from the switching element TR. The data storage element CAP may include a first electrode SN extending horizontally from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN on the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be arranged in the inner space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be connected to the common plate PL.

[0042] The data storage element CAP may be a three-dimensional structure. The first electrode SN may have a three-dimensional structure, and the first electrode SN may have a horizontal three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0043] According to another embodiment of the present invention, the first electrode SN may have a pillar shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which a pillar shape and a barrel shape are combined.

[0044] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as a second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0045] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer including two or more layers of the aforementioned high-k materials.

[0046] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacking structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide (ZrO2)-based layer. According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacking structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked sequentially. The HA stack and the HAH stack may be referred to as a hafnium oxide (HfO2)-based layer. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a dielectric constant lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a band gap energy greater than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as a high-band gap material. Since the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacking structure in which high-k materials and high bandgap materials are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacking structure, aluminum oxide (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0047] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material, and the dielectric layer DE may include a stacked structure in which multiple high-k materials and multiple high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0048] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0049] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0050] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0051] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0052] For example, the memory cell MC may include a thyristor, and the first conductive line BL may be a cathode line, and the data storage element CAP may be replaced by an anode line. Therefore, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows or a low conductance state in which a small amount of current or no current flows. Each memory cell MC according to an embodiment of the present invention may have a "1" state or a "0" state based on the high conductance state and the low conductance state of the thyristor.

[0053] Return to reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and each of the first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0054] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention. Figure 1D The memory cell MC1 shown may be similar to Figures 1A to 1C The memory cell MC shown in FIG. 1 may be omitted in the following text. Figures 1A to 1C Detailed description of the constituent elements in .

[0055] The memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0056] The memory cell MC1 may further include a first contact node BLC between the first conductive line BL and the horizontal layer HL, and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. Each of the first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0057] The second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be horizontally arranged in the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first conductive line BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The horizontal layer HL may have a thickness thinner than the thickness of each of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0058] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of materials having different work functions. The first work function electrode G11 may have a higher work function than the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-bandgap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include a low work function material. The second work function electrode G12 and the third work function electrode G13 may have a work function lower than the mid-bandgap work function of silicon. In other words, the high work function material may have a work function higher than about 4.5 eV, and the low work function material may have a work function lower than about 4.5 eV. The first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may include a semiconductor material.

[0059] The second work function electrode G12 and the third work function electrode G13 may include doped polysilicon doped with an N-type dopant (polysilicon doped with an N-type dopant). The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0060] According to this embodiment of the present invention, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a second work function electrode G12-a first work function electrode G11-a third work function electrode G13 horizontally arranged in the second direction D2. The first work function electrode G11 may include metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0061] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a PMP (polysilicon metal-polysilicon) structure, in which polysilicon, metal, and polysilicon are arranged horizontally in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may be N-type dopant-doped polysilicon, i.e., polysilicon doped with N-type dopants. The N-type dopant may include phosphorus or arsenic.

[0062] The first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the top surface, the bottom surface, and one side surface of the first work function electrode G11.

[0063] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13, and thus the second wire DWL may have a low resistance. The first work function electrode G11 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The second work function electrode G12 and the third work function electrode G13 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The overlapping area between the first work function electrode G11 and the horizontal layer HL may be greater than the overlapping area between the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The second and third work function electrodes G12 and G13 and the first work function electrode G11 may extend in the third direction D3, and the second and third work function electrodes G12 and G13 and the first work function electrode G11 may directly contact each other.

[0064] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a three-electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13 extending in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0065] like Figure 1CAs shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or an orthogonal shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 through the channel overlap portion WLP and the channel non-overlap portion NOL may have a notch-shaped sidewall. From a top-down perspective, the notch-shaped sidewall may be provided by a protruding portion of the channel overlap portion WLP and a recessed portion of the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, and the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0066] In the second direction D2, the first work function electrode G11 having a high work function can be disposed at the center of the second wire DWL, and the second work function electrode G12 and the third work function electrode G13 having a low work function can be disposed at both ends of the second wire DWL. In this way, leakage current problems such as gate induced drain leakage (GIDL) can be improved.

[0067] Since the first work function electrode G11 having a high work function is disposed at the center of the second wire DWL, the threshold voltage of the switching element TR can be increased. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field can be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second wire DWL.

[0068] As described above, the memory cell MC1 may include a second wire DWL having a three-work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap with the channel CH, and the second work function electrode G12 may be disposed adjacent to the first wire BL and the first doped region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, thereby reducing leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, thereby improving leakage current. Due to the high work function of the first work function electrode G11, a high threshold voltage of the switching element TR may be formed, and the formation of the low electric field may reduce the height of the memory cell MC1, which is advantageous in terms of integration.

[0069] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown. Figure 3B is along Figure 2 A cross-sectional view taken along line AA' is shown. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' is shown. Figure 3D is along Figure 2 A cross-sectional view taken along line B1-B1' is shown. Figure 3E is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0070] Reference Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. For individual memory cells MC, reference may be made to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0071] The memory cell array MCA may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may be horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include sub-memory cell arrays MCA1 adjacent to each other in the second direction D2. The sub-memory cell array MCA1 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 100 may further include a sub-memory cell array having a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which the memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 horizontally arranged in the third direction D3.

[0072] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked in the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer.

[0073] The cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC arranged in the third direction D3. The cell isolation layers ISOA and ISOB may be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a column structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP in the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL in the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB may include a stack of a cell isolation liner layer ISOL and a cell isolation gap-filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap-filling layer ISOG may include silicon oxide carbon.

[0074] The memory cell array MCA may be disposed on the lower structure LS.

[0075] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0076] like Figure 1C As shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or an orthogonal shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portion WLP and the channel non-overlap portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notch-shaped sidewall.

[0077] A plurality of first passivation layers BF1 may be disposed between the bottommost second wire DWL among the second wires DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first wire BL, the second wire DWL, and the data storage element CAP from the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may be referred to as bottom dielectric layers or bottom passivation layers. The lowest level inter-cell dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0078] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second wire DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0079] From a top view, the horizontal layer HL may have a cross shape or an orthogonal shape. According to another embodiment of the present invention, the side surface of the horizontal layer HL may have a curved shape or a rounded shape. Figure 1B As shown, the horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP.

[0080] The first cover layer BC may be disposed between the second wire DWL and the first wire BL. The second cover layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first cover layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first cover layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0081] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon carbon oxide, an air gap, or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0082] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and each of the first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0083] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 may share one first wire BL. The switching elements TR horizontally arranged in the third direction D3 may share one second wire DWL.

[0084] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP in the third direction D3. The first electrodes SN may be isolated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0085] The lower structure LS may include a semiconductor substrate, a metal interconnection structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit unit.

[0086] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnection structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be coupled by wafer bonding.

[0087] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may be referred to as a COP (unit above peripheral circuit) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc.

[0088] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The first conductive line BL may be coupled to the sense amplifier, and the second conductive line DWL may be coupled to the sub word line driver.

[0089] According to another embodiment of the present invention, the peripheral circuit unit may be arranged at a level higher than the memory cell array MCA. This may be referred to as a POC (Peripheral Circuit Over Cell) structure.

[0090] According to another embodiment of the present invention, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND memory, a ferroelectric RAM (FeRAM), a spin transfer torque RAM (STTRAM), a phase change RAM (PCRAM) or a resistive RAM (ReRAM).

[0091] According to another embodiment of the present invention, individual memory cells MC can be used Figure 1D The memory cell MC1 shown is replaced.

[0092] Return to reference Figure 2 , Figure 3C , Figure 3D and Figure 3E , the bottom surface of the first conductive line BL may be disposed at the first level H11, and the bottom surfaces of the first and second cell isolation layers ISOA and ISOB may be disposed at the second level H12. The second level H12 may be at a lower level than the first level H11.

[0093] A portion of the lower structure LS, for example, a support member LSP may be disposed under the first conductive line BL. The support member LSP may support the first conductive line BL and the data storage element CAP. The structural stability of the memory cell MC may be increased by the support member LSP. The support member LSP and the lower structure LS may include single crystal silicon.

[0094] The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a bubble-shaped structure. The first cell isolation layer ISOA and the second cell isolation layer ISOB may include a lower isolation region ISOL and an upper isolation region ISOU. A support member LSP may be disposed between the lower isolation regions ISOL. A first conductive line BL may be disposed between the upper isolation regions ISOU. A data storage element CAP may be disposed between the upper isolation regions ISOU. A width of the upper and lower isolation regions ISOL may be greater than a width of the upper isolation region ISOU in a third direction D3.

[0095] As described above, since the bottom surfaces of the first conductive line BL and the data storage element CAP are at a higher level than the bottom surfaces of the first and second cell isolation layers ISOA and ISOB due to the support member LSP, bunkers that may occur when forming the first conductive line BL and the data storage element CAP can be prevented.

[0096] FIG. 4A to FIG. 26B An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0097] Figure 4A is a plan view of the fourth layer 14 level showing a method of forming the stacked body SB and the sacrificial isolation openings 15A and 15B, and Figure 4B is along Figure 4A A cross-sectional view taken along line AA' is shown. Figure 4C is along Figure 4A A cross-sectional view taken along line B1-B1' is shown.

[0098] Reference FIG. 4A to FIG. 4C , the stack SB may be formed on the lower structure 11. The lower structure 11 may include a material suitable for semiconductor processing. The material of the lower structure 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. Different materials may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a silicon-containing material. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials, such as germanium. The lower structure 11 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0099] In the stacked body SB, a plurality of sub-stacks may be alternately stacked. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a semiconductor layer 14 stacked in the above order. The first layer 12A and the third layer 12B may be formed of the same material and may include silicon germanium. The second layer 13 and the fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be formed by an epitaxial growth process. The first layer 12A of the lowest level may be used as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the fourth layer 14 may be thicker than the second layer 13.

[0100] The stacked body SB may include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, and a third stack SB3. In the stacked body SB, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 may be stacked in the order mentioned. The second layer 13 may be set as the uppermost layer of the stacked body SB. Each of the first stack SB1, the second stack SB2, and the third stack SB3 may be a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first stack SB1, the second stack SB2, and the third stack SB3 may include a stack of a first silicon germanium / single crystal silicon / a second silicon germanium (SiGe / Si / SiGe).

[0101] The second layer 13 may include a first single crystal silicon layer, and the fourth layer 14 may include a second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer. Therefore, in the stacked body SB, the first stack SB1 may be disposed below the second single crystal silicon layer, and the second stack SB2 may be disposed above the second single crystal silicon layer. Each of the first stack SB1 and the second stack SB2 may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0102] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as “sacrificial layers”, and the fourth layer 14 may be referred to as a “recess target layer”.

[0103] The stack SB may be referred to as a vertical stack. The stack SB may be formed by alternating a plurality of sacrificial layers and a recessed target layer. The sacrificial layer may include a first stack SB1, a second stack SB2, and a third stack SB3, and each of the first stack SB1, the second stack SB2, and the third stack SB3 may include a stack of a first layer 12A / a second layer 13 / a third layer 12B. The recessed target layer may include a fourth layer 14. Each sacrificial layer may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and each recessed target layer may include a second single crystal silicon layer, wherein the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0104] As mentioned above Figures 2 to 3D As shown, when the memory cells MC are vertically stacked, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, and the third stack SB3 may be alternately stacked multiple times.

[0105] Subsequently, a portion of the stack SB may be etched to form a plurality of sacrificial isolation openings 15A and 15B. The sacrificial isolation openings 15A and 15B may be initial openings for cell isolation and may include a large opening 15A and a small opening 15B. The size of the large opening 15A may be greater than the size of the small opening 15B. From a top-down perspective, the large opening 15A and the small opening 15B may have a rectangular shape. According to another embodiment of the present invention, the large opening 15A and the small opening 15B may have a circular shape or an elliptical shape. According to another embodiment of the present invention, the sacrificial isolation openings 15A and 15B may be referred to as sacrificial isolation trenches. The large opening 15A and the small opening 15B may extend vertically in the first direction D1. The large opening 15A and the small opening 15B may be alternately arranged in the second direction D2. A plurality of large openings 15A may be arranged in the third direction D3. A plurality of small openings 15B may be arranged in the third direction D3. The large opening 15A and the small opening 15B may pass through the stack SB in the first direction D1.

[0106] After forming the sacrificial isolation openings 15A and 15B, the portion of the lower structure 11 exposed below the sacrificial isolation openings 15A and 15B may be etched. As a result, the bottom surfaces of the sacrificial isolation openings 15A and 15B may extend into the lower structure 11. The bottom surfaces of the sacrificial isolation openings 15A and 15B may include a U-shaped profile. Due to the sacrificial isolation openings 15A and 15B, the fourth layer 14 may have a mesh pattern.

[0107] Bottom surfaces of the sacrificial isolation openings 15A and 15B may be disposed at the first level H1 .

[0108] Figure 5A is a plan view of the fourth layer 14 level showing a method of forming sacrificial isolation layers 16A and 16B, and Figure 5B is along Figure 5A A cross-sectional view taken along line B1-B1' is shown.

[0109] Reference Figure 5A and Figure 5B , sacrificial isolation layers 16A and 16B may be formed to fill the sacrificial isolation openings 15A and 15B. The sacrificial isolation layers 16A and 16B may include a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A may fill the large opening 15A, and the second sacrificial isolation layer 16B may fill the small opening 15B.

[0110] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include forming a sacrificial isolation material on the stack SB to fill the sacrificial isolation openings 15A and 15B, and flattening the sacrificial isolation material to expose the uppermost layer of the stack SB. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A may be larger than the size (or volume) of the second sacrificial isolation layer 16B.

[0111] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in the second direction D2. A plurality of first sacrificial isolation layers 16A may be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may pass through the stack SB in the first direction D1.

[0112] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. For example, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbon nitride, or a combination thereof.

[0113] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A may be larger than that of the second sacrificial isolation layer 16B.

[0114] Each of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include a stack of a sacrificial liner layer L1 and a sacrificial gap-filling layer L2. The sacrificial liner layer L1 may include silicon nitride, and the sacrificial gap-filling layer L2 may include silicon oxide.

[0115] Forming the first and second sacrificial isolation layers 16A and 16B may include sequentially forming a sacrificial liner layer L1 and a sacrificial gap-filling layer L2 over the stacked body SB to fill the sacrificial isolation openings 15A and 15B and planarizing the sacrificial liner layer L1 and the sacrificial gap-filling layer L2 to expose an uppermost layer of the stacked body SB.

[0116] Bottom surfaces of the first and second sacrificial isolation layers 16A and 16B may be disposed at the first level H1.

[0117] Fig. 6A is a plan view of the hierarchy of the fourth layer 14 showing a method of forming the sacrificial vertical openings V1' and V2', and Figure 6B is along Fig. 6A A cross-sectional view taken along line AA' is shown. Figure 6C is along Fig. 6A A cross-sectional view taken along line B1-B1' is shown.

[0118] Reference FIG. 6A to FIG. 6C , a hard mask layer pattern 17 may be formed on the stacked body SB, the first sacrificial isolation layer 16A, and the second sacrificial isolation layer 16B. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a mask layer (not shown). The hard mask layer pattern 17 may have a plurality of defined hole-shaped openings.

[0119] Subsequently, a portion of the stacked body SB may be etched using the hard mask layer pattern 17 as an etch stopper. As a result, a plurality of sacrificial vertical openings V1' and V2' may be formed in the stacked body SB. The sacrificial vertical openings V1' and V2' may include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be hole-type openings. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may extend vertically in the first direction D1. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1' may be formed by etching the stacked body SB between the second sacrificial isolation layer 16B. The second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layers 16A. The first sacrificial vertical opening V1' may be disposed between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical opening V2' may be disposed between the first sacrificial isolation layers 16A in the third direction D3. From a plan viewpoint, cross-sections of the first sacrificial vertical opening V1 ′ and the second sacrificial vertical opening V2 ′ may have a square shape, a circular shape, or an elliptical shape.

[0120] The bottom surfaces of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be disposed at a second level H2. The second level H2 of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be higher than the first level H1 of the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B. The second level H2 of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be higher than the first level H1 of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B.

[0121] Fig. 7A is a plan view showing a method of forming the preliminary horizontal layer 14A, and Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' shown, and Figure 7C is along Fig. 7A A cross-sectional view taken along line B1-B1' is shown. Fig.7D is along Fig. 7A A cross-sectional view taken along line BB' is shown.

[0122] Reference 7A to 7D , a portion of the hard mask layer pattern 17 may be trimmed (refer to reference numeral ' 17T').

[0123] Subsequently, the first layer 12A and the third layer 12B may be selectively removed through the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2'. In order to selectively remove the first layer 12A and the third layer 12B, the difference in etching selectivity between the second layer 13 and the fourth layer 14 and the first layer 12A and the third layer 12B may be used. The first layer 12A and the third layer 12B may be removed using a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 and the fourth layer 14 include a single crystal silicon layer, the silicon germanium layer may be etched using an etchant or etching gas having selectivity relative to the single crystal silicon layer.

[0124] Subsequently, the second layer 13 and the fourth layer 14 may be recessed. In order to recess the second layer 13 and the fourth layer 14, a wet etching process or a dry etching process may be used. According to this embodiment of the present invention, the fourth layer 14 may be partially etched when the second layer 13 is removed. As a result, the second layer 13 may be removed and the fourth layer 14 may be thinned, as shown in the reference numeral "14A". The recess process for forming the thin fourth layer 14A (i.e., the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. In order to form the preliminary horizontal layer 14A, the top surface, the bottom surface, and the side surface of the fourth layer 14 may be recessed. The preliminary horizontal layer 14A may be referred to as a thin body active layer. The preliminary horizontal layer 14A may include a single crystal silicon layer. The recess process for forming the preliminary horizontal layer 14A may use, for example, HSC1 (Hot SC-1). The HSC1 may include a mixed solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) are mixed in a ratio of about 1:4:20. The second layer 13 and the fourth layer 14 may be selectively etched using the HSC1.

[0125] The preliminary horizontal layer 14A may be formed by the above-described recessing process for recessing the fourth layer 14, and the horizontal recesses 18 may be formed between the preliminary horizontal layers 14A. Each of the upper and bottom surfaces of the preliminary horizontal layer 14A may include a flat surface.

[0126] The preliminary horizontal layer 14A may have a cross shape from a top view perspective. A side surface of the preliminary horizontal layer 14A may have a curved shape or a rounded shape.

[0127] After forming the preliminary horizontal layer 14A, the first sacrificial vertical opening and the second sacrificial vertical opening may be expanded as shown in the reference numerals "V1" and "V2". The preliminary horizontal layer 14A may be spaced apart from each other by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 in the second direction D2. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged in the third direction D3.

[0128] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 may be recessed to a certain depth (see the reference numeral "11A"). As a result, the depth of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be increased. The bottom surface of the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be lowered from the second level H2 to the third level H3. The bottom surface of the extended first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be set at the third level H3. The third level H3 of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be higher than the first level H1 of the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B. The third level H3 of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be higher than the first level H1 of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. According to another embodiment of the present invention, the third level H3 of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be the same as the first level H1.

[0129] The first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be alternately disposed between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical openings V1 may be disposed between the second sacrificial isolation layers 16B in the third direction D3, and the second sacrificial vertical openings V2 may be disposed between the first sacrificial isolation layers 16A in the third direction D3.

[0130] Fig. 8A is a plan view showing a method of forming the first dielectric layer 19 and the second dielectric layer 20, and Figure 8B is along Fig. 8A A cross-sectional view taken along line AA' is shown. Figure 8C is along Fig. 8A A cross-sectional view taken along line B1-B1' is shown. Fig.8D is along Fig. 8A A cross-sectional view taken along line BB' is shown.

[0131] Reference FIG. 8A to FIG. 8D , a first dielectric layer 19 covering the preliminary horizontal layer 14A may be formed. The first dielectric layer 19 may include silicon nitride. The first dielectric layer 19 may completely cover the top surface, the bottom surface, and the side surface of the preliminary horizontal layer 14A.

[0132] When the first dielectric layer 19 is formed, a dummy dielectric layer 19D may be formed on the surface of the lower structure 11. Some of the first dielectric layer 19 may completely cover the top, bottom, and side surfaces of the hard mask layer pattern 17.

[0133] Subsequently, a second dielectric layer 20 may be formed on the first dielectric layer 19. The second dielectric layer 20 may fill between vertically adjacent first dielectric layers 19. The second dielectric layer 20 may include silicon oxide. Portions of the second dielectric layer 20 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. Figure 7B and Figure 7C 18) in the embodiment may be filled with a first dielectric layer 19 and a second dielectric layer 20.

[0134] Subsequently, a sacrificial column 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial column 21 may be a sacrificial material and may include amorphous carbon. According to another embodiment of the present invention, a column cover layer may be further formed on the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 21 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial column 21 may be performed until the first dielectric layer 19 of the uppermost level is exposed. Subsequently, the second dielectric layer 20 of the uppermost level may also be planarized until the first dielectric layer 19 of the uppermost level is exposed. The sacrificial column 21 may not be formed between the vertically stacked first dielectric layers 19.

[0135] The second dielectric layer 20 and the sacrificial column 21 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening V1 and the second sacrificial column structure SV2. The first sacrificial column structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial column structure SV2 may fill the second sacrificial vertical opening V2. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From a top-down perspective, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be hole-type sacrificial columns. According to another embodiment of the present invention, a portion of the first dielectric layer 19 may be conformally formed on the surface of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. Therefore, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may also include a portion of the first dielectric layer 19.

[0136] Bottom surfaces of the first and second sacrificial column structures SV1 and SV2 may be disposed at a third level H3 .

[0137] Reference Fig.8D, the first dielectric layer 19 may be formed between the preliminary horizontal layers 14A, and the second dielectric layer 20 may be formed inside the first dielectric layer 19. The first dielectric layer 19 may surround the second dielectric layer 20. The first dielectric layer 19 may include a first surrounding portion and a second surrounding portion, wherein the first surrounding portion may surround the preliminary horizontal layer 14A in the AA' direction, and the second surrounding portion may surround the second dielectric layer 20 in the BB' direction and the CC' direction.

[0138] As described above, a unit mold structure may be formed by forming a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. The unit mold structure may include a plurality of unit molds CM. Each unit mold CM may include a plurality of mold layers. The mold layer may refer to a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. Each unit mold CM may include an ONSN (oxide-nitride-silicon-nitride) stack. Here, an ONSN stack may refer to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are sequentially stacked. Silicon oxide may correspond to the second dielectric layer 20, and the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 19. The single crystal silicon layer may correspond to the preliminary horizontal layer 14A. A unit mold structure including a unit mold CM may be referred to as a vertical stack. From another perspective, a unit mold structure may include an ONSNNO (oxide-nitride-silicon-nitride-oxide) stack. Here, the ONSNO stack may refer to a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are sequentially stacked.

[0139] As described above, the sub-stacks of the stack SB can be formed by FIG. 4A to FIG. 8D The first layer 12A, the second layer 13, and the third layer 12B may be replaced with the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 may be changed into the preliminary horizontal layer 14A through the recess process. The first dielectric layer 19 may be referred to as a trimming target layer.

[0140] Fig.9A is a plan view showing a method of forming cell isolation openings 22A and 22B and a horizontal layer 14B, and Fig. 9B is along Fig.9A A cross-sectional view taken along line B1-B1' is shown. Fig. 9C is along Fig.9A A cross-sectional view taken along line BB' is shown.

[0141] Reference 9A to 9C, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be removed to form cell isolation openings 22A and 22B. The cell isolation openings 22A and 22B may include a first cell isolation opening 22A and a second cell isolation opening 22B. The first cell isolation opening 22A may be formed by removing the first sacrificial isolation layer 16A. The second cell isolation opening 22B may be formed by removing the second sacrificial isolation layer 16B. When the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B are removed, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be covered by a mask layer (not shown). The first cell isolation opening 22A and the second cell isolation opening 22B may expose the side surfaces of the preliminary horizontal layer 14A and the first dielectric layer 19 in the BB' direction.

[0142] Subsequently, the side surface of the preliminary horizontal layer 14A of the unit mold CM may be trimmed in the second direction D2 and the third direction D3 by the first unit isolation opening 22A and the second unit isolation opening 22B. As a result, a trimmed horizontal layer 14B may be formed. A horizontal layer level gap 14R may be formed on the side surface of the horizontal layer 14B. The horizontal layer level gap 14R and the horizontal layer 14B may be disposed between the first dielectric layer 19. The horizontal layer 14B may be referred to as a "trimmed horizontal layer pattern".

[0143] When the horizontal layer 14B is formed, the surface of the lower structure 11, such as the bottom surface of the first cell isolation opening 22A and the second cell isolation opening 22B, may be extended (see the reference numeral "11R"). As a result, the bottom surface of the first cell isolation opening 22A and the second cell isolation opening 22B may be set at the fourth level H4. The fourth level H4 of the first cell isolation opening 22A and the second cell isolation opening 22B may be lower than the third level H3 of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 and the first sacrificial column structure SV1 and the second sacrificial column structure SV2. The fourth level H4 of the first cell isolation opening 22A and the second cell isolation opening 22B may be lower than the first level H1 of the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B and the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. In this way, the bottom surface of the first cell isolation opening 22A and the second cell isolation opening 22B may be lower than the bottom surface of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 and the bottom surface of the first sacrificial column structure SV1 and the second sacrificial column structure SV2.

[0144] When the horizontal layer 14B is formed, a support member 11P may be formed under the first sacrificial column structure SV1 and the second sacrificial column structure SV2. The support member 11P may be disposed between the first cell isolation opening 22A and the second cell isolation opening 22B. The support member 11P may be formed by recessing the surface of the lower structure 11. When the lower structure 11 includes single crystal silicon, the support member 11P may also include single crystal silicon.

[0145] Each of the first cell isolation opening 22A and the second cell isolation opening 22B may have a lower region 22L disposed between the supports 11P and an upper region 22U disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2. The horizontal width of the lower region 22L may be greater than the horizontal width of the upper region 22U. As described above, since the lower region 22L and the upper region 22U have different horizontal widths, the cell isolation openings 22A and 22B may become bubble-shaped openings.

[0146] The horizontal layer 14B may be disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2 in the second direction D2. From a top-down perspective, the horizontal layer 14B may have a cross shape. The horizontal layer 14B may have a cross shape whose size is smaller than that of the preliminary horizontal layer 14A. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged, and the horizontal layer 14B may have a shape in which the cross shapes are individually separated in the third direction D3. A horizontal layer level gap 14R may be formed between the horizontal layers 14B arranged in the third direction D3. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be disposed between the horizontal layers 14B in the second direction D2.

[0147] Fig. 10A is a plan view showing a method of forming a horizontal layer-level spacer 23 and a first dielectric layer 19A, and Fig. 10B is along Fig. 10A A cross-sectional view taken along line B1-B1' is shown. Fig. 10C is along Fig. 10A A cross-sectional view taken along line BB' is shown.

[0148] Reference FIG. 10A to FIG. 10C , the horizontal layer level spacers 23 may be formed on the side surfaces of the horizontal layers 14B. Forming the horizontal layer level spacers 23 may include forming a spacer material on the side surfaces of the horizontal layers 14B and etching the spacer material. The horizontal layer level spacers 23 may include a dielectric material, such as silicon oxide. The horizontal layer level spacers 23 may fill the horizontal layer level gaps 14R. The horizontal layers 14B arranged in the third direction D3 may be isolated from each other by the horizontal layer level spacers 23.

[0149] Subsequently, a portion of the first dielectric layer 19 may be horizontally trimmed through the first cell isolation opening 22A and the second cell isolation opening 22B. After the trimming process, the first dielectric layer 19 may remain, as indicated by reference numeral "19A". Therefore, from the perspective of the BB' direction, a pair of first dielectric layers 19A may be disposed between the horizontal layers 14B, and one second dielectric layer 20 may be disposed between the pair of first dielectric layers 19A.

[0150] according to 9A to 10C The width of the first dielectric layer 19A in the third direction D3 between the first cell isolation openings 22A and between the second cell isolation openings 22B may be greater than the width of the horizontal layer 14B. The trimming depth of the first dielectric layer 19 in the third direction D3 may be less than the trimming depth of the preliminary horizontal layer 14A.

[0151] A pair of first dielectric layers 19A may vertically overlap one horizontal layer 14B. The trimmed first dielectric layer 19A may be referred to as a trimmed first dielectric layer.

[0152] Fig.11A is a plan view showing a method of forming cell isolation layers 24A and 24B, and Fig. 11B is along Fig.11A A cross-sectional view taken along line B1-B1' is shown. Fig. 11C is along Fig.11A The cross-sectional view is taken along the line BB' shown. Fig.11A may be a plan view at the level of the first dielectric layer 19A showing a method of forming the cell isolation layers 24A and 24B.

[0153] Reference FIG. 11A to FIG. 11C , cell isolation layers 24A and 24B may be formed to fill the first cell isolation opening 22A and the second cell isolation opening 22B. The cell isolation layers 24A and 24B may include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B may include the same material. The first cell isolation layer 24A and the second cell isolation layer 24B may be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide, silicon nitride, silicon oxide carbon, silicon nitride carbon, or a combination thereof. From a top view, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide.

[0154] Forming the first cell isolation layer 24A and the second cell isolation layer 24B may include forming a cell isolation material filling the first cell isolation opening 22A and the second cell isolation opening 22B, and planarizing the cell isolation material and the uppermost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first cell isolation layer 24A and the second cell isolation layer 24B may have different sizes or different volumes. The second sacrificial column structure SV2 may be disposed between the first cell isolation layers 24A in the third direction D3, and the first sacrificial column structure SV1 may be disposed between the second cell isolation layers 24B in the third direction D3. The first cell isolation layer 24A and the second cell isolation layer 24B may extend vertically in the first direction D1.

[0155] The first and second cell isolation layers 24A and 24B may correspond to Figures 2 to 3D Each of the first cell isolation layer 24A and the second cell isolation layer 24B may include a stack of a cell isolation liner layer ISOL and a cell isolation gap filling layer ISOG, which are shown in FIG. Figure 3C and Figure 3D The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap filling layer ISOG may include silicon oxide carbon. According to another embodiment of the present invention, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and the embedded air gap may be provided when the cell isolation gap filling layer ISOG is formed.

[0156] The first and second cell isolation layers 24A and 24B and the first dielectric layer 19A may directly contact each other. A horizontal layer level spacer 23 may be disposed between the horizontal layer 14B and the first and second cell isolation layers 24A and 24B.

[0157] The first cell isolation layer 24A and the second cell isolation layer 24B may be disposed at the fourth level H4, and the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be disposed at the third level H3. The fourth level H4 may be higher than the third level H3. According to the above description, the fourth level H4 may be extended from the first level H1, and the third level H3 may be extended from the second level H2. The fourth level H4 may be lower than the first level H1, the second level H2, and the third level H3.

[0158] Each of the first cell isolation layer 24A and the second cell isolation layer 24B may include a lower isolation region 24L disposed between the support members 11P and an upper isolation region 24U disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2. The horizontal width of the lower isolation region 24L may be greater than the horizontal width of the upper isolation region 24U. As described above, since the lower isolation region 24L and the upper isolation region 24U have different horizontal widths, the cell isolation layers 24A and 24B may be bubble-shaped isolation layers.

[0159] Fig.12 is a plan view showing a method of forming a first dielectric layer pattern 19B, and FIG. 13A to FIG. 13D is along Fig.12 The first dielectric layer pattern 19B is intercepted by the line AA′ shown.

[0160] Reference Fig.13A , the hard mask layer pattern 17 and the first dielectric layer 19A at the uppermost level may be removed to form a hard mask level recess 25 .

[0161] Reference Fig. 13B , a top dielectric layer 26 filling the hard mask level recess 25 may be formed. The top dielectric layer 26 may include silicon oxide.

[0162] Reference Fig. 13C , the initial vertical opening 27 may be formed by removing the first sacrificial pillar structure SV1. Subsequently, the second dielectric layer 20 may be horizontally recessed, and thus the first dielectric layer 19A and the dummy dielectric layer 19D may be exposed.

[0163] Reference Fig.13D , the dummy dielectric layer 19D and the first dielectric layer 19A may be selectively horizontally recessed. As a result, the first dielectric layer pattern 19B and the dielectric level recess 28 may be formed. Portions of the horizontal layer 14B may be exposed through the dielectric level recess 28.

[0164] Fig.14A is a plan view showing a method of forming a vertical sacrificial structure 29, and Fig. 14B is along Fig.14A A cross-sectional view taken along line AA' is shown.

[0165] Reference Fig.14A and Fig. 14B , a vertical sacrificial structure 29 may be formed to fill the dielectric level recess 28 and the initial vertical opening 27. The vertical sacrificial structure 29 may include a sacrificial material. The vertical sacrificial structure 29 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0166] Fig.15A is a plan view showing a method of forming the vertical hierarchical path 30, and Fig. 15Bis along Fig.15A A cross-sectional view taken along line AA' is shown.

[0167] Reference Fig.15A and Fig. 15B In order to form the vertical hierarchical path 30 , the sacrificial pillar 21 of the first sacrificial pillar structure SV1 may be removed.

[0168] Subsequently, the dummy dielectric layer 19D below the vertical level path 30 may be removed to form a lower level gap 19D′.

[0169] Fig.16A is a plan view showing a method of forming a first hole-type vertical opening 32, and Fig. 16B is along Fig.16A A cross-sectional view taken along line AA' is shown.

[0170] Reference Fig.16A and 16B , the second dielectric layer 20 can be cut (see 31 ) through the vertical hierarchical path 30 to form a first hole-type vertical opening 32 .

[0171] Subsequently, a first passivation layer BF1 may be formed to fill the lower level gap 19D'. The first passivation layer BF1 may include silicon oxide. Forming the first passivation layer BF1 may include depositing silicon oxide to fill the lower level gap 19D' and etching the silicon oxide.

[0172] Subsequently, the second passivation layer BF2 may be formed in a lower region of the first hole-type vertical opening 32. For example, the surface of the lower structure 11 may be oxidized to form the second passivation layer BF2.

[0173] Fig.17A is a plan view showing a method of forming the horizontal grade recess 33, and Fig. 17B is along Fig.17A A cross-sectional view taken along line AA' is shown. Fig. 17C is along Fig.17A A cross-sectional view taken along line BB' is shown.

[0174] Reference 17A to 17C , the first dielectric layer pattern 19B can be removed through the first hole-type vertical opening 32 to form a horizontal level recess 33. A portion of the horizontal layer 14B can be exposed through the horizontal level recess 33. Fig. 17C , the horizontal level recess 33 may be disposed between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal level recesses 33 may face each other with one horizontal layer 14B interposed therebetween.

[0175] Fig.18A is a plan view showing a method of forming the horizontal conductive line 35, and Fig.18B is along Fig.18AA cross-sectional view taken along line AA' is shown. Fig. 18C is along Fig.18A A cross-sectional view taken along line BB' is shown.

[0176] Reference 18A to 18C , an interlayer dielectric layer 34 may be formed on the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 may be referred to as a gate dielectric layer. The interlayer dielectric layer 34 may correspond to Figures 1A to 3B The interlayer dielectric layer GD is shown.

[0177] The interlayer dielectric layer 34 may be formed by oxidizing the surface of the horizontal layer 14B. According to another embodiment of the present invention, the interlayer dielectric layer 34 may be formed by a process including depositing silicon oxide. The interlayer dielectric layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0178] Subsequently, a horizontal conductor 35 filling the horizontal level recess 33 may be formed on the interlayer dielectric layer 34. Forming the horizontal conductor 35 may include depositing a conductive material filling the horizontal level recess 33 on the interlayer dielectric layer 34 and etching back the conductive material. The horizontal conductor 35 may include a pair of first horizontal conductors 35A and second horizontal conductors 35B facing each other and with the horizontal layer 14B disposed therebetween. The first horizontal conductor 35A and the second horizontal conductor 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductor 35A and the second horizontal conductor 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductor 35A and the second horizontal conductor 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductor 35A and the second horizontal conductor 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0179] The horizontal conductor 35 may correspond to Figures 1A to 1D The second wire DWL shown in FIG. 1A and the first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal wire G1 and the lower horizontal wire G2. Figures 1A to 1D , each of the first horizontal conductive line 35A and the second horizontal conductive line 35B may have a cross shape, and may include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0180] Fig.19Ais a plan view showing a method of forming the vertical wire 39, and Fig.19B is along Fig.19A A cross-sectional view taken along line AA' is shown. Fig.19C It is a cross-sectional view taken along the line BB′ shown in FIG. 19 .

[0181] Reference FIG. 19A to FIG. 19C , a first capping layer 36 may be formed on one side surface of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, silicon carbon oxide, an embedded air gap, or a combination thereof. A deposition process of the capping material and an etch-back process may be performed to form the first capping layer 36. When or after forming the first capping layer 36, a portion of the interlayer dielectric layer 34 may be removed to expose a first edge portion of each horizontal layer 14B.

[0182] Subsequently, a vertical conductive line 39 coupled to a first edge portion of each horizontal layer 14B may be formed. The vertical conductive line 39 may fill the first hole-type vertical opening 32. The vertical conductive lines 39 may be commonly coupled to the horizontal layers 14B arranged in the first direction D1. The vertical conductive lines 39 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive lines 39 may be referred to as bit lines or vertical bit lines.

[0183] Before forming the vertical conductive line 39, a first doped region 37 and a first contact node 38 may be formed. The first doped region 37 may be formed in a first edge portion of the horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doped region 37 may be formed by doping impurities.

[0184] The first contact node 38 may include doped polysilicon. The first doped region 37 may include impurities diffused from the first contact node 38. A metal silicide layer may be further formed between the vertical conductive line 39 and the first contact node 38.

[0185] The vertical conductors 39 may correspond to Figures 1A to 1D The first wire BL is shown.

[0186] Fig. 20A is a plan view showing a method of forming a preliminary second hole type vertical opening 29V, and Fig. 20B is along Fig. 20A A cross-sectional view taken along line AA' is shown.

[0187] Reference Fig. 20A and Fig. 20B, a portion of the vertical sacrificial structure 29 may be removed to form a preliminary second hole type vertical opening 29V. One side of the horizontal layer 14B, i.e., the second edge portion, may be exposed through the preliminary second hole type vertical opening 29V. After forming the preliminary second hole type vertical opening 29V, a preliminary second cover layer 29A may be formed on the upper and bottom surfaces of the horizontal layer 14B.

[0188] When the preliminary second capping layer 29A is formed, a lowermost level dielectric layer 29L may be formed on the side surface of the first passivation layer BF1 by removing a portion of the vertical sacrificial structure 29 .

[0189] Fig.21A is a plan view showing a method of recessing the horizontal layer HL, and Fig. 21B is along Fig.21A A cross-sectional view taken along line AA' is shown.

[0190] Reference Fig.21A and Fig. 21B , a third passivation layer BF3 may be formed on the surface of the lower structure 11. The third passivation layer BF3 may include silicon oxide.

[0191] Subsequently, the second edge portion of the horizontal layer 14B may be horizontally recessed in the second direction D2 (see reference numeral ' 14C'). As a result, the horizontal layer may remain as indicated by reference numeral 'HL'.

[0192] After forming the horizontal layer HL, the preliminary second hole type vertical opening may be expanded, as shown by reference numeral “ 40 .” Hereinafter, the expanded preliminary second hole type vertical opening may be simply referred to as the second hole type vertical opening 40 .

[0193] Fig.22A is a plan view showing a method of forming the storage opening 41, and Fig. 22B is along Fig.22A A cross-sectional view taken along line AA' is shown.

[0194] Reference Fig.22A and Fig. 22B , the second capping layer 29C may be formed by selectively recessing the preliminary second capping layer 29A. The second capping layer 29C may include silicon oxide, silicon nitride, or a combination thereof.

[0195] After forming the second cover layer 29C, a storage opening 41 horizontally extending from the second hole-type vertical opening 40 may be formed. The storage opening 41 may be referred to as a capacitor opening.

[0196] The horizontal layer HL may include a first edge and a second edge. The first edge may refer to a portion coupled to the first contact node 38 and the vertical conductive line 39 , and the second edge may refer to a portion exposed by the storage opening 41 .

[0197] The storage opening 41 may be disposed between the second dielectric layers 20. The second cover layers 29C may be disposed in lower and upper portions of the horizontal layer HL, respectively.

[0198] As described above, forming the horizontal layer HL and the storage opening 41 may include forming the second hole-type vertical opening 40 , recessing the horizontal layer 14B, and forming the second cover layer 29C.

[0199] Fig.23A is a plan view showing a method of forming the second contact node 42, and Fig. 23B is along Fig.23A A cross-sectional view taken along line AA' is shown.

[0200] Reference Fig.23A and Fig. 23B , the second doped regions 43 may be formed in the second edges of the horizontal layer HL, respectively. Forming the second doped regions 43 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped regions 43 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, after the heat treatment, the doped polysilicon may remain.

[0201] Subsequently, a second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doped region 43 may include impurities diffused from the second contact node 42.

[0202] The individual horizontal layers HL may include a first doping region 37, a second doping region 43, and a channel 44 horizontally arranged in the second direction D2. The channel 44 may be defined between the first doping region 37 and the second doping region 43. The channel 44 may vertically overlap the horizontal conductive line 35. Figures 1A to 1D As shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0203] Fig.24A is a plan view showing a method of forming the first electrode 45, and Fig. 24B is along Fig.24A A cross-sectional view taken along line AA' is shown.

[0204] Reference Fig.24A and Fig. 24B, the first electrode 45 of the data storage element may be formed on the second contact node 42. The first electrode 45 may have a horizontally oriented cylindrical shape. The first electrodes 45 may be respectively disposed in the storage openings 41. The first electrodes 45 adjacent in the second direction D2 may be spaced apart from each other by the second hole-type vertical opening 40. The first electrodes 45 adjacent in the third direction D3 may be spaced apart from each other by the second cell isolation layer 24A.

[0205] Fig.25A is a plan view showing a method of exposing the outer wall of the first electrode 45, and Fig.25B is along Fig.25A A cross-sectional view taken along line AA' is shown.

[0206] Reference Fig.25A and Fig.25B , the second dielectric layer 20 may be horizontally recessed (refer to reference numeral 46). As a result, the outer wall of the first electrode 45 may be exposed. The recessed second dielectric layer 20 may correspond to Figure 3B The inter-cell dielectric layer IL is shown.

[0207] Fig.26A is a plan view showing a method of forming the dielectric layer 47 and the second electrode 48, and Fig.26B is along Fig.26A A cross-sectional view taken along line AA' is shown.

[0208] Reference Fig.26A and Fig.26B , a dielectric layer 47 and a second electrode 48 may be sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 may form a data storage element CAP.

[0209] Each first electrode 45 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 45 may include a plurality of inner surfaces. The outer surface of the first electrode 45 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 45 may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode 45 may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode 45 may be a three-dimensional space. The dielectric layer 47 may conformally cover the inner and outer surfaces of the first electrode 45. The second electrode 48 may be disposed in the inner space of the first electrode 45 on the dielectric layer 47. Some outer surfaces of the first electrode 45 may be electrically connected to the second doped region 43 of the horizontal layer HL.

[0210] The first electrode 45 may have a cylindrical shape. The cylindrical shape of the first electrode 45 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surface of the first electrode 45 may be electrically connected to the second doping region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 may be disposed on the cylindrical inner surface of the first electrode 45. The second electrode 48 may extend vertically in the first direction D1.

[0211] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack or a combination thereof. The second electrode 48 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling an inner space of the first electrode 45, titanium nitride (TiN) may be used as a second electrode 48 of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0212] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 47 may include a high-k material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 47 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0213] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode 45 and the dielectric layer 47. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 48 and the dielectric layer 47.

[0214] According to the above-described embodiment of the present invention, since the bottom surfaces of the first and second cell isolation layers 24A and 24B are disposed at a level lower than the bottom surfaces of the vertical conductive line 39 and the data storage element CAP, pits that may occur when forming the vertical conductive line 39 and the data storage element CAP can be prevented.

[0215] Furthermore, since the cross-shaped horizontal layer HL is formed, the channel width and the bridge between the memory cells can be improved.

[0216] FIG. 27A to FIG. 27C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0217] Reference Fig.27A The stack SB10 may be formed on the lower structure 11. The stack SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack may include a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' alternately stacked by an epitaxial growth process. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 14' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4B The first layer 12A or the third layer 12B shown, and the single crystal silicon layer 14 'may correspond to Figure 4B The fourth layer 14 is shown. Figure 4B Unlike the illustrated stack SB, the stack SB10 may include an alternating stack of silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0218] Then, you can execute FIG. 4A to FIG. 5B For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B may be formed in the stacked body SB10.

[0219] Then, refer to Fig.27B , a hard mask layer pattern 17 may be formed on the stacked body SB10.

[0220] Subsequently, the stacked body SB may be etched using the hard mask layer pattern 17 as an etch barrier. As a result, a plurality of first and second sacrificial vertical openings V1 ′ and V2 ′ may be formed in the stacked body SB10 .

[0221] Reference Fig.27C, a preliminary horizontal layer 14A' and a horizontal depression 18 can be formed. The preliminary horizontal layer 14A' and the horizontal depression 18 can be formed by Fig.27B The recessing process of the silicon germanium layer 12 and the single crystal silicon layer 14' shown in FIG. After removing the silicon germanium layer 12, the recessing process of the single crystal silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 7B A preliminary horizontal layer 14A is shown.

[0222] A wet etching process or a dry etching process may be used to recess the silicon germanium layer 12. The silicon germanium layer 12 may be etched using an etchant or an etching gas having selectivity with respect to the single crystal silicon layer 14'.

[0223] The recessing process of the single crystal silicon layer 14' for forming the preliminary horizontal layer 14A' may use, for example, HSC1 (Hot SC-1). HSC1 may include a mixed solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) are mixed in a ratio of about 1:4:20. The single crystal silicon layer 14' may be selectively etched using HSC1.

[0224] After forming the preliminary horizontal layer 14A', the first sacrificial vertical opening and the second sacrificial vertical opening may be extended, as shown in the reference numerals "V1" and "V2". The preliminary horizontal layer 14A' may be spaced apart from each other by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 in the second direction D2. The preliminary horizontal layer 14A' may have a shape in which a plurality of cross shapes are merged in the third direction D3. When the preliminary horizontal layer 14A' is formed, the surface of the lower structure 11 may be recessed to a certain depth (see reference numeral "11A"). As a result, the depths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be increased.

[0225] Then, you can execute FIG. 8A to FIG. 26B A series of processes shown.

[0226] Figures 28 to 30 1 is a perspective view showing a memory cell array according to an embodiment of the present invention. The memory cell arrays MCA100, MCA200 and MCA300 may be connected to Figure 3A The memory cell array MCA shown is similar. Figure 3A For a detailed description of the constituent elements, reference can be made to the above-mentioned embodiments.

[0227] Reference Fig.28 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0228] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1, and the row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0229] The individual memory cells MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. Detailed descriptions of the first conductive line BL and the data storage element CAP may refer to the above embodiments.

[0230] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0231] The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other with the horizontal layer HL interposed therebetween. Figure 3B As shown, an interlayer dielectric layer GD may be formed on the upper and bottom surfaces of the horizontal layer HL.

[0232] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls. The flat sidewalls FS may have a linear shape extending in the third direction D3.

[0233] Reference Fig.29 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0234] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0235] The individual memory cells MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed descriptions of the first conductive line BL and the data storage element CAP, reference may be made to the above embodiments.

[0236] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0237] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed on the horizontal layer HL. Figure 3B , an interlayer dielectric layer GD may be formed between the top surface of the horizontal layer HL and the second conductive line SWL. According to another embodiment of the present invention, the second conductive line SWL may be disposed under the horizontal layer HL.

[0238] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0239] According to another embodiment of the present invention, the second wire SWL may include: Figure 1C A channel overlap portion WLP and a channel non-overlap portion NOL are shown.

[0240] Reference Fig.30 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0241] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0242] The individual memory cells MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed descriptions of the first conductive line BL and the data storage element CAP, reference may be made to the above embodiments.

[0243] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0244] The second conductive line GAA-WL may have a gate that fully surrounds the structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 and surround the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0245] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0246] According to an embodiment of the present invention, since the bottom surface of the cell isolation layer is lower than the bottom surface of the vertical conductive line, a pit that may occur when forming the vertical conductive line and the data storage element can be prevented.

[0247] According to an embodiment of the present invention, the structural stability of a memory cell may be increased by forming a support member under a vertical conductive line and a data storage element.

[0248] According to the embodiments of the present invention, low power consumption and high integration of a 3D memory cell can be achieved.

[0249] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

[0250] For example, although the described embodiments employ horizontally extending and vertically extending elements or layers, the disclosure of the present invention is not limited thereto. In some variations of this embodiment, the second direction D2 and the third direction D3 may be referred to as transverse directions defining a transverse plane, and the first direction D1 may be an upright direction extending at an orthogonal or substantially orthogonal angle above the transverse plane.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a plurality of recessed target layers over the lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers, the bottom surface of the sacrificial vertical opening being disposed at a lower level than the bottom surface of the sacrificial isolation opening; forming a preliminary horizontal layer by recessing the recess target layer through the sacrificial vertical opening; forming a sacrificial post structure filling the sacrificial vertical opening; forming a cell isolation opening by removing the sacrificial isolation layer; forming a horizontal layer by trimming the preliminary horizontal layer through the cell isolation opening; as well as A cell isolation layer filling the cell isolation opening is formed.

2. The method according to claim 1, wherein: A bottom surface of the cell isolation layer is disposed at a lower level than a bottom surface of the sacrificial post structure.

3. The method according to claim 1, wherein: When forming the horizontal layer, A bottom surface of the cell isolation opening is lowered, and a support member is formed under the sacrificial post structure.

4. The method according to claim 3, wherein: The lowered bottom surface of the cell isolation opening is disposed at a lower level than a bottom surface of the sacrificial post structure.

5. The method according to claim 1, wherein: Forming the preliminary horizontal layer includes lowering the bottom surface of the sacrificial vertical opening, and The lowered bottom surface of the sacrificial vertical opening is disposed at a higher level than a bottom surface of the sacrificial isolation layer.

6. The method according to claim 1, wherein: The recessed target layer includes a single crystal silicon layer.

7. The method according to claim 1, further comprising: Before forming the cell isolation layer, A horizontal layer-level spacer is formed on a side surface of the horizontal layer.

8. The method according to claim 1, wherein: Forming a stack including the recessed target layer includes: A plurality of sacrificial layers and the recessed target layers are alternately formed.

9. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a plurality of sub-stacks on the lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers, the bottom surface of the sacrificial vertical opening being disposed at a lower level than the sacrificial isolation opening; forming a sacrificial post structure filling the sacrificial vertical opening; forming a cell isolation opening by removing the sacrificial isolation layer; expanding the cell isolation opening to form a support member supporting the sacrificial post structure; as well as A cell isolation layer filling the expanded cell isolation opening is formed.

10. The method according to claim 9, wherein: A bottom surface of the cell isolation layer is disposed at a lower level than bottom surfaces of the sacrificial vertical opening and the sacrificial post structure.

11. The method according to claim 9, wherein: Each of the extended cell isolation openings comprises: a lower region disposed between the supports; and an upper region disposed between the sacrificial post structures, and The horizontal width of the lower region is formed to be greater than the horizontal width of the upper region.

12. The method according to claim 9, further comprising: After forming the sacrificial vertical openings, the sub-stack is replaced with a unit mold.

13. The method according to claim 12, wherein: The substack is formed by alternating sacrificial layers and recessed target layers, and Each of the unit molds comprises: Preliminary horizontal layer; a first dielectric layer covering the preliminary horizontal layer; and a second dielectric layer disposed in an upper portion and a lower portion of the first dielectric layer, and wherein the preliminary horizontal layer is formed by recessing the recess target layer, and The first dielectric layer and the second dielectric layer are formed by a replacement process of replacing the sacrificial layer with a dielectric material.

14. The method according to claim 13, further comprising: trimming the preliminary horizontal layer of the unit mold to form a horizontal layer; trimming the first dielectric layer of the unit mold to form a first dielectric layer pattern; replacing the first dielectric layer pattern with a horizontal conductive line; forming a vertical conductive line coupled to a first edge of the horizontal layer; as well as Data storage elements are formed, and the data storage elements are respectively coupled to the second edges of the horizontal layers.

15. The method according to claim 13, wherein: The first dielectric layer includes silicon nitride, and The second dielectric layer includes silicon oxide, and The recessed target layer includes a single crystal silicon layer.

16. A semiconductor device comprising: a cell isolation layer vertically oriented in a first direction; a horizontal layer horizontally oriented in a second direction intersecting the first direction and vertically stacked in the first direction between the cell isolation layers; a vertical conductive line oriented vertically in the first direction and coupled to a first edge of the horizontal layer; a horizontal conductive line that crosses each of the horizontal layers in a third direction that intersects the first direction and the second direction; data storage elements, respectively coupled to the second edges of the horizontal layers; as well as A support member is disposed under the vertical conductive line and the data storage element.

17. The semiconductor device according to claim 16, wherein: A bottom surface of the cell isolation layer is disposed at a lower level than a bottom surface of the vertical conductive line.

18. The semiconductor device according to claim 16, wherein: Each of the cell isolation layers comprises: a lower isolation region disposed between the supports; and an upper isolation region disposed between the vertical conductive lines, and The horizontal width of the lower isolation region is greater than the horizontal width of the upper isolation region.

19. The semiconductor device according to claim 16, wherein: The support member and the horizontal layer include single crystal silicon.

20. The semiconductor device according to claim 16, wherein Each horizontal conductive line includes dual structure horizontal lines facing each other, and the horizontal layers are respectively placed between the dual structure horizontal lines.

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