Semiconductor device, manufacturing method thereof and memory system
By designing a ring gate in semiconductor devices, the problem of insufficient gate control capability in conventional semiconductor devices is solved, and higher gate control capability and performance improvements are achieved.
Patent Information
- Application Number
- CN202311028019.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-21
AI Technical Summary
In conventional semiconductor devices, the gate control capability of transistors is weak and it is difficult to meet high performance requirements.
A semiconductor device is designed with a first gate surrounding the first drain and a first source surrounding the first gate, thereby forming a ring gate (ring gate) to enhance the control capability of the gate.
Through the design of the ring gate, the gate control capability is significantly improved and the performance of semiconductor devices is enhanced.
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Figure CN119497398A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art
[0002] In conventional semiconductor devices, the gate of a transistor is generally located on both sides of the source and the drain, and the gate control capability of the transistor needs to be improved. Summary of the invention
[0003] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system that can solve the above-mentioned technical problems.
[0004] To solve the above problems, the technical solutions provided by this application are as follows:
[0005] The present application provides a semiconductor device, including a first semiconductor structure, the first semiconductor structure including: a first transistor, including a first semiconductor layer and a first gate; wherein the first semiconductor layer includes a first source and a first drain, the first gate surrounds the first drain, and the first source surrounds the first gate.
[0006] In some embodiments, the first semiconductor structure further includes: a capacitor structure including a first electrode layer; a first transistor and the capacitor structure are stacked in a first direction, and one end of the first electrode layer is connected to a first gate of the first transistor.
[0007] In some embodiments, the first semiconductor structure further includes: a second transistor including a second semiconductor layer; the second transistor is located on a side of the capacitor structure away from the first transistor; and one end of the first electrode layer away from the first transistor is connected to the second semiconductor layer of the second transistor.
[0008] In some embodiments, the first drains of two adjacent first transistors are separated by a first source, and a plurality of first transistors share one first source.
[0009] In some embodiments, the first sources of two adjacent first transistors are separated by an isolation member located in the first semiconductor layer.
[0010] In some embodiments, the first semiconductor layer further includes: a first channel located between the first source and the first drain; wherein the first channel surrounds the first drain, the first source surrounds the first channel, and the orthographic projection of the first gate on the first semiconductor layer at least partially overlaps with the first channel.
[0011] In some embodiments, in the first direction, the first gate is located at one side of the first semiconductor layer.
[0012] In some embodiments, the first transistor further includes: a first gate insulating layer located on the first semiconductor layer and between the first channel and the first gate.
[0013] In some embodiments, the first gate is located within the first semiconductor layer.
[0014] In some embodiments, the first transistor further includes: a first gate insulating layer located in the first semiconductor layer and between the first gate and the first source and between the first gate and the first drain.
[0015] In some embodiments, the first semiconductor structure further includes: a first drain lead-out structure extending along the first direction and connected to the first drain; and a source lead-out structure extending along the first direction and connected to the first source.
[0016] In some embodiments, the first semiconductor structure further includes: a first insulating layer located on a side of the first semiconductor layer away from the capacitor structure; wherein the first drain lead-out structure and the source lead-out structure are located in the first insulating layer.
[0017] In some embodiments, the first semiconductor layer also includes: an initial semiconductor layer, located on a side of the first source, the first drain and the first channel away from the capacitor structure; the first semiconductor structure also includes: a first isolation layer, located in the initial semiconductor layer and extending along the first direction; the first isolation layer is arranged around the first drain lead-out structure, and the first drain lead-out structure is separated from the initial semiconductor layer by the first isolation layer; and a second isolation layer, located in the initial semiconductor layer and extending along the first direction; the second isolation layer is arranged around the source lead-out structure, and the source lead-out structure is separated from the initial semiconductor layer by the second isolation layer.
[0018] In some embodiments, the first semiconductor structure also includes: a first stacking structure, located on one side of the first semiconductor layer and covering the first gate; the first stacking structure includes a second insulating layer and a second electrode layer extending along a second direction perpendicular to the first direction, the second electrode layer is located between two adjacent second insulating layers, one of which is located on one side of the first semiconductor layer; and an energy storage structure, located in the first stacking structure; the energy storage structure includes a first electrode layer and an energy storage layer located between the second electrode layer and the first electrode layer; wherein the capacitor structure includes the second electrode layer and the energy storage structure.
[0019] In some embodiments, an orthographic projection of the first electrode layer on the first semiconductor layer covers the first drain and at least a portion of the first gate.
[0020] In some embodiments, the first semiconductor structure also includes: a second stacked structure, located on a side of the first stacked structure away from the first transistor; the second stacked structure includes a word line and a third insulating layer extending along a second direction, the word line is located between two adjacent third insulating layers, and one of the third insulating layers is connected to one of the second insulating layers; a channel structure, located in the second stacked structure and passing through the word line; wherein the channel structure includes a second semiconductor layer and a second gate insulating layer, one end of the second semiconductor layer is connected to an end of the first electrode layer away from the first gate, and the second gate insulating layer surrounds the second semiconductor layer and contacts the word line; wherein the second transistor includes a word line and a channel structure.
[0021] In some embodiments, the first semiconductor structure also includes: a second drain lead-out structure, extending along a third direction perpendicular to the first direction and intersecting the second direction and located on a side of the second semiconductor layer away from the capacitor structure; wherein a second drain lead-out structure is connected to one end of a second semiconductor layer away from the capacitor structure.
[0022] In some embodiments, the semiconductor device further includes: a second semiconductor structure having a circuit element for controlling the first semiconductor structure and located on one side of the first semiconductor structure; wherein the second semiconductor structure is bonded to the first semiconductor structure in a first direction.
[0023] The present application also provides a method for manufacturing a semiconductor device, comprising: forming a semiconductor substrate including a first source and a first drain, the first source surrounding the first drain; and forming a first gate, the first gate surrounding the first drain, and the first source surrounding the first gate in a first direction to obtain a first transistor.
[0024] In some embodiments, after the step of "forming a first gate, the first gate surrounds the first drain, and the first source surrounds the first gate in a first direction to obtain a first transistor", it also includes: forming a first stacked structure including a capacitor structure on one side of the semiconductor substrate, and the first electrode layer of the capacitor structure is connected to the first gate.
[0025] In some embodiments, after the step of forming a first stacking structure including a capacitor structure on one side of a semiconductor substrate and connecting a first electrode layer of the capacitor structure to a first gate, the step further includes: forming a second stacking structure including a second transistor on a side of the first stacking structure away from the semiconductor substrate, and connecting a second semiconductor layer of the second transistor to an end of the first electrode layer of the capacitor structure away from the first gate.
[0026] In some embodiments, in the step of forming a semiconductor substrate including a first source and a first drain, wherein the first source surrounds the first drain, the first drains of two adjacent first transistors are separated by the first source, and multiple first transistors share one first source.
[0027] In some embodiments, a first stacking structure including a capacitor structure is formed on one side of a semiconductor substrate, and the step of connecting a first electrode layer of the capacitor structure to a first gate comprises: forming a first stacking structure covering the first gate on one side of the semiconductor substrate, the first stacking structure including a second insulating layer and a second electrode layer extending in a second direction perpendicular to the first direction, the second electrode layer being located between two adjacent second insulating layers, one of the second insulating layers being located on one side of the first semiconductor layer; forming a first through hole on the first stacking structure, the first gate being exposed from the first through hole; and filling the first through hole with energy storage material and electrode material to obtain an energy storage structure including an energy storage layer and a first electrode layer, the second electrode layer surrounding the energy storage layer, the energy storage layer surrounding the first electrode layer, and the first electrode layer being connected to the first gate.
[0028] In some embodiments, the semiconductor substrate located between the first source and the first drain is a first channel; after the step of forming a second stacking structure including a second transistor on a side of the first stacking structure away from the semiconductor substrate, it also includes: removing a portion of the semiconductor substrate away from the first stacking structure to obtain a first semiconductor layer; the first semiconductor layer includes a first source, a first drain and a first channel; a first insulating layer is formed on a side of the first semiconductor layer away from the first stacking structure; and a first drain lead-out structure and a source lead-out structure extending along a first direction are formed in the first insulating layer, the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source.
[0029] In some embodiments, the semiconductor substrate located between the first source and the first drain is a first channel, and the first source, the first drain and the first channel are a first semiconductor layer; after the step of forming a second stacking structure including a second transistor on a side of the first stacking structure away from the semiconductor substrate, it also includes: forming a first drain lead-out structure and a source lead-out structure extending along a first direction on a side of the first semiconductor layer away from the first stacking structure, the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source.
[0030] In some embodiments, the semiconductor substrate other than the first semiconductor layer is an initial semiconductor layer; a first drain lead-out structure and a source lead-out structure extending along a first direction are formed on a side of the first semiconductor layer away from the first stacking structure, the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source. The steps include: forming a first isolation trench and a second isolation trench extending along a first direction in the initial semiconductor layer; filling the first isolation layer and the first drain lead-out structure in the first isolation trench, the initial semiconductor layer surrounds the first isolation layer, the first isolation layer surrounds the first drain lead-out structure, and the first drain lead-out structure is connected to the first drain; and at the same time, filling the second isolation layer and the source lead-out structure in the second isolation trench, the initial semiconductor layer surrounds the second isolation layer, the second isolation trench surrounds the source lead-out structure, and the source lead-out structure is connected to the first source.
[0031] In some embodiments, before the step of forming a first drain lead-out structure and a source lead-out structure extending along a first direction on a side of the first semiconductor layer away from the first stacking structure, the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source, the steps also include: removing the semiconductor substrate except the first semiconductor layer; and forming a first insulating layer on a side of the first semiconductor layer away from the capacitor structure; the first drain lead-out structure and the source lead-out structure are located in the first insulating layer.
[0032] The present application also provides a memory system, comprising: at least one semiconductor device as above; and a controller configured to control the semiconductor device.
[0033] The semiconductor device and its manufacturing method, and memory system provided by the present application are configured to obtain a ring gate (ring gate) by arranging the first gate of the transistor around the first drain and the first source around the first gate, thereby greatly increasing the gate control capability of the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
[0035] Figure 1 A cross-sectional view of a semiconductor structure (first transistor structure) provided for some embodiments of the present application.
[0036] Figure 2 For along Figure 1 A top view of a first transistor structure in the semiconductor structure is shown.
[0037] Figure 3 For along Figure 2A cross-sectional view of the first transistor structure along line AA' is shown.
[0038] Figure 4 A cross-sectional view of a second transistor structure provided for some other embodiments of the present application.
[0039] Figure 5 A cross-sectional view of a third transistor structure provided in some further embodiments of the present application.
[0040] Figure 6 A top view of a fourth transistor structure provided for some further embodiments of the present application.
[0041] Figure 7 For along Figure 6 A cross-sectional view taken along line BB' of the fourth transistor structure is shown.
[0042] Figure 8 A cross-sectional view of a semiconductor structure provided in the present application.
[0043] Fig. 9 A flowchart of a method for manufacturing a semiconductor device provided in the present application.
[0044] Fig.10 for Fig. 9 Flowchart of S3 is shown.
[0045] Fig.11 A cross-sectional view of an initial semiconductor structure provided in an embodiment of the present application.
[0046] Fig.12 exist Fig.11 A cross-sectional view of an initial semiconductor structure after a first stacked structure is formed is shown.
[0047] Fig.13 For Fig.11 The cross-sectional view of the first stacked structure after the first through hole is formed is shown.
[0048] Fig.14 For Fig.13 A cross-sectional view of the first through hole after an initial energy storage layer is formed therein is shown.
[0049] Fig.15 To remove Fig.14 The cross-sectional view of the portion of the initial energy storage layer after obtaining the energy storage layer is shown.
[0050] Fig.16 For Fig.15 A cross-sectional view showing a capacitor structure after a first electrode layer is formed in the first through hole.
[0051] Fig.17 For Fig.16The diagram shows a first stacked structure after a second transistor structure is formed on a side of the first stacked structure away from the semiconductor layer.
[0052] Fig.18 for Fig.17 A cross-sectional view of the channel structure shown.
[0053] Fig.19 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION
[0054] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.
[0055] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0056] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is less than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.
[0057] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.
[0058] The present application aims at the technical problem that the gate control ability of conventional semiconductor devices is relatively weak. The present application provides a semiconductor device, which includes a first semiconductor structure, the first semiconductor structure includes a first transistor, and the first transistor includes a first semiconductor layer and a first gate. The first semiconductor layer includes a first source and a first drain, the first gate surrounds the first drain, and the first source surrounds the first gate. By arranging the first gate of the transistor around the first drain and the first source around the first gate to obtain a ring gate, the gate control ability of the gate can be greatly increased.
[0059] The following will be combined Figures 1 to 8 , specifically describe the specific structure of the semiconductor structure.
[0060] See also Figures 1 to 3 Some embodiments of the present application provide a semiconductor device 100, which includes a first semiconductor structure 101. The first semiconductor structure 101 includes a first transistor 110. The first transistor 110 includes a first semiconductor layer 11 and a first gate 12. The first semiconductor layer 11 includes a first source 111 and a first drain 112. The first gate 12 surrounds the first drain 112, and the first source 111 surrounds the first gate 12.
[0061] The first gate 12 is located on one side of the first semiconductor layer 11 and is a ring gate, which can be understood as a ring gate. The ring-shaped first gate 12 has a large contact area with the corresponding channel, and the control capability is enhanced, which can greatly increase the gate control capability of the gate.
[0062] The first semiconductor layer 11 further includes a first channel 113, and the first channel 113 is located between the first source 111 and the first drain 112. The first channel 113 surrounds the first drain 112, the first source 111 surrounds the first channel 113, and the orthographic projection of the first gate 12 on the first semiconductor layer 11 at least partially overlaps with the first channel 113.
[0063] Specifically, the first semiconductor layer 11 includes a first surface 114 and a second surface 115 opposite to the first surface 114 . The first source 111 and the first drain 112 extend from the first surface 114 to the second surface 115 . The first gate 12 is located on the first surface and opposite to the first channel 113 .
[0064] In some embodiments, the first gate 12 is separated from the first semiconductor layer 11 by a first gate insulating layer 13. Specifically, the first gate insulating layer 13 is located on the first semiconductor layer 11 and between the first gate 12 and the first channel 113.
[0065] In this embodiment, the first semiconductor structure 101 further includes a first insulating layer 14 . The first insulating layer 14 is located on a side of the first semiconductor layer 11 away from the first gate 12 .
[0066] In some embodiments, the material of the first semiconductor layer 11 is at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials and other semiconductor materials. The first source 111 and the first drain 112 are formed in corresponding regions of the first semiconductor layer 11 by ion implantation, ion doping or other ion doping methods, and the region of the first semiconductor layer 11 that is not ion doped and is located between the first source 111 and the first drain 112 is the first channel 113.
[0067] In some embodiments, the material of the first gate 12 includes a conductive material, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium. In this embodiment, the material of the first gate 12 is polycrystalline silicon. The first gate 12 can be formed by a thin film deposition process.
[0068] In some embodiments, the material of the first gate insulating layer 13 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the material of the first gate insulating layer 13 is silicon oxide.
[0069] In some embodiments, the material of the first insulating layer 14 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this embodiment, the material of the first insulating layer 14 is silicon oxide.
[0070] The first semiconductor structure 101 further includes a first drain lead-out structure 15 and a source lead-out structure 16, wherein the first drain lead-out structure 15 extends along a first direction Z and is connected to the first drain 112. The source lead-out structure 16 extends along a first direction Z and is connected to the first source 111. The first drain lead-out structure 15 and the source lead-out structure 16 are located in the first insulating layer 14. In the present embodiment, the first direction Z refers to the stacking direction of the first gate 12 and the first semiconductor layer 11.
[0071] The first semiconductor layer 11 , the first gate electrode 12 , the first gate insulating layer 13 , the first insulating layer 14 , the first drain lead-out structure 15 and the source lead-out structure 16 constitute a first transistor structure 1001 .
[0072] In some embodiments, the number of the first drain lead-out structures 15 is equal to the number of the first gates 12 , and the number of the source lead-out structures 16 is equal to the number of the first sources 111 .
[0073] Please refer again Figures 2 to 3In some embodiments, the first semiconductor structure 101 includes a plurality of first transistors 110, the plurality of first transistors 110 share a first source 111, and the first drains 112 of two adjacent first transistors 110 are isolated by the first source 111 of each first transistor 110. In this embodiment, the plurality of first transistors 110 share a first source 111, and the first drains 112 of two adjacent first transistors 110 may also be isolated by the first source 111 of each first transistor 110.
[0074] Since the first drains 112 of two adjacent first transistors 110 are naturally separated by the first source 111 of each first transistor 110, there is no need to set an additional isolation member (e.g., shallow trench isolation (STI)) between the first drains 112 of the two adjacent first transistors 110, thereby avoiding the area waste caused by setting the STI, which is conducive to the miniaturization of semiconductor devices and can simplify the manufacturing process of semiconductor devices. In addition, multiple first transistors 110 share a first source 111, and the sources of adjacent devices can be naturally connected through the doped region (common gate), eliminating the need for winding.
[0075] Please continue reading Figure 1 The first semiconductor structure 101 also includes a capacitor structure 120, the capacitor structure 120 includes a first electrode layer 21, the first transistor 110 and the capacitor structure 120 are stacked in the first direction Z, and one end of the first electrode layer 21 is connected to the first gate 12 of the first transistor 110.
[0076] Specifically, the first semiconductor structure 101 further includes a first stacked structure 20, which is located on one side of the first semiconductor layer 11 and covers the first gate 12. The first stacked structure 20 includes a second insulating layer 22 and a second electrode layer 23 extending along a second direction X perpendicular to the first direction Z, wherein the second electrode layer 23 is located between two adjacent second insulating layers 22, wherein one second insulating layer 22 is located on the first semiconductor layer 11.
[0077] Specifically, the first semiconductor structure 101 further includes an energy storage structure 30, which is located in the first stacked structure 20. The energy storage structure 30 includes a first electrode layer 21 and an energy storage layer 24 located between the second electrode layer 23 and the first electrode layer 21, and the capacitor structure 120 includes the second electrode layer 23 and the energy storage structure 30.
[0078] In some embodiments, the materials of the first electrode layer 21 and the second electrode layer 23 include conductive materials, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium. The material of the insulating layer 22 includes insulating materials, such as silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the constituent material of the first electrode layer 21 is tungsten, and the material of the second electrode layer 23 is polycrystalline silicon. The material of the insulating layer 22 is silicon oxide.
[0079] In some embodiments, the material of the energy storage layer 24 includes: ferroelectric material or antiferroelectric material. Among them, the ferroelectric material has two or more possible orientations of spontaneous polarization at a finite temperature, and the orientation of this spontaneous polarization can be changed under the action of an electric field. The ions inside the lattice of the antiferroelectric material will undergo spontaneous polarization similar to that of the ferroelectric material, but unlike the ferroelectric material, the adjacent lattices inside the antiferroelectric material have spontaneous polarizations in opposite directions. For example, the material of the energy storage layer 24 can be selected from hafnium dioxide (HfO 2 ), silicon-doped hafnium dioxide (Si a (HfO 2 ) b ), aluminum-doped hafnium dioxide (Al a (HfO 2 ) b ), zirconium-doped hafnium dioxide (Zr a (HfO 2 ) b ) or zirconium oxide (ZrO), etc. Here, a and b are positive numbers. The energy storage layer 24 can be formed by a thin film deposition process, etc.
[0080] The orthographic projection of the energy storage structure 30 on the first semiconductor layer 11 at least partially overlaps with the orthographic projection of the first gate 12 on the first semiconductor layer 11 .
[0081] In some embodiments, the orthographic projection of the first electrode layer 21 on the first semiconductor layer 11 covers the first drain 112 and at least a portion of the first gate 12. The first electrode layer 21 is annular or U-shaped, and one end of the first electrode layer 21 can be directly or indirectly connected to the first gate 12. In this embodiment, the first electrode layer 21 is U-shaped.
[0082] In some embodiments, one end of the energy storage layer 24 may be connected to the first gate 12 or to a portion of the second insulating layer 22 surrounding the first gate 12. In this embodiment, one end of the energy storage layer 24 is connected to the first gate 12.
[0083] In some embodiments, the energy storage structure 30 further includes a bonding layer 25, and the bonding layer 25 is located between the energy storage layer 24 and the first electrode layer 21. It can be understood that the bonding layer 25 bonds the energy storage layer 24 and the first electrode layer 21.
[0084] In some embodiments, the orthographic projection of the bonding layer 25 on the first semiconductor layer 11 covers at least a portion of the first gate 12 or at least a portion of the first gate 12 and the first drain 112. The bonding layer 25 is annular or U-shaped, and one end of the bonding layer 25 is connected to the first gate 12.
[0085] In this embodiment, the bonding layer 25 and the first electrode layer 21 are both U-shaped, one end of the bonding layer 25 is directly connected to the first gate 12 . Accordingly, the bonding layer 25 is conductive, and one end of the first electrode layer 21 is connected to the first gate 12 through the bonding layer 25 .
[0086] In some embodiments, the bonding layer 25 is annular, and the first electrode layer 21 may be annular or U-shaped. One end of the bonding layer 25 and the first electrode layer 21 are respectively connected to the first gate 12. At this time, the bonding layer 25 may or may not be conductive.
[0087] In some embodiments, the energy storage structure 30 further includes a filling layer 26, and the filling layer 26 is located on a side of the first electrode layer 21 away from the energy storage layer 24. It can be understood that the first electrode layer 21 surrounds the filling layer 26.
[0088] In some embodiments, the number of capacitor structures 120 is the same as the number of transistors 110, and one energy storage structure 30 corresponds to one first drain 112. A portion of the second insulating layer 22 is provided between one end of the energy storage structure 30 and the corresponding first drain 112. Specifically, one end of the bonding layer 25 is located on at least a portion of the first gate 12 and at least a portion of the second insulating layer 22 located in the annular cavity of the first gate 12.
[0089] In some embodiments, the first semiconductor structure 101 also includes a second transistor 130, the second transistor 130 includes a second semiconductor layer 31, the second transistor 130 is located on a side of the capacitor structure 120 away from the first transistor 110, and the end of the first electrode layer 21 away from the first transistor 110 is connected to the second semiconductor layer 31 of the second transistor 130.
[0090] Specifically, the first semiconductor structure 101 further includes a second stacked structure 40 and a channel structure 50. The second stacked structure 40 is located on a side of the first stacked structure 20 away from the first transistor 110. The channel structure 50 is located in the second stacked structure 40.
[0091] The second stacked structure 40 includes a word line 41 and a third insulating layer 42 extending along the second direction X. The word line 41 is located between two adjacent third insulating layers 42 . One of the third insulating layers 42 is connected to one of the second insulating layers 22 .
[0092] The channel structure 50 runs through the word line 41. The channel structure 50 includes a second semiconductor layer 31 and a second gate insulating layer 51. One end of the second semiconductor layer 31 is connected to an end of the first electrode layer 21 away from the first gate 12. The second gate insulating layer 51 surrounds the second semiconductor layer 31 and contacts the word line 41. The second transistor 130 includes the word line 41 and the channel structure 50.
[0093] In some embodiments, the second semiconductor layer 31 includes a second source 311 , a second drain 312 and a second channel 313 , the second source 311 is connected to the first electrode layer 21 , and the word line 41 surrounds the second channel 313 , which can be understood as the word line 41 facing the second channel 313 from all directions.
[0094] In some embodiments, the second channel 313 is located between the second source 311 and the second drain 312. In other embodiments, the specific structure of the second channel 313 can be set according to actual conditions.
[0095] In some embodiments, the first semiconductor structure 101 further includes a second drain lead-out structure 60, which extends along a third direction Y perpendicular to the first direction Z and intersecting the second direction X and is located on a side of the second semiconductor layer 31 away from the capacitor structure 120. One second drain lead-out structure 60 is connected to one end of the second semiconductor layer 31 away from the capacitor structure 120. Specifically, one second drain lead-out structure 60 is connected to the second drain 312. The second drain lead-out structure 60 is used to read or write the stored state of the basic unit.
[0096] Specifically, in some embodiments, the second drain lead-out structure 60 is located in the third insulating layer 42 away from the capacitor structure 120. Of course, in other embodiments, the insulating layer used to protect the second drain lead-out structure 60 may also be an insulating layer independent of the third insulating layer 42.
[0097] See also Figure 4Some embodiments of the present application also provide another second transistor structure 1002, the structure of the second transistor structure 1002 is similar to that of the first semiconductor structure 101, and the difference is that the second transistor structure 1002 also includes an initial semiconductor layer 71, and the initial semiconductor layer 71 is located on the side of the first source 111, the first drain 112 and the first channel 113 away from the capacitor structure 120. It can be understood that the initial semiconductor layer 71 replaces the first insulating layer 14 of the first semiconductor structure 101. In this embodiment, the first channel 113 is integrally formed with the first source 111, the first drain 112 and the first channel 113. It can be understood that the first source 111 and the first drain 112 are formed by a part of the substrate through ion doping and other processes, the first channel 113 is a part of the substrate located between the first source 111 and the first drain 112, and the initial semiconductor layer 71 is a part of the substrate located on the side of the first source 111, the first drain 112 and the first channel 113 away from the capacitor structure 120.
[0098] In some embodiments, the second transistor structure 1002 further includes a first isolation layer 72 and a second isolation layer 73. The first isolation layer 72 is located in the initial semiconductor layer 71 and extends along the first direction Z. The first isolation layer 72 is disposed around the first drain lead-out structure 15. The first drain lead-out structure 15 is separated from the initial semiconductor layer 71 by the first isolation layer 72. The second isolation layer 73 is located in the initial semiconductor layer 71 and extends along the first direction Z. The second isolation layer 73 is disposed around the source lead-out structure 16. The source lead-out structure 16 is separated from the initial semiconductor layer 71 by the second isolation layer 73.
[0099] Compared with the first semiconductor structure 101 in which the first drain lead-out structure 15 and the source lead-out structure 16 are arranged in the first insulating layer 14, the second transistor structure 1002 in which the first drain lead-out structure 15 and the source lead-out structure 16 are arranged in the initial semiconductor layer 71 can omit the step of removing part of the semiconductor layer (substrate) located on the side of the first source 111, the first drain 112 and the first channel 113 away from the capacitor structure 120.
[0100] See also Figure 5Some embodiments of the present application also provide another third transistor structure 1003. The structure of the third transistor structure 1003 is similar to that of the second transistor structure 1002, except that the first gate 81 of the third transistor structure 1003 is located in the first semiconductor layer 11 and extends from the first surface 114 to the initial semiconductor layer 71 along the first direction Z. At this time, the first gate insulating layer 82 of the third transistor structure 1003 is located in the first semiconductor layer 11 and is located between the first gate 81 and the first source 111 and between the first gate 81 and the first drain 112. It can be understood that the first gate 81 is separated from the initial semiconductor layer 71 by the first gate insulating layer 82. The portion of the initial semiconductor layer 71 surrounding the first gate insulating layer 82 is the first channel of the third transistor structure 1003.
[0101] It can be understood that the first transistor 140 of the third transistor structure 1003 is a transistor having a recessed channel and a buried ring gate. The buried ring gate refers to a gate that is a ring gate and is located in the first semiconductor layer 11 and the initial semiconductor layer 71 together with the first channel 113. The transistor with a recessed channel and a buried ring gate can increase the effective gate length of the first gate by changing the depth of the first gate in the initial semiconductor layer 71 while keeping the length of the first gate (i.e., the distance between the first source and the first drain) unchanged, so as to improve the integration.
[0102] Correspondingly, the surface of the second insulating layer 22 of the first stacked structure 20 that contacts the first semiconductor layer 11 is a plane. The end of the energy storage structure 30 away from the second transistor 130 is located on the first gate 81 and the first drain 112. It can be understood that there is an insulating layer between the end of the energy storage structure 30 away from the second transistor 130 and the first drain 112.
[0103] See also Figure 6 and Figure 7 Some embodiments of the present application also provide another fourth transistor structure 1004. The structure of the fourth transistor structure 1004 is similar to that of the second transistor structure 1002, except that: the multiple first transistors 150 of the fourth transistor structure 1004 do not share a gate, and the first sources 111 of two adjacent first transistors 150 are separated by an isolation member 83 located in the first semiconductor layer 11 for electrical isolation.
[0104] Correspondingly, the second insulating layer 22 of the first stacked structure 20 in contact with the first semiconductor layer 11 is also located on the isolation member 83 .
[0105] See also Figure 8In some embodiments, the semiconductor device 100 further includes a second semiconductor structure 102, the second semiconductor structure 102 having a circuit element 1021 for controlling the first semiconductor structure 101 and being located on one side of the first semiconductor structure 101, and the second semiconductor structure 102 is bonded to the first semiconductor structure 101 in a first direction Z.
[0106] The circuit element 1021 may be at least one of a resistor, a capacitor, and a CMOS tube, or any combination thereof.
[0107] See also Fig. 9 The present application also provides a method for preparing a semiconductor device. To facilitate description of a specific method for preparing a semiconductor device, the following will take a method for preparing a semiconductor device including a first semiconductor device 101 as an example for description.
[0108] Specifically, see Figures 9 to 18 The present application also provides a method for preparing a semiconductor device, comprising:
[0109] Step S1, see Fig. 9 and Fig.11 , a semiconductor substrate 1011 including a first source 111 and a first drain 112 is formed, and the first source 111 surrounds the first drain 112 .
[0110] Step S1 includes: providing a semiconductor substrate 1011 , and forming a first source 111 and a first drain 112 in designated regions of the semiconductor substrate 1011 .
[0111] In some embodiments, the first source 111 and the first drain 112 may be formed in corresponding regions of the semiconductor substrate 1011 by ion implantation, ion doping, or other plasma doping methods.
[0112] In some embodiments, the constituent materials of the semiconductor substrate 1011 include: single-element semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, Silicon-On-Insulator (SOI) or other semiconductor materials known in the art. In this embodiment, the semiconductor substrate 1011 is a silicon substrate.
[0113] In some embodiments, step S1 further includes: making two adjacent first drains 112 separated by the first source 111 , and making a plurality of first drains 112 correspond to one first source 111 , so as to obtain an initial semiconductor structure 1012 .
[0114] Step S2, see Fig. 9 and Fig.11, a first gate 12 is formed in or / on the semiconductor substrate 1011 , the first gate 12 surrounds the first drain 112 , and the first source 111 surrounds the first gate 12 in a first direction, so as to obtain a first transistor 110 .
[0115] In some embodiments, a first channel 113 is further formed on the semiconductor substrate 1011, and the first channel 113 is located between the first source 111 and the first drain 112. The first channel 113 surrounds the first drain 112, the first source 111 surrounds the first channel 113, and the orthographic projection of the first gate 12 on the semiconductor substrate 1011 at least partially overlaps with the first channel 113. The first channel 113, the first source 111, and the first drain 112 are the first semiconductor layer 11, and the first gate 12 is located on the first semiconductor layer 11. The first gate 12 is separated from the first semiconductor layer 11 by a first gate insulating layer 13. Specifically, the first gate insulating layer 13 is located on the first semiconductor layer 11 and between the first gate 12 and the first channel 113.
[0116] Please refer again Figure 2 In some embodiments, the first semiconductor structure 101 includes a plurality of first transistors 110 , the plurality of first transistors 110 share a first source 111 , and the first drains 112 of two adjacent first transistors 110 are separated by the first source 111 .
[0117] Please refer again Figure 5 In some embodiments, the first transistor 140 may also be a transistor having a recessed channel and a buried ring gate.
[0118] Please refer again Figure 6-7 In some embodiments, the first sources 111 of two adjacent first transistors 150 are separated by an isolation member 83 located in the first semiconductor layer 11 for electrical isolation.
[0119] Step S3, see Fig. 9 and Figures 13 to 17 A first stacked structure 20 including a capacitor structure 120 is formed on one side of the semiconductor substrate 1011 , and a first electrode layer 21 of the capacitor structure 120 is connected to the first gate 12 .
[0120] See also Fig.10 and Figures 12 to 17 , S3 includes the following steps:
[0121] Step S31, see Fig.10 and Fig.12A first stacked structure 20 is formed on one side of the semiconductor substrate 1011 where the first gate 12 is formed. The first stacked structure 20 includes a second insulating layer 22 and a second electrode layer 23 extending along a second direction X perpendicular to the first direction Z, and the second electrode layer 23 is located between two adjacent second insulating layers 22, wherein one second insulating layer 22 is located on the first semiconductor layer 11.
[0122] Step S32, see Fig.10 and Fig.13 A first through hole 201 is formed on the first stacked structure 20 , and the first gate 12 is exposed from the first through hole 201 .
[0123] It can be understood that the first through hole 201 penetrates the first stacked structure 20. Specifically, the first through hole 201 penetrates the second insulating layers 22 and the second electrode layer 23 from a side of the first stacked structure 20 away from the first semiconductor layer 11.
[0124] In some embodiments, the second insulating layer 22 contacting the first semiconductor layer 11 and covering the first gate 12 is partially penetrated, which can be understood as that part of the second insulating layer 22 is still filled in the cavity enclosed by the first gate 12 .
[0125] Step S33, see Fig.10 and Figures 14 to 16 , energy storage material and electrode material are filled in the first through hole 201 to obtain an energy storage structure 30 including an energy storage layer 24 and a first electrode layer 21 , the second electrode layer 23 surrounds the energy storage layer 24 , the energy storage layer 24 surrounds the first electrode layer 21 , and the first electrode layer 21 is connected to the first gate 12 .
[0126] See also Fig.14 and Fig.15 In some embodiments, the formation of the energy storage layer 24 includes: first, forming an energy storage material in the first through hole 201 and on the surface of the first stacking structure 20 away from the first semiconductor layer 11 to obtain an initial energy storage layer 241; second, removing part of the initial energy storage layer 241 located on the surface of the first stacking structure 20 away from the first semiconductor layer 11 and on the bottom wall of the first through hole 201 to obtain an energy storage layer 24 located on the side wall of the first through hole 201 and connected to the second insulating layer 22 and the second electrode layer 23.
[0127] See also Fig.16 In some embodiments, step S33 further includes: forming a bonding layer 25 between the energy storage layer 24 and the first electrode layer 21 to bond the energy storage layer 24 and the first electrode layer 21. This step may be performed before forming the first electrode layer 21.
[0128] In some embodiments, the bonding layer 25 and the first electrode layer 21 are both U-shaped, one end of the bonding layer 25 is directly connected to the first gate 12 . Accordingly, the bonding layer 25 is conductive, and one end of the first electrode layer 21 is connected to the first gate 12 through the bonding layer 25 .
[0129] In some embodiments, the bonding layer 25 is annular, and the first electrode layer 21 may be annular or U-shaped. One end of the bonding layer 25 and the first electrode layer 21 are respectively connected to the first gate 12. At this time, the bonding layer 25 may or may not be conductive.
[0130] In some embodiments, after forming the first electrode layer 21, the steps are also included: forming a filling layer 26 on a side of the first electrode layer 21 away from the energy storage layer 24; and forming an electrical contact block 27 at an end of the filling layer 26 away from the semiconductor layer 11, and the electrical contact block 27 is connected to the end of the first electrode layer 21 away from the first semiconductor layer 11.
[0131] In some embodiments, the number of capacitor structures 120 is the same as the number of transistors 110, and one energy storage structure 30 corresponds to one first drain 112. A portion of the second insulating layer 22 is provided between one end of the energy storage structure 30 and the corresponding first drain 112. Specifically, one end of the bonding layer 25 is located on at least a portion of the first gate 12 and at least a portion of the second insulating layer 22 located in the annular cavity of the first gate 12.
[0132] Step S4, see Fig.11 and Figure 17 to Figure 18 A second stacked structure 40 including a second transistor 130 is formed on a side of the first stacked structure 20 away from the semiconductor substrate 1011 .
[0133] The second transistor 130 includes a second semiconductor layer 31 . The second transistor 130 is located on a side of the capacitor structure 120 away from the first transistor 110 . One end of the first electrode layer 21 away from the first transistor 110 is connected to the second semiconductor layer 31 of the second transistor 130 .
[0134] The second stacked structure 40 includes a word line 41 and a third insulating layer 42 extending along the second direction X. The word line 41 is located between two adjacent third insulating layers 42 . One of the third insulating layers 42 is connected to one of the second insulating layers 22 .
[0135] In some embodiments, step S4 includes: first, forming a second stacking structure 40 on a side of the first stacking structure 20 away from the semiconductor substrate 1011; second, forming a second through hole 401 in the second stacking structure 40, and the orthographic projection of the second through hole 401 on the first stacking structure 20 falls on the energy storage structure 30; and third, filling the second through hole 401 with a channel material to form a channel structure 50 in the second through hole 401.
[0136] See also Fig.18 , the channel structure 50 includes a second semiconductor layer 31 and a second gate insulating layer 51, one end of the second semiconductor layer 31 is connected to the end of the first electrode layer 21 away from the first gate 12, and the second gate insulating layer 51 surrounds the second semiconductor layer 31 and contacts the word line 41. Among them, the second transistor 130 includes the word line 41 and the channel structure 50. The second semiconductor layer 31 includes a second source 311, a second drain 312 and a second channel 313, the second source 311 is connected to the first electrode layer 21, and the word line 41 surrounds the second channel 313, which can be understood as the word line 41 facing the second channel 313 from all directions.
[0137] See also Fig.17 After step S4, step S5 is also included: forming a second drain lead-out structure 60 in or on the second stacked structure 40 to obtain a first semiconductor structure 101, wherein the second drain lead-out structure 60 extends along a third direction Y perpendicular to the first direction Z and intersecting the second direction X and is connected to an end of the second semiconductor layer 31 away from the capacitor structure 120.
[0138] In some embodiments, see Fig.10 and Figure 1 After step S5, the method for manufacturing a semiconductor device also includes step S6: forming a first drain lead-out structure 15 and a source lead-out structure 16 extending along the first direction Z on a side of the first semiconductor layer 141 away from the first stacked structure 20, the first drain lead-out structure 15 being connected to the first drain 112, and the source lead-out structure 16 being connected to the first source 111.
[0139] In some embodiments, see Figure 1 Before step S6, the method for manufacturing the semiconductor device also includes the steps of: removing the semiconductor substrate 1011 except the first semiconductor layer 11; and forming a first insulating layer 14 on a side of the first semiconductor layer 11 away from the capacitor structure 120; wherein the first drain lead-out structure 15 and the source lead-out structure 16 are located in the first insulating layer 14.
[0140] In some embodiments, see Figure 4Before step S6, the method for manufacturing the semiconductor device does not include the step of removing the semiconductor substrate 1011 except the first semiconductor layer 11. At this time, step S6 includes: first, forming a first isolation groove 1101 and a second isolation groove 1102 extending along the first direction Z in the initial semiconductor layer 71; secondly, filling the first isolation layer 72 and the first drain lead-out structure 15 in the first isolation groove 1101, the initial semiconductor layer 71 surrounds the first isolation layer 72, the first isolation layer 72 surrounds the first drain lead-out structure 15, and the first drain lead-out structure 15 is connected to the first drain 112; at the same time, filling the second isolation layer 73 and the source lead-out structure 16 in the second isolation groove 1102, the initial semiconductor layer 71 surrounds the second isolation layer 73, the second isolation layer 73 surrounds the source lead-out structure 16, and the source lead-out structure 16 is connected to the first source 111.
[0141] After step S6, step S7 is also included: see Figure 8 and Fig. 9 A second semiconductor structure 102 having a circuit element for controlling the first semiconductor structure 101 and bonded to the first semiconductor structure 101 is formed on one side of the first semiconductor structure 101 .
[0142] See also Fig.19 The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 as described above and a controller 200 , wherein the controller 200 is connected to the semiconductor device 100 , and the controller 200 is configured to control the semiconductor device 100 .
[0143] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.
[0144] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.
[0145] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.
[0146] The semiconductor device and its manufacturing method, and memory system provided by the present application are configured to obtain a ring gate (ring gate) by arranging the first gate of the transistor around the first drain and the first source around the first gate, thereby greatly increasing the gate control capability of the gate.
[0147] In addition, multiple first transistors share a first source, and the first drains of two adjacent first transistors are separated by the first source. There is no need to set an additional isolation member (for example, STI) between the first drains of two adjacent first transistors, thereby avoiding the waste of area caused by setting STI, which is conducive to the miniaturization of semiconductor devices and can simplify the manufacturing process of semiconductor devices. In addition, multiple first transistors share a first source, and the sources of adjacent devices can be naturally connected through the doped region (shared gate), eliminating the need for winding.
[0148] In addition, the semiconductor device and its manufacturing method, and the memory system provided by the present application use a transistor with a recessed channel and a buried ring gate. While keeping the length of the first gate (i.e., the distance between the first source and the first drain) unchanged, the effective gate length of the first gate can be increased by changing the depth of the first gate in the initial semiconductor layer 71 to improve the integration.
[0149] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.
Claims
1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: A first transistor comprising a first semiconductor layer and a first gate; The first semiconductor layer includes a first source and a first drain, the first gate surrounds the first drain, and the first source surrounds the first gate.
2. The semiconductor device according to claim 1, wherein The first semiconductor structure further comprises: A capacitor structure including a first electrode layer; The first transistor and the capacitor structure are stacked in a first direction, and one end of the first electrode layer is connected to the first gate of the first transistor.
3. The semiconductor device according to claim 2, wherein: The first semiconductor structure further comprises: A second transistor comprising a second semiconductor layer; the second transistor is located on a side of the capacitor structure away from the first transistor; One end of the first electrode layer away from the first transistor is connected to the second semiconductor layer of the second transistor.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The first drains of two adjacent first transistors are separated by the first source, and a plurality of first transistors share one first source.
5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The first sources of two adjacent first transistors are separated by an isolation member located in the first semiconductor layer.
6. The semiconductor device according to claim 2, wherein: The first semiconductor layer further comprises: A first channel, located between the first source and the first drain; The first channel surrounds the first drain, the first source surrounds the first channel, and the orthographic projection of the first gate on the first semiconductor layer at least partially overlaps with the first channel.
7. The semiconductor device according to claim 6, wherein: In the first direction, the first gate is located at one side of the first semiconductor layer.
8. The semiconductor device according to claim 7, wherein: The first transistor further includes: The first gate insulating layer is located on the first semiconductor layer and between the first channel and the first gate.
9. The semiconductor device according to claim 6, wherein: The first gate is located in the first semiconductor layer.
10. The semiconductor device according to claim 9, wherein: The first transistor further includes: The first gate insulating layer is located in the first semiconductor layer and between the first gate and the first source and between the first gate and the first drain.
11. The semiconductor device according to claim 2, wherein: The first semiconductor structure further comprises: A first drain lead-out structure extending along the first direction and connected to the first drain; and The source lead-out structure extends along the first direction and is connected to the first source.
12. The semiconductor device according to claim 11, wherein The first semiconductor structure further comprises: A first insulating layer, located on a side of the first semiconductor layer away from the capacitor structure; The first drain lead-out structure and the source lead-out structure are located in the first insulating layer.
13. The semiconductor device according to claim 11, wherein The first semiconductor layer further comprises: An initial semiconductor layer, located on a side of the first source and the first drain away from the capacitor structure; The first semiconductor structure further comprises: a first isolation layer, located in the initial semiconductor layer and extending along the first direction; the first isolation layer is disposed around the first drain lead-out structure, and the first drain lead-out structure is separated from the initial semiconductor layer by the first isolation layer; and The second isolation layer is located in the initial semiconductor layer and extends along the first direction; the second isolation layer is arranged around the source lead-out structure, and the source lead-out structure is separated from the initial semiconductor layer by the second isolation layer.
14. The semiconductor device according to claim 3, wherein: The first semiconductor structure further comprises: A first stacked structure is located on one side of the first semiconductor layer and covers the first gate; the first stacked structure includes a second insulating layer and a second electrode layer extending in a second direction perpendicular to the first direction, the second electrode layer is located between two adjacent second insulating layers, and one of the second insulating layers is located on one side of the first semiconductor layer; and An energy storage structure, located in the first stacking structure; the energy storage structure includes the first electrode layer and an energy storage layer located between the second electrode layer and the first electrode layer; Wherein, the capacitor structure includes the second electrode layer and the energy storage structure.
15. The semiconductor device according to claim 14, wherein: The orthographic projection of the first electrode layer on the first semiconductor layer covers the first drain and at least a portion of the first gate.
16. The semiconductor device according to claim 14, wherein: The first semiconductor structure further comprises: A second stacking structure is located on a side of the first stacking structure away from the first transistor; the second stacking structure comprises a word line and a third insulating layer extending along the second direction, the word line is located between two adjacent third insulating layers, and one of the third insulating layers is connected to one of the second insulating layers; a channel structure, located in the second stacked structure and passing through the word line; The channel structure includes the second semiconductor layer and a second gate insulating layer, one end of the second semiconductor layer is connected to an end of the first electrode layer away from the first gate, and the second gate insulating layer surrounds the second semiconductor layer and contacts the word line; The second transistor includes the word line and the channel structure.
17. The semiconductor device according to claim 16, wherein: The first semiconductor structure further comprises: A second drain lead-out structure, extending along a third direction perpendicular to the first direction and crossing the second direction and located at a side of the second semiconductor layer away from the capacitor structure; Wherein, one of the second drain lead-out structures is connected to one end of the second semiconductor layer away from the capacitor structure.
18. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device further comprises: A second semiconductor structure having a circuit element for controlling the first semiconductor structure and located on one side of the first semiconductor structure; The second semiconductor structure is bonded to the first semiconductor structure in the first direction.
19. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor substrate including a first source and a first drain, wherein the first source surrounds the first drain; and A first gate is formed, wherein the first gate surrounds the first drain, and the first source surrounds the first gate, so as to obtain a first transistor.
20. The method for manufacturing a semiconductor device according to claim 19, wherein: After the step of "forming a first gate, wherein the first gate surrounds the first drain, and the first source surrounds the first gate, so as to obtain a first transistor", the method further includes: A first stacked structure including a capacitor structure is formed on one side of the semiconductor substrate, and a first electrode layer of the capacitor structure is connected to the first gate.
21. The method for manufacturing a semiconductor device according to claim 20, wherein: After forming a first stacked structure including a capacitor structure on one side of the semiconductor substrate, and connecting a first electrode layer of the capacitor structure to the first gate, the method further includes: A second stacked structure including a second transistor is formed on a side of the first stacked structure away from the semiconductor substrate, and a second semiconductor layer of the second transistor is connected to an end of the first electrode layer of the capacitor structure away from the first gate.
22. The method for manufacturing a semiconductor device according to claim 19, wherein: The step of forming a semiconductor substrate including a first source and a first drain, wherein the first source surrounds the first drain, further includes: The first drains of two adjacent first transistors are separated by the first source, and a plurality of first transistors share one first source.
23. The method for manufacturing a semiconductor device according to claim 20 or 21, characterized in that: The semiconductor substrate and the capacitor structure are stacked in a first direction, a first stacked structure including the capacitor structure is formed on one side of the semiconductor substrate, and the first electrode layer of the capacitor structure is connected to the first gate comprises: A first stacked structure covering the first gate is formed on one side of the semiconductor substrate, wherein the first stacked structure includes a second insulating layer and a second electrode layer extending in a second direction perpendicular to the first direction, wherein the second electrode layer is located between two adjacent second insulating layers, and one of the second insulating layers is located on one side of the first semiconductor layer; forming a first through hole on the first stack structure, wherein the first gate is exposed from the first through hole; and The first through hole is filled with energy storage material and electrode material to obtain an energy storage structure including an energy storage layer and the first electrode layer. The second electrode layer surrounds the energy storage layer, the energy storage layer surrounds the first electrode layer, and the first electrode layer is connected to the first gate.
24. The method for manufacturing a semiconductor device according to claim 21, wherein: The semiconductor substrate located between the first source and the first drain is a first channel; After the step of forming a second stacked structure including a second transistor on a side of the first stacked structure away from the semiconductor substrate, the method further includes: Removing a portion of the semiconductor substrate away from the first stacked structure to obtain a first semiconductor layer; the first semiconductor layer includes a first source electrode, a first drain electrode and the first channel; forming a first insulating layer on a side of the first semiconductor layer away from the first stacked structure; and A first drain lead-out structure and a source lead-out structure extending along the first direction are formed in the first insulating layer, wherein the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source.
25. The method for manufacturing a semiconductor device according to claim 21, wherein: The semiconductor substrate between the first source and the first drain is a first channel, and the first source, the first drain and the first channel are a first semiconductor layer; After the step of forming a second stacked structure including a second transistor on a side of the first stacked structure away from the semiconductor substrate, the method further includes: A first drain lead-out structure and a source lead-out structure extending along the first direction are formed on a side of the first semiconductor layer away from the first stacked structure, wherein the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source.
26. The method for manufacturing a semiconductor device according to claim 25, wherein: The semiconductor substrate except the first semiconductor layer is an initial semiconductor layer; The step of forming a first drain lead-out structure and a source lead-out structure extending along the first direction on a side of the first semiconductor layer away from the first stacked structure, wherein the first drain lead-out structure is connected to the first drain, and the source lead-out structure is connected to the first source comprises: forming a first isolation trench and a second isolation trench extending along the first direction in the initial semiconductor layer; A first isolation layer and a first drain lead-out structure are filled in the first isolation trench, the initial semiconductor layer surrounds the first isolation layer, the first isolation layer surrounds the first drain lead-out structure, and the first drain lead-out structure is connected to the first drain; at the same time, a second isolation layer and a source lead-out structure are filled in the second isolation trench, the initial semiconductor layer surrounds the second isolation layer, the second isolation trench surrounds the source lead-out structure, and the source lead-out structure is connected to the first source.
27. The method for manufacturing a semiconductor device according to claim 25, wherein: Before the step of forming a first drain lead-out structure and a source lead-out structure extending along the first direction on a side of the first semiconductor layer away from the first stacked structure, wherein the first drain lead-out structure is connected to the first drain and the source lead-out structure is connected to the first source, the step further includes: removing the semiconductor substrate except the first semiconductor layer; and forming a first insulating layer on a side of the first semiconductor layer away from the capacitor structure; The first drain lead-out structure and the source lead-out structure are located in the first insulating layer.
28. A memory system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 18; and A controller is configured to control the semiconductor device.