Memory device, memory system, and method of manufacturing memory device

Abstract

The embodiment of the invention provides a memory device, a memory system and a manufacturing method of the memory device. The memory device includes a first electrode layer; the first stacking structure is located on one side of the first electrode layer and comprises first dielectric layers and plate line layers which are alternately arranged; the storage column penetrates through the first stacking structure and the first electrode layer and protrudes out of the first electrode layer, and the storage column comprises a storage function layer and an inner electrode which are sequentially arranged from outside to inside; the first channel layer covers the part, protruding out of the first electrode layer, of the storage function layer and the first electrode layer; and the second electrode is positioned on one side, far away from the first electrode layer, of the first channel layer and is electrically connected with the first channel layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a memory device, a memory system, and a method for manufacturing a memory device. Background Art

[0002] New memories (e.g., ferroelectric memories) are widely used in portable medical devices, wearable devices, IoT sensors, industrial and automotive applications, etc. due to their advantages such as high-speed interfaces, ultra-low power operation, instant non-volatile storage, and unlimited read and write cycle endurance.

[0003] In the novel memory, each memory cell may include a transistor and a capacitor unit. Currently, how to optimize the structure and performance of transistors is one of the problems that the art is committed to solving. Summary of the invention

[0004] The present application provides a memory device, a memory system, and a method for manufacturing a memory device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] In a first aspect, some embodiments of the present application provide a memory device. The memory device includes: a first electrode layer; a first stacked structure, located on one side of the first electrode layer, and including a first dielectric layer and a plate line layer alternately arranged; a storage column, which passes through the first stacked structure and the first electrode layer and protrudes from the first electrode layer, and the storage column includes a storage function layer and an inner electrode arranged in sequence from the outside to the inside; a first channel layer, covering a portion of the storage function layer protruding from the first electrode layer and the first electrode layer; and a second electrode, located on a side of the first channel layer away from the first electrode layer, and electrically connected to the first channel layer.

[0006] In some embodiments, the first electrode layer, the first channel layer, the second electrode, and portions of the inner electrode and the storage function layer protruding from the first stacked structure respectively form a transistor.

[0007] In some embodiments, the storage function layer and the inner electrode respectively correspond to a portion of a plate line layer, and the plate line layer forms a capacitor unit.

[0008] In some embodiments, the plurality of capacitor units are arranged along a stacking direction of the first stacking structure, and the plurality of capacitor units and the transistor share a storage function layer and an inner electrode.

[0009] In some embodiments, the memory device further includes a first insulating layer covering the first channel layer, wherein the second electrode passes through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with an axis of the storage pillar.

[0010] In some embodiments, the memory device also includes: a second stacking structure located on a side of the first stacking structure away from the first electrode layer, including a gate layer and a second dielectric layer located on a side of the gate layer away from the first stacking structure; and a channel structure, extending through the second stacking structure to the storage column, and including a gate dielectric layer and a second channel layer column sequentially arranged from the outside to the inside, and the second channel layer is electrically connected to the inner electrode.

[0011] In some embodiments, the memory device further includes: a second insulating layer located on a side of the second stack structure away from the first stack structure; and a bit line connection structure penetrating the second insulating layer and electrically connected to the second channel layer.

[0012] In some embodiments, the memory device further includes: a gate connection structure penetrating the second insulating layer and extending to the gate layer.

[0013] In some embodiments, a material of the second channel layer includes a semiconductor having a first conductivity type dopant, the internal electrode includes a metal pillar and a semiconductor plug, a material of the semiconductor plug includes a semiconductor having a second conductivity type dopant, and the second channel layer contacts the semiconductor plug.

[0014] In some embodiments, the material of the storage function layer includes a ferroelectric material and an antiferroelectric material.

[0015] In a second aspect, some embodiments of the present application provide a memory system, which includes: a memory device as mentioned in any of the above embodiments; and a controller coupled to the memory device and used to control the memory device to store data.

[0016] In a third aspect, some embodiments of the present application provide a method for manufacturing a memory device. The method for manufacturing the memory device includes: forming a first electrode layer and a first stacking structure on a first side of a substrate in sequence, the first stacking structure including a first dielectric layer and a plate line layer arranged alternately; forming a storage column that penetrates the first stacking structure and the first electrode layer and extends toward the substrate, the storage column including a storage function layer and an inner electrode arranged in sequence from the outside to the inside; and removing the substrate and exposing the first electrode layer and the portion of the storage function layer protruding from the first electrode layer; forming a first channel layer that covers the storage function layer protruding from the first electrode layer; and forming a second electrode electrically connected to the first channel layer.

[0017] In some embodiments, before forming a first electrode layer and a first stacking structure in sequence on the first side of the substrate, the method further includes: forming a stop layer and an insulating material layer in sequence on the first side of the substrate; wherein, forming a storage column that passes through the first stacking structure and the first electrode layer and extends toward the substrate includes: forming a storage column that passes through the first stacking structure, the first electrode layer, the insulating material layer to the stop layer in sequence.

[0018] In some embodiments, forming a storage column that sequentially passes through the first stacking structure, the first electrode layer, the insulating material layer to the stop layer includes: forming a storage hole that sequentially passes through the first stacking structure, the first electrode layer, the insulating material layer to the stop layer; and sequentially forming a storage functional layer and an internal electrode in the storage hole.

[0019] In some embodiments, removing the substrate and exposing the first electrode layer and the storage function layer protruding from the first electrode layer includes: removing the substrate, the stop layer, and the insulating material layer to expose the first electrode layer and the storage function layer protruding from the first electrode layer.

[0020] In some embodiments, forming a second electrode electrically connected to the first channel layer includes: forming a first insulating layer covering the first channel layer; and forming a second electrode passing through the first insulating layer to the first channel layer, the second electrode being at least partially aligned with the axis of the storage column.

[0021] In some embodiments, the method also includes: forming a second stacking structure on a side of the first stacking structure away from the substrate, the second stacking structure including a gate layer and a second dielectric layer located on a side of the gate layer away from the first stacking structure; and forming a channel structure that penetrates the second stacking structure to the storage column, the channel structure including a gate dielectric layer and a second channel layer arranged in sequence from the outside to the inside, and the second channel layer is electrically connected to the inner electrode.

[0022] In some embodiments, the method further includes: forming a second insulating layer on a side of the second stack structure away from the first stack structure; and forming a bit line connection structure penetrating the second insulating layer to the second channel layer.

[0023] In some embodiments, the method further includes: forming a gate connection structure penetrating the second insulating layer and extending to the gate layer.

[0024] According to at least one embodiment of the present application, the memory device, memory system, and memory device manufacturing method provided by the present application can reduce the plane occupied area by forming a structure of a memory cell including multiple capacitor units and CAA transistors. At the same time, since the CAA transistor is a closed gate structure, the gate length and gate control capability of the transistor in the memory cell can be improved. On the other hand, the CAA transistor can share the storage function layer and the inner electrode with multiple capacitor units through a self-alignment process, thereby improving the uniformity and consistency of the corresponding structure size in the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0027] Figure 2 is a circuit diagram of a storage unit provided in an embodiment of the present application;

[0028] Figure 3 is a schematic cross-sectional structural diagram of a memory device provided in an embodiment of the present application;

[0029] Figure 4 is a flow chart of a method for manufacturing a memory device provided in an embodiment of the present application; and

[0030] FIG. 5A to FIG. 5D It is a schematic diagram of the cross-sectional structure of the memory device provided in an embodiment of the present application during the manufacturing process. DETAILED DESCRIPTION

[0031] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first stacking structure discussed in this application may also be referred to as the second stacking structure, and vice versa.

[0033] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0034] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0035] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0036] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0037] In addition, when "connect" or "couple" is used in the present application, it can indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0038] Figure 1 is a block diagram of a system having a memory system provided by an embodiment of the present application. Figure 1 As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 1As shown, the system 11 may include a host 18 and a memory system 12. The memory system 12 has one or more memory devices 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the memory device 14.

[0039] In some embodiments, the controller 16 is coupled to the memory device 14 and the host 18, and is configured to control the memory device 14. For example, the controller 16 may be configured to control the memory device 14 such as read, erase, and program operations. The controller 16 may also manage data stored in the memory device 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 and one or more memory devices 14 may be integrated into one chip to constitute the memory system 12. For another example, the controller 16 and one or more memory devices 14 may be integrated into two chips respectively to constitute the memory system 12.

[0040] Figure 2 1 is a circuit diagram of a storage unit provided in an embodiment of the present application. For example, the memory device 14 may include a plurality of storage units. Figure 2 As shown, the memory cell 100 may include a first transistor T1 and a second transistor T2. For example, the first transistor T1 and the second transistor T2 may each include a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the first transistor T1 and / or the second transistor T2 may use an NMOS (N-channel metal-oxide-semiconductor transistor) tube. For another example, the first transistor T1 and / or the second transistor T2 may use a PMOS (P-channel metal-oxide-semiconductor transistor) tube. The memory cell 100 may also include at least two capacitor units C. For example, the capacitor unit C may be implemented as a ferroelectric capacitor unit. Figure 2 It is exemplarily shown that the storage unit 100 includes two capacitor units C. Of course, it may also include three capacitor units C, or more capacitor units C.

[0041] In the memory cell 100, the first electrode of the second transistor T2 is electrically connected to the second bit line BL2, and the control end of the second transistor T2 is electrically connected to the second word line WL2. The first ends of the plurality of capacitor units C are electrically connected to the second electrode of the second transistor T2, and the first ends of the plurality of capacitor units C are also electrically connected to the control end of the first transistor T1. The second end of each capacitor unit C is electrically connected to the plate line PL, respectively. The first electrode of the first transistor T1 is electrically connected to the first bit line BL1, and the second electrode of the first transistor T1 is electrically connected to the first word line WL1. For example, the first word line WL1 is a read word line, and the first bit line BL1 is a read bit line. The second word line WL2 is a write word line, and the second bit line BL2 is a write bit line. In the present application, one of the drain or source of the first transistor T1 and / or the second transistor T2 is referred to as the first electrode, and the corresponding other electrode is referred to as the second electrode, and the control end of the first transistor T1 and / or the second transistor T2 is the gate.

[0042] In this embodiment, a memory cell 100 includes a plurality of capacitor units C electrically connected to a first transistor T1 and a second transistor T2, so that a memory cell 100 can be used to store multiple bits of data to increase the storage capacity of each memory cell 100. From another perspective, the plurality of capacitor units C share two transistors T1 and T2, which can reduce the number of transistors configured in each memory cell 100 to increase storage density.

[0043] Will Figure 2 The memory cells 100 shown are arranged in an array to obtain a memory cell array. The circuit structure of each memory cell 100 is the same. Those skilled in the art can design the arrangement of the memory cells 100 and the number of the memory cells 100 in the memory cell array according to the storage capacity requirements of the memory devices in the memory system.

[0044] Figure 3 1 is a schematic diagram of a cross-sectional structure of a memory device provided in an embodiment of the present application. For example, the memory device may be the memory device 14 (refer to Figure 1 ). It should be noted that in the following, the x direction, y direction, and z direction in each figure show the spatial relationship of the components in the memory device. For example, the z direction is the stacking direction of the first stacking structure, and the x direction and the y direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the memory device.

[0045] like Figure 3As shown, the memory device 200 includes a first electrode layer 211. For example, the first electrode layer 211 may extend laterally in a plane perpendicular to the z-direction. Exemplarily, the material of the first electrode layer 211 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0046] The memory device 200 may further include a first stacked structure 221 located on one side (e.g., the surface) of the first electrode layer 211. The first stacked structure 221 includes first dielectric layers 222 and plate line layers 223 that are alternately arranged. For example, the material of the first dielectric layer 222 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, the material of the plate line layer 223 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material. In the first stacked structure 221, the thickness of each of the multiple first dielectric layers 222 may be the same or different, and the thickness of each of the multiple plate line layers 223 may be the same or different. The thickness of the first dielectric layer 222 and the plate line layer 223 can be selected according to actual needs. In addition, Figure 3 It is exemplarily shown that the first stacking structure 221 includes two board line layers 223. In an optional embodiment, the first stacking structure 221 may also include three board line layers 223, or more board line layers 223, and the present application does not impose any specific limitation on this.

[0047] The memory device 200 further includes a storage pillar 231. The storage pillar 231 penetrates the first stacked structure 221 and the first electrode layer 211, and protrudes from the first electrode layer 211. For example, the storage pillar 231 may have an outer contour that is approximately cylindrical, and sequentially penetrates the first stacked structure 221 and the first electrode layer 211, for example, along the z direction, and extends from the first electrode layer 211. The storage pillar 231 includes a storage function layer 232 and an inner electrode 233 that are sequentially arranged from the outside to the inside. For example, the storage function layer 232 may be a tubular structure with one end closed, and the closed end of the storage function layer 232 may be an end extending from the first electrode layer 211. The inner electrode 233 may be embedded inside the storage function layer 232 and contact the storage function layer 232.

[0048] In some embodiments, the inner electrode 233 may include a metal pillar 2331 and a semiconductor plug 2332. For example, the metal pillar 2331 may extend in the z direction to occupy the inner space of the storage function layer 232. The semiconductor plug 2332 may be located at the end of the metal pillar 2331 away from the first electrode layer 211. In some examples, the sidewall of the semiconductor plug 2332 is in contact with the metal layer 2331. In other examples, the sidewall of the semiconductor plug 2332 is in contact with the storage function layer 232 (not shown). For example, the material of the metal pillar 2331 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. The material of the semiconductor plug 2332 may be one or more of polycrystalline silicon (poly-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material. Optionally, a dopant may be added to the material of the semiconductor plug 2332. For example, the conductivity type of the dopant may be N-type or P-type, so that the semiconductor plug 2332 is N-type conductive or P-type conductive. In other embodiments, the inner electrode 233 may have other internal structures. For example, the inner electrode 233 may be composed of a conductive layer in contact with the storage function layer 232 and an insulating column located inside the conductive layer (not shown), which is not specifically limited in the present application.

[0049] In some embodiments, the material of the storage function layer 232 may be a ferroelectric material. Ferroelectric materials may include zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2 and one or more of other elements doped based on ferroelectric materials. When an electric field is applied to the ferroelectric material layer, the central atoms stop at a low energy state along the electric field. Conversely, when the electric field is reversed and applied to the ferroelectric material layer, the central atoms move in the crystal along the direction of the electric field and stop at another low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of the electric field. The polarization charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarization charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. The binary stable state of this ferroelectric material enables it to be used as the storage function layer 232 to store logical information. In other embodiments, the material of the storage function layer 232 may be an antiferroelectric material. The antiferroelectric material may include lead zirconate (PbZrO3), lead hafnium oxide (PbHfO3), sodium niobate (NaNbO3), ammonium dihydrogen phosphate (NH4H2PO4), ammonium iodate (NH4IO3), tungsten trioxide (WO3), etc. Antiferroelectric materials have better stability, and their application in memory devices will have better data retention characteristics. For example, when the material of the storage function layer 232 is a ferroelectric material or an antiferroelectric material, the memory device 200 may be called a ferroelectric random access memory (FeRAM). It should be noted that the ferroelectric material and antiferroelectric material described above also have insulating properties.

[0050] Continue to refer Figure 3 , the memory device 200 further includes a first channel layer 241. The first channel layer 241 covers the portion of the storage function layer 232 protruding from the first electrode layer 211 and the first electrode layer 211. The material of the first channel layer 241 may be one or more of polysilicon (poly-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other appropriate semiconductor material. The memory device 200 may further include a second electrode 242. The second electrode 242 is located on a side of the first channel layer 241 away from the first electrode layer 211 and is electrically connected to the first channel layer 241. For example, the second electrode 242 may have a substantially columnar outer profile and contact the first channel layer 241. The material of the second electrode 242 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other appropriate conductive material.

[0051] In some embodiments, the memory device 200 may further include a first insulating layer 243. The first insulating layer 243 covers the first channel layer 241. For example, the material of the first insulating layer 243 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The second electrode 242 passes through the first insulating layer 243 to the first channel layer 241 to contact the first channel layer 241, so that the second electrode 242 is electrically connected to the first channel layer 241. The second electrode 242 may be at least partially aligned with the axis of the storage column 231. For example, in the case where the second electrode 242 is substantially columnar, the axis of the second electrode 242 substantially coincides with the axis of the storage column 231.

[0052] In some embodiments, the first electrode layer 211, the first channel layer 241, the second electrode 242, and the inner electrode 233 and the memory function layer 232 protrude from the first stacked structure 221 to form a first transistor T1. For example, a portion of the first electrode layer 211 in contact with the first channel layer 241 may serve as a second electrode (e.g., a source) of the first transistor T1, and the rest of the first electrode layer 211 may serve as a first word line WL1 (see Figure 2 ). The portion of the inner electrode 233 protruding from the first stacked structure 221 can serve as the control terminal (e.g., gate) of the first transistor T1. The portion of the storage function layer 232 protruding from the first stacked structure 221 can serve as the gate dielectric layer of the first transistor T1. The second electrode 242 can serve as the first electrode (e.g., drain) of the first transistor T1. In the first transistor T1, the first channel layer 241 surrounds the outer side of the portion of the inner electrode 233 protruding from the first stacked structure 221 to increase the gate length and gate control capability. The first transistor T1 can be a Channel-All-Around Field-Effect Transistor (CAA FET).

[0053] In some embodiments, the portion of the storage function layer 232 and the inner electrode 233 respectively surrounded by a plate line layer 223, and the portion of the plate line layer 223 in contact with the storage function layer 232 constitute a capacitor unit C. The portion of the inner electrode 233 surrounded by the plate line layer 223 serves as a first end of the capacitor unit C, the portion of the plate line layer 223 in contact with the storage function layer 232 serves as a second end of the capacitor unit C, and the rest of the plate line layer 223 serves as a plate line PL (refer to Figure 2 ).

[0054] In some embodiments, a plurality of (e.g., two) capacitor units C are arranged along the z direction. The first ends of the capacitor units C share the inner electrode 233 to achieve electrical connection with each other, and the first ends of the capacitor units C also share the inner electrode 233 with the control end of the first transistor T1 to achieve electrical connection with the control end of the first transistor T1.

[0055] According to the above embodiments, the present application provides a structure of a memory cell including a plurality of capacitor units and a CAA transistor. The memory cell can reduce the plane occupied area. At the same time, since the CAA transistor is a closed gate structure, the gate length and gate control capability of the transistor in the memory cell can be improved. On the other hand, the CAA transistor can share the storage function layer and the inner electrode with the plurality of capacitor units through a self-alignment process, thereby improving the uniformity and consistency of the corresponding structure size in the transistor.

[0056] In some embodiments, the memory device 200 may further include a second stacked structure 251. The second stacked structure 251 may be located on a side of the first stacked structure 221 away from the first electrode layer 211, and include a gate layer 253 and two second dielectric layers 252 located on opposite sides of the gate layer 253. For example, the two second dielectric layers 252 may include a second dielectric layer 252 on a side of the gate layer 253 away from the first stacked structure 221 and a second dielectric layer 252 on a side of the gate layer 253 close to the first stacked structure 221. Exemplarily, the material of the second dielectric layer 252 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the gate layer 253 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material. In the case where the second dielectric layer 252 and the first dielectric layer 222 are made of the same material, there may be no obvious interface between the two.

[0057] In some embodiments, the memory device 200 further includes a channel structure 261. The channel structure 261 may penetrate the second stacked structure 251 to the storage column 231 to be connected to the storage column 231. The channel structure 261 may include a gate dielectric layer 262 and a second channel layer 263 arranged sequentially from the outside to the inside. Among them, the second channel layer 263 is electrically connected to the inner electrode 233, for example, by contacting with the semiconductor plug 2332 to achieve electrical connection. Exemplarily, the channel structure 261 may have an outer contour that is approximately cylindrical. The gate dielectric layer 262 may be approximately a tubular structure with openings at both ends, and the second channel layer 263 may be located on the inner side of the gate dielectric layer 262. In other words, the gate dielectric layer 262 surrounds the outer sidewall of the second channel layer 263. In some examples, the second channel layer 263 may be approximately a columnar structure. In other examples, the second channel layer may be approximately a tubular structure, and an insulating column (not shown) is disposed inside it. For example, the material of the gate dielectric layer 262 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, the material of the second channel layer 263 may be one or more semiconductor materials such as polycrystalline silicon (Poly-Si), amorphous silicon (α-Si), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO), etc. Optionally, a dopant may be added to the material of the second channel layer 263. For example, the conductivity type of the dopant may be N-type or P-type, so that the second channel layer 263 is N-type conductive or P-type conductive.

[0058] In some embodiments, the second channel layer 263, the gate dielectric layer 262, and a portion of the gate layer 253 in contact with the gate dielectric layer 262 may constitute a second transistor T2. The second transistor T2 may be a vertical channel transistor. For example, the end of the second channel layer 263 away from the storage column 231 may serve as the first electrode of the second transistor T2, the semiconductor plug 2332 may serve as the second electrode of the second transistor T2, a portion of the gate layer 253 in contact with the gate dielectric layer 262 may serve as the gate of the second transistor T2, and the rest of the gate layer 253 may serve as the second word line WL2. The second transistor T2, the first transistor T1 described above, and the plurality of capacitor units C may constitute a storage unit.

[0059] In some embodiments, the conductivity type of the dopant doped into the material of the second channel layer 263 may be different from the conductivity type of the dopant doped into the material of the semiconductor plug 2332. For example, the material of the second channel layer 263 may be polysilicon with a first conductivity type dopant. The material of the semiconductor plug 2232 may be polysilicon with a second conductivity type dopant. Alternatively, the first conductivity type dopant may include boron (B), and the second conductivity type dopant may include phosphorus (P), so that the second transistor T2 may be an NMOS tube.

[0060] In some embodiments, the memory device 200 may further include a second insulating layer 271 and a bit line connection structure 272. The second insulating layer 271 may be located on a side (e.g., a surface) of the second stacked structure 251 away from the first stacked structure 221. The bit line connection structure 272 may penetrate the second insulating layer 271 and be electrically connected to (e.g., in contact with) the second channel layer 263. For example, the bit line connection structure 272 may be a roughly columnar structure. The bit line connection structure 272 may be used to lead the second channel layer 263 out from the z direction to connect to the second bit line (not shown). Exemplarily, the material of the bit line connection structure 272 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0061] In some embodiments, the memory device 200 may further include a gate connection structure 273. The gate connection structure 273 may penetrate the second insulating layer 271 and extend to the gate layer 253. For example, the gate connection structure 273 may be a substantially columnar structure. The gate connection structure 273 may be used to lead the gate layer 253 out from the z direction. Exemplarily, the material of the gate connection structure 273 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0062] An embodiment of the present application also provides a method for manufacturing a memory device. Figure 4 FIG. 1 is a flow chart of a method for manufacturing a memory device provided in an embodiment of the present application. Figure 4 As shown, a method 300 for manufacturing a memory device (hereinafter referred to as manufacturing method 300 ) may include the following steps.

[0063] S310, forming a first electrode layer and a first stacking structure in sequence on a first side of a substrate, wherein the first stacking structure includes first dielectric layers and board line layers that are alternately arranged.

[0064] S320, forming a storage column that penetrates the first stacked structure and the first electrode layer and extends toward the substrate, wherein the storage column includes a storage function layer and an inner electrode that are sequentially arranged from the outside to the inside.

[0065] S330, removing the substrate, and exposing the first electrode layer and a portion of the storage function layer protruding from the first electrode layer.

[0066] S340, forming a first channel layer that covers the storage function layer and protrudes from the first electrode layer.

[0067] S350 , forming a second electrode electrically connected to the first channel layer.

[0068] According to the manufacturing method of the memory device provided by this embodiment, by removing the substrate and exposing the first electrode layer and the portion of the storage function layer protruding from the first electrode layer, and forming the first channel layer and the second electrode, a structure of a memory cell including a plurality of capacitor units and a CAA transistor can be formed by a self-alignment process, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor. In addition, the memory cell can reduce the plane occupied area. At the same time, since the CAA transistor is a closed gate structure, the gate length and gate control capability of the transistor in the memory cell can be improved.

[0069] FIG. 5A to FIG. 5D is a schematic diagram of a cross-sectional structure of a memory device provided in an embodiment of the present application during the manufacturing process. For example, the intermediate structure of the memory device in the manufacturing process of this embodiment can be based on Figure 4 The manufacturing method shown is formed and used to form Figure 3 The memory device 200 is shown. FIG. 5A to FIG. 5D as well as Figure 3 The above-mentioned steps S310 to S350 are described.

[0070] In step S310, Figure 5A As shown, a first dielectric layer 222 and a board line layer 223 may be alternately formed on a first side of a substrate 212 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, thereby forming a first stacked structure 221.

[0071] In some embodiments, the substrate 212 may be used to support the first stacked structure 221. For example, the substrate 212 may be a semiconductor substrate. For example, the material of the substrate 212 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). For example, the substrate 212 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc.

[0072] In some embodiments, before forming the first electrode layer 211 and the first stacked structure 221, the manufacturing method 200 may further include the step of sequentially forming a stop layer 213 and an insulating material layer 214 on the first side of the substrate 212. Exemplarily, the stop layer 213 and the insulating material layer 214 may be formed before the substrate 212 and the first stacked structure 221 by using a thin film deposition process of CVD, PVD, ALD or any combination thereof. For example, the stop layer 213 is in contact with the substrate 212 and the insulating material layer 214, respectively, and the insulating material layer 214 is in contact with the stop layer 213 and the first stacked structure 221 (for example, the first dielectric layer 222), respectively. The material of the stop layer 213 and the material of the insulating material layer 214 are different from each other, so that the two have different etching selectivities with respect to the same etching material. For example, the material of the insulating material layer 214 may be silicon oxide (SiO2), and the material of the stop layer 213 may be silicon nitride (Si3N4). In addition, the thickness of the insulating material layer 214 may be determined according to the second transistor T2 to be formed (reference Figure 3 ) is adjusted according to actual needs of the gate length of the second transistor T2, and the present application does not impose any specific restrictions on the thickness of the insulating material layer 214. In other words, the gate length of the second transistor T2 can be controlled by controlling the thickness of the insulating material layer 214, and the process steps are simple.

[0073] In step S320, continue to refer to Figure 5A The storage pillar 231 that penetrates the first stacked structure 221 and the first electrode layer 211 and extends toward the substrate 212 (for example, the z direction) can be formed by photolithography and etching processes and thin film deposition processes. The storage pillar 231 includes a storage function layer 232 and an inner electrode 233 that are sequentially arranged from the outside to the inside.

[0074] In some embodiments, in the case where the insulating material layer 214 having the stop layer 213 is formed on the first side of the substrate 212, the storage pillar 231 may sequentially penetrate the first stacked structure 221, the first electrode layer 211, the insulating material layer 214 to the stop layer 213. Exemplarily, the storage pillar 231 may be formed by the manufacturing method described below. First, a storage hole (corresponding to the outer contour of the storage pillar 231) that sequentially penetrates the first stacked structure 221, the first electrode layer 211, the insulating material layer 214 to the stop layer 213 may be formed by photolithography and etching (e.g., dry etching or wet etching) processes. Next, a storage function layer 232 may be formed on the inner wall of the storage hole by a thin film deposition process of CVD, PVD, ALD, or any combination thereof, and an inner electrode 233 may be formed on the inner side of the storage function layer 232. Optionally, in the process of forming the internal electrode 233, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be first used to fill a metal material inside the storage function layer 232 to form a metal pillar 2331. Then, the metal pillar 2331 is etched back to remove a portion away from the substrate 212, so as to form a semiconductor plug 2332 at the end of the metal pillar 2331 away from the substrate 212, thereby forming the internal electrode 233.

[0075] In some embodiments, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a second stack structure 251 on a side of the first stack structure 221 away from the substrate 212. The second stack structure 251 may include a gate layer 253 and a second dielectric layer 252 located on a side of the gate layer 253 away from the first stack structure 221. For example, a second dielectric layer 252, a gate layer 253, and another second dielectric layer 252 may be sequentially formed on a surface of the first stack structure 221 away from the substrate 212, such that the second dielectric layer 252 is located on opposite sides of the gate layer 253.

[0076] In some embodiments, a channel structure 261 that passes through the second stacked structure 251 to the storage column 231 may be formed by photolithography and etching processes and thin film deposition processes. The channel structure 261 may include a gate dielectric layer 262 and a second channel layer 263 that are sequentially arranged from the outside to the inside, and the second channel layer 263 is electrically connected (e.g., in contact) with the internal electrode 233 (e.g., semiconductor plug 2332). Exemplarily, the channel structure 261 may be formed by the manufacturing method described below. First, a channel hole (corresponding to the outer contour of the channel structure 261) that passes through the second stacked structure 251 to the storage column 231 may be formed by photolithography and etching (e.g., dry etching or wet etching) processes. Next, a gate dielectric layer 262 may be formed on the sidewall of the channel hole by a thin film deposition process of CVD, PVD, ALD, or any combination thereof, and a second channel layer 263 may be formed on the inner side of the gate dielectric layer 262. As an option, a second channel layer may be formed on the sidewall of the gate dielectric layer 262 , and an insulating pillar (not shown) may be formed inside the second channel layer.

[0077] In some embodiments, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a second insulating layer 271 on a side of the second stacked structure 251 away from the first stacked structure 221. Further, a photolithography and etching process and a thin film deposition process may be used to form a bit line connection structure 272 that penetrates the second insulating layer 271 to the second channel layer 263. Optionally, a photolithography and etching process and a thin film deposition process may also be used to form a gate connection structure 273 that penetrates the second insulating layer 271 and extends to the gate layer 253.

[0078] In step S330, Figure 5A and Figure 5B As shown, an etching (eg, wet etching and / or dry etching) process may be used to remove the substrate 212 and expose the first electrode layer 211 and a portion of the storage function layer 232 in the storage pillar 231 protruding from the first electrode layer 211 .

[0079] In some embodiments, when an insulating material layer 214 having a stop layer 213 is formed on the first side of the substrate 212, after removing the substrate 212, an etching (e.g., wet etching and / or dry etching) process can be used to further remove the stop layer 213 and the insulating material layer 214 to expose the first electrode layer 211 and the portion of the storage function layer 232 protruding from the first electrode layer 211.

[0080] In step S340, if Figure 5B and Figure 5CAs shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a first channel layer 241 that covers the storage function layer 232 and protrudes from the first electrode layer 211. For example, the first channel layer 241 also covers the surface of the first electrode layer 211.

[0081] In step S350, Figure 3 As shown, a second electrode 242 electrically connected to (eg, in contact with) the first channel layer 241 may be formed by photolithography and etching processes and thin film deposition processes. For example, the second electrode 242 may be formed by the manufacturing method described below. First, as Figure 5C and Figure 5D As shown, a first insulating layer 243 covering the first channel layer 241 may be formed by a thin film deposition process of CVD, PVD, ALD or any combination thereof. Next, a contact hole (corresponding to the outer contour of the second electrode 242) passing through the first insulating layer 243 to the first channel layer 241 may be formed by a photolithography and etching (e.g., dry etching or wet etching) process, wherein the contact hole is at least partially aligned with the axis of the storage pillar 231. For example, the axis of the contact hole substantially coincides with the axis of the storage pillar 231. Then, one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other appropriate conductive material is filled in the contact hole to form the second electrode 242.

[0082] It should be noted that the steps of forming the second stacked structure 251 , the second insulating layer 271 , the bit line connection structure 272 and the gate connection structure 273 described above may be formed after forming the second electrode 242 , and the present application does not impose any specific limitation on this.

[0083] In this embodiment, by removing the substrate and exposing the first electrode layer and the portion of the storage function layer protruding from the first electrode layer, and forming the first channel layer and the second electrode, a structure of a storage unit including a plurality of capacitor units and a CAA transistor can be formed by a self-alignment process, thereby improving the uniformity and consistency of the corresponding structural dimensions in the transistor. In addition, the storage unit can reduce the plane occupied area. At the same time, since the CAA transistor is a closed gate structure, the gate length and gate control capability of the transistor in the storage unit can be improved.

[0084] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A memory device, characterized in that: include: a first electrode layer; A first stacked structure, located on one side of the first electrode layer, and comprising first dielectric layers and plate line layers alternately arranged; a storage column, which penetrates the first stacked structure and the first electrode layer and protrudes from the first electrode layer, wherein the storage column comprises a storage function layer and an inner electrode which are sequentially arranged from the outside to the inside; a first channel layer, covering a portion of the storage function layer protruding from the first electrode layer and the first electrode layer; as well as The second electrode is located on a side of the first channel layer away from the first electrode layer and is electrically connected to the first channel layer.

2. The memory device according to claim 1, wherein: The first electrode layer, the first channel layer, the second electrode, and portions of the inner electrode and the storage function layer protruding from the first stacked structure respectively form transistors.

3. The memory device according to claim 2, wherein: The storage function layer and the inner electrode respectively correspond to a portion of a plate line layer, and the plate line layer forms a capacitor unit.

4. The memory device according to claim 3, wherein: The plurality of capacitor units are arranged along a stacking direction of the first stacking structure, and the plurality of capacitor units and the transistor share the storage function layer and the inner electrode.

5. The memory device according to claim 1, wherein: It also includes a first insulating layer covering the first channel layer, wherein the second electrode passes through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with the axis of the storage column.

6. The memory device according to claim 1, wherein: Also includes: A second stacking structure, located on a side of the first stacking structure away from the first electrode layer, comprising a gate layer and a second dielectric layer located on a side of the gate layer away from the first stacking structure; as well as The channel structure penetrates the second stack structure to the storage column and includes a gate dielectric layer and a second channel layer arranged in sequence from the outside to the inside, and the second channel layer is electrically connected to the inner electrode.

7. The memory device according to claim 6, wherein: Also includes: a second insulating layer, located on a side of the second stacking structure away from the first stacking structure; as well as A bit line connection structure penetrates the second insulating layer and is electrically connected to the second channel layer.

8. The memory device according to claim 7, wherein: Also includes: A gate connection structure penetrates the second insulating layer and extends to the gate layer.

9. The memory device according to claim 6, wherein: The material of the second channel layer includes a semiconductor having a first conductive type dopant, the internal electrode includes a metal pillar and a semiconductor plug, the material of the semiconductor plug includes a semiconductor having a second conductive type dopant, and the second channel layer contacts the semiconductor plug.

10. The memory device according to any one of claims 1 to 9, wherein: The material of the storage function layer includes ferroelectric material and antiferroelectric material.

11. A memory system, characterized in that: include: The memory device according to any one of claims 1 to 10; as well as The controller is coupled to the memory device and is used to control the memory device to store data.

12. A method for manufacturing a memory device, characterized in that: include: Sequentially forming a first electrode layer and a first stacking structure on a first side of the substrate, wherein the first stacking structure includes first dielectric layers and plate line layers that are alternately arranged; forming a storage column penetrating the first stacked structure and the first electrode layer and extending toward the substrate, wherein the storage column comprises a storage function layer and an inner electrode arranged in sequence from outside to inside; as well as removing the substrate, and exposing the first electrode layer and a portion of the storage function layer protruding from the first electrode layer; forming a first channel layer covering the storage function layer and protruding from the first electrode layer; as well as A second electrode electrically connected to the first channel layer is formed.

13. The manufacturing method according to claim 12, wherein: Before sequentially forming the first electrode layer and the first stacked structure on the first side of the substrate, the method further includes: forming a stop layer and an insulating material layer in sequence on the first side of the substrate; Wherein, forming a storage column that penetrates the first stacked structure and the first electrode layer and extends toward the substrate includes: The storage column is formed to sequentially penetrate the first stacked structure, the first electrode layer, the insulating material layer to the stop layer.

14. The manufacturing method according to claim 13, wherein: Forming the storage column sequentially penetrating the first stacked structure, the first electrode layer, the insulating material layer to the stop layer comprises: forming a storage hole sequentially penetrating the first stacked structure, the first electrode layer, the insulating material layer and the stop layer; The memory function layer and the inner electrode are sequentially formed in the memory hole.

15. The manufacturing method according to claim 13, wherein: Removing the substrate and exposing the first electrode layer and a portion of the storage function layer protruding from the first electrode layer comprises: The substrate, the stop layer, and the insulating material layer are removed to expose the first electrode layer and a portion of the storage function layer protruding from the first electrode layer.

16. The manufacturing method according to claim 12, wherein: Forming a second electrode electrically connected to the first channel layer includes: forming a first insulating layer covering the first channel layer; and The second electrode is formed through the first insulating layer to the first channel layer, and the second electrode is at least partially aligned with the axis of the storage pillar.

17. The manufacturing method according to claim 12, wherein: Also includes: forming a second stacked structure on a side of the first stacked structure away from the substrate, the second stacked structure comprising a gate layer and a second dielectric layer located on a side of the gate layer away from the first stacked structure; as well as A channel structure is formed that penetrates the second stack structure to the storage column, wherein the channel structure includes a gate dielectric layer and a second channel layer that are sequentially arranged from the outside to the inside, and the second channel layer is electrically connected to the inner electrode.

18. The manufacturing method according to claim 17, wherein: Also includes: forming a second insulating layer on a side of the second stacking structure away from the first stacking structure; as well as A bit line connection structure is formed that penetrates the second insulating layer to the second channel layer.

19. The manufacturing method according to claim 18, wherein: Also includes: A gate connection structure is formed which penetrates the second insulating layer and extends to the gate layer.

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