Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a first conductive line; a second conductive line over the first conductive line, in which the first conductive line and the second conductive line extend in different directions intersecting each other; a variable resistance pattern between the first conductive line and the second conductive line; a first electrode pattern between the first conductive line and the variable resistance pattern; a first resistivity barrier pattern between the first conductive line and the first electrode pattern; and a first diffusion barrier pattern between the first resistivity barrier pattern and the first electrode pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0108007, filed on August 18, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to electronic devices and methods of manufacturing the electronic devices, and more particularly, to semiconductor devices and methods of manufacturing the semiconductor devices. Background Art

[0004] The degree of integration of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the degree of integration of a semiconductor device for forming a memory cell in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. In addition, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. Summary of the invention

[0005] In one embodiment, a semiconductor device may include: a first conductive line; a second conductive line located above the first conductive line, wherein the first conductive line and the second conductive line extend in different directions intersecting each other; a variable resistance pattern located between the first conductive line and the second conductive line; a first electrode pattern located between the first conductive line and the variable resistance pattern; a first resistivity barrier pattern located between the first conductive line and the first electrode pattern; and a first diffusion barrier pattern located between the first resistivity barrier pattern and the first electrode pattern.

[0006] In one embodiment, a method for manufacturing a semiconductor device may include: forming a first resistivity barrier layer above a first conductive layer; forming a first diffusion barrier layer above the first resistivity barrier layer; forming a first electrode layer above the first diffusion barrier layer; forming a variable resistance layer above the first electrode layer; forming a second electrode layer above the variable resistance layer; and forming a second conductive layer above the second electrode layer.

[0007] In one embodiment, a manufacturing method may include: forming a first conductive layer; forming a first resistivity barrier layer above the first conductive layer; forming a first diffusion barrier layer above the first resistivity barrier layer; forming a first electrode layer above the first diffusion barrier layer; forming a variable resistance layer above the first electrode layer; forming a second electrode layer above the variable resistance layer; forming a memory line by etching the second electrode layer, the variable resistance layer and the first electrode layer in a first direction, the memory line including a second electrode line, a variable resistance line and a first electrode line; forming a first diffusion barrier line and a first resistivity barrier line by etching the first diffusion barrier layer and the first resistivity barrier layer in the first direction; forming a second conductive layer above the memory line; forming a second conductive line by etching the second conductive layer in a second direction intersecting the first direction; forming a memory cell by etching the memory line in the second direction, the memory cell including a second electrode pattern, a variable resistance pattern and a first electrode pattern; and forming a first diffusion barrier pattern and a first resistivity barrier pattern by etching the first diffusion barrier line and the first resistivity barrier line in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and Figure 1B A semiconductor device according to one embodiment is illustrated.

[0009] Figure 2A and Figure 2B A semiconductor device according to another embodiment is illustrated.

[0010] Figure 3A and Figure 3B Each illustrates a semiconductor device according to yet another embodiment.

[0011] Figure 4 A method for manufacturing a semiconductor device according to an embodiment is illustrated.

[0012] FIG. 5A to FIG. 9B A method for manufacturing a semiconductor device according to an embodiment is illustrated. DETAILED DESCRIPTION

[0013] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0014] According to the present technology, a semiconductor device having a stable structure and improved reliability can be provided.

[0015] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0016] Figure 1A and Figure 1B A semiconductor device according to one embodiment is illustrated. Figure 1Ais a plan view, and Figure 1B is along Figure 1A A cross-sectional view taken along line AA'.

[0017] refer to Figure 1A and Figure 1B , the semiconductor device may include a first conductive line 110, a second conductive line 190, a memory cell MC, or a combination thereof, over a substrate (not shown). The semiconductor device may also include a first gap-filling pattern GFP1, a second gap-filling pattern GFP2, a first resistivity barrier pattern 120, a first diffusion barrier pattern 130, a second resistivity barrier pattern 180, a second diffusion barrier pattern 170, or a combination thereof. Here, the memory cell MC may include a first electrode pattern 140, a variable resistance pattern 150, a second electrode pattern 160, or a combination thereof.

[0018] The first conductive line 110 may be a word line or a bit line. The second conductive line 190 may be located above the first conductive line 110. When viewed in a plan view, the second conductive line 190 may intersect the first conductive line 110. The second conductive line 190 may be a bit line or a word line. For example, when the first conductive line 110 is a word line, the second conductive line 190 may be a bit line. On the other hand, when the first conductive line 110 is a bit line, the second conductive line 190 may be a word line.

[0019] The variable resistance pattern 150 may be located between the first conductive line 110 and the second conductive line 190 in a third direction (or vertical direction) III perpendicular to the top surface of the substrate. The variable resistance pattern 150 may include a resistive material and switch between different resistance states based on an applied voltage or current.

[0020] The variable resistance pattern 150 may include transition metal oxides or other metal oxides, such as those based on perovskite materials. Thus, an electrical path is generated or disappears in the variable resistance pattern 150, so that data can be stored in the memory cell MC.

[0021] The variable resistance pattern 150 may have a magnetic tunnel junction (MTJ) structure including a magnetized pinned layer, a magnetized free layer, and a tunnel barrier layer, the tunnel barrier layer being interposed between the magnetized pinned layer and the magnetized free layer. For example, the magnetized pinned layer and the magnetized free layer may each include a magnetic material, and the tunnel barrier layer may include an oxide of magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), etc. Here, the magnetization direction of the magnetized free layer may be changed by the spin torque of electrons in the applied current. Therefore, data may be stored in the memory cell MC based on the change in the magnetization direction of the magnetized free layer relative to the magnetization direction of the magnetized pinned layer.

[0022] The variable resistance pattern 150 may include a phase change material, such as a chalcogenide. The variable resistance pattern 150 may include chalcogenide glass, a chalcogenide alloy, and the like. The variable resistance pattern 150 may include elements including, but not limited to, silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), or a combination thereof. The variable resistance pattern 150 may be made of Ge-Sb-Te (GST) such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7. The variable resistance pattern 150 may change its phase according to a programming operation. For example, the variable resistance pattern 150 may have a low resistance crystalline state by a setting operation. On the other hand, the variable resistance pattern 150 may have a high resistance amorphous state by a reset operation. Therefore, data may be stored in the memory cell MC based on the resistance difference corresponding to the phase of the variable resistance pattern 150.

[0023] The variable resistance pattern 150 may be composed of a material that changes resistance without undergoing a phase change, or may be composed of a chalcogenide-based material. The variable resistance pattern 150 may include an element including, but not limited to, germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium (Se), silicon (Si), indium (In), tin (Sn), sulfur (S), gallium (Ga), or a combination thereof.

[0024] The variable resistance pattern 150 may include a chalcogenide that remains in an amorphous state during a programming operation. Therefore, during a programming operation, the variable resistance pattern 150 may remain in an amorphous state without being transformed into a crystalline state. Therefore, the threshold voltage of the memory cell MC may be changed depending on the programming voltage applied to the memory cell MC, and the memory cell MC may be programmed to one of at least two states. For example, when a negative programming voltage is applied to the memory cell MC, the memory cell MC may have a relatively high threshold voltage. On the other hand, when a positive programming voltage is applied to the memory cell MC, the memory cell MC may have a relatively low threshold voltage. Therefore, data may be stored in the memory cell MC based on the difference in the threshold voltage of the memory cell MC.

[0025] The first electrode pattern 140 may be located above the first conductive line 110. For example, the first electrode pattern 140 may be located between the first conductive line 110 and the variable resistance pattern 150 in the third direction III. The first electrode pattern 140 may be a part of a word line or a bit line, or may be electrically connected to the word line or the bit line. The first electrode pattern 140 may include a conductive material such as polysilicon or a metal. For example, the first electrode pattern 140 may include a material including, but not limited to, polysilicon, tungsten (W), tungsten nitride (WN x ), tungsten silicide (WSix ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru) or a combination thereof.

[0026] The second electrode pattern 160 may be located below the second conductive line 190 in the third direction III. For example, the second electrode pattern 160 may be located between the variable resistance pattern 150 and the second conductive line 190. The second electrode pattern 160 may be part of a bit line or a word line, or may be electrically connected to the bit line or the word line. For example, when the first electrode pattern 140 is electrically connected to the word line, the second electrode pattern 160 may be electrically connected to the bit line. The second electrode pattern 160 may include a conductive material such as polysilicon or a metal. For example, the second electrode pattern 160 may include a material including, but not limited to, polysilicon, tungsten (W), tungsten nitride (WN x ), tungsten silicide (WSi x ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru) or a combination thereof.

[0027] The first gap filling pattern GFP1 may be located between memory cells MC adjacent to each other in the second direction II. The second gap filling pattern GFP2 may be located between memory cells MC adjacent to each other in the first direction I, the first direction I intersecting the second direction II. The first gap filling pattern GFP1, the second gap filling pattern GFP2, or both may include an insulating material. For example, the first gap filling pattern GFP1, the second gap filling pattern GFP2, or both may include an oxide. The first direction I and the second direction II are parallel to the top surface of the substrate, and thus they are perpendicular to the third direction III.

[0028] The first resistivity barrier pattern 120 may be located above the first conductive line 110 in the third direction III. For example, the first resistivity barrier pattern 120 may be located between the first conductive line 110 and the first electrode pattern 140. The first resistivity barrier pattern 120 may have a first thickness T1. The first resistivity barrier pattern 120 may include WSiN.

[0029] The memory cell MC may be operated by receiving a current supplied through the first conductive line 110. When the memory cell MC operates, a spike current may occur. The first resistivity barrier pattern 120 may prevent or reduce damage to the memory cell MC due to the spike current. For example, the first resistivity barrier pattern 120 may reduce the transmission of the spike current to the memory cell MC through the first conductive line 110 because it is located between the memory cell MC and the first conductive line 110. Therefore, the first resistivity barrier pattern 120 may have a relatively high resistivity.

[0030] When the memory cell MC is repeatedly operated, the first resistivity barrier pattern 120 may be degraded due to Joule heating and electrical stress. For example, the first resistivity barrier pattern 120 may be aggregated. When the first resistivity barrier pattern 120 is degraded, elements in the first resistivity barrier pattern 120 may diffuse into the memory cell MC. For example, elements in the first resistivity barrier pattern 120 may diffuse into the variable resistance pattern 150. For example, when the first resistivity barrier pattern 120 includes WSiN, at least one of tungsten (W) and silicon (Si) may diffuse into the variable resistance pattern 150.

[0031] When the elements in the first resistivity barrier pattern 120 diffuse into the variable resistance pattern 150, the variable resistance pattern 150 may be damaged. In order to reduce damage to the variable resistance pattern 150, the first diffusion barrier pattern 130 may be located between the first resistivity barrier pattern 120 and the variable resistance pattern 150. The first diffusion barrier pattern 130 may prevent the elements in the first resistivity barrier pattern 120 from diffusing into the variable resistance pattern 150. Therefore, the memory cell MC may be prevented from being damaged by the elements in the first resistivity barrier pattern 120.

[0032] When the first diffusion barrier pattern 130 is located between the first resistivity barrier pattern 120 and the variable resistance pattern 150 , the first electrode pattern 140 may be located between the first diffusion barrier pattern 130 and the variable resistance pattern 150 .

[0033] The first diffusion barrier pattern 130 may have a second thickness T2. The second thickness T2 may be substantially the same as or different from the first thickness T1 of the first resistivity barrier pattern 120. For example, the second thickness T2 may be greater than the first thickness T1. The resistivity of the first diffusion barrier pattern 130 may be substantially the same as or different from the resistivity of the first resistivity barrier pattern 120. For example, the resistivity of the first diffusion barrier pattern 130 may be lower than the resistivity of the first resistivity barrier pattern 120. The first diffusion barrier pattern 130 may include tungsten nitride (WN) or titanium nitride (TiN).

[0034] The grain boundaries in the first diffusion barrier pattern 130 may be used as a path for the elements from the first resistivity barrier pattern 120 to diffuse into the variable resistance pattern 150. Therefore, according to one embodiment of the present disclosure, other elements may be located at the grain boundaries of the metal elements within the first diffusion barrier pattern 130. For example, the nitrogen element (N) may be located at the grain boundaries of tungsten (W) or titanium (Ti). By blocking the diffusion path along the grain boundaries using the nitrogen element (N), the diffusion of the elements from the first resistivity barrier pattern 120 may be reduced. In other words, the first diffusion barrier pattern 130 may reduce or prevent the diffusion of the elements from the first resistivity barrier pattern 120 into the variable resistance pattern 150, and thus the memory cell MC may be prevented from being damaged.

[0035] The second resistivity barrier pattern 180 may be located below the second conductive line 190 in the third direction III. For example, the second resistivity barrier pattern 180 may be located between the second conductive line 190 and the second electrode pattern 160. The second resistivity barrier pattern 180 may have a third thickness T3. The third thickness T3 may be substantially the same as or different from the first thickness T1. For example, the third thickness T3 may be substantially the same as the first thickness T1. The second resistivity barrier pattern 180 may include a material similar to that of the first resistivity barrier pattern 120. For example, the second resistivity barrier pattern 180 may include WSiN.

[0036] The second resistivity barrier pattern 180 can reduce the transmission of the spike current to the memory cell MC through the second conductive line 190 because it is located between the memory cell MC and the second conductive line 190. Therefore, the second resistivity barrier pattern 180 can have a relatively high resistivity. In addition, the element (e.g., tungsten (W), silicon (Si) or both) in the second resistivity barrier pattern 180 may diffuse into the variable resistance pattern 150.

[0037] The second diffusion barrier pattern 170 may be located between the second resistivity barrier pattern 180 and the variable resistance pattern 150 in the third direction III. For example, the second diffusion barrier pattern 170 may be located between the second resistivity barrier pattern 180 and the second electrode pattern 160. The second diffusion barrier pattern 170 may have a fourth thickness T4. The fourth thickness T4 may be substantially the same as or different from the third thickness T3. For example, the fourth thickness T4 may be greater than the third thickness T3. The resistivity of the second diffusion barrier pattern 170 may be substantially the same as or different from the resistivity of the second resistivity barrier pattern 180. For example, the resistivity of the second diffusion barrier pattern 170 may be lower than the resistivity of the second resistivity barrier pattern 180. The second diffusion barrier pattern 170 may include tungsten nitride (WN) or titanium nitride (TiN). The second diffusion barrier pattern 170 may prevent the elements in the second resistivity barrier pattern 180 from diffusing into the variable resistance pattern 150.

[0038] According to other embodiments, at least one of the first resistivity barrier pattern 120, the first diffusion barrier pattern 130, the second resistivity barrier pattern 180, and the second diffusion barrier pattern 170 may be omitted. For example, the first resistivity barrier pattern 120 and the first diffusion barrier pattern 130 may be located between the first conductive line 110 and the first electrode pattern 140, and the second resistivity barrier pattern 180 and the second diffusion barrier pattern 170 may be omitted. In an alternative configuration, the second resistivity barrier pattern 180 and the second diffusion barrier pattern 170 may be located between the second conductive line 190 and the second electrode pattern 160, and the first resistivity barrier pattern 120 and the first diffusion barrier pattern 130 may be omitted.

[0039] Alternatively, the position of at least one of the first resistivity barrier pattern 120, the first diffusion barrier pattern 130, the second resistivity barrier pattern 180, and the second diffusion barrier pattern 170 may be changed. For example, the first resistivity barrier pattern 120 may be located between the first conductive line 110 and the first electrode pattern 140, and the first diffusion barrier pattern 130 may be located between the first electrode pattern 140 and the variable resistance pattern 150. Here, the second resistivity barrier pattern 180 may be located between the second conductive line 190 and the second electrode pattern 160, and the second diffusion barrier pattern 170 may be located between the second electrode pattern 160 and the variable resistance pattern 150. In an alternative configuration, the first resistivity barrier pattern 120 and the first diffusion barrier pattern 130 may be located between the first electrode pattern 140 and the variable resistance pattern 150, and the second resistivity barrier pattern 180 and the second diffusion barrier pattern 170 may be located between the second electrode pattern 160 and the variable resistance pattern 150.

[0040] According to the above structure, the first diffusion barrier pattern 130 may be located between the first resistivity barrier pattern 120 and the first electrode pattern 140, and the second diffusion barrier pattern 170 may be located between the second resistivity barrier pattern 180 and the second electrode pattern 160. Therefore, the first diffusion barrier pattern 120 may reduce diffusion of elements from the first resistivity barrier pattern 120 into the variable resistance pattern 150, and the second diffusion barrier pattern 170 may reduce diffusion of elements from the second resistivity barrier pattern 180 into the variable resistance pattern 150. As a result, damage to the memory cells MC may be reduced or prevented.

[0041] Figure 2A and Figure 2B A semiconductor device according to another embodiment is illustrated. Figure 2A is a plan view, Figure 2B is along Figure 2A Hereinafter, contents overlapping with the previously described contents will be omitted.

[0042] refer to Figure 2A and Figure 2B , the semiconductor device may include a first conductive line 210, a second conductive line 290, a memory cell MC, or a combination thereof, over a substrate (not shown). The semiconductor device may also include a first gap filling pattern GFP1, a second gap filling pattern GFP2, a first resistivity barrier pattern 220, a first diffusion barrier pattern 230, a second resistivity barrier pattern 280, a second diffusion barrier pattern 270, or a combination thereof. Here, the memory cell MC may include a first electrode pattern 240A, a first variable resistance pattern 250, a second electrode pattern 240B, a second variable resistance pattern 260, a third electrode pattern 240C, or a combination thereof.

[0043] The first resistivity barrier pattern 220, the first diffusion barrier pattern 230, or both may be located between the first conductive line 210 and the first electrode pattern 240A in the third direction III. For example, the first resistivity barrier pattern 220 may be located on the first conductive line 210, and the first diffusion barrier pattern 230 may be located between the first resistivity barrier pattern 220 and the first electrode pattern 240A. The first variable resistance pattern 250 may be located on the first electrode pattern 240A, and the second electrode pattern 240B may be located on the first variable resistance pattern 250.

[0044] The selection element may include a first electrode pattern 240A, a first variable resistance pattern 250, a second electrode pattern 240B, or a combination thereof. The selection element may be a diode, a positive-negative-positive (PNP) diode, a transistor, a vertical transistor, a bipolar junction transistor (BJT), a metal insulator transition (MIT) element, a mixed ion-electron conduction (MIEC) element, a bidirectional threshold switching (OTS) element, etc. The first variable resistance pattern 250 may include a chalcogenide material. The first electrode pattern 240A may be a lower electrode, and the second electrode pattern 240B may be an intermediate electrode. The first electrode pattern 240A, the second electrode pattern 240B, or both may include a metal or a metal nitride.

[0045] The second resistivity barrier pattern 280, the second diffusion barrier pattern 270, or both may be located between the second conductive line 290 and the third electrode pattern 240C in the third direction III. For example, the second resistivity barrier pattern 280 may be located below the second conductive line 290, and the second diffusion barrier pattern 270 may be located between the second resistivity barrier pattern 280 and the third electrode pattern 240C. The second variable resistance pattern 260 may be located between the second electrode pattern 240B and the third electrode pattern 240C.

[0046] The memory element may include a second electrode pattern 240B, a second variable resistance pattern 260, a third electrode pattern 240C, or a combination thereof. The memory element may share the second electrode pattern 240B with the selection element. The second variable resistance pattern 260 may include a chalcogenide material. The third electrode pattern 240C may be an upper electrode. The third electrode pattern 240C may include a metal or a metal nitride.

[0047] The first diffusion barrier pattern 230, the second diffusion barrier pattern 270, or both may include tungsten nitride (WN) or titanium nitride (TiN). The first resistivity barrier pattern 220, the second resistivity barrier pattern 280, or both may include WSiN. The first diffusion barrier pattern 230 may reduce diffusion of elements from the first resistivity barrier pattern 220 into the memory cell MC. The second diffusion barrier pattern 270 may reduce diffusion of elements from the second resistivity barrier pattern 280 into the memory cell MC. Here, the elements in the first resistivity barrier pattern 220, the elements in the second resistivity barrier pattern 280, or both may include at least one of tungsten and silicon. Therefore, the diffusion barrier patterns 230 and 270 may respectively reduce diffusion of elements from the resistivity barrier patterns 220 and 280 into the variable resistance patterns 250 and 260 to reduce or prevent damage to the memory cell MC.

[0048] According to other embodiments, at least one of the first resistivity barrier pattern 220, the first diffusion barrier pattern 230, the second resistivity barrier pattern 280, and the second diffusion barrier pattern 270 may be omitted. Alternatively, the position of at least one of the first resistivity barrier pattern 220, the first diffusion barrier pattern 230, the second diffusion barrier pattern 270, and the second resistivity barrier pattern 280 may be changed.

[0049] According to the above structure, the memory cell MC may be composed of a memory element and a selection element. The first resistivity barrier pattern 220 may be located between the first conductive line 210 and the memory cell MC, and the first diffusion barrier pattern 230 may be located between the first resistivity barrier pattern 220 and the memory cell MC. The second resistivity barrier pattern 280 may be located between the second conductive line 290 and the memory cell MC, and the second diffusion barrier pattern 270 may be located between the second resistivity barrier pattern 280 and the memory cell MC. Therefore, the diffusion barrier patterns 230 and 270 may respectively reduce or prevent the diffusion of elements from the resistivity barrier patterns 220 and 280 into the variable resistance patterns 250 and 260 of the memory cell MC to reduce or prevent damage to the memory cell MC.

[0050] Figure 3A and Figure 3B Each illustrates a semiconductor device according to yet another embodiment. Hereinafter, contents overlapping with previously described contents will be omitted.

[0051] refer to Figure 3A and Figure 3B , the semiconductor device may have a stacked structure in which a plurality of memory cells are arranged relative to each other. Figure 3A and Figure 3B The orientation is stacked in a vertical direction. The vertical direction can be perpendicular to the top surface of the substrate (not shown).

[0052] refer to Figure 3A , the semiconductor device may include a stack ST1, a memory cell section MCS, a first resistivity barrier pattern 320A, a first diffusion barrier pattern 330A, a second resistivity barrier pattern 380A, a second diffusion barrier pattern 370A, or a combination thereof. Here, the memory cell section MCS may include a first electrode pattern 340A, a second electrode pattern 360A, a variable resistance pattern 350A, or a combination thereof.

[0053] The stack ST1 may include first conductive lines 310 and insulating layers IL1 alternately stacked in a vertical direction. The first conductive lines 310 may each include a conductive material such as polysilicon or a metal. The first conductive lines 310 may each include a material including, but not limited to, polysilicon, tungsten (W), tungsten nitride (WN x), tungsten silicide (WSi x ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru) or a combination thereof. For example, the first conductive lines 310 may each include carbon. The first conductive lines 310 may each be a word line or a bit line. The insulating layer IL1 is used to insulate the first conductive lines 310 from each other, and may each include an insulating material such as an oxide or a nitride.

[0054] The second conductive line 390 may be formed to penetrate the stack ST1 in the vertical direction. Here, the structure of the second conductive line 390 may fill up to the central area of ​​the stack ST1. Therefore, the second conductive line 390 may extend in a direction intersecting with the first conductive line 310. The second conductive line 390 may include a material including, but not limited to, polysilicon, tungsten (W), tungsten nitride (WN x ), tungsten silicide (WSi x ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru), or a combination thereof. The second conductive line 390 may be a bit line or a word line. When the first conductive line 310 is a word line, the second conductive line 390 may be a bit line. On the other hand, when the first conductive line 310 is a bit line, the second conductive line 390 may be a word line.

[0055] refer to Figure 3A , the first electrode pattern 340A may be located between the first conductive line 310 and the second conductive line 390 in a horizontal direction substantially perpendicular to the vertical direction. The first electrode pattern 340A may extend in a direction parallel to the direction in which the second conductive line 390 extends, and may surround the sidewall of the second conductive line 390. The direction in which the second conductive line 390 extends may correspond to the vertical direction.

[0056] The second electrode pattern 360A may be located between the first electrode pattern 340A and the second conductive line 390 in the horizontal direction. The second electrode pattern 360A may extend in the vertical direction and may surround a sidewall of the second conductive line 390.

[0057] The variable resistance pattern 350A may be located between the first electrode pattern 340A and the second electrode pattern 360A in the horizontal direction. The variable resistance pattern 350A may extend in the vertical direction and may surround the sidewall of the second conductive line 390 .

[0058] The first resistivity barrier pattern 320A may be located between the first conductive line 310 and the first electrode pattern 340A in a horizontal direction. The first resistivity barrier pattern 320A may extend in a vertical direction and may surround an outer sidewall of the memory cell portion MCS.

[0059] The first diffusion barrier pattern 330A may be located between the first resistivity barrier pattern 320A and the first electrode pattern 340A in the horizontal direction. The first diffusion barrier pattern 330A may extend in the vertical direction and may surround an outer sidewall of the memory cell portion MCS.

[0060] The second resistivity barrier pattern 380A may be located between the second conductive line 390 and the second electrode pattern 360A in the horizontal direction. The second resistivity barrier pattern 380A may extend in the vertical direction and may surround the inner sidewall of the memory cell portion MCS.

[0061] The second diffusion barrier pattern 370A may be located between the second resistivity barrier pattern 380A and the second electrode pattern 360A in the horizontal direction. The second diffusion barrier pattern 370A may extend in the vertical direction and may surround the inner sidewall of the memory cell section MCS. The inner sidewall of the memory cell section MCS may be closer to the second conductive line 390 than the outer sidewall of the memory cell section MCS.

[0062] exist Figure 3A In the embodiment illustrated in FIG. 1 , the memory cell may be defined as a portion of the memory cell section MCS disposed between each of the first conductive lines 310 and the second conductive line 390. Therefore, the memory cell section MCS includes a plurality of memory cells disposed between the first conductive line 310 and the second conductive line 390 and stacked in a vertical direction.

[0063] exist Figure 3B In the embodiment illustrated in , a plurality of memory cells stacked in a vertical direction are separated from each other by an insulating layer IL2 , which is disposed between the plurality of memory cells in the vertical direction.

[0064] refer to Figure 3B, in each memory cell MC, the first electrode pattern 340B may be located between a corresponding one of the first conductive lines 310 and the second conductive line 390 in the horizontal direction. The first electrode pattern 340B may be located at substantially the same level as a corresponding one of the first conductive lines 310 in the vertical direction. The first electrode pattern 340B may surround a corresponding portion of a sidewall of the second conductive line 390. The second electrode pattern 360B may be located between the first electrode pattern 340B and the second conductive line 390 in the horizontal direction. The second electrode pattern 360B may surround a corresponding portion of a sidewall of the second conductive line 390. The variable resistance pattern 350B may be located between the first electrode pattern 340B and the second electrode pattern 360B in the horizontal direction. The variable resistance pattern 350B may surround a corresponding portion of a sidewall of the second conductive line 390. In the vertical direction, a corresponding portion of the sidewall of the second conductive line 390 may correspond to the thickness of the first conductive line 310.

[0065] The first resistivity barrier pattern 320B may be located between a corresponding one of the first conductive lines 310 and the first electrode pattern 340B. The first resistivity barrier pattern 320B may be located at substantially the same level as a corresponding one of the first conductive lines 310 in a vertical direction. The first resistivity barrier pattern 320B may surround an outer sidewall of the memory cell MC.

[0066] The first diffusion barrier pattern 330B may be located between the first resistivity barrier pattern 320B and the first electrode pattern 340B in a horizontal direction. The first diffusion barrier pattern 330B may surround outer sidewalls of the memory cells MC.

[0067] The second resistivity barrier pattern 380B may be located between the second conductive line 390 and the second electrode pattern 360B in a horizontal direction. The second resistivity barrier pattern 380B may surround inner sidewalls of the memory cells MC.

[0068] The second diffusion barrier pattern 370B may be located between the second resistivity barrier pattern 380B and the second electrode pattern 360B in a horizontal direction. The second diffusion barrier pattern 370B may surround inner sidewalls of the memory cells MC.

[0069] refer to Figure 3A and Figure 3BIn each of the figures, the first diffusion barrier patterns 330A and 330B can reduce the diffusion of elements from the first resistivity barrier patterns 320A and 320B into the memory cells MC. The second diffusion barrier patterns 370A and 370B can reduce the diffusion of elements from the second resistivity barrier patterns 380A and 380B into the memory cells MC. Therefore, the diffusion barrier patterns 330A and 370A and 330B and 370B can reduce or prevent the diffusion of elements from the resistivity barrier patterns 320A and 380A and 320B and 380B into the variable resistance patterns 350A and 350B to reduce or prevent damage to the memory cells MC.

[0070] According to other embodiments, at least one of the first resistivity barrier pattern, the first diffusion barrier pattern, the second resistivity barrier pattern, and the second diffusion barrier pattern may be omitted. Alternatively, the position of at least one of the first resistivity barrier pattern, the first diffusion barrier pattern, the second diffusion barrier pattern, and the second resistivity barrier pattern may be changed.

[0071] According to the above structure, the memory cell MC may be located in a region where a corresponding one of the first conductive lines 310 and the second conductive line 390 intersect each other. Figure 3A As shown, the memory cells MC disposed between the first conductive line 310 and the second conductive line 390 may share the first resistivity barrier pattern 320A, the first diffusion barrier pattern 330A, the second resistivity barrier pattern 380A, and the second diffusion barrier pattern 370A with each other.

[0072] Figure 4 A method for manufacturing a semiconductor device according to an embodiment is illustrated. Hereinafter, contents overlapping with the previously described contents will be omitted.

[0073] refer to Figure 4 , a first conductive layer 410 may be formed over a substrate (not shown). The first conductive layer 410 may be a word line or a bit line. A first resistivity barrier layer 420 may be formed on the first conductive layer 410. The first resistivity barrier layer 420 may be formed using at least one of a radio frequency (RF) sputtering method, a direct current (DC) sputtering method, an atomic layer deposition (ALD) method, and a chemical vapor deposition (CVD) method. The first resistivity barrier layer 420 may have a first thickness T1. The first resistivity barrier layer 420 may include WSiN.

[0074] The first diffusion barrier layer 430 may be formed on the first resistivity barrier layer 420. The first diffusion barrier layer 430 may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The first diffusion barrier layer 430 may have a second thickness T2. The second thickness T2 may be substantially the same as or different from the first thickness T1 of the first resistivity barrier layer 420. For example, the second thickness T2 may be greater than the first thickness T1. The resistivity of the first diffusion barrier layer 430 may be substantially the same as or different from the resistivity of the first resistivity barrier layer 420. For example, the resistivity of the first diffusion barrier layer 430 may be lower than the resistivity of the first resistivity barrier layer 420. The first diffusion barrier layer 430 may include tungsten nitride (WN) or titanium nitride (TiN).

[0075] A first electrode layer 440 may be formed on the first diffusion barrier layer 430. The first electrode layer 440 may be part of a word line or a bit line, or it may be electrically connected to the word line or the bit line. The first electrode layer 440 may include a conductive material such as polysilicon or a metal. For example, the first electrode layer 440 may include polysilicon, tungsten (W), etc.

[0076] The variable resistance layer 450 may be formed on the first electrode layer 440. The variable resistance layer 450 may include a transition metal oxide or a metal oxide such as a perovskite-based material. The variable resistance layer 450 may have an MTJ structure and may include a phase change material such as chalcogenide that maintains an amorphous state during a programming operation.

[0077] A second electrode layer 460 may be formed on the variable resistance layer 450. Thus, a memory cell MC may be defined, which includes the first electrode layer 440, the variable resistance layer 450, and the second electrode layer 460. The second electrode layer 460 may be part of a word line or a bit line, or may be electrically connected to the word line or the bit line. When the first electrode layer 440 is electrically connected to the word line, the second electrode layer 460 may be electrically connected to the bit line. The second electrode layer 460 may include a conductive material such as polysilicon or a metal. The second electrode layer 460 may include polysilicon, tungsten (W), or the like.

[0078] A second diffusion barrier layer 470 may be formed on the second electrode layer 460. The second diffusion barrier layer 470 may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The second diffusion barrier layer 470 may have a fourth thickness T4. The second diffusion barrier layer 470 may include tungsten nitride (WN) or titanium nitride (TiN).

[0079] A second resistivity barrier layer 480 may be formed on the second diffusion barrier layer 470. The second resistivity barrier layer 480 may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The second resistivity barrier layer 480 may have a third thickness T3. The third thickness T3 may be substantially the same as or different from a fourth thickness T4 of the second diffusion barrier layer 470. For example, the fourth thickness T4 may be greater than the third thickness T3. The second resistivity barrier layer 480 may include WSiN.

[0080] A second conductive layer 490 may be formed on the second resistivity barrier layer 480. When viewed in a plan view, the second conductive layer 490 may be patterned to intersect the first conductive layer 410. The second conductive layer 490 may be a bit line or a word line. For example, when the first conductive layer 410 is a word line, the second conductive layer 490 may be a bit line. On the other hand, when the first conductive layer 410 is a bit line, the second conductive layer 490 may be a word line.

[0081] The memory cell MC may be operated by receiving a current supplied through the first conductive layer 410 or the second conductive layer 490. When the memory cell MC is operated, a spike current may occur. Therefore, in order to reduce the transmission of the spike current through the first conductive layer 410 or the second conductive layer 490 to the memory cell MC, a first resistivity barrier layer 420 may be formed between the first conductive layer 410 and the memory cell MC, and a second resistivity barrier layer 480 may be formed between the second conductive layer 490 and the memory cell MC. The resistivity barrier layers 420 and 480 may each include a material having a relatively high resistivity. For example, the resistivity barrier layers 420 and 480 may each include WSiN. Therefore, the resistivity barrier layers 420 and 480 may prevent or reduce damage to the memory cell MC due to the spike current.

[0082] In addition, when the memory cell MC is repeatedly operated, the resistivity barrier layers 420 and 480 may be degraded due to Joule heating and electrical stress. For example, the resistivity barrier layers 420 and 480 may be aggregated. When the resistivity barrier layers 420 and 480 are degraded, the elements in the resistivity barrier layers 420 and 480 may diffuse into the memory cell MC. For example, the elements in the resistivity barrier layers 420 and 480 may diffuse into the variable resistance layer 450. Here, the elements in the resistivity barrier layers 420 and 480 may each be at least one of tungsten (W), silicon (Si), or a combination thereof.

[0083] When the elements in the resistivity barrier layers 420 and 480 diffuse into the variable resistance layer 450, the variable resistance layer 450 may be damaged. In order to reduce damage to the variable resistance layer 450, a first diffusion barrier layer 430 may be formed between the first resistivity barrier layer 420 and the variable resistance layer 450, and a second diffusion barrier layer 470 may be formed between the second resistivity barrier layer 480 and the variable resistance layer 450. The first diffusion barrier layer 430 may reduce diffusion of elements from the first resistivity barrier layer 420 into the variable resistance layer 450, and the second diffusion barrier layer 470 may reduce diffusion of elements from the second resistivity barrier layer 480 into the variable resistance layer 450. Therefore, the memory cell MC may be prevented from being damaged by the elements included in the resistivity barrier layers 420 and 480.

[0084] The grain boundaries in the diffusion barrier layers 430 and 470 may be used as paths for elements from the resistivity barrier layers 420 and 480 to diffuse into the variable resistance layer 450. Therefore, according to one embodiment of the present disclosure, other elements may be located at the grain boundaries of the metal elements in the diffusion barrier layers 430 and 470. For example, in the process of forming the diffusion barrier layers 430 and 470, the nitrogen element (N) may be located at the grain boundaries of tungsten (W) or titanium (Ti). By blocking the diffusion path through the grain boundaries with the nitrogen element (N), the diffusion of elements from the resistivity barrier layers 420 and 480 into the variable resistance layer 450 may be reduced. In other words, the diffusion barrier layers 430 and 470 may reduce or prevent the elements from the resistivity barrier layers 420 and 480 from diffusing into the variable resistance layer 450, and thus the memory cell MC may be prevented from being damaged.

[0085] According to other embodiments, at least one of the first resistivity barrier layer 420, the first diffusion barrier layer 430, the second diffusion barrier layer 470, and the second resistivity barrier layer 480 may be omitted. For example, the first resistivity barrier layer 420 and the first diffusion barrier layer 430 may be formed between the first conductive layer 410 and the first electrode layer 440, and the process of forming the second diffusion barrier layer 470 and the second resistivity barrier layer 480 may be omitted. In an alternative configuration, the second diffusion barrier layer 470 and the second resistivity barrier layer 480 may be formed between the second conductive layer 490 and the second electrode layer 460, and the process of forming the first resistivity barrier layer 420 and the first diffusion barrier layer 430 may be omitted.

[0086] Alternatively, the formation order of at least one of the first resistivity barrier layer 420, the first diffusion barrier layer 430, the second resistivity barrier layer 480, and the second diffusion barrier layer 470 may be changed. For example, the first resistivity barrier layer 420 may be formed on the first conductive layer 410, and the first electrode layer 440 may be formed on the first resistivity barrier layer 420. Subsequently, the first diffusion barrier layer 430 may be formed on the first electrode layer 440, and the variable resistance layer 450 may be formed on the first diffusion barrier layer 430. In an alternative configuration, the first resistivity barrier layer 420 and the first diffusion barrier layer 430 may be sequentially formed on the first electrode layer 440. Subsequently, the variable resistance layer 450 may be formed on the first diffusion barrier layer 430.

[0087] According to the above-described manufacturing method, the first diffusion barrier layer 430 may be formed between the first resistivity barrier layer 420 and the first electrode layer 440, and the second diffusion barrier layer 470 may be formed between the second resistivity barrier layer 480 and the second electrode layer 460. The diffusion barrier layers 430 and 470 may reduce diffusion of elements from the resistivity barrier layers 420 and 480 into the variable resistance layer 450. Therefore, damage to the memory cell MC may be reduced or prevented.

[0088] FIG. 5A to FIG. 9B A method for manufacturing a semiconductor device according to an embodiment is illustrated. Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A Can be a plan view, and Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B Can be respectively along Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A A cross-sectional view taken along line AA' or line BB' of FIG. 8 is shown in FIG.

[0089] refer to Figure 5A and Figure 5B , a first conductive layer 510A may be formed over a substrate (not shown). Subsequently, a first resistivity barrier layer 520A may be formed on the first conductive layer 510A. The first resistivity barrier layer 520A may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The first resistivity barrier layer 520A may include tungsten, silicon, or both. For example, the first resistivity barrier layer 520A may include WSiN.

[0090] Subsequently, a first diffusion barrier layer 530A may be formed on the first resistivity barrier layer 520A. The first diffusion barrier layer 530A may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The first diffusion barrier layer 530A may include tungsten nitride (WN), titanium nitride (TiN), or a combination thereof.

[0091] Subsequently, a first electrode layer 540A may be formed on the first diffusion barrier layer 530A. A variable resistance layer 550A may be formed on the first electrode layer 540A. A second electrode layer 560A may be formed on the variable resistance layer 550A.

[0092] A second diffusion barrier layer 570A may be formed on the second electrode layer 560A. The second diffusion barrier layer 570A may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The second diffusion barrier layer 570A may include tungsten nitride (WN), titanium nitride (TiN), or a combination thereof.

[0093] Subsequently, a second resistivity barrier layer 580A may be formed on the second diffusion barrier layer 570A. The second resistivity barrier layer 580A may be formed using at least one of an RF sputtering method, a DC sputtering method, an ALD method, and a CVD method. The second resistivity barrier layer 580A may include tungsten, silicon, or both. For example, the second resistivity barrier layer 580A may include WSiN.

[0094] refer to Fig. 6A and Figure 6B , the second resistivity barrier line 580L and the second diffusion barrier line 570L may be formed by etching the second resistivity barrier layer 580A and the second diffusion barrier layer 570A so that the second resistivity barrier line 580L and the second diffusion barrier line 570L extend in the first direction I.

[0095] Subsequently, a plurality of memory lines ML may be formed. For example, a plurality of memory lines ML may be formed by etching the second electrode layer 560A, the variable resistance layer 550A, and the first electrode layer 540A, each of the plurality of memory lines ML including the second electrode line 560L, the variable resistance line 550L, and the first electrode line 540L. Here, when viewed in a plan view, each of the plurality of memory lines ML may extend in a first direction I, and the plurality of memory lines ML may be aligned in parallel in a second direction II.

[0096] Subsequently, first diffusion barrier lines 530L and first resistivity barrier lines 520L may be formed by etching the first diffusion barrier layer 530A and the first resistivity barrier layer 520A such that they extend in the first direction I when viewed in a plan view.

[0097] Subsequently, the first conductive line 510 may be formed by etching the first conductive layer 510A such that, when viewed in a plan view, the first conductive line 510 extends in the first direction I. The first conductive line 510 may be a word line or a bit line.

[0098] refer to Fig. 7A and Figure 7B , the first gap-filling layer GF1 may be formed between the plurality of memory lines ML. For example, the first gap-filling layers GF1 may be respectively formed between the plurality of memory lines ML spaced apart from each other in the second direction II, which intersects the first direction I. Here, when viewed in a plan view, the first gap-filling layer GF1 may extend in the first direction I. The first gap-filling layers GF1 may each include an insulating material such as an oxide.

[0099] refer to Fig. 8A and Figure 8B , a second conductive line 590 may be formed. First, a second conductive layer (not shown) may be formed on the plurality of memory lines ML and the first gap filling layer GF1. Subsequently, the second conductive line 590 may be formed by etching the second conductive layer (not shown) so that the second conductive line 590 extends in the second direction II when viewed in a plan view. The second conductive line 590 may be a word line or a bit line. For example, when the first conductive line 510 is a word line, the second conductive line 590 may be a bit line. On the other hand, when the first conductive line 510 is a bit line, the second conductive line 590 may be a word line.

[0100] Subsequently, the second resistivity barrier pattern 580 and the second diffusion barrier pattern 570 may be formed by etching the second resistivity barrier line 580L and the second diffusion barrier line 570L (e.g., using the second conductive line 590 as an etching barrier). Thus, a plurality of second resistivity barrier patterns 580 may be formed to be arranged in the first direction I and the second direction II, and a plurality of second diffusion barrier patterns 570 may be formed to be arranged in the first direction I and the second direction II.

[0101] Subsequently, a memory cell MC may be formed. For example, a memory cell MC may be formed by etching the second electrode line 560L, the variable resistance line 550L, and the first electrode line 540L, the memory cell MC including the second electrode pattern 560, the variable resistance pattern 550, and the first electrode pattern 540. Here, a plurality of memory cells MC may be formed to be arranged in the first direction I and the second direction II.

[0102] Subsequently, the first diffusion barrier pattern 530 and the first resistivity barrier pattern 520 may be formed by etching the first diffusion barrier line 530L and the first resistivity barrier line 520L. Thus, a plurality of first diffusion barrier patterns 530 may be formed to be arranged in the first direction I and the second direction II, and a plurality of first resistivity barrier patterns 520 may be formed to be arranged in the first direction I and the second direction II. Through the above-described etching process, each of the first gap filling layers GF1 may be separated into a plurality of first gap filling patterns GFP1 in the first direction I.

[0103] refer to Fig. 9A and Fig. 9B , the second gap filling pattern GFP2 may be formed between the memory cells MC. For example, the second gap filling patterns GFP2 may be respectively formed between the memory cells MC spaced apart from each other in the first direction I. First, a second gap filling layer (not shown) may be formed to fill the space between the memory cells MC spaced apart from each other in the first direction I and cover the plurality of memory cells MC. Subsequently, the second gap filling pattern GFP2 may be formed by planarizing the second gap filling layer (not shown) until the upper surface of the second conductive line 590 is exposed. Here, when viewed in a planar view, the second gap filling patterns GFP2 may extend in the second direction II, and may each include an insulating material such as an oxide.

[0104] The memory cell MC may operate by receiving a voltage or current supplied through the first conductive line 510 or the second conductive line 590. When the memory cell MC operates, a spike current may occur. The resistivity barrier patterns 520 and 580 may prevent or reduce damage to the memory cell MC due to the spike current.

[0105] When the memory cell MC is repeatedly operated, the resistivity barrier patterns 520 and 580 may be degraded. For example, the resistivity barrier patterns 520 and 580 may be aggregated. When the resistivity barrier patterns 520 and 580 are degraded, an element included in the resistivity barrier patterns 520 and 580 may diffuse into the memory cell MC. For example, at least one of tungsten (W) and silicon (Si) included in the resistivity barrier patterns 520 and 580 may diffuse into the variable resistance pattern 550 of the memory cell MC.

[0106] When the elements included in the resistivity barrier patterns 520 and 580 diffuse into the memory cell MC, the memory cell MC may be damaged. In order to reduce the damage to the memory cell MC, a first diffusion barrier pattern 530 may be formed between the first resistivity barrier pattern 520 and the variable resistance pattern 550, and a second diffusion barrier pattern 570 may be formed between the second resistivity barrier pattern 580 and the variable resistance pattern 550. Here, the first diffusion barrier pattern 530 may prevent the elements included in the first resistivity barrier pattern 520 from diffusing into the variable resistance pattern 550, and the second diffusion barrier pattern 570 may prevent the elements included in the second resistivity barrier pattern 580 from diffusing into the variable resistance pattern 550. Therefore, the damage to the memory cell MC by the elements included in the resistivity barrier patterns 520 and 580 may be reduced or prevented.

[0107] According to other embodiments, one or more of the resistivity barrier patterns 520 and 580 and the diffusion barrier patterns 530 and 570 may be omitted. Alternatively, the formation order of one or more of the resistivity barrier patterns 520 and 580 and the diffusion barrier patterns 530 and 570 may be changed.

[0108] According to the above-described manufacturing method, the diffusion barrier patterns 530 and 570 may reduce diffusion of elements included in the resistivity barrier patterns 520 and 580 into the variable resistance pattern 550. Therefore, the diffusion barrier patterns 530 and 570 may reduce or prevent damage to the memory cells MC.

[0109] Although the embodiments according to the technical ideas of the present disclosure have been described above with reference to the accompanying drawings, this is only used to explain the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical ideas of the present disclosure defined in the attached claims, technicians in the field to which the present disclosure belongs can make various types of substitutions, modifications and changes to the embodiments, and it should be understood that these substitutions, modifications and changes belong to the scope of the present disclosure.

Claims

1. A semiconductor device comprising: a first conductive line; a second conductive line located above the first conductive line, wherein the first conductive line and the second conductive line extend in different directions intersecting each other; a variable resistance pattern, located between the first conductive line and the second conductive line; a first electrode pattern, located between the first conductive line and the variable resistor pattern; a first resistivity barrier pattern, which is located between the first conductive line and the first electrode pattern; as well as The first diffusion barrier pattern is located between the first resistivity barrier pattern and the first electrode pattern. 2 . The semiconductor device according to claim 1 , wherein the first diffusion barrier pattern comprises tungsten nitride (WN) or titanium nitride (TiN). 3 . The semiconductor device of claim 2 , wherein the first resistivity barrier pattern comprises WSiN. 4 . The semiconductor device of claim 2 , wherein the first diffusion barrier pattern prevents an element included in the first resistivity barrier pattern from diffusing into the variable resistance pattern.

5. The semiconductor device of claim 4, wherein the element comprises tungsten, silicon, or both. 6 . The semiconductor device of claim 1 , wherein a resistivity of the first diffusion barrier pattern is lower than a resistivity of the first resistivity barrier pattern. 7 . The semiconductor device of claim 1 , wherein the first resistivity barrier pattern has a first thickness, and the first diffusion barrier pattern has a second thickness greater than the first thickness.

8. The semiconductor device according to claim 1, further comprising: a second electrode pattern, located between the variable resistor pattern and the second conductive line; a second resistivity barrier pattern located between the second electrode pattern and the second conductive line; as well as The second diffusion barrier pattern is located between the second electrode pattern and the second resistivity barrier pattern. 9 . The semiconductor device according to claim 8 , wherein the second diffusion barrier pattern comprises tungsten nitride (WN) or titanium nitride (TiN). 10 . The semiconductor device of claim 8 , wherein the second resistivity barrier pattern comprises WSiN. 11 . The semiconductor device of claim 8 , wherein the second diffusion barrier pattern prevents an element included in the second resistivity barrier pattern from diffusing into the variable resistance pattern. 12 . The semiconductor device of claim 8 , wherein a resistivity of the second diffusion barrier pattern is lower than a resistivity of the second resistivity barrier pattern. 13 . The semiconductor device of claim 8 , wherein the second resistivity barrier pattern has a third thickness, and the second diffusion barrier pattern has a fourth thickness greater than the third thickness.

14. A method for manufacturing a semiconductor device, the method comprising: forming a first resistivity barrier layer over the first conductive layer; forming a first diffusion barrier layer over the first resistivity barrier layer; forming a first electrode layer on the first diffusion barrier layer; forming a variable resistance layer above the first electrode layer; forming a second electrode layer above the variable resistance layer; as well as A second conductive layer is formed over the second electrode layer.

15. The manufacturing method according to claim 14, further comprising: forming a second diffusion barrier layer above the second electrode layer; as well as A second resistivity barrier layer is formed over the second diffusion barrier layer. 16 . The manufacturing method according to claim 15 , wherein at least one of the first diffusion barrier layer and the second diffusion barrier layer comprises tungsten nitride (WN) or titanium nitride (TiN). 17 . The manufacturing method of claim 16 , wherein the first resistivity barrier layer, the second resistivity barrier layer, or both comprise WSiN.

18. The manufacturing method according to claim 16, wherein the first diffusion barrier layer prevents an element included in the first resistivity barrier layer from diffusing into the variable resistance layer, and the second diffusion barrier layer prevents an element included in the second resistivity barrier layer from diffusing into the variable resistance layer.

19. The manufacturing method of claim 18, wherein the element included in the first resistivity barrier layer, the element included in the second resistivity barrier layer, or both include tungsten, silicon, or both. 20 . The manufacturing method according to claim 15 , wherein the resistivity of the first diffusion barrier layer is lower than that of the first resistivity barrier layer, and the resistivity of the second diffusion barrier layer is lower than that of the second resistivity barrier layer.

21. The manufacturing method of claim 14, wherein the first resistivity barrier layer has a first thickness, and the first diffusion barrier layer has a second thickness greater than the first thickness. 22 . The manufacturing method of claim 15 , wherein the second resistivity barrier layer has a third thickness, and the second diffusion barrier layer has a fourth thickness greater than the third thickness.

23. A method for manufacturing a semiconductor device, the method comprising: forming a first conductive layer; forming a first resistivity barrier layer over the first conductive layer; forming a first diffusion barrier layer over the first resistivity barrier layer; forming a first electrode layer on the first diffusion barrier layer; forming a variable resistance layer above the first electrode layer; forming a second electrode layer above the variable resistance layer; forming a memory line by etching the second electrode layer, the variable resistance layer and the first electrode layer in a first direction, the memory line comprising a second electrode line, a variable resistance line and a first electrode line; forming a first diffusion barrier line and a first resistivity barrier line by etching the first diffusion barrier layer and the first resistivity barrier layer in the first direction; forming a second conductive layer over the memory line; forming a second conductive line by etching the second conductive layer in a second direction intersecting the first direction; forming a memory cell by etching the memory line in the second direction, the memory cell comprising a second electrode pattern, a variable resistance pattern, and a first electrode pattern; as well as A first diffusion barrier pattern and a first resistivity barrier pattern are formed by etching the first diffusion barrier line and the first resistivity barrier line in the second direction.

24. The manufacturing method according to claim 23, further comprising: forming a second diffusion barrier layer above the second electrode layer; as well as A second resistivity barrier layer is formed over the second diffusion barrier layer. 25 . The manufacturing method according to claim 24 , further comprising forming a second resistivity barrier line and a second diffusion barrier line by etching the second resistivity barrier layer and the second diffusion barrier layer in the first direction. 26 . The manufacturing method of claim 25 , further comprising forming a second resistivity barrier pattern and a second diffusion barrier pattern by etching the second resistivity barrier line and the second diffusion barrier line in the second direction. 27 . The manufacturing method of claim 26 , wherein the first diffusion barrier pattern prevents an element included in the first resistivity barrier pattern from diffusing into the variable resistance pattern, and the second diffusion barrier pattern prevents an element included in the second resistivity barrier pattern from diffusing into the variable resistance pattern. 28 . The manufacturing method of claim 27 , wherein the element included in the first resistivity barrier pattern, the element included in the second resistivity barrier pattern, or both include tungsten, silicon, or both. 29 . The manufacturing method according to claim 24 , wherein at least one of the first diffusion barrier layer and the second diffusion barrier layer comprises tungsten nitride (WN) or titanium nitride (TiN).

30. The manufacturing method of claim 24, wherein the first resistivity barrier layer, the second resistivity barrier layer, or both comprise WSiN.

31. The manufacturing method of claim 24, wherein the resistivity of the first diffusion barrier layer is lower than the resistivity of the first resistivity barrier layer, and the resistivity of the second diffusion barrier layer is lower than the resistivity of the second resistivity barrier layer.

32. The manufacturing method of claim 23, wherein the first resistivity barrier layer has a first thickness, and the first diffusion barrier layer has a second thickness greater than the first thickness.

33. The manufacturing method of claim 24, wherein the second resistivity barrier layer has a third thickness, and the second diffusion barrier layer has a fourth thickness greater than the third thickness.

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