Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a first source / drain region; a second source / drain region; a fin-shaped structure disposed between the first source / drain region and the second source / drain region; and a gate structure disposed on a top surface and a plurality of sidewalls of the fin structure, the gate structure including: a gate dielectric layer; and a work function metal film stack, wherein the work function metal film stack is non-conformal in at least one of thickness and phase. In some embodiments, a FinFET transistor is provided having a gate structure that includes one or more non-conformal work function metal layers. In some embodiments, the work function metal layer may be non-conformal in at least one of thickness, composition, and / or phase. The non-conformal property of the work function metal layer reduces leakage, improves device performance, and increases device reliability.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] As semiconductor devices become smaller and smaller, various processing technologies are applied to manufacture devices with smaller and smaller dimensions. As semiconductor devices continue to shrink, new challenges may arise in existing process technologies and existing device structures. For example, when manufacturing fin field effect transistors (FinFETs), conformal films are deposited as gate dielectric layers and gate electrode layers. However, as device dimensions shrink, conformally formed films may lead to gate leakage or other defects because the top portion of the conformal film may become thinner or be damaged during processing. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor device includes: a first source / drain region; a second source / drain region; a fin-shaped structure disposed between the first source / drain region and the second source / drain region; and a gate structure disposed on a top surface and multiple sidewalls of the fin-shaped structure, wherein the gate structure includes: a gate dielectric layer; and a work function metal film stack, wherein the work function metal film stack is non-conformal in at least one of thickness and phase.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes: a first source / drain region; a second source / drain region; a fin-shaped structure disposed between the first source / drain region and the second source / drain region, wherein the fin-shaped structure has a first sidewall, a second sidewall opposite to the first sidewall, and a top surface connecting the first sidewall and the second sidewall; and a gate structure disposed above the top surface, the first sidewall, and the second sidewall of the fin-shaped structure, wherein the gate structure includes: a gate dielectric layer; a work function metal film stack located on the gate dielectric layer; and a gate fill layer located on the work function metal film stack, wherein the work function metal film stack has a first thickness on the top surface of the fin-shaped structure and has a second thickness along the first sidewall and the second sidewall of the fin-shaped structure, and the first thickness is greater than the second thickness.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes the following steps: forming a fin-shaped structure; forming a sacrificial gate structure above the fin-shaped structure; etching the fin-shaped structure on both sides of the sacrificial gate structure to form multiple source / drain grooves; forming multiple source / drain regions in the multiple source / drain grooves; removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin-shaped structure; depositing a gate dielectric layer on the top surface and two sidewalls of the fin-shaped structure; depositing a work function metal film stack above the gate dielectric layer, wherein the work function metal film stack has a first thickness on the top surface of the fin-shaped structure and a second thickness along the two sidewalls of the fin-shaped structure, and the first thickness is greater than the second thickness; and depositing a gate fill layer on the work function metal film stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a flow chart of an exemplary method for forming a semiconductor device according to an embodiment of the present disclosure;

[0008] Figures 2 to 6 , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B , FIG. 9A to FIG. 9B , FIG. 10A to FIG. 10D , FIG. 11A to FIG. 11C , Fig.12 as well as FIG. 12A to FIG. 12B is a schematic diagram of a semiconductor device at various stages of manufacturing the semiconductor device according to an embodiment of the present disclosure;

[0009] FIG. 13A to FIG. 13F is a schematic cross-sectional view of a work function metal film stack according to an embodiment of the present disclosure;

[0010] FIG. 14A to FIG. 14H are transmission electron microscopy (TEM) images and graphs of semiconductor devices manufactured according to embodiments of the present disclosure;

[0011] Fig.15 is a flow chart of an exemplary method for forming a semiconductor device according to an embodiment of the present disclosure;

[0012] FIG. 16A to FIG. 16B as well as FIG. 17A to FIG. 17B is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013]

Explanation of symbols

[0014] 10, 12, 14, 20, 22, 30, 32: Curve

[0015] 100, 300: Method

[0016] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 320, 322: Operation

[0017] 200, 200a, 200b, 200c, 400a: semiconductor device

[0018] 202:Substrate

[0019] 204, 204a, 204b: fin-shaped structure

[0020] 204s: Sidewall

[0021] 204t: Top surface

[0022] 206: Groove

[0023] 208: Isolation layer

[0024] 210: Sacrificial gate structure

[0025] 212: Sacrificial gate dielectric layer

[0026] 214: Sacrificial gate electrode layer

[0027] 216: cushion layer

[0028] 218: Mask layer

[0029] 220: spacer layer

[0030] 220b: Bottom spacer

[0031] 220f: Sidewall spacer

[0032] 220ft: Top spacer

[0033] 220g: Sidewall spacer

[0034] 220gt: Top spacer

[0035] 222, 222a, 222b: epitaxial source / drain regions

[0036] 224:CESL

[0037] 226:ILD layer

[0038] 228: Gate cavity

[0039] 230:Interface dielectric layer

[0040] 232: Gate dielectric layer

[0041] 234, 234', 234", 434, 434a: work function metal layer

[0042] 234c, 236c, 240c: conformal work function metal layer

[0043] 234n, 236n, 240n: non-conformal work function metal layer

[0044] 236, 236', 236", 440: work function metal layer

[0045] 238, 238', 238": Combined non-conformal layer

[0046] 240, 240': work function metal layer

[0047] 242: Gate filling layer

[0048] 400:Semiconductor devices

[0049] 4341: Polycrystalline part

[0050] 4342: Non-crystalline part

[0051] AA, BB: Line

[0052] H, H1, H1', ​​H1", H2, H2', H2", H3, Ha, Ha', Ha": horizontal thickness

[0053] P:Interval

[0054] PI: Pitch

[0055] S, S1, S1', S1", S2, S2', S2", S3, Sa, Sa', Sa": Thickness

[0056] W1: Width DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0058] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," "over," "top," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0059] The foregoing broadly summarizes some aspects of the embodiments described in the present disclosure. Although some embodiments described herein are described in the context of FinFETs, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, Fin-FETs, horizontal all-around gates (Horizontal Gate AllAround, HGAA) FETs, vertical all-around gates (Vertical Gate All Around, VGAA) FETs, and other suitable devices. It should be readily understood by those generally familiar with the art that other modifications that may be made are contemplated within the scope of the present disclosure. In addition, although the method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. In the present disclosure, the source / drain region refers to the source and / or drain. The source and drain may be used interchangeably.

[0060] Embodiments of the present disclosure provide a FinFET transistor having a gate structure that includes one or more non-conformal work function metal layers. In some embodiments, the work function metal layer may be non-conformal in at least one of thickness, composition, and / or phase. In some embodiments, the non-conformal work function metal layer has a non-conformal thickness along the semiconductor fin in the FinFET transistor. For example, the total thickness of the work function metal layer is thicker along the top side of the semiconductor fin and thinner along the sidewall of the semiconductor fin. In some embodiments, the work function metal layer may be non-conformal in terms of phase. For example, a first portion of the work function metal layer may be an amorphous material, and a second portion of the work function metal layer may be a crystalline or polycrystalline material. In some embodiments, the work function metal layer may include a non-crystalline portion formed above the top surface of the semiconductor fin. The non-conformality of the work function metal layer can reduce leakage, reduce vertical resistance, improve device performance, and increase device reliability.

[0061] Figure 1 is a flow chart of an exemplary method 100 for forming a semiconductor device according to an embodiment of the present disclosure.

[0062] Figures 2 to 6 , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B , FIG. 9A to FIG. 9B , FIG. 10A to FIG. 10D , FIG. 11A to FIG. 11C , Fig.12 as well as FIG. 12A to FIG. 12B is a schematic perspective view of a semiconductor device 200 at various stages of manufacturing the semiconductor device 200 according to an embodiment of the present disclosure. In some embodiments, the semiconductor device 200 may be manufactured using the method 100 .

[0063] In operation 102 of method 100, fin structures 204a, 204b (collectively referred to as 204) are formed on a substrate 202, such as Figure 2 as shown in . Figure 21 is a schematic perspective view of semiconductor device 200 after operation 102. Substrate 202 may include single crystalline semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Substrate 202 may include various doping configurations depending on the circuit design. For example, different doping profiles, such as n-type well, p-type well, may be formed in substrate 202 in areas designed for different device types such as n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). In some embodiments, substrate 202 may be a silicon-on-insulator (SOI) substrate including an insulator structure for enhancement.

[0064] In some embodiments, the fin structure 204 may be formed by depositing an epitaxial semiconductor layer over the substrate 202, depending on the type of device to be formed. The fin structure 204 is then formed by lithography and etching processes using one or more patterned layers. In some embodiments, the fin structure 204 may include a fin structure 204a for a first type of device and a fin structure 204b for a second type of device.

[0065] Each of the fin structures 204a may include a well portion formed in the first well region of the substrate 202 and a fin portion formed by an epitaxially grown layer above the substrate 202. The fin portion may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon (Si), or other epitaxially grown semiconductor materials, such as germanium (Ge); compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the fin structure 204a is used to serve as a channel region for an N-type device. The well portion may include pure silicon or silicon with a p-type dopant. The fin portion of the fin structure 204a may include an epitaxially grown semiconductor material with tensile stress, such as SiP for NMOS.

[0066] Each of the fin structures 204b may include a well portion formed in the second well region of the substrate 202 and a fin portion formed by an epitaxially grown layer above the substrate 202. The fin portion may include epitaxially grown Si, epitaxially grown SiGe, or other epitaxially grown semiconductor materials, such as Ge; compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, the fin structure 204b is used to serve as a channel region for a P-type device. In some embodiments, the well portion may be pure silicon. In other embodiments, the well portion may be formed in an n-type well and include an n-type dopant. The fin portion of the fin structure 204b may include an epitaxially grown semiconductor material having a compressive stress, such as epitaxially grown SiGe.

[0067] The fin-shaped structures 204 extend from the substrate 202 to form trenches between adjacent fins. Figure 2 As shown in , trenches 206 are formed between adjacent fin structures 204. In some embodiments, the fin structures 204 are arranged in parallel and have a pitch PI. In some embodiments, the pitch PI is in a range between about 10 nm and about 32 nm. Figure 2 As shown in , the fin structure 204 has a width W1 along the y direction, and the trench 206 has a spacing P along the y direction. In some embodiments, the width W1 is in a range between about 4 nm and about 8 nm. In some embodiments, the spacing P is in a range between about 6 nm and about 24 nm. In some embodiments, the ratio of the spacing P to the width W1 is in a range between about 1.1 and about 6.0.

[0068] In operation 104, an isolation layer 208 is formed in the trench 206 between the fin structures 204, such as Figure 3 as shown in . Figure 3 is a schematic perspective view of the semiconductor device 200 after operation 104 .

[0069] An isolation layer 208 is formed in the trenches between the fin structures 204 by suitable deposition, followed by an etch-back process. As an example, the bottom profile of the isolation layer 208 is shown as being curved. The isolation layer 208 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 208 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or a combination thereof. In some embodiments, the isolation layer 208 may be formed by conformally depositing one or more layers of isolation material to fill the trenches 206. The one or more layers of isolation material are then etched back to expose the upper portion or fin portion of the fin structure 204. The isolation layer 208 fills the lower portion of the trenches 206.

[0070] In operation 106, a sacrificial gate structure 210 is formed over the isolation layer 208 and around the exposed portions of the fin structures 204a, 204b. Figure 3 A sacrificial gate structure 210 is formed over the portion of the fin structures 204a, 204b that will become the channel region. The sacrificial gate structure 210 is substantially perpendicular to the fin structure 204. The sacrificial gate structure 210 may include a sacrificial gate dielectric layer 212, a sacrificial gate electrode layer 214, a liner layer 216, and a mask layer 218.

[0071] A sacrificial gate dielectric layer 212 may be conformally formed over the fin structures 204a, 204b and the isolation layer 208. In some embodiments, the sacrificial gate dielectric layer 212 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 212 may include one or more layers of dielectric materials, such as SiO2, SiN, high-k dielectric materials, and / or other suitable dielectric materials.

[0072] A sacrificial gate electrode layer 214 may be blanket deposited over the sacrificial gate dielectric layer 212. The sacrificial gate electrode layer 214 includes silicon, such as polysilicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range between about 42 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer 214 is subjected to a planarization operation. The sacrificial gate electrode layer 214 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0073] Subsequently, a liner layer 216 and a mask layer 218 are formed over the sacrificial gate electrode layer 214. The liner layer 216 may include silicon nitride. The mask layer 218 may include silicon oxide. Next, a processing sequence including patterning and etching is performed on the mask layer 218, the liner layer 216, the sacrificial gate electrode layer 214, and the sacrificial gate dielectric layer 212 to form a sacrificial gate structure 210. Portions of the sacrificial gate electrode layer 214 and the sacrificial gate dielectric layer 212 are sequentially removed using the pattern formed in the mask layer 218 to form the sacrificial gate structure 210. In some embodiments, the sacrificial gate electrode layer 214 is first etched using the sacrificial gate dielectric layer 212 as an etch stop layer. The sacrificial gate dielectric layer 212 is then selectively removed from the fin structure 204 and the isolation layer 208 to expose the exposed portion of the fin structure 204, as shown in FIG. Figure 3 as shown in .

[0074] In operation 108, a spacer layer 220 is formed over the semiconductor device 200, such as Figure 4 As shown in Figure 4 2 is a schematic perspective view of a semiconductor device 200. After forming the sacrificial gate structure 210, a spacer layer 220 may be deposited over the semiconductor device 200 by blanket depositing one or more insulating materials. Figure 4 Only one layer is shown in the figure, and the spacer layer 220 may also include two or more dielectric material layers. In some embodiments, the spacer layer 220 may include one or more insulating materials. The spacer layer 220 may include a silicon nitride-based material such as SiN, SiON, SiOCN or SiCN and combinations thereof.

[0075] like Figure 4 As shown in , the spacer layer 220 covers the sacrificial gate structure 210, the fin-shaped structures 204a, 204b and the isolation layer 208. For the sake of clarity of description, the portion of the spacer layer 220 formed on the sidewall of the sacrificial gate structure 210 is referred to as the gate sidewall spacer 220g, the portion of the spacer layer 220 formed on the sidewall of the fin-shaped structures 204a, 204b is referred to as the fin sidewall spacer 220f, the portion of the spacer layer formed on the isolation layer 208 is referred to as the bottom spacer 220b, the portion of the spacer layer 220 formed on the top surface of the sacrificial gate structure 210 is referred to as the gate top spacer 220gt, and the portion of the spacer layer 220 formed on the top surface 204t of the fin-shaped structures 204a, 204b is referred to as the fin top spacer 220ft.

[0076] In operation 110, epitaxial source / drain regions 222a, 222b (collectively referred to as 222) are formed, such as Figure 5 As shown in Figure 52 is a schematic perspective view of a semiconductor device 200. The fin structure 204 in the area not covered by the sacrificial gate structure 210 and the gate sidewall spacer 220g is first recessed etched to form a source / drain recess. The bottom spacer 220b, the gate top spacer 220gt, the fin top spacer 220f, and a portion of the fin sidewall spacer 220f are removed during the etch back of the fin structure 204. In some embodiments, a suitable dry etch and / or wet etch may be used to remove the semiconductor material in the fin structure 204. In some embodiments, the fin structures 204a, 204b are recessed to a level below the isolation layer 208.

[0077] Epitaxial source / drain regions 222 are then formed in the source / drain recesses. The epitaxial source / drain regions 222 may be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. The epitaxial source / drain regions 222 may be grown in an epitaxial chamber by a suitable process. For example, the epitaxial source / drain regions 222 are formed by a selective etching growth process, in which a thin film is deposited by introducing a reactive gas containing both a deposition agent and an etching agent. In some embodiments, an optional etching process may be performed to achieve a desired shape and / or thickness of the epitaxial layer being formed.

[0078] The epitaxial source / drain regions 222 may include one or more layers of Si, SiP, SiC, and SiCP for n-type devices or one or more layers of Si, SiGe, Ge for p-type devices. For n-type devices, the epitaxial source / drain regions 222 also include n-type dopants such as phosphorus (P), arsenic (As), etc. For p-type devices, the epitaxial source / drain regions 222 include p-type dopants such as boron (B). The epitaxial source / drain regions 222a, 222b may be formed separately using a mask and a suitable patterning process.

[0079] In operation 112, a contact etch stop layer (CESL) 224 and an interlayer dielectric (ILD) layer 226 are formed over the semiconductor device 200. Figure 6 and FIG. 6A to FIG. 6B as shown in . Figure 6 is a schematic perspective view of the semiconductor device 200 . Fig. 6A The semiconductor device 200 is along Figure 6 Schematic cross-sectional view along line AA. Figure 6B The semiconductor device 200 is along Figure 62 is a schematic cross-sectional view of line BB of FIG. 2. A CESL 224 is conformally formed over the exposed surface of the semiconductor device 200. The CESL 224 is formed over the epitaxial source / drain regions 222, the sidewall spacers 220g, and the isolation layer 208 (if exposed). The CESL 224 may include SiN, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0080] An ILD layer 226 is formed over the CESL 224. Materials for the ILD layer 226 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the ILD layer 226. In some embodiments, the ILD layer 226 may be formed by flowable CVD (FCVD). The ILD layer 226 protects the epitaxial source / drain regions 222 during removal of the sacrificial gate structure 210.

[0081] In operation 114, the sacrificial gate structure 210 is removed, such as Fig. 7A and Figure 7B as shown in . Fig. 7A The semiconductor device 200 is along Figure 6 Cross-sectional view along line AA. Figure 7B The semiconductor device 200 is along Figure 6 The sacrificial gate structure 210 is removed to form a gate cavity 228 and expose the fin structure 204 so that a replacement gate structure can be formed in the gate cavity 228 .

[0082] The mask layer 218, the liner layer 216, the sacrificial gate electrode layer 214, and the sacrificial gate dielectric layer 212 may be removed in sequence by one or more suitable processes such as dry etching, wet etching, or a combination thereof to expose the fin structures 204. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution is used. After operation 114, the sidewalls 204s and the top surface 204t of each fin structure 204 are exposed to the gate cavity 228.

[0083] After operation 116, an interfacial dielectric layer 230 is formed over the fin structure 204, such as Fig. 7A and Figure 7B As shown in FIG. , an interfacial dielectric layer 230 may be formed on the exposed surface of the fin structure 204. FIG. 7A to FIG. 7B As shown in FIG. 2 , an interfacial dielectric layer 230 may be formed over the sidewalls 204s and the top surface 204t of the fin structure 204. In some embodiments, the interfacial dielectric layer 230 is substantially conformally formed on the sidewalls 204s and the top surface 204t of the fin structure 204.

[0084] The interfacial dielectric layer 230 may be an ultra-thin interfacial dielectric layer, which means that the interfacial dielectric layer 230 has a thickness in a range between about 5 angstroms and about 15 angstroms, for example, the interfacial dielectric layer 230 has a thickness less than or equal to about 10 angstroms.

[0085] The interfacial dielectric layer 230 may be an oxygen-containing layer, such as a silicon oxide (SiO2) layer or a silicon oxynitride (SiON) layer. The interfacial dielectric layer 230 may be formed by a chemical oxidation technique, a thermal oxidation technique, an atomic layer deposition (ALD), a chemical vapor deposition (CVD), or other suitable techniques. In some embodiments, the interfacial dielectric layer 230 includes at least one of HfSiO or SiON formed by at least one of atomic layer deposition (ALD), CVD, PVD, thermal oxidation and nitridation, plasma oxidation, or nitridation. In some embodiments, a Hf film is formed on a thermal oxide by ALD, CVD, or PVD, and then the Hf film is oxidized by hot O2 to form HfSiO. In some embodiments, the Hf film is formed by ALD, CVD, or PVD in a reactive O2 and H2O environment. In some embodiments, a cleaning process, such as a cleaning process using a hydrofluoric (HF) acid solution, may be performed before the interfacial dielectric layer 230 is formed over the fin structure 204.

[0086] In operation 118, a gate dielectric layer 232 is formed over the fin structure 204, such as FIG. 8A to FIG. 8B as shown in . Fig. 8A The semiconductor device 200 is along Figure 6 Cross-sectional view along line AA. Figure 8B The semiconductor device 200 is along Figure 6 Cross-sectional view along line BB in FIG.

[0087] A gate dielectric layer 232 is deposited over the interfacial dielectric layer 230 and other exposed surfaces such as the isolation layer 208. The gate dielectric layer 232 may be conformally deposited on the exposed surfaces in the gate cavity 228. The gate dielectric layer 232 may have a thickness ranging between about 5 angstroms to about 30 angstroms depending on the device design.

[0088] The gate dielectric layer 232 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. In some embodiments, the gate dielectric layer 232 includes hafnium oxide (HfO2). In other embodiments, the gate dielectric layer 232 includes Hf-XO material, where X is silicon or a metal, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HfTiO), or hafnium zirconium oxide (HfZrO); hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy; zirconium oxide (ZrO2); Zr-XO material, where X is silicon or a metal, such as zirconium silicate (ZrSiO4) or zirconium aluminate (ZrAlO); titanium oxide (TiO2); Ti-XO, where X is silicon or a metal; lanthanum oxide (La2O3); La-XO material, where X is silicon or a metal; rare earth oxides; other suitable high-k dielectric materials; or combinations thereof.

[0089] The gate dielectric layer 232 may be formed by a suitable process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, other suitable processes, or a combination thereof.

[0090] The gate dielectric layer 232 may have different compositions and dimensions for N-type devices and P-type devices, and may be formed separately using a patterned mask layer and different deposition recipes. The gate dielectric layer 232 may be formed by CVD, ALD, or any suitable method.

[0091] In operation 120, a first work function metal layer 234 is formed over the gate dielectric layer 232, such as FIG. 9A to FIG. 9B as shown in . Fig.9A The semiconductor device 200 is along Figure 6 Cross-sectional view along line AA. Fig. 9B The semiconductor device 200 is along Figure 6 Cross-sectional view along line BB in FIG.

[0092] The first work function metal layer 234 is deposited over the gate dielectric layer 232. In some embodiments, the first work function metal layer 234 may include a material for removing impurity atoms such as oxygen impurities from the interfacial dielectric layer 230.

[0093] In some embodiments, the first work function metal layer 234 includes a titanium-rich or tantalum-rich material. For example, the first work function metal layer 234 includes a transition metal nitride such as titanium nitride (TiN) or a transition metal carbide such as tantalum carbide (TaC). The first work function metal layer 234 is rich in metal, such as titanium-rich or tantalum-rich, because it is envisioned that the ratio of metal to nitrogen or carbon is greater than one. In some embodiments, the first work function metal layer 234 is a titanium-rich TiN layer having a Ti:N ratio in a range between about 1.05:1 to about 2:1. In other embodiments, the first work function metal layer 234 is a tantalum-rich TaC layer having a Ta:C ratio in a range between about 1.05:1 to about 2:1. Alternatively, the first work function metal layer 234 may include a reactive metal material to facilitate the removal of impurity atoms from the dielectric layer, such as hafnium (Hf), titanium (Ti), cobalt (Co), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), other reactive metals, or combinations thereof. In some embodiments, the reactive metal material is a material that is capable of reacting with oxygen.

[0094] In some embodiments, the first work function metal layer 234 is a non-conformal layer. Specifically, the first work function metal layer 234 has a non-uniform thickness. In some embodiments, the first work function metal layer 234 has a sidewall thickness S1 along the sidewall 204s of the fin structure 204 and a horizontal thickness H1 above the top surface 204t of the fin structure 204. The sidewall thickness S1 is different from the horizontal thickness H1. Specifically, the horizontal thickness H1 is greater than the sidewall thickness S1. In some embodiments, the ratio of the horizontal thickness H1 to the sidewall thickness S1 is in a range between about 1.1 and about 1.5. In some embodiments, depending on the device design, the sidewall thickness S1 is in a thickness range of about 5 angstroms to about 30 angstroms.

[0095] For a larger horizontal thickness H1, the first work function metal layer 234 is thicker at the top of the fin structure 204. Because the top portion of the fin structure 204 will be more exposed to the processing environment than the sidewall portion of the fin structure 204 during subsequent processing, the thicker first work function metal layer 234 above the top surface 204t will avoid being damaged and causing leakage. The thinner portion of the first work function metal layer 234 on the sidewall 204s of the fin structure 204 leaves additional space for low resistance conductive material in the gate cavity 228 between the fin structures 204, thereby improving device performance. In addition, due to the geometry of the fin structure 204, during operation of the semiconductor device 200, the current density is higher near the top surface 204t of the fin structure 204, and the larger thickness of the first work function metal layer 234 can provide better leakage control around the top portion of the fin structure 204. The thicker work function metal layer 234 on the top surface makes it easier to turn on the device because the carrier density at the top is higher in the on state. Therefore, the thicker work function metal layer 234 on the top of the fin can improve device performance. In addition, the thicker work function metal layer 234 on the top area of ​​the fin makes it more difficult for oxygen to diffuse into the interface layer and the gate dielectric layer, thereby preventing the regrowth of the interface layer and resulting in a lower oxide thickness, thereby improving device performance. In the off state, current leakage mainly comes from the central part of the fin. If the work function metal layer 234 is thinner on the sidewall 204s, the sidewall area will require a larger threshold voltage Vt to turn on. Therefore, the thinner work function metal layer 234 on the sidewall 204s can also help reduce leakage current in the off state.

[0096] In some embodiments, the first work function metal layer 234 may be formed by ALD. In some embodiments, the non-conformal thickness of the first work function metal layer 234 may be achieved by adjusting the process pressure and / or pulse duration of the precursor during the ALD process. In some embodiments, the process pressure of the ALD process may be reduced to a level between about 40% and about 60% of the pressure level for conformal deposition to achieve a greater horizontal thickness H1. In other embodiments, the precursor injection pulse of the ALD process may be reduced to a length between about 30% and about 70% of the pulse length for conformal deposition to achieve a greater horizontal thickness H1.

[0097] In operation 122, a second work function metal layer 236 is formed over the first work function metal layer 234. FIG. 10A to FIG. 10B as shown in . Fig. 10A The semiconductor device 200 is along Figure 6 Cross-sectional view along line AA. Fig. 10B The semiconductor device 200 is along Figure 6 Cross-sectional view along line BB in FIG.

[0098] A second work function metal layer 236 is deposited over the first work function metal layer 234. The second work function metal layer 236 may act as a barrier layer. In some embodiments, the second work function metal layer 236 may include a material to prevent a small metal element such as aluminum in a subsequent film from diffusing into the gate dielectric layer 232. In some embodiments, the second work function metal layer 236 is a multi-metal layer structure. The second work function metal layer 236 is at least one of tungsten nitride (WN), tantalum nitride (TaN), or ruthenium (Ru). In some embodiments, for example, for an N-type device, the second work function metal layer 236 includes TaN. In some embodiments, for example, for a P-type device, the second work function metal layer 236 is titanium nitride / tungsten nitride (TiN / WN).

[0099] In some embodiments, the second work function metal layer 236 is a non-conformal layer. Specifically, the second work function metal layer 236 has a non-uniform thickness. In some embodiments, the second work function metal layer 236 has a sidewall thickness S2 along the sidewall 204s of the fin structure 204 and a horizontal thickness H2 above the top surface 204t of the fin structure 204. The sidewall thickness S2 is different from the horizontal thickness H2. Specifically, the horizontal thickness H2 is greater than the sidewall thickness S2. In some embodiments, the ratio of the horizontal thickness H2 to the sidewall thickness S2 is in a range between about 1.1 and about 1.5. In some embodiments, depending on the device design, the sidewall thickness S2 is in a thickness range of about 10 angstroms to about 50 angstroms.

[0100] For a larger horizontal thickness H2, the second work function metal layer 236 is thicker at the top of the fin structure 204. Because the top portion of the fin structure 204 will be more exposed to the processing environment than the sidewall portion of the fin structure 204 during subsequent processing, the thicker second work function metal layer 236 above the top surface 204t will avoid being damaged and causing leakage. The thinner portion of the second work function metal layer 236 on the sidewall 204s of the fin structure 204 leaves additional space for low resistance conductive material in the gate cavity 228 between the fin structures 204, thereby improving device performance. In addition, due to the geometry of the fin structure 204, during operation of the semiconductor device 200, the current density is higher near the top surface 204t of the fin structure 204, and the larger thickness of the second work function metal layer 236 can provide better leakage control around the top of the fin structure 204. The thicker second work function metal layer 236 near the top surface 204t makes it easier to turn on the device because the carrier density at the top of the fin is higher in the on state. Therefore, the thicker second work function metal layer 236 near the top surface 204t can improve device performance. In addition, the thicker second work function metal layer 236 near the top surface 204t can prevent anisotropic process damage and make it difficult for Al atoms to be driven into the interface layer and the high-k dielectric layer. In the off state, current leakage mainly comes from the central area of ​​the fin. If the work function metal layer 236 is thinner near the sidewall 204s of the fin, the sidewall area may require a larger threshold voltage Vt to turn on, so it reduces the leakage current in the off state.

[0101] In some embodiments, the second work function metal layer 236 may be formed by ALD, CVD, or PVD. In some embodiments, the non-conformal thickness of the second work function metal layer 236 may be achieved by adjusting the process pressure and / or pulse duration of the precursor during the ALD process. In some embodiments, the process pressure of the ALD process may be reduced to a level between about 50% and about 60% of the pressure level for conformal deposition to achieve a greater horizontal thickness H2. In other embodiments, the precursor injection pulse of the ALD process may be reduced to a length between about 30% and about 70% of the pulse length for conformal deposition to achieve a greater horizontal thickness H2.

[0102] like FIG. 10A to FIG. 10B As shown in , the first work function metal layer 234 and the second work function metal layer 236 form a combined non-conformal layer 238 having a horizontal thickness Ha and a sidewall thickness Sa. The horizontal thickness Ha is greater than the sidewall thickness Sa. In some embodiments, the ratio of the sidewall thickness Sa of the combined non-conformal layer 238 to the width W1 of the fin structure 204 is in a range between about 0.5 and about 1.0. The ratio of the horizontal thickness Ha to the sidewall thickness Sa is in a range between about 1.1 and about 1.5.

[0103] The size of the combined non-conformal layer 238 can be achieved by adjusting the size of the first work function metal layer 234 and the second work function metal layer 236. FIG. 10A to FIG. 10B In the embodiment shown in , both the first work function metal layer 234 and the second work function metal layer 236 are non-conformal layers. Alternatively, only one of the first work function metal layer 234 and the second work function metal layer 236 is non-conformal.

[0104] Fig. 10C is a schematic cross-sectional view of a semiconductor device 200a according to another embodiment of the present disclosure. The semiconductor device 200a is similar to the semiconductor device 200, except that the semiconductor device 200a includes a first work function metal layer 234' and a second work function metal layer 236'. The first work function metal layer 234' is conformal, while the second work function metal layer 236' is non-conformal. The first work function metal layer 234' and the second work function metal layer 236' form a combined non-conformal layer 238'. The first work function metal layer 234' has a sidewall thickness S1' that is substantially the same as the horizontal thickness H1'. The second work function metal layer 236' has a horizontal thickness H2' that is greater than the sidewall thickness S2'. The combined non-conformal layer 238' has a horizontal thickness Ha' that is greater than the sidewall thickness Sa'.

[0105] Fig. 10D is a schematic cross-sectional view of a semiconductor device 200b according to another embodiment of the present disclosure. The semiconductor device 200b is similar to the semiconductor device 200, except that the semiconductor device 200b includes a first work function metal layer 234" and a second work function metal layer 236". The first work function metal layer 234" is non-conformal, while the second work function metal layer 236" is conformal. The first work function metal layer 234" and the second work function metal layer 236" form a combined non-conformal layer 238". The first work function metal layer 234" has a horizontal thickness H1" that is greater than the sidewall thickness S1". The second work function metal layer 236" has a horizontal thickness H2" that is substantially the same as the sidewall thickness S2". The combined non-conformal layer 238" has a horizontal thickness Ha" that is greater than the sidewall thickness Sa".

[0106] In operation 124, a third work function metal layer 240 is formed over the combined non-conformal layer 238, such as FIG. 11A to FIG. 11B as shown in . Fig.11A The semiconductor device 200 is along Figure 6 Cross-sectional view along line AA. Fig. 11B The semiconductor device 200 is along Figure 6 Cross-sectional view along line BB in FIG.

[0107] The third work function metal layer 240 may include one or more conductive materials. In some embodiments, the third work function metal layer 240 is designed to adjust and achieve a target threshold voltage. In some embodiments, the third work function metal layer 240 may include one or more layers of conductive materials, such as Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, Ti, Ta, Zr, TiAl, TiAlN, metal compounds / alloys such as TiN, brass, phosphor bronze, cast steel, and / or combinations thereof. In some embodiments, the third work function metal layer 240 may include a titanium aluminum (TiAl) layer or a titanium aluminum nitride (TiAlN) layer. The third work function metal layer 240 may be formed using ALD, CVD, or other suitable methods.

[0108] In some embodiments, the third work function metal layer 240 is a non-conformal layer. Specifically, the third work function metal layer 240 has a non-uniform thickness. In some embodiments, the third work function metal layer 240 has a sidewall thickness S3 along the sidewall 204s of the fin structure 204 and a horizontal thickness H3 above the top surface 204t of the fin structure 204. The sidewall thickness S3 is different from the horizontal thickness H3. Specifically, the horizontal thickness H3 is greater than the sidewall thickness S3. In some embodiments, based on the material type, the ratio of the horizontal thickness H3 to the sidewall thickness S3 is in a range between about 1.1 and about 1.8. In some embodiments, the sidewall thickness S3 is in a thickness range of about 6 angstroms to about 50 angstroms.

[0109] For a larger horizontal thickness H3, the third work function metal layer 240 is thicker at the top of the fin structure 204. Because the top portion of the fin structure 204 has a higher current density than the sidewalls, a third work function metal layer 240 with a larger horizontal thickness H3 can be used to achieve ion current requirements with a lower threshold voltage. The lower threshold voltage has several benefits. For example, the lower threshold voltage corresponds to a smaller electric field in the gate dielectric layer 232, thereby improving reliability. The lower threshold voltage also provides room for device boosting using threshold voltage and ion adjustment. In addition, the lower threshold voltage can reduce the off-state current (Ioff), thereby achieving better leakage control. In addition, the thinner portion of the third work function metal layer 240 on the sidewalls 204s of the fin structure 204 leaves additional space for low-resistance conductive material in the gate cavity 228 between the fin structures 204, thereby improving device performance.

[0110] The work function metal layers 234, 236, 240 for n-type FET and p-type FET may include different materials or have different combinations to achieve different threshold voltages. The work function metal layers for n-type devices and p-type devices may be formed separately using one or more patterning processes.

[0111] Alternatively, the third work function metal layer 240 may be conformally formed over the sidewalls 204 s and the top surface 204 t of the fin structure 204 . Fig. 11C is a schematic cross-sectional view of a semiconductor device 200 c according to one embodiment of the present disclosure. The semiconductor device 200 c is similar to the semiconductor device 200 except that the semiconductor device 200 c includes a third work function metal layer 240 ′ having a conformal thickness around the fin structure 204 .

[0112] like Fig. 12A As shown in FIG. 1 , the first work function metal layer 234, the second work function metal layer 236, and the third work function metal layer 240 form a work function metal film stack having a sidewall thickness S and a horizontal thickness H. The sidewall thickness S may be designed according to the width W1 of the fin structure 204. In some embodiments, the ratio of the sidewall thickness S to the fin width W1 may be in the range of about 0.5 to about 1.0. The horizontal thickness H is greater than the sidewall thickness S. In some embodiments, the ratio of the horizontal thickness H to the sidewall thickness S may be in the range of about 1.1 to about 1.5.

[0113] In operation 126, a gate filling layer 242 is formed in the gate cavity 228, such as Fig.12 and FIG. 12A to FIG. 12B as shown in . Fig.12 is a schematic perspective view of the semiconductor device 200 . Fig. 12A The semiconductor device 200 is along Fig.12 Cross-sectional view along line AA. Fig. 12B The semiconductor device 200 is along Fig.12 Cross-sectional view along line BB in FIG.

[0114] The gate filling layer 242 then forms the third work function metal layer 240 to fill the gate cavity 228. The gate filling layer 242 may include one or more layers of conductive materials, such as tungsten, copper, aluminum, metal alloys, other suitable materials and / or combinations thereof. In some embodiments, the gate filling layer 242 may be formed by CVD, ALD, electroplating or other suitable methods. After the gate filling layer 242 is formed, a planarization process, such as a CMP process, is performed to remove excess deposition of gate electrode material and expose the top surface of the ILD layer 226.

[0115] As described above, embodiments of the present disclosure provide a work function metal film stack that is non-conformal. In particular, the non-conformality may be characterized by a larger thickness above the top surface of the fin structure and a smaller thickness along the sidewalls of the fin structure. The non-conformality may be achieved by forming one or more non-conformal films in the work function metal film stack.

[0116] In the semiconductor device 200, the work function metal film stack includes a first work function metal layer 234, a second work function metal layer 236, and a third work function metal layer 240. The first work function metal layer 234 includes a reactive metal material to facilitate the removal of impurity atoms from the gate dielectric layer. The second work function metal layer 236 includes a barrier material for preventing metal atoms from diffusing from the third work function metal layer 240 into the gate dielectric layer. The third work function metal layer 240 is used to achieve a target threshold voltage. According to design requirements, one or more of the first work function metal layer 234, the second work function metal layer 236, and the third work function metal layer 240 can be formed non-conformally.

[0117] FIG. 13A to FIG. 13F Various work function metal film stack designs according to embodiments of the present disclosure are schematically illustrated. FIG. 13A to FIG. 13F In the embodiment, various work function metal film stacks are formed by different combinations of conformal work function metal layers 234c, 236c, 240c and non-conformal work function metal layers 234n, 236n, 240n.

[0118] Fig.14A is a transmission electron microscopy (TEM) image of a cross section of an exemplary semiconductor device having a non-conformal work function metal layer according to the present disclosure. Fig.14A The semiconductor device shown in FIG. 1 is a core device having a thin gate dielectric layer. Fig.14A As shown in FIG. 1 , the first work function metal layer 234 and the second work function metal layer 236 form a combined non-conformal layer. The combined layer has a thickness Ha over the top of the fin structure 204 and a thickness Sa on the sidewalls of the fin structure 204. Fig.14A , a ratio of the thickness Ha to the thickness Sa is in a range between 1.06 and 1.30.

[0119] Fig. 14B is a TEM image of a cross section of an exemplary semiconductor device having a non-conformal work function metal layer according to the present disclosure. Fig. 14B The semiconductor device shown in is an I / O device with a thick gate dielectric layer. Fig. 14B As shown in FIG. 1 , the first work function metal layer 234 and the second work function metal layer 236 form a combined non-conformal layer. The combined layer has a thickness Ha over the top of the fin structure 204 and a thickness Sa on the sidewalls of the fin structure 204. Fig. 14B , a ratio of the thickness Ha to the thickness Sa is in a range between 1.15 and 1.35.

[0120] Fig. 14C Contains a graph showing the profile of a work function metal layer over a semiconductor fin. Fig. 14CThe x-axis in is the ratio of the work function metal layer thickness on the top of the fin to the work function metal layer thickness on the sidewall of the fin. Fig. 14C The y-axis of represents the distance from a reference point near the middle of the semiconductor fin. Fig. 14C In FIG. 1 , a quantile-quantile graph is used to show the difference between the embodiments of the present disclosure and the existing technology. Curve 10 is the profile of the work function metal layer formed according to the current technology. Curves 12 and 14 are the profiles of the work function metal layer formed according to the present disclosure. Curves 12 and 14 show a greater thickness of the work function metal layer on top of the semiconductor fin. Curve 14 is an optimized process and has more cycle time than curve 12, so the thickness is increased by about 20% to 25%.

[0121] Fig.14D is a TEM image of a cross section of an exemplary semiconductor device having a non-conformal work function metal layer according to the present disclosure. Fig.14D The semiconductor device shown in FIG. 1 has a non-conformal second work function metal layer 236 that acts as a barrier layer. The second work function metal layer has a thickness H2 over the top of the fin structure 204 and a thickness S2 on the sidewalls of the fin structure 204. Fig.14D , the ratio of thickness H2 to thickness S2 is about 1.39. The greater thickness of the second work function metal layer 236 increases the breakdown voltage of the gate dielectric layer and the maximum current without leakage. Fig.14E and Fig.14F The invention shows the improved reliability of the device according to the present disclosure and includes a graph showing the breakdown voltage. Curves 20, 22 and 30, 32 show that the non-conformal WFM barrier layer has a higher oxide breakdown voltage (from Fig.14E +0.1V to Fig.14F +0.6V in the output).

[0122] Figure 14G is an image of a cross-section of an exemplary semiconductor device having a non-conformal work function metal layer according to the present disclosure. Figure 14G A plurality of fin structures 204 are shown. Figure 14G As shown in FIG. 1 , the first work function metal layer 234, the second work function metal layer 236, and the third work function metal layer 240 form a combined non-conformal layer. The combined layer has a thickness Ha over the top of the fin structure 204 and a thickness Sa on the sidewalls of the fin structure 204. The non-conformal work function metal film stack results in an increase in the space SR between the fin structures 204, where a low resistance material or gate fill layer 242 is formed. Fig.14H Schematic equivalent circuit including gate dielectric layer, work function metal layer stack and gate fill layer around fin structure. The increase in volume between fin-to-fin space of gate fill layer will reduce Rv, thus improving device performance.

[0123] Fig.15 1 is a flow chart of an exemplary method 300 for forming a semiconductor device according to an embodiment of the present disclosure. Method 300 is similar to method 100, except that instead of forming a work function metal film having a non-conformal thickness, method 300 includes an operation of forming a work function metal film stack having a non-uniform solid phase. Method 300 includes operations 102-118, operations 102-118 are performed at Figures 2 to 8A to Figure 8B Schematically illustrated and described in FIG.

[0124] In operation 320, a first work function metal layer 434 is formed over the gate dielectric layer 232, such as Fig.16A The first work function metal layer 434 includes a portion of amorphous material to provide a better diffusion barrier than a polycrystalline film. In some embodiments, the first work function metal layer 434 includes a metal carbonitride (Ta x C y N z The amorphous phase of the first work function metal layer 434 may be selected from the group consisting of TiN, TaCN, WN, TaN, Ru, TiN / WN, and TiSiN (amorphous TiN doped with Si). The amorphous phase of the first work function metal layer 434 may be achieved by adjusting the deposition temperature, pressure, or other process parameters. In some embodiments, the amorphous first work function metal layer 434 has a thickness in a range between about 5 angstroms and about 30 angstroms.

[0125] In operation 322, a second work function metal layer 440 is formed over the work function metal layer 434, such as Fig.16A As shown in . The second work function metal layer 440 may include one or more conductive materials. In some embodiments, the second work function metal layer 440 is designed to adjust and achieve a target threshold voltage. In some embodiments, the second work function metal layer 440 may include one or more layers of conductive materials, such as Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, Ti, Ta, Zr, TiAl, TiAlN, metal compounds / alloys such as TiN, brass, phosphor bronze, cast steel and / or combinations thereof. In some embodiments, the second work function metal layer 440 may include a titanium aluminum (TiAl) layer or a titanium aluminum nitride (TiAlN) layer. The second work function metal layer 440 may be formed using ALD, CVD or other suitable methods. In some embodiments, the second work function metal layer 440 is a non-conformal layer, such as Fig.16A Alternatively, the second work function metal layer 440 may be a conformal layer.

[0126] Fig. 16BThe work function metal film stack of the semiconductor device 400 is schematically illustrated. The amorphous first work function metal layer 434 prevents metal atoms such as aluminum from diffusing through and into the gate dielectric layer 232 .

[0127] exist Fig.16A In the embodiment of the present invention, the first work function metal layer 434 includes a single layer of amorphous film. Alternatively, the first work function metal layer 434 may include one or more layers having other solid phases. For example, the first work function metal layer 434 may include a material layer or portion of other phases such as a polycrystalline phase or a crystalline phase.

[0128] Fig.17A A semiconductor device 400a manufactured using method 300 is schematically illustrated. Semiconductor device 400a is similar to semiconductor device 400, except that semiconductor device 400a includes a first work function metal layer 434a having a polycrystalline portion 4341 and an amorphous portion 4342. In some embodiments, polycrystalline portion 4341 may be formed over gate dielectric layer 232. In some embodiments, polycrystalline portion 4341 may have a conformal thickness. In some embodiments, polycrystalline portion 4341 may have a non-conformal thickness, such as being thicker at the top of the fin and thinner at the sidewalls of fin structure 204. Amorphous portion 4342 is formed over polycrystalline portion 4341. In some embodiments, amorphous portion 4342 is formed over a portion of polycrystalline portion 4341. For example, Fig.17A As shown in FIG. 4 , a non-crystalline portion 4342 is formed on the polycrystalline portion 4341 over the top surface 204t of the fin structure 204, but not on the polycrystalline portion 4341 over the sidewall 204s of the fin structure 204. In some embodiments, the non-crystalline portion 4342 has a thickness in a range between about 3 angstroms and about 20 angstroms.

[0129] Alternatively, the non-crystalline portion 4342 is formed over the entire polycrystalline portion 4341. In some embodiments, the non-crystalline portion 4342 may be formed conformally over the entire polycrystalline portion 4341. In some embodiments, the non-crystalline portion 4342 may be formed non-conformally over the entire polycrystalline portion 4341, for example, thicker over the top of the fin and thinner on the sidewalls.

[0130] Fig. 17B The work function metal film stack of the semiconductor device 400 a is schematically illustrated. The non-crystalline portion 4342 is disposed against the second work function metal layer 440 , thereby preventing metal atoms such as aluminum from diffusing through and into the gate dielectric layer 232 .

[0131] Embodiments of the present disclosure provide a FinFET transistor having a gate structure that includes one or more non-conformal work function metal layers. In some embodiments, the work function metal layer may be non-conformal in at least one of thickness, composition, and / or phase. The non-uniformity of the work function metal layer reduces leakage, improves device performance, and increases device reliability.

[0132] It should be understood that not all advantages must be discussed herein, not all embodiments or examples require a particular advantage, and other embodiments or examples may provide different advantages.

[0133] Some embodiments of the present disclosure are directed to a semiconductor device, comprising: a first source / drain region; a second source / drain region; a fin-shaped structure disposed between the first source / drain region and the second source / drain region; and a gate structure disposed above a top surface and sidewalls of the fin-shaped structure, wherein the gate structure comprises: a gate dielectric layer; and a work function metal film stack, wherein the work function metal film stack is non-conformal in at least one of thickness and phase. According to some embodiments of the present disclosure, the work function metal film stack has a first thickness on the top surface of the fin-shaped structure and a second thickness along the plurality of sidewalls of the fin-shaped structure, and the first thickness is greater than the second thickness. According to some embodiments of the present disclosure, the work function metal film stack includes: a first work function metal layer disposed on the gate dielectric layer; a second work function metal layer disposed on the first work function metal layer; and a third work function metal layer disposed on the second work function metal layer, wherein at least one of the first work function metal layer, the second work function metal layer and the third work function metal layer has a greater thickness on the top surface of the fin structure than on the multiple sidewalls of the fin structure. According to some embodiments of the present disclosure, the first work function metal layer has a greater thickness on the top surface of the fin structure than on the multiple sidewalls of the fin structure. According to some embodiments of the present disclosure, the second work function metal layer has a greater thickness on the top surface of the fin structure than on the multiple sidewalls of the fin structure. According to some embodiments of the present disclosure, the third work function metal layer has a greater thickness on the top surface of the fin structure than on the multiple sidewalls of the fin structure. According to some embodiments of the present disclosure, the work function metal film stack has an amorphous portion and a polycrystalline portion. According to some embodiments of the present disclosure, the work function metal film stack includes: a first work function metal layer disposed on the gate dielectric layer, wherein the amorphous portion is located in the first work function metal layer; and a second work function metal layer disposed on the first work function metal layer. According to some embodiments of the present disclosure, the first work function metal layer is amorphous on the top surface and the plurality of sidewalls of the fin-shaped structure. According to some embodiments of the present disclosure, the first work function metal layer is amorphous on the top surface of the fin-shaped structure and is polycrystalline on the plurality of sidewalls of the fin-shaped structure.

[0134] Some embodiments of the present disclosure are related to a semiconductor device, comprising: a first source / drain region; a second source / drain region; a fin-shaped structure disposed between the first source / drain region and the second source / drain region, wherein the fin-shaped structure has a first sidewall, a second sidewall opposite to the first sidewall, and a top surface connecting the first sidewall and the second sidewall; and a gate structure disposed above the top surface, the first sidewall, and the second sidewall of the fin-shaped structure, wherein the gate structure comprises: a gate dielectric layer; a work function metal film stack disposed on the gate dielectric layer; and a gate filling layer disposed on the work function metal film stack, wherein the work function metal film stack has a first thickness above the top surface of the fin-shaped structure and has a second thickness along the first sidewall and the second sidewall of the fin-shaped structure, and the first thickness is greater than the second thickness. According to some embodiments of the present disclosure, a ratio of the first thickness to the second thickness is in a range between about 1.1 and about 1.5. According to some embodiments of the present disclosure, the fin structure has a width from the first sidewall to the second sidewall, and a ratio of the second thickness to the width is in a range between about 0.5 and about 1.0. According to some embodiments of the present disclosure, the work function metal film stack includes: a first work function metal layer disposed on the gate dielectric layer; a second work function metal layer disposed on the first work function metal layer; and a third work function metal layer disposed on the second work function metal layer, wherein at least one of the first work function metal layer, the second work function metal layer and the third work function metal layer has a greater thickness on the top surface of the fin structure than on the first sidewall and the second sidewall of the fin structure. According to some embodiments of the present disclosure, the work function metal film stack includes: an amorphous portion disposed on the top surface of the fin structure; and a polycrystalline portion disposed on the first sidewall, the second sidewall and the top surface of the fin structure.

[0135] Some embodiments of the present disclosure are related to a method, including: forming a fin-shaped structure; forming a sacrificial gate structure above the fin-shaped structure; etching the fin-shaped structure on both sides of the sacrificial gate structure to form a source / drain groove; forming a source / drain region in the source / drain groove; removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin-shaped structure; depositing a gate dielectric layer on the top surface and two sidewalls of the fin-shaped structure; depositing a work function metal film stack above the gate dielectric layer, wherein the work function metal film stack has a first thickness above the top surface of the fin-shaped structure and a second thickness along the two sidewalls of the fin-shaped structure, and the first thickness is greater than the second thickness; and depositing a gate fill layer above the work function metal film stack. According to some embodiments of the present disclosure, the step of depositing the work function metal film stack includes: forming a first work function metal layer on the gate dielectric layer; forming a second work function metal layer on the first work function metal layer; and forming a third work function metal layer on the second work function metal layer, wherein at least one of the first work function metal layer, the second work function metal layer and the third work function metal layer has a greater thickness on the top surface of the fin structure than on the two sidewalls of the fin structure. According to some embodiments of the present disclosure, the step of depositing the work function metal film stack includes: using an atomic layer deposition process with a reduced pressure and a reduced pulse to form one of the first work function metal layer, the second work function metal layer and the third work function metal layer to obtain a greater thickness on the top surface of the fin structure. According to some embodiments of the present disclosure, the step of depositing the work function metal film stack includes: forming an amorphous portion on the gate dielectric layer. According to some embodiments of the present disclosure, the step of depositing the work function metal film stack further includes: depositing a polycrystalline film on the gate dielectric layer, wherein the amorphous portion is formed on the polycrystalline film on the top surface of the fin structure.

[0136] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first source / drain region; a second source / drain region; A fin-shaped structure disposed between the first source / drain region and the second source / drain region; and A gate structure is disposed on a top surface and a plurality of sidewalls of the fin-shaped structure, wherein the gate structure comprises: a gate dielectric layer; and A work function metal film stack, wherein the work function metal film stack is non-conformal in at least one of thickness and phase.

2. The semiconductor device according to claim 1, wherein The work function metal film stack has a first thickness on the top surface of the fin-shaped structure and a second thickness along the sidewalls of the fin-shaped structure, and the first thickness is greater than the second thickness.

3. The semiconductor device according to claim 2, wherein: The work function metal film stack includes: a first work function metal layer disposed on the gate dielectric layer; a second work function metal layer disposed on the first work function metal layer; and A third work function metal layer is disposed on the second work function metal layer, wherein at least one of the first work function metal layer, the second work function metal layer and the third work function metal layer has a greater thickness on the top surface of the fin structure than on the multiple side walls of the fin structure.

4. The semiconductor device according to claim 3, wherein: The first work function metal layer has a greater thickness on the top surface of the fin structure than on the sidewalls of the fin structure.

5. The semiconductor device according to claim 3, wherein: The second work function metal layer has a greater thickness on the top surface of the fin structure than on the sidewalls of the fin structure.

6. The semiconductor device according to claim 3, wherein: The third work function metal layer has a greater thickness on the top surface of the fin structure than on the sidewalls of the fin structure.

7. The semiconductor device according to claim 1, wherein The work function metal film stack has an amorphous portion and a polycrystalline portion.

8. The semiconductor device according to claim 7, wherein: The work function metal film stack includes: a first work function metal layer disposed on the gate dielectric layer, wherein the amorphous portion is located in the first work function metal layer; and A second work function metal layer is disposed on the first work function metal layer.

9. A semiconductor device, characterized in that: include: a first source / drain region; a second source / drain region; A fin-shaped structure is disposed between the first source / drain region and the second source / drain region, wherein the fin-shaped structure has a first sidewall, a second sidewall opposite to the first sidewall, and a top surface connecting the first sidewall and the second sidewall; and A gate structure is disposed above the top surface, the first sidewall and the second sidewall of the fin-shaped structure, wherein the gate structure comprises: a gate dielectric layer; a work function metal film stack located on the gate dielectric layer; and a gate filling layer, located on the work function metal film stack, The work function metal film stack has a first thickness on the top surface of the fin-shaped structure and a second thickness along the first sidewall and the second sidewall of the fin-shaped structure, and the first thickness is greater than the second thickness.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: forming a fin-shaped structure; forming a sacrificial gate structure above the fin structure; Etching the fin-shaped structure on both sides of the sacrificial gate structure to form a plurality of source / drain grooves; forming a plurality of source / drain regions in the plurality of source / drain recesses; removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin-shaped structure; Depositing a gate dielectric layer on the top surface and the two sidewalls of the fin structure; Depositing a work function metal film stack over the gate dielectric layer, wherein the work function metal film stack has a first thickness on the top surface of the fin structure and a second thickness along the two sidewalls of the fin structure, and the first thickness is greater than the second thickness; and A gate filling layer is deposited on the work function metal film stack.

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