Semiconductor device and preparation method thereof

Abstract

The present invention discloses a semiconductor device and a preparation method. The semiconductor device comprises: a substrate and a channel layer; a composite barrier layer, comprising a first barrier layer and a second barrier layer; the second barrier layer comprises a first sublayer, a second sublayer and a third sublayer in sequence; the first sublayer is an undoped barrier layer, the second sublayer is a first conductive type barrier layer, and the third sublayer is an undoped barrier layer; the second barrier layer is provided with a first groove, and the first groove runs through the second barrier layer; a stress release layer is located on a side of the third sublayer away from the second sublayer, and the stress release layer is provided with a second groove; a doped III-V semiconductor layer is located in the first groove and the second groove; a gate comprises a first part and a second part, the first part is located in the second groove, and the second part protrudes from the side of the stress release layer away from the third sublayer. The above technical scheme avoids etching damage to the semiconductor film layer inside the semiconductor device and improves the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] Gallium nitride semiconductor devices have the characteristics of high power, high frequency, low loss, high voltage resistance and high temperature resistance because of the presence of a large concentration of two-dimensional electron gas (2DEG) in the heterojunction formed by the channel layer and the barrier layer.

[0003] The semiconductor film layer of the enhancement-mode GaN high electron mobility transistor (HEMT) has etching damage, which results in poor electrical performance of the GaN semiconductor device. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method to avoid etching damage to a semiconductor film layer inside the semiconductor device and improve the electrical performance of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] substrate;

[0007] A channel layer, located on one side of the substrate;

[0008] A composite barrier layer, comprising a first barrier layer and a second barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer sequentially comprises a first sublayer, a second sublayer and a third sublayer, the first sublayer is located on a side of the first barrier layer away from the channel layer; the first sublayer is an undoped barrier layer, the second sublayer is a first conductivity type barrier layer, and the third sublayer is an undoped barrier layer; the second barrier layer is provided with a first groove, and the first groove penetrates the second barrier layer;

[0009] a stress release layer, located on a side of the third sub-layer away from the second sub-layer, the stress release layer being provided with a second groove, the second groove penetrating the stress release layer and being connected to the first groove; the stress release layer being an insulating layer;

[0010] The doped III-V semiconductor layer is set to the second conductivity type and is located in the first groove and the second groove, and the thickness of the doped III-V semiconductor layer is greater than the depth of the first groove and less than the sum of the depths of the first groove and the second groove;

[0011] a gate, comprising a first portion and a second portion, wherein the first portion is located in the second groove, and the second portion protrudes from a side of the stress release layer away from the third sub-layer;

[0012] a source electrode, located on a side of the second sub-layer or the first barrier layer away from the channel layer;

[0013] The drain is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

[0014] Optionally, the stress release layer includes a silicon nitride stress release layer.

[0015] Optionally, a field plate layer is further included, which is located on a side of the stress release layer away from the third sub-layer. The field plate layer and the gate are spaced apart and are manufactured in the same layer.

[0016] Optionally, the gate has an inverted T-shape in a cross-section perpendicular to the substrate.

[0017] Optionally, the composite barrier layer includes aluminum gallium nitride, and / or the doped III-V group semiconductor layer includes P-type gallium nitride.

[0018] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0019] providing a substrate;

[0020] forming a channel layer on one side of the substrate;

[0021] forming a first barrier layer on one side of the channel layer;

[0022] Forming a sacrificial layer on a side of the first barrier layer away from the channel layer; wherein a vertical projection area of ​​the sacrificial layer on the substrate is smaller than a vertical projection area of ​​the first barrier layer on the substrate;

[0023] A second barrier layer is formed on a side of the first barrier layer away from the channel layer, wherein the second barrier layer includes a first sublayer, a second sublayer and a third sublayer in sequence, and the first sublayer is located on a side of the first barrier layer away from the channel layer; the first sublayer is an undoped barrier layer, the second sublayer is a first conductive type barrier layer, and the third sublayer is an undoped barrier layer; the first barrier layer is in contact with a side surface of the sacrificial layer, and a height of the first barrier layer is less than a thickness of the sacrificial layer; the first barrier layer and the second barrier layer constitute a composite barrier layer;

[0024] A stress release layer is formed on a side of the third sub-layer away from the second sub-layer, the stress release layer is in contact with a side surface of the sacrificial layer and is flush with the sacrificial layer; the stress release layer is an insulating layer;

[0025] The sacrificial layer is removed by a wet etching process to form a first groove and a second groove, wherein the first groove is arranged in the second barrier layer and penetrates the second barrier layer; the second groove is arranged in the stress release layer and penetrates the stress release layer and communicates with the first groove;

[0026] forming a doped III-V semiconductor layer of a second conductivity type in the first groove and the second groove, wherein the thickness of the doped III-V semiconductor layer is greater than the depth of the first groove and less than the sum of the depths of the first groove and the second groove;

[0027] forming a gate, the gate comprising a first portion and a second portion, the first portion being located in the second groove, and the second portion protruding from a side of the stress release layer away from the third sub-layer;

[0028] forming a source electrode, wherein the source electrode is located on a side of the second sub-layer or the first barrier layer away from the channel layer;

[0029] A drain is formed, where the drain is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

[0030] Optionally, before removing the sacrificial layer by a wet etching process, the method further includes:

[0031] The stress release layer and the sacrificial layer are planarized.

[0032] Optionally, forming the gate includes:

[0033] forming a conductive layer on a side of the stress release layer away from the third sub-layer, the conductive layer comprising a first layer and a second layer, the first layer being located in the second groove, and the second layer covering the stress release layer and the first layer;

[0034] The conductive layer is patterned to obtain the gate and the field plate layer. The field plate layer is located on a side of the stress release layer away from the third sub-layer and away from the second sub-layer. The field plate layer and the gate are spaced apart.

[0035] Optionally, forming the gate includes:

[0036] A gate electrode is formed in an inverted T-shape in a cross-section perpendicular to the substrate.

[0037] Optionally, the stress release layer includes a silicon nitride stress release layer.

[0038] Optionally, the composite barrier layer includes aluminum gallium nitride, and / or the doped III-V group semiconductor layer includes P-type gallium nitride.

[0039] Optionally, forming a sacrificial layer on a side of the first barrier layer away from the channel layer includes:

[0040] forming a whole sacrificial layer on a side of the first barrier layer away from the channel layer, wherein a vertical projection area of ​​the whole sacrificial layer on the substrate is equal to a vertical projection area of ​​the first barrier layer on the substrate;

[0041] forming a photoresist layer on a side of the entire sacrificial layer away from the first barrier layer;

[0042] forming a plurality of opening patterns arranged in an array in the photoresist layer;

[0043] The entire sacrificial layer is patterned to form a plurality of sacrificial layers.

[0044] In the semiconductor device and preparation method provided by the embodiment of the present invention, the doped III-V semiconductor layer is set to the second conductivity type and is located in the first groove and the second groove. The first groove and the second groove are prepared by wet etching of the sacrificial layer, which will not cause etching damage to the second barrier layer and the first barrier layer, thereby improving the electrical performance of the semiconductor device. And because the doped III-V semiconductor layer is used as a gate cap layer, its thickness is less than the sum of the depths of the first groove and the second groove, and there is no need to perform an etching process on the doped III-V semiconductor layer, thereby avoiding etching damage and improving the electrical performance of the semiconductor device. And the first groove and the second groove are prepared by wet etching of the sacrificial layer, and a plurality of etching patterns arranged in an array can be formed by a photolithography process, and a plurality of patterned sacrificial layers arranged in an array can be formed by an etching process, and then the first groove and the second groove arranged in an array can be formed in batches by wet etching the sacrificial layer, thereby providing a semiconductor device suitable for large-scale industrial production.

[0045] Wherein, the second barrier layer includes the first sublayer, the second sublayer and the third sublayer in sequence, and the first sublayer, the second sublayer and the third sublayer constitute a three-layer sandwich structure, which can also significantly improve the polarization electric field strength and the 2DEG concentration. The second barrier layer is completed by a regrowth process on the side of the first barrier layer away from the channel layer, which can repair the surface quality of the first barrier layer. And the second barrier layer including the third sublayer can further provide more electrons, and can also significantly improve the polarization electric field strength. Wherein, the arrangement of the first sublayer and the third sublayer can avoid the diffusion of the first conductive type doping atoms in the second sublayer. The first conductive type doping atoms can be, for example, silicon atoms.

[0046] After the gate is formed on the top, the gate metal outside the gate can be used as a field plate layer through a graphic process. When the gate is completed, the field plate layer is prepared, which simplifies the preparation process and reduces the production cost.

[0047] It should be noted that the stress release layer is an insulating layer, which is located on the side of the third sublayer away from the second sublayer. On the one hand, it avoids etching damage to the composite barrier layer during the formation of the gate and increases the 2DEG concentration at the heterojunction interface. On the other hand, it releases the tensile stress inside the second barrier layer including the three sublayers, thereby improving the structural stability of the semiconductor device.

[0048] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1-Figure 4 It is a flowchart corresponding to each step of a method for preparing a trench-gate gallium nitride device in the prior art;

[0051] Figure 5-Figure 8 It is a flow chart corresponding to each step of a method for preparing a gallium nitride device in the prior art;

[0052] Fig. 9 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0053] Fig.10 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0054] Fig.11 yes Fig.10 A schematic diagram of the process included in S340;

[0055] Figure 12-Figure 20 yes Fig.11 A schematic diagram of the structure of each relevant step in the process;

[0056] Fig.21 yes Fig.10 Schematic diagram of the process included in S390;

[0057] Figure 22-Figure 23 yes Fig.21 Schematic diagram of the structure of each related step in . DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] Figure 1-Figure 4 The present invention is a flowchart corresponding to each step of a method for preparing a groove-gate gallium nitride device in the prior art, and the method for preparing the groove-gate gallium nitride device comprises the following steps: S110, providing a substrate 100, a channel layer 101 and a barrier layer 102. S120, forming a first photoresist layer 103 on a side of the barrier layer 102 away from the channel layer 101. S130, exposing and developing the first photoresist layer 103 to form an etching pattern, and forming a groove-gate structure on the surface of the barrier layer 102. S140, removing the first photoresist layer 103, and forming a gate 104 in the groove-gate structure.

[0061] Figure 5-Figure 8 The present invention is a flowchart corresponding to each step of a method for preparing a gallium nitride device in the prior art, and the method for preparing a gallium nitride device includes the following steps: S210, providing a substrate 100, a channel layer 101, a barrier layer 102 and a gate cap layer 105. S220, forming a second photoresist layer 106 on a side of the gate cap layer 105 away from the barrier layer 102. S230, exposing and developing the second photoresist layer 106 to form an etching pattern. S240, etching the gate cap layer 105, and forming a gate 104 on a side of the gate cap layer 105 away from the barrier layer 102.

[0062] The above-mentioned GaN devices are all enhancement-mode GaN high electron mobility transistors (HEMTs). Figure 1-Figure 4The formed trench-gate gallium nitride device has etching damage on the bottom and side walls of the trench-gate structure formed by the etching process, and there are many non-radiative recombination centers on the surface, which causes current collapse and leads to poor electrical performance of the gallium nitride semiconductor device.

[0063] Figure 5-Figure 8 In the formed GaN device, the interface of the gate cap layer 105 after being etched will also have etching damage, resulting in poor gate control ability of the gate cap layer 105, thereby resulting in poor electrical performance of the GaN device.

[0064] In order to avoid etching damage to the semiconductor film layer inside the semiconductor device and improve the electrical performance of the semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0065] like Fig. 9 As shown, Fig. 9 1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a substrate 200; a channel layer 201, located on one side of the substrate 200; a composite barrier layer 202, comprising a first barrier layer 203 and a second barrier layer 204; the first barrier layer 203 is located on the side of the channel layer 201 away from the substrate 200; the second barrier layer 204 comprises a first sublayer 205, a second sublayer 206 and a third sublayer 207 in sequence, the first sublayer 205 is located on the side of the first barrier layer 203 away from the channel layer 201; the first sublayer 205 is an undoped barrier layer, the second sublayer 206 is a first conductive type barrier layer, and the third sublayer 207 is an undoped barrier layer; the second barrier layer 204 is provided with a first groove T1, the first groove T1 runs through the second barrier layer 204; a stress release layer 211, located on the third sublayer 207 away from the second sublayer On one side of 206, the stress release layer 211 is provided with a second groove T2, the second groove T2 penetrates the stress release layer 211, and is connected to the first groove T1; the stress release layer 211 is an insulating layer; the doped III-V semiconductor layer 212 is set to the second conductivity type, and is located in the first groove T1 and the second groove T2, and the thickness of the doped III-V semiconductor layer 212 is greater than the depth of the first groove T1, and less than the sum of the depths of the first groove T1 and the second groove T2; the gate 213 includes a first part and a second part, the first part is located in the second groove T2, and the second part protrudes from the side of the stress release layer 211 away from the third sublayer 207; the source is located on the side of the second sublayer 206 or the first barrier layer 203 away from the channel layer 201; the drain is located on the side of the second sublayer 206 or the first barrier layer 203 away from the channel layer 201.

[0066] It should be noted that the source and drain are not marked in the drawings of the embodiments of the present invention.

[0067] In the technical solution provided by the embodiment of the present invention, the doped III-V semiconductor layer 212 is set to the second conductivity type, located in the first groove T1 and the second groove T2, and the first groove T1 and the second groove T2 are prepared by wet etching of the sacrificial layer, which will not cause etching damage to the second barrier layer 204 and the first barrier layer 203, thereby improving the electrical performance of the semiconductor device. And because the doped III-V semiconductor layer 212 is used as a gate cap layer, its thickness is less than the sum of the depths of the first groove T1 and the second groove T2, and there is no need to perform an etching process on the doped III-V semiconductor layer 212, thereby avoiding etching damage and improving the electrical performance of the semiconductor device. And the first groove T1 and the second groove T2 are prepared by wet etching of the sacrificial layer, and a plurality of etching patterns arranged in an array can be formed by a photolithography process, and a plurality of patterned sacrificial layers arranged in an array can be formed by an etching process, and then the first groove T1 and the second groove T2 arranged in an array can be formed in batches by wet etching of the sacrificial layer, thereby providing a semiconductor device suitable for large-scale industrial production.

[0068] Among them, the second barrier layer 204 includes a first sublayer 205, a second sublayer 206 and a third sublayer 207 in sequence, and the first sublayer 205, the second sublayer 206 and the third sublayer 207 constitute a three-layer sandwich structure, which can also significantly improve the polarization electric field strength and the 2DEG concentration. The second barrier layer 204 is completed by a regrowth process on the side of the first barrier layer 203 away from the channel layer 201, which can repair the surface quality of the first barrier layer 203. And the second barrier layer 204 including the third sublayer 207 can further provide more electrons and can also significantly improve the polarization electric field strength. Among them, the setting of the first sublayer 205 and the third sublayer 207 can avoid the diffusion of the first conductive type doping atoms in the second sublayer 206. The first conductive type doping atoms can be, for example, silicon atoms.

[0069] After the gate 213 is formed on the top, the gate metal outside the gate 213 can be used as a field plate layer through a graphic process. When the gate 213 is completed, the field plate layer is prepared, which simplifies the preparation process and reduces the production cost.

[0070] It should be noted that the stress release layer 211 is an insulating layer, which is located on the side of the third sublayer 207 away from the second sublayer 206. On the one hand, it avoids etching damage to the composite barrier layer 202 during the formation of the gate 213, thereby increasing the 2DEG concentration at the heterojunction interface; on the other hand, it releases the tensile stress inside the second barrier layer 204 including three sublayers, thereby improving the structural stability of the semiconductor device.

[0071] Optionally, based on the above technical solution, Fig. 9As shown, the stress release layer 211 includes a silicon nitride stress release layer. The silicon nitride stress release layer can be formed by a metal organic chemical vapor deposition (MOCVD) process.

[0072] Optionally, based on the above technical solution, Fig. 9 As shown, a field plate layer 214 is also included, which is located on a side of the stress release layer 211 away from the third sub-layer 207 . The field plate layer 214 and the gate 213 are arranged at intervals and are manufactured in the same layer.

[0073] Specifically, after the gate 213 is formed on the top, the gate metal outside the gate 213 can be used as the field plate layer 214 through a graphic process. When the gate 213 is completed, the field plate layer 214 is prepared, which simplifies the preparation process and reduces the production cost.

[0074] Optionally, based on the above technical solution, Fig. 9 As shown, the gate 213 has an inverted T-shape in a cross-section perpendicular to the substrate 200 .

[0075] Specifically, the gate 213 includes a first portion and a second portion, the first portion is located in the second groove T2, and the second portion protrudes from the side of the stress release layer 211 away from the third sublayer 207. The gate 213 has an inverted T-shape in a cross-section perpendicular to the substrate 200, that is, the vertical projection area of ​​the second portion on the substrate 200 is smaller than the vertical projection area of ​​the first portion on the substrate 200, which can avoid depletion of the 2DEG of the channel.

[0076] Optionally, based on the above technical solution, Fig. 9 As shown, the composite barrier layer 202 includes aluminum gallium nitride, and / or the doped III-V semiconductor layer includes P-type gallium nitride.

[0077] Exemplarily, the second sublayer 206 is an N+ barrier layer. The second barrier layer 204 including three sublayers can further increase the electron concentration at the channel. Among them, the first sublayer 205 and the third sublayer 207 can prevent the diffusion of the first conductive type doping atoms in the second sublayer 206. The first conductive type doping atoms can be, for example, silicon atoms.

[0078] The embodiment of the present invention also provides a flow chart of a method for preparing a semiconductor device. Fig.10 As shown, Fig.10 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, and the method for preparing a semiconductor device comprises the following steps:

[0079] S310 , providing a substrate.

[0080] like Fig.12 As shown, a substrate 200 is provided.

[0081] S320 , forming a channel layer on one side of the substrate.

[0082] like Fig.12 As shown, a channel layer 201 is formed on one side of the substrate 200. The channel layer 201 includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. In other optional embodiments, a buffer layer may be formed on one side of the substrate 200 before forming the channel layer 201, and the buffer layer is used to alleviate the lattice mismatch problem between the substrate 200 and the channel layer 201.

[0083] S330 , forming a first barrier layer on one side of the channel layer.

[0084] like Fig.12 As shown, a first barrier layer 203 is formed on one side of the channel layer 201. The first barrier layer 203 includes one or more of a GaN layer, an AlGaN layer and an InGaN layer.

[0085] S340, forming a sacrificial layer on a side of the first barrier layer away from the channel layer; wherein a vertical projection area of ​​the sacrificial layer on the substrate is smaller than a vertical projection area of ​​the first barrier layer on the substrate.

[0086] Alternatively, if Fig.11 As shown, Fig.11 yes Fig.10 The process diagram included in S340, S340 forms a sacrificial layer on a side of the first barrier layer away from the channel layer, including the following steps:

[0087] S3401, forming a whole sacrificial layer on a side of the first barrier layer away from the channel layer, wherein a vertical projection area of ​​the whole sacrificial layer on the substrate is equal to a vertical projection area of ​​the first barrier layer on the substrate.

[0088] like Fig.12 As shown, a whole sacrificial layer 209a is formed on one side of the first barrier layer 203 away from the channel layer 201. Exemplarily, the whole sacrificial layer 209a is silicon dioxide. The vertical projection area of ​​the whole sacrificial layer 209a on the substrate 200 is equal to the vertical projection area of ​​the first barrier layer 203 on the substrate 200.

[0089] S3402, forming a photoresist layer on a side of the entire sacrificial layer away from the first barrier layer.

[0090] like Fig.13 and Fig.14 As shown, a third photoresist layer 210 is formed on a side of the entire sacrificial layer 209 a away from the first barrier layer 203 .

[0091] S3403, forming a plurality of opening patterns arranged in an array in the photoresist layer.

[0092] like Fig.13 and Fig.14 As shown, a plurality of opening patterns arranged in an array are formed in the third photoresist layer 210 through exposure and development processes, so that in the subsequent steps, a plurality of patterned sacrificial layers 209 arranged in an array are formed through an etching process, and then the sacrificial layers are wet-etched to batch form first grooves and second grooves arranged in an array, thereby providing a semiconductor device suitable for large-scale industrial production.

[0093] S3404, patterning the entire sacrificial layer to form multiple sacrificial layers.

[0094] like Fig.15 As shown, the entire sacrificial layer 209 a is dry-etched so that the vertical projection area of ​​the entire sacrificial layer 209 a on the substrate 200 is smaller than the vertical projection area of ​​the first barrier layer 203 on the substrate 200 .

[0095] S350. Form a second barrier layer on a side of the first barrier layer away from the channel layer, wherein the second barrier layer includes a first sublayer, a second sublayer and a third sublayer in sequence, and the first sublayer is located on a side of the first barrier layer away from the channel layer; the first sublayer is an undoped barrier layer, the second sublayer is a first conductive type barrier layer, and the third sublayer is an undoped barrier layer; the first barrier layer is in contact with the side of the sacrificial layer, and the height of the first barrier layer is less than the thickness of the sacrificial layer; the first barrier layer and the second barrier layer constitute a composite barrier layer.

[0096] like Fig.16 As shown, a second barrier layer 204 is formed on a side of the first barrier layer 203 away from the channel layer 201, wherein the second barrier layer 204 includes a first sublayer 205, a second sublayer 206 and a third sublayer 207 in sequence, and the first sublayer 205 is located on a side of the first barrier layer 203 away from the channel layer 201; the first sublayer 205 is an undoped barrier layer, the second sublayer 206 is a first conductive type barrier layer, and the third sublayer 207 is an undoped barrier layer; the first barrier layer 203 is in contact with the side of the sacrificial layer 209, and the height of the first barrier layer 203 is less than the thickness of the sacrificial layer 209; the first barrier layer 203 and the second barrier layer 204 constitute a composite barrier layer 202.

[0097] The first sub-layer 205, the second sub-layer 206 and the third sub-layer 207 are completed by a reproduction process MOCVD.

[0098] S360, forming a stress release layer on a side of the third sub-layer away from the second sub-layer, the stress release layer contacts the side of the sacrificial layer and is flush with the sacrificial layer; the stress release layer is an insulating layer.

[0099] like Fig.17As shown, a stress release layer 211 is formed on a side of the third sub-layer 207 away from the second sub-layer 206 , and the stress release layer 211 contacts the side of the sacrificial layer 209 and is flush with the sacrificial layer 209 ; the stress release layer 211 is an insulating layer.

[0100] Optionally, before S360, removing the sacrificial layer by a wet etching process, the method further includes:

[0101] The stress release layer and the sacrificial layer are planarized.

[0102] like Fig.18 As shown, since the surfaces of the grown sacrificial layer 209 and the stress release layer 211 are poorly planarized, the stress release layer 211 and the sacrificial layer 209 are planarized by a chemical mechanical polishing (CMP) process.

[0103] S370, removing the sacrificial layer by a wet etching process to form a first groove and a second groove, wherein the first groove is arranged in the second barrier layer and the first groove penetrates the second barrier layer; the second groove is arranged in the stress release layer and the second groove penetrates the stress release layer and is connected to the first groove.

[0104] like Fig.19 As shown, the sacrificial layer 209 is removed by a wet etching process to form a first groove T1 and a second groove T2. The first groove T1 is arranged in the second barrier layer 204 and penetrates the second barrier layer 204. The second groove T2 is arranged in the stress release layer 211 and penetrates the stress release layer 211 and is connected to the first groove T1.

[0105] Exemplarily, when the sacrificial layer 209 is silicon dioxide, the etching solution of the wet etching process may be a hydrofluoric acid (HF) solution.

[0106] S380, forming a doped III-V semiconductor layer in the first groove and the second groove, wherein the thickness of the doped III-V semiconductor layer is greater than the depth of the first groove and less than the sum of the depths of the first groove and the second groove.

[0107] like Fig. 20 As shown, a doped III-V semiconductor layer 212 of the second conductivity type is formed in the first groove T1 and the second groove T2, and the thickness of the doped III-V semiconductor layer 212 is greater than the depth of the first groove T1 and less than the sum of the depths of the first groove T1 and the second groove T2.

[0108] By controlling the growth process parameters of the doped III-V semiconductor layer 212, the thickness of the doped III-V semiconductor layer 212 is less than the sum of the depths of the first groove T1 and the second groove T2, and the doped III-V semiconductor layer 212 does not need to be etched, thereby avoiding etching damage and improving the electrical performance of the semiconductor device. In addition, the second groove T2 is disposed in the stress release layer 211, and the side of the doped III-V semiconductor layer 212 can avoid etching damage.

[0109] S390, forming a gate, the gate comprising a first portion and a second portion, the first portion is located in the second groove, and the second portion protrudes from a side of the stress release layer away from the third sub-layer.

[0110] like Fig. 9 As shown, a gate 213 is formed, and the gate 213 includes a first portion and a second portion. The first portion is located in the second groove T2 , and the second portion protrudes from a side of the stress release layer 211 away from the third sub-layer 207 .

[0111] S400 , forming a source electrode, wherein the source electrode is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

[0112] The source is located on the side of the second sub-layer 206 or the first barrier layer 203 away from the channel layer 201 , but the source is not marked in the figure.

[0113] S410 , forming a drain electrode, wherein the drain electrode is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

[0114] A drain is formed on a side of the second sub-layer 206 or the first barrier layer 203 away from the channel layer 201 , but the drain is not marked in the figure.

[0115] In the technical solution provided by the embodiment of the present invention, the doped III-V semiconductor layer 212 is set to the second conductivity type and is located in the first groove T1 and the second groove T2. The first groove T1 and the second groove T2 are prepared by wet etching of the sacrificial layer, which will not cause etching damage to the second barrier layer 204 and the first barrier layer 203, thereby improving the electrical performance of the semiconductor device. And because the doped III-V semiconductor layer 212 is used as a gate cap layer, its thickness is less than the sum of the depths of the first groove T1 and the second groove T2, and there is no need to perform an etching process on the doped III-V semiconductor layer 212, thereby avoiding etching damage and improving the electrical performance of the semiconductor device. And the second groove T2 is set in the stress release layer 211, and the side of the doped III-V semiconductor layer 212 can avoid etching damage. Among them, the first groove T1 and the second groove T2 are prepared by wet etching of the sacrificial layer, and a plurality of etched patterns arranged in an array can be formed by a photolithography process, and a plurality of patterned sacrificial layers arranged in an array are formed by an etching process, and then the sacrificial layer is wet etched to batch form the first groove T1 and the second groove T2 arranged in an array, thereby providing a semiconductor device suitable for large-scale industrial production.

[0116] Among them, the second barrier layer 204 includes a first sublayer 205, a second sublayer 206 and a third sublayer 207 in sequence, and the first sublayer 205, the second sublayer 206 and the third sublayer 207 constitute a three-layer sandwich structure, which can also significantly improve the polarization electric field strength and the 2DEG concentration. The second barrier layer 204 is completed by a regrowth process on the side of the first barrier layer 203 away from the channel layer 201, which can repair the surface quality of the first barrier layer 203. And the second barrier layer 204 including the third sublayer 207 can further provide more electrons and can also significantly improve the polarization electric field strength. Among them, the setting of the first sublayer 205 and the third sublayer 207 can avoid the diffusion of the first conductive type doping atoms in the second sublayer 206. The first conductive type doping atoms can be, for example, silicon atoms.

[0117] After the gate 213 is formed on the top, the gate metal outside the gate 213 can be used as the field plate layer 214 through a patterning process. When the gate 213 is completed, the field plate layer 214 is prepared, which simplifies the preparation process and reduces the production cost.

[0118] It should be noted that the stress release layer 211 is an insulating layer, which is located on the side of the third sublayer 207 away from the second sublayer 206. On the one hand, it avoids etching damage to the composite barrier layer 202 during the formation of the gate 213, thereby increasing the 2DEG concentration at the heterojunction interface; on the other hand, it releases the tensile stress inside the second barrier layer 204 including three sublayers, thereby improving the structural stability of the semiconductor device.

[0119] Optionally, based on the above technical solution, Fig.21 As shown, Fig.21 yes Fig.10 The schematic diagram of the process included in S390, S390 forming a gate includes:

[0120] S3901, forming a conductive layer on a side of the stress release layer away from the third sub-layer, the conductive layer comprising a first layer and a second layer, the first layer being located in the second groove, and the second layer covering the stress release layer and the first layer.

[0121] like Fig. 22 As shown, a conductive layer 213 a is formed on a side of the stress release layer 211 away from the third sub-layer 207 . The conductive layer 213 a includes a first layer and a second layer. The first layer is located in the second groove T2 , and the second layer covers the stress release layer 211 and the first layer.

[0122] S3902, patterning the conductive layer to obtain a gate and a field plate layer, wherein the field plate layer is located on a side of the stress release layer away from the third sub-layer and away from the second sub-layer, and the field plate layer and the gate are spaced apart.

[0123] like Fig.23 As shown, a fourth photoresist layer 215 is formed on a side of the conductive layer 213a away from the stress release layer 211, and the fourth photoresist layer 215 is exposed and developed to form an etching pattern.

[0124] like Fig. 9 As shown, the conductive layer is patterned to obtain a gate 213 and a field plate layer 214 . The field plate layer 214 is located on a side of the stress release layer 211 away from the third sub-layer 207 . The field plate layer 214 and the gate 213 are spaced apart and are manufactured in the same layer.

[0125] Specifically, after the gate 213 is formed on the top, the gate metal outside the gate 213 can be used as the field plate layer 214 through a graphic process. When the gate 213 is completed, the field plate layer 214 is prepared, which simplifies the preparation process and reduces the production cost.

[0126] Optionally, based on the above technical solution, Fig. 9 As shown, the gate 213 has an inverted T-shape in a cross-section perpendicular to the substrate 200 .

[0127] Specifically, the gate 213 includes a first portion and a second portion, the first portion is located in the second groove T2, and the second portion protrudes from the side of the stress release layer 211 away from the third sublayer 207. The gate 213 has an inverted T-shape in a cross-section perpendicular to the substrate 200, that is, the vertical projection area of ​​the second portion on the substrate 200 is smaller than the vertical projection area of ​​the first portion on the substrate 200, which can avoid depletion of the 2DEG of the channel.

[0128] Optionally, based on the above technical solution, Fig. 9 As shown, the stress release layer 211 includes a silicon nitride stress release layer.

[0129] The silicon nitride stress relief layer may be formed by an MOCVD process.

[0130] Optionally, based on the above technical solution, Fig. 9 As shown, the composite barrier layer 202 includes aluminum gallium nitride, and / or the doped III-V semiconductor layer includes P-type gallium nitride.

[0131] Exemplarily, the second sublayer 206 is an N+ barrier layer. The second barrier layer 204 including three sublayers can further increase the electron concentration at the channel. Among them, the first sublayer 205 and the third sublayer 207 can prevent the diffusion of the first conductive type doping atoms in the second sublayer 206. The first conductive type doping atoms can be, for example, silicon atoms.

[0132] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0133] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A channel layer, located on one side of the substrate; A composite barrier layer, comprising a first barrier layer and a second barrier layer; the first barrier layer is located on a side of the channel layer away from the substrate; the second barrier layer sequentially comprises a first sublayer, a second sublayer and a third sublayer, the first sublayer is located on a side of the first barrier layer away from the channel layer; the first sublayer is an undoped barrier layer, the second sublayer is a first conductivity type barrier layer, and the third sublayer is an undoped barrier layer; the second barrier layer is provided with a first groove, and the first groove penetrates the second barrier layer; a stress release layer, located on a side of the third sub-layer away from the second sub-layer, the stress release layer being provided with a second groove, the second groove penetrating the stress release layer and being connected to the first groove; the stress release layer being an insulating layer; The doped III-V semiconductor layer is set to the second conductivity type and is located in the first groove and the second groove, and the thickness of the doped III-V semiconductor layer is greater than the depth of the first groove and less than the sum of the depths of the first groove and the second groove; a gate, comprising a first portion and a second portion, wherein the first portion is located in the second groove, and the second portion protrudes from a side of the stress release layer away from the third sub-layer; a source electrode, located on a side of the second sub-layer or the first barrier layer away from the channel layer; The drain is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

2. The semiconductor device according to claim 1, wherein: The stress release layer includes a silicon nitride stress release layer.

3. The semiconductor device according to claim 1, wherein: It also includes a field plate layer, which is located on a side of the stress release layer away from the third sub-layer. The field plate layer and the gate are spaced apart and are manufactured in the same layer.

4. The semiconductor device according to claim 1, wherein: The gate has an inverted T-shape in a cross-section perpendicular to the substrate.

5. The semiconductor device according to claim 1, wherein: The composite barrier layer includes aluminum gallium nitride, and / or the doped III-V group semiconductor layer includes P-type gallium nitride.

6. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer on one side of the substrate; forming a first barrier layer on one side of the channel layer; Forming a sacrificial layer on a side of the first barrier layer away from the channel layer; wherein a vertical projection area of ​​the sacrificial layer on the substrate is smaller than a vertical projection area of ​​the first barrier layer on the substrate; A second barrier layer is formed on a side of the first barrier layer away from the channel layer, wherein the second barrier layer includes a first sublayer, a second sublayer and a third sublayer in sequence, and the first sublayer is located on a side of the first barrier layer away from the channel layer; the first sublayer is an undoped barrier layer, the second sublayer is a first conductive type barrier layer, and the third sublayer is an undoped barrier layer; the first barrier layer is in contact with a side surface of the sacrificial layer, and a height of the first barrier layer is less than a thickness of the sacrificial layer; the first barrier layer and the second barrier layer constitute a composite barrier layer; A stress release layer is formed on a side of the third sub-layer away from the second sub-layer, the stress release layer is in contact with a side surface of the sacrificial layer and is flush with the sacrificial layer; the stress release layer is an insulating layer; The sacrificial layer is removed by a wet etching process to form a first groove and a second groove, wherein the first groove is arranged in the second barrier layer and penetrates the second barrier layer; the second groove is arranged in the stress release layer and penetrates the stress release layer and communicates with the first groove; forming a doped III-V semiconductor layer of a second conductivity type in the first groove and the second groove, wherein the thickness of the doped III-V semiconductor layer is greater than the depth of the first groove and less than the sum of the depths of the first groove and the second groove; forming a gate, the gate comprising a first portion and a second portion, the first portion being located in the second groove, and the second portion protruding from a side of the stress release layer away from the third sub-layer; forming a source electrode, wherein the source electrode is located on a side of the second sub-layer or the first barrier layer away from the channel layer; A drain is formed, where the drain is located on a side of the second sub-layer or the first barrier layer away from the channel layer.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: Before removing the sacrificial layer by a wet etching process, the method further includes: The stress release layer and the sacrificial layer are planarized.

8. The method for preparing a semiconductor device according to claim 6, characterized in that: Forming the gate includes: forming a conductive layer on a side of the stress release layer away from the third sub-layer, the conductive layer comprising a first layer and a second layer, the first layer being located in the second groove, and the second layer covering the stress release layer and the first layer; The conductive layer is patterned to obtain the gate and the field plate layer. The field plate layer is located on a side of the stress release layer away from the third sub-layer and away from the second sub-layer. The field plate layer and the gate are spaced apart.

9. The method for preparing a semiconductor device according to claim 6, wherein: Forming the gate includes: A gate electrode is formed in an inverted T-shape in a cross-section perpendicular to the substrate.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: The stress release layer includes a silicon nitride stress release layer.

11. The method for preparing a semiconductor device according to claim 6, characterized in that: The composite barrier layer includes aluminum gallium nitride, and / or the doped III-V group semiconductor layer includes P-type gallium nitride.

12. The method for preparing a semiconductor device according to claim 6, characterized in that: Forming a sacrificial layer on a side of the first barrier layer away from the channel layer comprises: forming a whole sacrificial layer on a side of the first barrier layer away from the channel layer, wherein a vertical projection area of ​​the whole sacrificial layer on the substrate is equal to a vertical projection area of ​​the first barrier layer on the substrate; forming a photoresist layer on a side of the entire sacrificial layer away from the first barrier layer; forming a plurality of opening patterns arranged in an array in the photoresist layer; The entire sacrificial layer is patterned to form a plurality of sacrificial layers.

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