A silicon carbide semiconductor device with N-top region and a method for manufacturing the same

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a silicon carbide semiconductor device with an N-top region, including a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer includes an N substrate layer and an N drift layer, wherein the interior of the N drift layer is formed with a P+ well layer, an N well layer and a P well layer by ion implantation; an N-type doping region 1 is formed by ion implantation inside the N drift layer and directly below the gate, and a P-type doping region is formed inside the N-type doping region 1 by ion implantation. The PN junction formed by the P-type doping of the present invention will produce a large depletion layer, and the depletion layer mainly extends to the JFET region with a lower doping concentration, and the short-circuit current flows at a position closer to the center of the JFET region, and by increasing the N-type doping region 1 and the P-type doping region, the short-circuit current density can be effectively reduced, and the short-circuit withstand time of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a silicon carbide semiconductor device with an N-top region and a preparation method thereof. Background Art

[0002] SiC MOSFET has a tendency to gradually replace silicon-based IGBT due to its excellent characteristics such as high withstand voltage, low on-resistance, and low switching loss. Since SiC materials can work under higher field strengths, SiC MOSFET gate oxide will face a more severe working environment. Short-circuit testing is an important experiment to characterize device reliability.

[0003] The existing patent discloses a SiCDT-MOSFET structure with a Ptop region (publication number CN115799305A). Based on the conventional SiCDT-MOSFET structure, this structure introduces a P-top doping region at the center of the surface below the gate oxide layer. In the technology disclosed in the patent, the PN junction formed by P-type doping will produce a large depletion layer, and the depletion layer mainly extends to the JFET region with a lower doping concentration, which causes the semiconductor device to form a high-density short-circuit charge accumulation during the switching process. This high-density charge will increase the hysteresis time of the semiconductor device switch. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a silicon carbide semiconductor device with an N-top region and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide semiconductor device with an N-top region includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer includes an N substrate layer and an N drift layer, and a P+ well layer, an N well layer and a P well layer are formed inside the N drift layer by ion implantation;

[0006] An N-type doping region 1 is formed inside the N-drift layer and directly below the gate by ion implantation, and a P-type doping region is formed inside the N-type doping region 1 by ion implantation.

[0007] Furthermore, an N-type doping region 2 and an N-type high-doping region are formed inside the N-drift layer by ion implantation.

[0008] Furthermore, the second N-type doping region and the N-type high-doping region are alternately distributed at the bottom of the N drift layer.

[0009] Furthermore, the P+ well layer also includes a penetrating P+ well layer, and the penetrating P+ well layer penetrates to the bottom of the N drift layer.

[0010] A method for preparing a silicon carbide semiconductor device having an N-top region comprises the following steps:

[0011] S1. Selecting a semiconductor epitaxial layer liner, and chemically cleaning and polishing the surface of the semiconductor epitaxial layer to remove surface defects and impurities;

[0012] S2, forming an N-type doping region 2 at the bottom of the N drift layer by injecting low concentration ions;

[0013] S3, continue to inject high-concentration ions into the N-type doping region 2 to form an N-type high-doping region;

[0014] S4, forming an N-type doping region 1 in the upper layer of the N drift layer by ion implantation, and continuing to dope inside the N-type doping region 1 to form a P-type doping region;

[0015] S5, using sputtering technology to deposit metal materials on the surface of the semiconductor epitaxial layer to form a source, a drain and a gate;

[0016] S6. Detect the electrical performance of semiconductor devices.

[0017] Furthermore, in step S6, whether the electrical performance of the semiconductor device meets the standard is determined based on the absolute value of the threshold voltage difference, the absolute value of the on-resistance difference, and the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 1 and the P-type doping region added and the semiconductor device without the N-type doping region 1 and the P-type doping region added, as follows:

[0018]

[0019] In the formula, Indicates the electrical performance stability factor of the semiconductor device being tested; It represents the absolute value of the threshold voltage difference between the semiconductor device with the N-type doping region 1 and the P-type doping region added and the semiconductor device without the N-type doping region 1 and the P-type doping region added; It represents the absolute value of the on-resistance difference between the semiconductor device with the N-type doping region 1 and the P-type doping region added and the semiconductor device without the N-type doping region 1 and the P-type doping region added; It represents the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 1 and the P-type doping region added and the semiconductor device without the N-type doping region 1 and the P-type doping region added.

[0020] Furthermore, when When , it indicates that the electrical performance of the semiconductor device being tested is excellent;

[0021] when When , it means that the electrical performance of the tested semiconductor device is qualified;

[0022] when When , it means that the electrical performance of the semiconductor device being tested is unqualified.

[0023] Furthermore, the N-type doping region 2, the N-type high doping region and the N-type doping region 1 are all formed by implanting pentavalent phosphorus ions, and the P-type doping region is formed by implanting trivalent boron ions.

[0024] Beneficial effects:

[0025] 1. The PN junction formed by P-type doping in the present invention will produce a large depletion layer, which mainly extends to the JFET area with a lower doping concentration. The short-circuit current flows at a position closer to the center of the JFET area. By adding an N-type doping area and a P-type doping area, the short-circuit current density can be effectively reduced and the short-circuit withstand time of the device can be improved.

[0026] 2. In the present invention, the conduction charges of the drain and source under low power will be formed preferentially in the N-type high-doped region. When the drain and source are connected to a high-power voltage electric field, the N-type doped region 2 can prevent the formed charges from being concentrated on the nearest route, thereby causing the semiconductor device to be broken down.

[0027] 3. The present invention isolates the charges in adjacent MOS cells from flowing to each other by penetrating the P+ well layer, thereby allocating the flow of charges and preventing the charges from accumulating and flowing to the MOS cell with the smallest resistance, thereby improving the overall service life of the semiconductor device.

[0028] 4. The present invention can quickly and accurately determine whether the prepared semiconductor device meets the use requirements by measuring the absolute value of the threshold voltage difference, the absolute value of the on-resistance difference, and the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 1 and the P-type doping region added and the semiconductor device without the N-type doping region 1 and the P-type doping region added. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention;

[0030] Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention.

[0032] In the figure: 1, drain; 2, source; 3, gate; 4, gate oxide layer; 5, N substrate layer; 6, N drift layer; 7, P+ well layer; 8, N well layer; 9, P well layer; 10, P-type doped region; 11, N-type doped region 1; 12, N-type doped region 2; 13, N-type high-doped region; 71, through the P+ well layer. DETAILED DESCRIPTION

[0033] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1-3 As shown, a method for preparing a silicon carbide semiconductor device having an N-top region comprises the following steps:

[0035] Step 1: Select a semiconductor epitaxial layer liner, and chemically clean and polish the surface of the semiconductor epitaxial layer to remove surface defects and impurities.

[0036] Step 2: Form an N-type doping region 12 at the bottom of the N-drift layer 6 by injecting low-concentration ions.

[0037] Step 3: Continue to implant high-concentration ions into the N-type doping region 12 to form an N-type high-doping region 13 .

[0038] Step 4: Form an N-type doping region 11 in the upper layer of the N drift layer 6 by ion implantation, and continue to dope inside the N-type doping region 11 to form a P-type doping region 10; the N-type doping region 2 12, the N-type high-doping region 13 and the N-type doping region 11 are all formed by implanting pentavalent phosphorus ions, and the P-type doping region 10 is formed by implanting trivalent boron ions.

[0039] Step 5: Use sputtering technology to deposit metal material on the surface of the semiconductor epitaxial layer to form a source 2, a drain 1 and a gate 3.

[0040] Step 6: Detect the electrical performance of the semiconductor device.

[0041] In step 6, whether the electrical performance of the semiconductor device meets the standard is determined based on the absolute value of the threshold voltage difference, the absolute value of the on-resistance difference, and the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 added and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 added, and:

[0042]

[0043] In the formula, Indicates the electrical performance stability factor of the semiconductor device being tested; represents the absolute value of the threshold voltage difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 added and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 added; represents the absolute value of the on-resistance difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 added and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 added; It represents the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 and the semiconductor device without the N-type doping region 11 and the P-type doping region 10.

[0044] when When , it indicates that the electrical performance of the semiconductor device being tested is excellent;

[0045] when When , it means that the electrical performance of the tested semiconductor device is qualified;

[0046] when When , it means that the electrical performance of the semiconductor device being tested is unqualified.

[0047] The electrical performance test is performed on any device X. The absolute value of the threshold voltage difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 is taken as (V); the absolute value of the on-resistance difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 is taken as (Ohm); the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 11 and the P-type doping region 10 and the semiconductor device without the N-type doping region 11 and the P-type doping region 10 is taken as (nanoseconds), then:

[0048]

[0049] From the above calculation, it can be known that after the electrical performance test of any device X, the electrical performance of the tested semiconductor device X is excellent.

[0050] Example 1

[0051] like Figure 1As shown, a silicon carbide semiconductor device with an N-top region includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4 covering the surface of the gate 3, the semiconductor epitaxial layer includes an N substrate layer 5 and an N drift layer 6, and a P+ well layer 7, an N well layer 8, and a P well layer 9 are formed inside the N drift layer 6 by ion implantation. An N-type doping region 11 is formed inside the N drift layer 6 and directly below the gate 3 by ion implantation, and a P-type doping region 10 is formed inside the N-type doping region 11 by ion implantation. An N-type doping region 11 is formed above the N drift layer 6 by ion implantation, thereby forming an N-type top region. When the device enters a short-circuit state, the device operates in a saturation region, and the PN junction formed by the P-type doping 10 will produce a large depletion layer. The depletion layer mainly extends to the JFET region with a lower doping concentration (the original N-type top region), and the short-circuit current flows closer to the center of the JFET region. By increasing the N-type doping region 11 and the P-type doping region 10, the short-circuit current density can be effectively reduced, thereby improving the short-circuit withstand time of the device.

[0052] Example 2

[0053] like Figure 2 As shown, a silicon carbide semiconductor device with an N-top region includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4 covering the surface of the gate 3, the semiconductor epitaxial layer includes an N substrate layer 5 and an N drift layer 6, and a P+ well layer 7, an N well layer 8, and a P well layer 9 are formed inside the N drift layer 6 by ion implantation. An N-type doping region 2 12 and an N-type high doping region 13 are formed inside the N drift layer 6 by ion implantation, and the N-type doping region 2 12 and the N-type high doping region 13 are alternately distributed at the bottom of the N drift layer 6. An N-type doping region 2 12 and an N-type high doping region 13 with different concentrations are formed by ion implantation at the junction of the N drift layer 6 and the N substrate layer 5. Since the on-resistance of the N-type doping region 2 12 is larger than that of the N-type high doping region 13, the conduction charge of the drain 1 and the source 2 at low power is preferentially formed through the N-type high doping region 13. When the drain 1 and the source 2 are connected to a high power voltage electric field, a path for conducting charges will be formed inside the N-type doped region 12, and the formed charges can be prevented from being concentrated on the nearest route, thereby causing breakdown of the semiconductor device.

[0054] Example 3

[0055] like Figure 3As shown, a silicon carbide semiconductor device with an N-top region includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4 covering the surface of the gate 3. The semiconductor epitaxial layer includes an N substrate layer 5 and an N drift layer 6. The interior of the N drift layer 6 is formed by ion implantation with a P+ well layer 7, an N well layer 8, and a P well layer 9. The P+ well layer 7 also includes a through P+ well layer 71, which penetrates the P+ well layer 71 to the bottom of the N drift layer 6. In adjacent MOS cells (such as Figure 3 When several MOS cells are placed in parallel, they will form a semiconductor device with a certain power. They are isolated from each other by penetrating the P+ well layer 71. In this way, when the conductivity of each MOS cell is different due to the difference in the material itself, the charge will not mainly pass through the MOS cell with strong conductivity, but will share the flow of charge, thereby increasing the service life of the semiconductor device.

[0056] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A silicon carbide semiconductor device having an N-top region, comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3), and a gate oxide layer (4) covering the surface of the gate (3), characterized in that: The semiconductor epitaxial layer comprises an N substrate layer (5) and an N drift layer (6), wherein a P+ well layer (7), an N well layer (8) and a P well layer (9) are formed inside the N drift layer (6) by ion implantation; An N-type doping region 1 (11) is formed by ion implantation inside the N-drift layer (6) and directly below the gate (3), and a P-type doping region (10) is formed by ion implantation inside the N-type doping region 1 (11); The N-type doping region 2 (12) and the N-type high-doping region (13) are formed inside the N-drift layer (6) by ion implantation, and the N-type doping region 2 (12) and the N-type high-doping region (13) are alternately distributed at the bottom of the N-drift layer (6).

2. The silicon carbide semiconductor device with an N-top region according to claim 1, characterized in that: The P+ well layer (7) further comprises a through P+ well layer (71), wherein the through P+ well layer (71) penetrates to the bottom of the N drift layer (6).

3. A method for preparing a silicon carbide semiconductor device having an N-top region according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1. Selecting a semiconductor epitaxial layer liner, and chemically cleaning and polishing the surface of the semiconductor epitaxial layer to remove surface defects and impurities; S2, forming an N-type doping region 2 (12) at the bottom of the N drift layer (6) by injecting low concentration ions; S3, continue to inject high concentration ions into the N-type doping region 2 (12) to form an N-type high doping region (13); S4, forming an N-type doping region 1 (11) in the upper layer of the N drift layer (6) by ion implantation, and continuing to dope inside the N-type doping region 1 (11) to form a P-type doping region (10); S5, using a sputtering technique to deposit a metal material on the surface of the semiconductor epitaxial layer to form a source electrode (2), a drain electrode (1) and a gate electrode (3); S6. Detect the electrical performance of semiconductor devices.

4. The method for preparing a silicon carbide semiconductor device having an N-top region according to claim 3, characterized in that: In step S6, whether the electrical performance of the semiconductor device meets the standard is determined based on the absolute value of the threshold voltage difference, the absolute value of the on-resistance difference, and the absolute value of the switching speed difference between the semiconductor device with the N-type doping region 1 (11) and the P-type doping region (10) added and the semiconductor device without the N-type doping region 1 (11) and the P-type doping region (10) added, wherein: In the formula, Indicates the electrical performance stability factor of the semiconductor device being tested; represents the absolute value of the threshold voltage difference between a semiconductor device having an N-type doping region 1 (11) and a P-type doping region (10) added thereto and a semiconductor device having no N-type doping region 1 (11) and a P-type doping region (10) added thereto; Indicates the absolute value of the on-resistance difference between a semiconductor device having an N-type doping region 1 (11) and a P-type doping region (10) added thereto and a semiconductor device having no N-type doping region 1 (11) and a P-type doping region (10) added thereto; Indicates the absolute value of the difference in switching speed between a semiconductor device having an N-type doping region 1 (11) and a P-type doping region (10) added thereto and a semiconductor device having no N-type doping region 1 (11) and a P-type doping region (10) added thereto.

5. The method for preparing a silicon carbide semiconductor device having an N-top region according to claim 4, characterized in that: when When , it indicates that the electrical performance of the semiconductor device being tested is excellent; when When , it means that the electrical performance of the tested semiconductor device is qualified; when When , it means that the electrical performance of the semiconductor device being tested is unqualified.

6. The method for preparing a silicon carbide semiconductor device having an N-top region according to claim 3, characterized in that: The N-type doping region 2 (12), the N-type high doping region (13) and the N-type doping region 1 (11) are all formed by injecting pentavalent phosphorus ions, and the P-type doping region (10) is formed by injecting trivalent boron ions.

Images