Semiconductor device including super junction structure

Abstract

A semiconductor device including a super junction structure is disclosed. A semiconductor device (10) includes a transistor. The transistor includes a plurality of gate trenches (111) formed in a semiconductor substrate (100), the gate trenches (111) patterning the semiconductor substrate (100) into ridges (114). The transistor further comprises a gate electrode (110) arranged in at least one of the gate trenches (111). A source region (124), a channel region (122), a partial current diffusion region (126) are arranged in the ridge (114). The semiconductor device (10) further includes a super junction structure (117) arranged at a greater distance from the source region (124) than the channel region (122). The super junction structure (117) includes a first compensation region (118) of a first conductivity type and a second compensation region (119) of a second conductivity type. A doping concentration of a doped portion (120) of the second conductivity type of the channel region (122) decreases from a region close to the gate electrode (110) to a central portion of the ridge (114) in a second horizontal direction intersecting the first horizontal direction.

Description

Technical Field

[0001] Examples of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices including transistors including super junction structures. Background Art

[0002] Transistors in which a gate electrode is arranged in a trench adjacent to a channel region are widely used. Attempts are being made to further improve the characteristics of these transistors.

[0003] The present disclosure is directed to semiconductor devices including improved transistors that may be beneficially applied to, for example, silicon carbide substrates. Summary of the invention

[0004] According to an example, a semiconductor device includes a transistor. The transistor includes a plurality of gate trenches formed in a semiconductor substrate. The gate trenches pattern the semiconductor substrate into ridges extending in a first horizontal direction. The ridges are arranged between two adjacent gate trenches, respectively. The transistor also includes a gate electrode arranged in at least one of the gate trenches. The transistor also includes: a source region, which is of a first conductivity type and electrically coupled to a source terminal; a channel region, which includes a doped portion of a second conductivity type; a current diffusion region of the first conductivity type; and a drain region electrically coupled to a drain terminal. The source region, the channel region, and a portion of the current diffusion region are arranged in the ridge. The gate electrode is insulated from the channel region and the current diffusion region, wherein the width of the source region corresponds to the width of the ridge. The semiconductor device also includes a super junction structure, which is arranged at a greater distance from the source region than the channel region. The super junction structure includes a first compensation region of a first conductivity type, the first compensation region being electrically coupled to the drain terminal. The super junction structure also includes a second compensation region of a second conductivity type, the second compensation region being electrically coupled to the doped portion of the second conductivity type of the channel region. The first compensation region and the second compensation region are adjacent to each other. The doping concentration of the second conductivity type doping portion of the channel region decreases from a region close to the gate electrode to a central portion of the ridge in a second horizontal direction intersecting the first horizontal direction.

[0005] According to another example, a semiconductor device includes a transistor. The transistor includes a plurality of gate trenches formed in a SiC substrate. The gate trenches pattern the semiconductor substrate into ridges extending in a first horizontal direction, and the ridges are respectively arranged between two adjacent gate trenches. The transistor also includes a gate electrode, which is arranged in at least one of the gate trenches. The transistor also includes: a source region, which is of a first conductivity type and electrically coupled to a source terminal; a channel region, which includes a doped portion of a second conductivity type; a current diffusion region of the first conductivity type; and a drain region electrically coupled to a drain terminal. The source region, the channel region, and a portion of the current diffusion region are arranged in the ridge. The gate electrode is insulated from the channel region and the current diffusion region. The width of the source region corresponds to the width of the ridge. The semiconductor device also includes a super junction structure, which is arranged at a greater distance from the source region than the channel region. The super junction structure includes a first compensation region of a first conductivity type, and the first compensation region is electrically coupled to the drain terminal. The super junction structure also includes a second compensation region of a second conductivity type. The second compensation region is electrically coupled to the second conductivity type doped portion of the channel region, and the first compensation region and the second compensation region are adjacent to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0007] Figure 1A An example of a vertical cross-sectional view of a portion of a semiconductor device according to an example is shown.

[0008] Figure 1B A vertical cross-sectional view of a portion of a semiconductor device according to another example is shown.

[0009] Figure 2A A horizontal cross-sectional view of a semiconductor device according to an example is shown.

[0010] Figure 2B A vertical cross-sectional view illustrating a portion of a semiconductor device according to an example.

[0011] Figure 2C A vertical cross-sectional view of a portion of a semiconductor device according to another example is shown.

[0012] Figure 3A A horizontal cross-sectional view of a semiconductor device according to another example is shown.

[0013] Figure 3B is a vertical cross-sectional view of a portion of a semiconductor device according to an example.

[0014] Figure 3C An example of doping concentration in the channel region is shown.

[0015] Figure 4A A horizontal cross-sectional view of a portion of a semiconductor device according to an example is shown.

[0016] Figure 4B Vertical cross-sectional views of a portion of a semiconductor device at different locations are shown.

[0017] Figure 5A A horizontal cross-sectional view of a semiconductor device according to another example is shown.

[0018] Figure 5B and Figure 5C Vertical cross-sectional views of a semiconductor device at different locations are shown.

[0019] Figure 5D Another horizontal cross-sectional view of a semiconductor device is shown.

[0020] Figure 5E and Fig. 5F Vertical cross-sectional views of another semiconductor device at different positions are shown.

[0021] Figure 5G Another horizontal cross-sectional view of a semiconductor device is shown.

[0022] Fig. 6A A horizontal cross-sectional view of a semiconductor device according to another example is shown.

[0023] Figure 6B A vertical cross-sectional view of a semiconductor device is shown.

[0024] Figure 6C Another horizontal cross-sectional view of a semiconductor device is shown.

[0025] Fig.6D and Fig. 6E Vertical cross-sectional views of a semiconductor device at different locations according to another example are shown.

[0026] Fig. 6F Another horizontal cross-sectional view of a semiconductor device is shown.

[0027] Fig. 7A A horizontal cross-sectional view of a semiconductor device according to another example is shown.

[0028] Figure 7B and Figure 7C Vertical cross-sectional views of the semiconductor device at different positions along the second direction are shown.

[0029] Fig.7D and Fig. 7E Vertical cross-sectional views of a semiconductor device at different positions along a first direction are shown.

[0030] Figure 7F Another horizontal cross-sectional view of a semiconductor device is shown.

[0031] Fig. 8A A horizontal cross-sectional view of a portion of a semiconductor device according to another example is shown.

[0032] Figure 8B and Figure 8C Vertical cross-sectional views of the semiconductor device at different positions along the second direction are shown.

[0033] Fig.8D and Fig. 8E Vertical cross-sectional views of a semiconductor device at different positions along a first direction are shown.

[0034] 9A to 9H A cross-sectional view illustrating a workpiece when a method of manufacturing a semiconductor device according to an example is performed.

[0035] Fig.9I and Figure 9J A cross-sectional view of a workpiece when a method according to a modification is performed is shown.

[0036] FIG. 10A to FIG. 10H A cross-sectional view illustrating a workpiece when a method of manufacturing a semiconductor device according to an example is performed.

[0037] FIG. 11A to FIG. 11H A cross-sectional view of a workpiece is shown when performing a method according to a further example. DETAILED DESCRIPTION

[0038] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and in which specific embodiments in which the present invention can be practiced are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in other embodiments or used in combination with other embodiments to produce yet another embodiment. The present invention is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The accompanying drawings are not to scale and are for illustrative purposes only. For clarity, if not otherwise stated, the same elements have been indicated by corresponding reference numerals in different drawings.

[0039] The terms "having", "comprising", "including", "comprising", etc. are open ended and the terms indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. The quantifiers "a", "an", and the pronoun "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0040] Ranges given for physical dimensions include the boundary values. For example, a range for parameter y from a to b is read as a≤y≤b. Parameter y with a value of at least c is read as c≤y, and parameter y with a value of at most d is read as y≤d.

[0041] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is “on” another element (e.g., a layer is “on” another layer or “on” a substrate or semiconductor body), further components (e.g., further layers) may be located between the two elements (e.g., if a layer is “on” a substrate, the further layers may be located between the layer and the substrate).

[0042] The elements of the transistor unit of the field effect transistor are described throughout this specification. Generally, the field effect transistor may include a plurality of transistor units connected in parallel. For example, each single transistor unit may include a single gate electrode, a single channel region and another component. The gate electrode of the single transistor unit may be connected (e.g., electrically connected) and / or formed by the same material. For example, the gate electrode of the single transistor unit may be connected to a common terminal (e.g., a gate terminal). The other components of the single transistor unit (e.g., a source region) may be connected to a common source terminal accordingly. Another component of the single transistor unit (e.g., a current diffusion region or a drift region) may be shared among at least some transistor units. This specification mainly describes the function and structure of a single transistor unit. As is easily understood, this description may also be applicable to other single transistor units. The description of the general elements and structure of the transistor realized by combining the elements of the single transistor unit (such as "a gate electrode arranged in a gate trench") is intended to mean that the single gate electrode of the corresponding transistor unit is arranged in the corresponding gate trench.

[0043] Examples of semiconductor devices include transistors. The transistor may include a plurality of gate trenches formed in a semiconductor substrate. The gate trenches may pattern the semiconductor substrate into ridges extending in a first horizontal direction. The ridges may be arranged between two adjacent gate trenches, respectively.

[0044] The transistor may further include a gate electrode disposed in at least one of the gate trenches.

[0045] The transistor may also include a source region of the first conductivity type and electrically coupled to the source terminal. The transistor may also include a channel region including a doped portion of the second conductivity type and a current diffusion region of the first conductivity type. The source region, the channel region, and a portion of the current diffusion region are arranged in the ridge. The transistor may also include a drain region electrically coupled to the drain terminal.

[0046] The gate electrode may be insulated from the channel region and the current diffusion region. The source region may be arranged at least in a central portion of the ridge. The term "central portion" may refer to a central portion relative to a second horizontal direction perpendicular to the first horizontal direction. Thus, the source region may be arranged in a portion of the ridge having approximately equal distances from the first side and the second side of the ridge, respectively. According to another embodiment, the arrangement of the source regions does not need to be symmetrical relative to the second horizontal direction. The term "source region arranged at least in the central portion of the ridge" is intended to refer to an arrangement according to which a doped portion of the second conductivity type may be arranged in a horizontal edge portion of the ridge, for example adjacent to at least one of the side surfaces of the ridge.

[0047] The semiconductor device may also include a super junction structure arranged at a greater distance from the source region than the channel region. The super junction structure may include a first compensation region of a first conductivity type and a second compensation region of a second conductivity type. The first compensation region may be electrically coupled to the drain terminal. The second compensation region may be electrically coupled to a doped portion of the second conductivity type of the channel region. The first compensation region and the second compensation region may be arranged adjacent to each other.

[0048] The doping concentration of the second conductivity type doped portion of the channel region may decrease from a region close to the gate electrode to a central portion of the ridge in a second horizontal direction intersecting the first horizontal direction. For example, the channel region may include a first conductivity type doped portion in a central portion of the ridge.

[0049] When a suitable voltage is applied to the gate electrode, a conductive channel is formed in the channel region. Therefore, a current path having a vertical component is formed between the source region, the channel region, the current diffusion region, and the drain region. The current path from the source region to the current diffusion region may extend in the depth direction of the silicon carbide substrate. For example, the depth direction may correspond to a vertical direction, such as a z direction. According to another embodiment, the depth direction may be a direction different from the vertical direction. Generally, the depth direction is a direction different from a lateral or horizontal direction. For example, the depth direction may have a component perpendicular to the lateral direction or the main surface of the silicon carbide substrate. For example, the depth direction may be inclined relative to the vertical direction.

[0050] The term "ridge" as used in the present disclosure is intended to mean a structure including two sidewalls and a top portion between the sidewalls, such as a table. The sidewalls extend in the depth direction. For example, the sidewalls may be inclined relative to the vertical direction. According to another interpretation, the term "ridge" may also be understood to implement a "fin". Since the channel of the transistor is arranged in the ridge, the transistor is also referred to as a "FinFET".

[0051] The transistors described herein may specifically include IGFETs ("insulated gate field effect transistors"). IGFETs are voltage controlled devices including MOSFETs ("metal oxide semiconductor FETs") and other FETs including gate electrodes based on doped semiconductor materials and / or including gate dielectrics that are not based or not exclusively based on oxides. As is to be clearly understood, additional transistors may be related to IGBTs ("insulated gate bipolar transistors").

[0052] Depending on the implementation, the width of the source region may correspond to the width of the ridge. Thus, the source region may extend from one side of the ridge to the other side of the ridge. In other words, it is possible that further trenches or doped portions of another conductivity type are not present in the source region.

[0053] For example, a doped portion of the second conductivity type of the channel region may be electrically connected to the source terminal via the body contact portion.

[0054] For example, the second compensation region may be electrically coupled to the source terminal. For example, the second compensation region may be electrically coupled to a doped portion of the second conductivity type of the channel region. Thus, the second compensation region may be electrically coupled to the source terminal via the channel region.

[0055] Compared with the drift zone of the first conductivity type without the superjunction structure, the superjunction structure allows the breakdown voltage V br The lateral width of the first compensation region and the second compensation region may be smaller than the extension of the first compensation region and the second compensation region in the depth direction.

[0056] The gate electrode may be insulated from the channel region and the current diffusion region. For example, the gate electrode may be insulated from the channel region and the current diffusion region by means of a gate dielectric such as, for example, silicon oxide, silicon nitride, or a combination of these materials. According to another example, any other dielectric material, such as a high-k dielectric, may be used.

[0057] In summary, the semiconductor device combines a FinFET structure with a super junction structure. Due to the FinFET structure, the channel resistance can be reduced. Due to the super junction structure, the resistance in the drift region can be reduced. As a result, a power transistor with low on-state loss can be realized.

[0058] For example, the channel region may include a doped portion of the first conductivity type in a central portion of the ridge. In this case, the first compensation region may be electrically coupled to the doped portion of the first conductivity type.

[0059] Additionally, the second compensation region may be electrically coupled to the source terminal via a body contact portion electrically coupling a doped portion of the second conductivity type of the channel region to the source terminal.

[0060] By way of example, the semiconductor device may further include a shielding portion of the second conductivity type, which is accordingly arranged below the gate trench. For example, the shielding portion may be doped with a higher doping concentration than the second compensation region. The second compensation region may be electrically coupled to the shielding portion.

[0061] The shielding portion may contribute to shielding the gate dielectric from a potential that may be applied at the back side of the silicon carbide body. In a blocking mode of the silicon carbide device, the shielding portion may reduce the electric field in the gate dielectric and may therefore contribute to increasing device reliability. For example, the shielding portion may be doped at a higher doping level than a doped portion of the second conductivity type of the channel region. The shielding portion may be in contact with the current diffusion region. The shielding portion may be in contact with a source metallization layer electrically coupled to a source terminal.

[0062] According to an example, the super junction structure may extend in a first horizontal direction.

[0063] According to another example, the super junction structure may extend in a second horizontal direction intersecting the first horizontal direction.

[0064] According to an example, the source region may continuously extend along the first horizontal direction in the ridge.

[0065] According to another example, the source region may be segmented into source region segments along the first horizontal direction.The transistor may further include a body contact portion arranged between adjacent source region segments.

[0066] According to an example, the transistor may further include a drift region of the first conductivity type arranged between the super junction structure and the drain region.

[0067] By way of example, the gate trench may extend continuously in the first horizontal direction.

[0068] The semiconductor device may also include a contact groove that runs in a first horizontal direction. The contact groove may extend through the gate trench in a depth direction. The metal layer arranged in the contact groove may be electrically coupled to the source terminal. The metal layer may further be electrically coupled to a second compensation region of a second conductivity type. The contact groove may further or alternatively contact the shielding portion. In this way, the shielding portion may be electrically coupled to the source terminal. Further or alternatively, the metal layer in the contact groove may contact the body contact portion. For example, the metal layer in the contact groove may be disconnected from the portion of the first conductivity type to avoid a direct, uncontrollable current path between the source region and the drain region.

[0069] For example, the contact groove may extend continuously in the first horizontal direction. According to another example, the contact groove may be segmented into contact groove islands. In this case, the gate electrode may exist between adjacent contact groove islands.

[0070] According to another example, the gate trench may be segmented into a plurality of trench segments arranged along the first horizontal direction.

[0071] For example, the semiconductor device may further include a metal layer electrically coupled to the source terminal. The metal layer may be arranged to contact the source region between adjacent trench segments. For example, in this way, the source region and the doped portion of the second conductivity type of the channel region may be electrically coupled to the source terminal.

[0072] According to another example, a semiconductor device may include a transistor. The transistor may include a plurality of gate trenches formed in a SiC substrate. The gate trenches may pattern the semiconductor substrate into a ridge extending in a first horizontal direction. The ridges may be arranged between two adjacent gate trenches, respectively. The transistor may further include: a gate electrode arranged in at least one gate trench; and a source region of a first conductivity type and electrically coupled to a source terminal. The transistor may further include: a channel region including a doped portion of a second conductivity type, a current diffusion region of a first conductivity type, and a drain region electrically coupled to a drain terminal. The source region, the channel region, and a portion of the current diffusion region may be arranged in the ridge. The gate electrode may be insulated from the channel region and the current diffusion region. The width of the source region may correspond to the width of the ridge.

[0073] The semiconductor device may further include a super junction structure arranged at a greater distance from the source region than the channel region. The super junction structure may include: a first compensation region of a first conductivity type electrically coupled to the drain terminal; and a second compensation region of a second conductivity type. The second compensation region may be electrically coupled to a doped portion of the second conductivity type of the channel region. The first compensation region and the second compensation region may be arranged adjacent to each other.

[0074] For example, the first compensation region may be electrically coupled to the current spreading region.

[0075] By way of example, the doping concentration of the second conductivity type doped portion of the channel region may decrease from a region close to the gate electrode to a central portion of the ridge in a second horizontal direction intersecting the first horizontal direction.

[0076] For example, the channel region may further include a doped portion of the first conductivity type in a central portion of the ridge.The first compensation region may be electrically coupled to the doped portion of the first conductivity type in the central portion of the ridge.

[0077] As described herein, the semiconductor substrate may be a silicon carbide (SiC) substrate. According to an example, the silicon carbide substrate may have a hexagonal crystal lattice with a c-plane and an additional principal plane. The additional principal plane may include an a-plane or an m-plane.

[0078] The c-plane is the {0001} lattice plane. Other principal planes may include the a-plane ({11-20} lattice plane family) and the m-plane ({1-100} lattice plane family). The a-plane includes six lattice planes of different orientations: (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10). The m-plane includes six lattice planes of different orientations: (1-100), (10-10), (01-10), (-1100), (-1010), and (0-110).

[0079] The average surface plane of the silicon carbide substrate can be tilted toward the c-plane at an off-axis angle. In other words, the c-axis can be tilted toward the vertical direction at an off-axis angle. The off-axis angle can be in the range of from 2 degrees to 8 degrees, for example, in the range of from 3 degrees to 5 degrees. In particular, the off-axis angle can be approximately 4 degrees. For example, the c-axis can be tilted so that the plane spanned by the vertical direction and the c-axis is parallel to the {11-20}> plane. According to another example, the c-axis can be tilted so that the plane spanned by the vertical direction and the c-axis is parallel to the {1-100} plane. At the back side of the silicon carbide substrate, the second main surface of the silicon carbide substrate can extend parallel or approximately parallel to the average surface plane at the front side.

[0080] The first main surface at the front side of the silicon carbide substrate may be flat or ribbed. The average surface plane of the first main surface extends along the horizontal direction. The average surface plane of the flat first main surface is the same as the flat first main surface. The average surface plane of the ribbed first main surface is defined by a flat least squares plane of the ribbed first main surface. The position and orientation of the flat least squares plane are defined so that the sum of the squares of the deviations of the surface points of the ribbed first main surface from the flat least squares plane has a minimum value.

[0081] The silicon carbide substrate may extend horizontally along a plane spanned by a horizontal direction. Thus, the silicon carbide body may have a surface extension along two horizontal directions and may have a thickness along a vertical direction perpendicular to the horizontal direction. In other words, the vertical direction is parallel to the surface normal to the average surface plane.

[0082] The gate trench may pattern the first portion of the silicon carbide substrate into a ridge.By way of example, at least one of the sidewalls of the gate trench and the ridge may be parallel to a (1-100) or (-1100) plane.

[0083] The terms "first horizontal direction" and "second horizontal direction" define intersecting horizontal directions. Although some figures show the x-direction and the y-direction as examples of the first horizontal direction and the second horizontal direction by way of illustration, it is clear that it is to be understood that the first horizontal direction and the second horizontal direction need not be perpendicular to each other. The term "depth direction" defines a direction having a component perpendicular to the average surface plane. The term "depth direction" encompasses the vertical direction and any other direction different from the horizontal direction.

[0084] Figure 1A A vertical cross-sectional view of a semiconductor device 10 according to an example is shown. The semiconductor device 10 includes a transistor. The transistor includes a plurality of gate trenches 111 formed in a semiconductor substrate 100 (e.g., a SiC substrate). The gate trenches 111 pattern the semiconductor device substrate 100 into ridges 114 extending in a first horizontal direction (e.g., y direction). The ridges 114 are respectively arranged between two adjacent gate trenches 111. The transistor also includes a gate electrode 110, which is arranged in at least one of the gate trenches 111. The semiconductor device 10 also includes a source region 124 of a first conductivity type (e.g., n-type) electrically coupled to a source terminal 130. The transistor also includes: a channel region 122 including a doped portion of a second conductivity type (e.g., p-type), a current diffusion region 126 of the first conductivity type, and a drain region 125 electrically coupled to a drain terminal 129.

[0085] The source region 124, the channel region 122, and a portion of the current diffusion region 126 are arranged in the ridge 114. The gate electrode 110 is insulated from the channel region 122 and the current diffusion region 126. The source region 124 is arranged in a central portion of the ridge 114. A width w of the source region 124 may correspond to a width of the ridge 114. The channel portion 122 may be electrically coupled to a source terminal 130.

[0086] The semiconductor device also includes a super junction structure 117, which is arranged at a greater distance from the source region 124 than the channel region 122. The super junction structure 117 includes a first compensation region 118 of a first conductivity type. The first compensation region 118 is electrically coupled to a drain terminal 129. The super junction structure also includes a second compensation region 119 of a second conductivity type. The second compensation region 119 is electrically coupled to a doped portion of the second conductivity type of the channel region 122. In addition, the second compensation region 119 can be electrically coupled to the source terminal 130 via a body contact portion 123. The first compensation region 118 and the second compensation region 119 are arranged adjacent to each other. The super junction structure is arranged at a greater depth within the semiconductor substrate than the source region and the channel region.

[0087] As in Figure 1A As shown in FIG. 1 , the first compensation regions 118 and the second compensation regions 119 are alternately arranged below a region in which the gate trench 111 is formed. The order in which the first compensation regions 118 and the second compensation regions 119 are arranged may be continuous.

[0088] Figure 1B FIG. 1 is a vertical cross-sectional view of a semiconductor device 10 according to another example. The semiconductor device 10 includes Figure 1A Components similar or identical to the semiconductor device 10 shown in FIG. Figure 1A Unlike the example illustrated in FIG. 1 , the extended trench portion 113 is arranged below the gate trench 111. In more detail, Figure 1B The superjunction structure 117 of the semiconductor device 10 shown in FIG. 1 is similar to that already described with reference to FIG. Figure 1A A similar manner of explanation includes a first compensation region 118 of a first conductivity type. A second compensation region 119 of a second conductivity type is implemented by a doped sidewall portion at the extended trench portion 113. This particular arrangement of the super junction structure 117 can be attributed to a manufacturing process that includes an inclined ion implantation process. During this process, after performing the ion implantation process, a portion of the trench is retained. When the extended trench portion 113 is completely embedded in the second conductivity type doping material, the gate dielectric 112 can be effectively shielded in some examples. In other examples, it is possible that the gate dielectric 112 is not effectively shielded. In addition, current diffusion losses can be reduced.

[0089] According to Figure 1A and Figure 1B In the example illustrated in FIG. 1 , the first compensation region 118 may be arranged under the ridge 114. Furthermore, for example, the second compensation region 119 may be arranged under the gate trench 111.

[0090] As in Figure 1AAs shown in FIG. 1 , the semiconductor device may further include a drift region 127 of the first conductivity type disposed between the super junction structure 117 and the drain region 125 . The drift region 127 may be disposed between the drain region 125 and the current diffusion region 126 .

[0091] According to an example, the channel region 122 may be doped with a constant doping profile. According to another example, the doping concentration of the second conductivity type may decrease in the horizontal direction from the edge portion of the channel region 122 to its central portion. According to another implementation, the channel region 122 may include a doping portion of the first conductivity type in its central portion. This will be explained in more detail below.

[0092] Figure 2A A horizontal cross-sectional view of a semiconductor device 10 according to another example is shown. As shown, the semiconductor substrate is patterned by a gate trench 111 into a ridge 114. For example, the width of the gate trench 111 measured in the second horizontal direction can be much larger than the width of the ridge 114 measured in the second horizontal direction. For example, the width of the gate trench 111 can be greater than 3*(width of the ridge 114). In addition, the source region 124 can be segmented into source region segments 109 along the first horizontal direction. The semiconductor device 10 may also include a body contact portion 123, which is between adjacent source region segments 109 along the first horizontal direction.

[0093] Figure 2B Show that when Figure 1A 2 is a cross-sectional view of a semiconductor device when a super junction structure 117 is implemented in a similar manner as shown in FIG. In more detail, the first compensation regions 118 and the second compensation regions 119 are continuously alternated along the second direction. Figure 2B The left hand portion of shows a cross-sectional view taken at position 1 so as to intersect source region segment 109 . Figure 2B The right hand portion of is taken at position 2 so as to intersect with body contact portion 123.

[0094] Figure 2B A portion of a gate trench 111 is shown. A gate electrode 110 is arranged in the gate trench. The gate electrode may be insulated from further elements of the transistor by means of a gate dielectric 112. The first compensation region 118 and the second compensation region 119 extend in a depth direction (e.g., the z direction or another direction having a component in the z direction) and are arranged sequentially along the second direction. As shown in Figure 2BAs shown in the left hand part of , the source region 124 is arranged adjacent to the first main surface 101 of the semiconductor substrate 100 and in direct contact with the source metallization layer 103. The channel region 122 is arranged below the source region 124. The current diffusion region 126 is arranged below the channel region 122. The first compensation region 118 can be electrically coupled to the current diffusion region 126. The second compensation region 119 is arranged adjacent to the first compensation region. The super junction structure 117 includes the first compensation region 118 and the second compensation region 119.

[0095] Figure 2B The right-hand portion of shows a portion of the cross-sectional view at position 2 intersecting with body contact portion 123 . Figure 2B A shielding portion 116 of the second conductivity type is further shown, which is arranged adjacent to the channel region 122. The second compensation region 119 may be electrically coupled to the channel region 122 via the shielding portion 116.

[0096] The shielding portion may contribute to shielding the gate dielectric from potentials that may be applied at the back side of the silicon carbide body. In a blocking mode of the silicon carbide device, the shielding portion may reduce the electric field in the gate dielectric and may therefore contribute to increasing device reliability.

[0097] Figure 2C An implementation of the semiconductor device 10 is shown when the super junction structure 117 includes sidewall doping of the extended trench portion 113 . Figure 2C The left hand portion of exemplifies a cross-sectional view intersecting the source region 124 . Figure 2C The left hand part of Figure 2B Similar to the structure shown in the left hand portion of Figure 2B Unlike the example illustrated in FIG. 1 , a second compensation region 119 of the second conductivity type is doped as a sidewall of the extended trench portion 113 .

[0098] Figure 2C The right hand portion shows the Figure 2B A similar structure is shown in the right hand portion of Figure 2B Unlike the example shown in FIG. 1 , the second compensation region 119 of the second conductivity type is formed as a sidewall doping of the extended trench portion 113. The dielectric layer 115 may be arranged adjacent to the sidewall of the extended trench portion 113. Figure 2B In a similar manner as shown in the right-hand portion of , the second compensation region 119 may be electrically coupled to the channel region 122 via the shielding portion 116 .

[0099] Depending on the implementation, the doping concentration within the channel region 122 may vary along the second horizontal direction from the edge portion of the ridge 114 to the central portion of the ridge 114. For example, the concentration of the second conductivity type dopant may decrease in a direction going to the central portion of the ridge. According to another example, the channel region 122 may include a doped portion 121 of the first conductivity type in the central portion of the ridge.

[0100] Figure 3A A horizontal cross-sectional view of a semiconductor device 10 is shown. As shown, the semiconductor substrate is patterned into ridges 114 by gate trenches 111. Each of the ridges 114 includes a doped portion 120 of a second conductivity type at an edge portion and a doped portion 121 of a first conductivity type in a central region. The doped portion 121 of the first conductivity type may extend continuously along a first horizontal direction. In addition, the doped portion 120 of the second conductivity type may extend continuously along the first direction.

[0101] Figure 3B A vertical cross-sectional view of a semiconductor device is shown. As shown, the channel region 122 includes a doped portion 121 of a first conductivity type in a central portion. The source region 124 is arranged above the doped portion 121 of the first conductivity type of the channel region 122. The source region 124 is in direct contact with the source metallization layer 103. In addition, a body contact portion 123 is electrically coupled to the doped portion 120 of the second conductivity type of the channel region. The body contact portion 123 may be in direct contact with the source metallization layer.

[0102] The super junction structure 117 includes a first compensation region 118 of a first conductivity type and a second compensation region 119 of a second conductivity type. The first compensation region 118 can be electrically connected to a doped portion 121 of a first conductivity type. Therefore, due to the presence of the doped portion 121 of the first conductivity type, electrical contact can be easily completed. In addition, the mobility of carriers in the channel region can be increased. The large doping at the side of the channel region 122 can suppress the formation of an inversion layer near the interface. On the contrary, an electron accumulation layer can be formed in the doped portion 121 of the first conductivity type in the channel region. In this way, compared with a FinFET with uniform doping of the second conductivity type, bulk enhancement can be achieved using a wider width of the mesa or ridge 114. As also shown in Figure 3A As shown in FIG. 1 , contact elements for contacting the doped portions of the first conductivity type and the second conductivity type may be arranged one after the other. Figure 3B As shown in FIG. 1 , the second compensation region 119 can be implemented as a sidewall doped portion adjacent to the extended trench portion 113. According to another concept, for example, the second compensation region 119 can be implemented as a sidewall doped portion adjacent to the extended trench portion 113. Figure 1A and Figure 2B The super junction structure 117 is realized in the described manner.

[0103] Figure 3C Schematic representation of the doping concentration of the second conductivity type dopant in the channel region 122 is shown. As indicated by curve (a), the doping concentration decreases from the edge portion to the central portion of the ridge 114. The doping concentration of the second conductivity type dopant has a positive value. In other words, the channel region 122 does not include a doped portion of the first conductivity type.

[0104] According to the curve (b), the doping concentration becomes negative in the central portion. Therefore, the channel region 122 includes the doping portion 121 of the first conductivity type.

[0105] Figure 4A An example of a semiconductor device is shown in which the source region 124 is segmented into source region segments 109. The source region segments 109 and the body contact portions 123 are alternately arranged along the first direction.

[0106] Figure 4B A vertical cross-sectional view of a semiconductor device is shown. Figure 4B As shown in the left hand part of FIG. 1 , at position 1 the source region 124 is arranged in direct contact with the source metallization layer 103. The source metallization layer 103 may be electrically coupled to a source terminal. Figure 4B The right hand portion of FIG. 1 shows a cross-sectional view including a body contact portion 123. The body contact portion 123 is in direct contact with the source metallization 103. The other components of the semiconductor device are Figure 3B The components explained in are similar or identical.

[0107] FIG. 5A to FIG. 5G A cross-sectional diagram illustrating an example of a semiconductor device 10 in which a channel region 122 includes a doped portion of a second conductivity type and does not include a doped portion of a first conductivity type.

[0108] Figure 5A is a horizontal cross-sectional view of the semiconductor device 10. As shown, the gate trenches 111 pattern the semiconductor substrate into ridges 114. The source regions 124 and the body contact portions 123 are alternately arranged along the first direction. Figure 5A Also shown is a contact recess 106, which extends in the first horizontal direction and is arranged at a central portion of the gate trench 111. A conductive material is filled in the contact recess 106 to form a recess contact 128.

[0109] Figure 5B A cross-sectional view taken between I and I' is shown so as to intersect a portion where the source region 124 is in electrical contact with the source metallization layer 103. FIG. 5A to FIG. 5DThe structure shown in refers to a structure in which a contact groove 106 is additionally arranged in the central portion of the gate trench 111 to contact the shielding portion 116. The contact groove 106 extends through the gate electrode 110. Therefore, the contact groove 106 extends to a deeper depth than the embodiment in which the contact is completed via the surface of the ridge or the table. For example, the contact groove can extend to a deeper depth than the gate trench 111. The conductive material in the contact groove 106 forms a groove contact 128. Therefore, the gate electrode 110 can be interrupted along the second direction. The source region 124 is arranged in the upper portion of the ridge 114 and is arranged to be in electrical contact with the source metallization layer 103. In addition, the channel region 122 is arranged in the ridge below the source region 124. The current diffusion region 126 of the first conductivity type is arranged adjacent to the channel region 122. The current diffusion region 126 does not extend continuously along the second horizontal direction. The shielding portion 116 of the second conductivity type is arranged between adjacent portions of the current diffusion region 126. Shielding portion 116 is electrically coupled to source metallization layer 103 via recessed contact 128 .

[0110] The super junction structure 117 is arranged below the current diffusion region 126 and the shielding portion 116. The super junction structure 117 includes a first compensation region 118 of a first conductivity type and a second compensation region 119 of a second conductivity type. For example, the first compensation region 118 may be electrically coupled to the current diffusion region 126. In addition, the second compensation region 119 may be electrically coupled to the shielding portion 116. The current diffusion region 126 and the first compensation region 118 may be arranged below the ridge. In addition, a portion of the current diffusion region 126 and a portion of the shielding portion 116 are arranged below the gate electrode. The current diffusion region 126 and the shielding portion 116 extend in the first direction. The second compensation region 119 may be arranged below the shielding portion 116 and below the gate trench 111.

[0111] Figure 5C A cross-sectional view taken between II and II′ is shown so as to intersect with the body contact portion 123 . Figure 5C The cross-sectional view of Figure 5B The cross-sectional view is similar or identical to that of Figure 5B Unlike the cross-sectional view of , the body contact portion 123 is in contact with the source metallization layer 103 .

[0112] Figure 5D is a horizontal cross-sectional view of the semiconductor device taken between III and III', as also shown in Figure 5B and Figure 5C 1 so as to intersect with the super junction structure 117. As shown, the first compensation region 118 and the second compensation region 119 extend in the first horizontal direction. The first compensation region 118 and the second compensation region 119 are alternately arranged along the second horizontal direction.

[0113] According to another example, the first compensation area 118 and the second compensation area 119 may extend in the second horizontal direction.

[0114] Figure 5E A vertical cross-sectional view of the semiconductor device 10 is shown, in which the arrangement of the source region 114, the channel region 122, the current diffusion region 126 and the shielding portion 116 is the same as in FIG. FIG. 5A to FIG. 5C Similar to the figure in . Figure 5E The cross-sectional view is taken between I and I', as in Figure 5A As shown in FIG. 1 , the first compensation region 118 may extend in the second horizontal direction so as to intersect the source region 124 . As shown, the first compensation region 118 may extend in the second horizontal direction. The first compensation region 118 may be electrically coupled to the current diffusion region 126 .

[0115] Fig. 5F A vertical cross-sectional view taken between II and II' is shown, also as in Figure 5A , so as to intersect with the body contact portion 123. As shown, the second compensation region 119 can extend in the second horizontal direction. The second compensation region 119 can be electrically coupled to the shielding portion 116.

[0116] Figure 5G is a horizontal cross-sectional view of the semiconductor device taken between III and III', as also shown in Figure 5E and Fig. 5F , so as to intersect with the super junction structure 117. As shown, the first compensation region 118 and the second compensation region 119 extend in the second horizontal direction. The first compensation region 118 and the second compensation region 119 are alternately arranged along the first horizontal direction.

[0117] according to FIG. 5A to FIG. 5G The source region 124 may be contacted from the top of the semiconductor device via the source metallization 103. The shielding portion 116 and the second compensation region 119 of the second conductivity type are contacted via a recess contact 128. Furthermore, the body contact portion 123 provides an electrical contact between the source terminal and the channel region 122.

[0118] Fig. 6A 1 shows a horizontal cross-sectional view of the semiconductor device 10, wherein the channel region 122 includes a doped portion 120 of the second conductivity type, and further includes a doped portion 121 of the first conductivity type, which is arranged in the central portion of the ridge 114. Figure 5A In a similar manner as explained, the gate trench 111 patterns the semiconductor substrate into a ridge 114. Additionally, a contact recess 106 is arranged in a central portion of the gate trench 111. The contact recess 106 extends in a first horizontal direction. The source region 124 extends continuously along the first direction.

[0119] Figure 6B 1 is a vertical cross-sectional view taken between I and I'. As shown, a doped portion 121 of a first conductivity type is arranged in a central portion of each of the ridges 114. A doped portion 120 of a second conductivity type is in contact with the shielding portion 116. A first compensation region 118 of a first conductivity type can be electrically coupled to the doped portion 121 of the first conductivity type via a current diffusion region 126. The gate electrode 110 is arranged adjacent to the channel region 122. The gate electrode 110 is insulated from the channel region 122 by means of a gate dielectric 112. The gate electrode 110 can be divided into two gate electrodes by means of a contact groove 106. For example, the source metallization layer 103 can be arranged in the contact groove 106 to realize a groove contact 128. Due to the groove contact 128, the shielding portion 116 can be electrically coupled to the source terminal.

[0120] exist Fig. 6A and Figure 6B The semiconductor device illustrated in FIG. 1 has a low gate-drain capacitance because the gate is completely embedded in the source metallization layer and the doped portion 120 of the second conductivity type electrically coupled to the source terminal 130 .

[0121] As in Figure 6B As further illustrated in FIG. 1 , the doped portion 120 of the second conductivity type is contacted from below by the shielding portion 116. In this configuration, the shielding portion 116 may be arranged in a self-aligned manner when performing an implantation process in the gate trench 111.

[0122] Figure 6C is a horizontal cross-sectional view of the semiconductor device so as to intersect the super junction structure 117. As shown, the first compensation region 118 and the second compensation region 119 extend in the first horizontal direction. The first compensation region 118 and the second compensation region 119 are alternately arranged along the second horizontal direction.

[0123] According to another example, the first compensation area 118 and the second compensation area 119 may extend in the second horizontal direction.

[0124] Fig.6D A vertical cross-sectional view of the semiconductor device 10 is shown, in which the arrangement of the source region 114, the channel region 122, the current diffusion region 126 and the shielding portion 116 is the same as in FIG. Fig. 6A and Figure 6B Similar to the figure in . Fig.6D The cross-sectional view is taken between I and I', as also shown in Fig. 6A As shown in FIG. 1 , the first compensation region 118 may extend in the second horizontal direction. The first compensation region 118 may be electrically coupled to the current spreading region 126 .

[0125] Fig. 6E A vertical cross-sectional view taken between II and II' is shown, also as in Fig. 6A As shown, the second compensation region 119 may extend in the second horizontal direction. The second compensation region 119 may be electrically coupled to the shielding portion 116.

[0126] Fig. 6F is a horizontal cross-sectional view of a semiconductor device taken so as to intersect a super junction structure 117. As shown, first compensation regions 118 and second compensation regions 119 extend in a second horizontal direction. First compensation regions 118 and second compensation regions 119 are alternately arranged along the first horizontal direction.

[0127] Fig. 7A A horizontal cross-sectional view of a semiconductor device 10 according to another example is shown. Fig. 7A Semiconductor devices and Figure 5A Similar to the semiconductor device shown in FIG. Figure 5A Unlike the example illustrated in , the contact groove 106 and thus the groove contact 128 are not implemented so as to extend continuously along the first direction. Instead, the groove contact 128 is implemented as an island or segment. Fig. 7A As shown in FIG. 1 , the gate trench 111 patterns the semiconductor substrate into a ridge 114. The source region 124 is arranged in the ridge 114 and extends continuously in the first direction. Figure 7C As explained, body contact to the channel region 122 may be achieved via the shielding portion 116. The recess contact 128 may be arranged as a recess contact island 108 within the gate trench 111.

[0128] Figure 7B 1 is a cross-sectional view of a semiconductor device between I and I' in a region where there is no recessed contact island 108. Figure 7B As shown in FIG. 1 , the gate trench 111 patterns the semiconductor substrate 100 into a ridge 114. The source region 124 is arranged in the upper portion of the ridge. The channel region 122 of the second conductivity type is arranged adjacent to the source region 124. The current diffusion region 126 of the first conductivity type is partially arranged within the ridge 114. Optionally, a doped portion of the second conductivity type may be arranged below the gate trench 111. As a result, the gate-drain capacitance C GD can be reduced, and the gate-source capacitance C GS can be increased. Therefore, the risk of parasitic turn-on can be reduced. The gate electrode 110 is arranged in the gate trench between adjacent ridges 114. The gate electrode is insulated from the channel region 122 by means of the gate dielectric 112. According to an example, the first compensation region 118 and the second compensation region 119 can extend in a second horizontal direction intersecting the first direction. Therefore, as in Figure 7B As shown in FIG. 1 , the first compensation region 118 of the first conductivity type may be arranged below the current spreading region 126 .

[0129] Figure 7C A cross-sectional view taken between II and II′ at a position intersecting with the contact groove 128 is shown. Figure 7C The cross-sectional view further intersects with a portion where a shielding portion 116 of the second conductivity type is arranged below the gate trench and below the ridge 114. In addition, a second compensation region 119 is arranged below the gate trench. Figure 7B and Figure 7C As can be seen from the comparison, the strips of the current diffusion region 126 and the shielding portion 116 can be arranged alternately along the first direction. The strips of the current diffusion region 126 and the shielding portion 116 extend in the second horizontal direction. In a corresponding manner, the first compensation region 118 and the second compensation region 119 are arranged as strips extending in the second direction. The first compensation region 118 and the second compensation region 119 are arranged alternately along the first horizontal direction. The shielding portion 116 is arranged so as to overlap with the second compensation region 119. In addition, the current diffusion region 126 is arranged so as to overlap with the first compensation region 118.

[0130] exist Figure 7C In the cross-sectional view of FIG. 1 , the recess contact 128 extends to the shielding portion 116. Therefore, the source metallization layer 103 is in contact with the shielding portion 116. In this way, the channel region 122 is electrically coupled to the source terminal 130 by means of the shielding portion 116 and the recess contact 128.

[0131] Fig.7D A cross-sectional view taken between III and III' along the gate trench 111 including the recessed contact 128 is shown. As shown, the first compensation region 118 and the second compensation region 119 are alternately arranged along the first direction. In addition, the current diffusion region 126 and the shielding portion 116 are alternately arranged along the first direction. The first compensation region 118 and the current diffusion region 126 are arranged in a portion below the gate electrode 110. The shielding portion 116 and the second compensation region 119 are arranged below the source metallization layer 103.

[0132] Fig. 7E A cross-sectional view taken between IV and IV' along a first horizontal direction at the location of the source region 124 or ridge is shown. As shown, the channel region 122 is arranged continuously below the source region 124. The shielding portions 116 and the current spreading regions 126 are alternately arranged along the first direction.

[0133] Figure 7F is like Figure 7B and 7CHorizontal cross-sectional view taken between V and V' indicated in FIG. As shown, the first compensation area 118 and the second compensation area 119 extend in the second horizontal direction. The first compensation area 118 and the second compensation area 119 are alternately arranged along the first horizontal direction.

[0134] Fig. 8A 1 is a horizontal cross-sectional view of a semiconductor device 10 according to another example. Figure 8B and Figure 8C The indicated V and V' are obtained between Fig. 8A According to the cross-sectional view of Fig. 8A In the embodiment illustrated in FIG. 1 , the gate trench 111 is formed as a segmented trench. Therefore, the gate trench does not extend continuously along the first horizontal direction. Instead, trench segments 107 are formed. For example, the lateral length of the gate trench segment 107 in the first horizontal direction can be smaller than the width in the second horizontal direction.

[0135] As in Fig. 8A As shown in FIG. 1 , the ridge 114 is arranged between adjacent trench segments 107 along the second horizontal direction. In addition, alternating doping portions of the first conductivity type and the second conductivity type are formed between adjacent trench segments 107 along the first direction. A gate metal layer portion is formed above the trench segments 107 and extends along the second direction. As will be described below with reference to FIG. FIG. 8B to FIG. 8E As explained, the source metallization layer 103 may be arranged over the entire arrangement. The source metallization layer 103 may be in direct contact with the source regions 124 and the body contact portions 123 between adjacent trench segments 107 .

[0136] Figure 8B A cross-sectional view of a semiconductor device between I and I' is shown. Figure 8B The cross-sectional view of is formed to intersect with the trench segment 107. The cross-sectional view is taken along the second horizontal direction. As shown, the trench segment 107 patterns the semiconductor substrate into a ridge 114. The source region 124 and the channel region 122 and a portion of the current diffusion region 126 are arranged in the ridge 114. The gate electrode 110 is arranged in the trench segment 107. The gate electrode 110 is insulated from the channel region 122 by means of a gate dielectric layer 112. A portion of the conductive material forming the gate electrode 110 is arranged between the source region 124 and the source metallization layer 103. A shielding portion 116 of the second conductivity type is arranged below the trench segment 107. The first compensation region 118 is arranged below the current diffusion region 126. A portion of the gate dielectric layer 112 may be arranged between the conductive material forming the gate electrode 110 and the source metallization layer 103.

[0137] Figure 8CA cross-sectional view taken between II and II' along the second horizontal direction at a position where no groove segmentation is present is shown. Figure 8C , the source regions 124 are arranged alternately with the body contact portions 123 of the second conductivity type. The doped portions 105 of the second conductivity type are arranged below the source regions 124. The source regions 124 and the body contact portions 123 are in contact with the source metallization layer 103. The shielding portion 116 is indicated by a dotted line. The second compensation region 119 is arranged below the doped portions 105 of the second conductivity type.

[0138] Fig.8D A cross-sectional view taken between III and III' along a first horizontal direction is shown. As shown, the trench segment 107 is arranged in the central portion. The gate electrode 110 is arranged in the trench segment 107 and is insulated from the adjacent semiconductor material by means of a gate dielectric 112. The source metallization layer 103 is arranged above the gate electrode 110. The source metallization layer 103 is insulated from the gate electrode 110. The doped portion 105 of the second conductivity type is arranged to be adjacent to the gate electrode 110 in the lateral direction. The shielding portion 116 of the second conductivity type is arranged below the gate electrode 110. A super junction structure 117 including a first compensation region 118 and a second compensation region 119 is arranged below the gate electrode. The first compensation region 118 overlaps horizontally with the gate electrode 110. The second compensation region 119 is arranged to be adjacent to the gate electrode 110 in the lateral direction.

[0139] Fig. 8E As shown in Fig. 8A 1 and 1 . A cross-sectional view taken between IV and IV' indicated in . A cross-sectional view taken along the ridge 114. As shown, portions of the channel region 122 and the current diffusion region 126 are arranged in the ridge 114. The source region 124 extends continuously along the first horizontal direction. The first compensation region 118 is arranged below the current diffusion region 126. In addition, the second conductivity type doped portion 105 is arranged adjacent to the ridge 114. In addition, the second compensation region 119 is arranged adjacent to the first compensation region 118 in the lateral direction.

[0140] For example, when manufacturing FIG. 8A to FIG. 8E When the semiconductor device 10 is shown in FIG. 1 , a low energy implantation process may be used to define the shielding portion 116 via the gate trench 111. In addition, a doped portion of the channel region 122 may be formed within the ridge 114. Figure 8B As shown in FIG. 1 , the source region 124 does not contact the source metallization layer 103 at the top of the ridge 114. Contact to the source metallization layer 103 can be made at the mountain-shaped end of the ridge 114, such as at Figure 8CAs shown in FIG. 1 . The channel region 122 may be electrically coupled to the source metallization layer 103 via the second conductivity type doped portion 105 and the body contact portion 123. The shielding portion 116 may be electrically coupled to the source metallization layer 103 via the second conductivity type doped portion 105, as shown in FIG. Figure 8C According to another implementation, a different contact scheme may be used.

[0141] A method for manufacturing the semiconductor device that has been explained above will be described below. Fig.9A An example of a workpiece 15 including an epitaxially grown portion 134 (eg, a SiC portion) is shown. Fig. 9B As shown in FIG. 1 , an ion implantation process 133 may be performed to provide a first doped portion 131 of a first conductivity type and a second doped portion 132 of a second conductivity type. For example, an ion implantation process 133 may be performed using a doping mask to provide the first doped portion 131 and the second doped portion 132.

[0142] Reference Fig. 9C , a further epitaxial growth method may be performed to provide a further epitaxial growth portion 134. Then, referring to Fig.9D , an additional ion implantation process 133 may be performed to provide a first doped portion 131 and a second doped portion 132. Fig. 9C and Fig.9D The sequence described in is repeated until the desired heights of the first doped portion and the second doped portion are provided.

[0143] Fig.9E A further process of epitaxially growing a semiconductor portion 134 is shown. Thereafter, a further implantation process 133 is performed to provide a source region 124 of the first conductivity type adjacent to the first main surface of the workpiece 15. Thereafter, a gate trench 111 is defined in the main surface of the resulting workpiece, as in Figure 9G For example, the gate trench 111 may be etched to a bottom portion of the epitaxially grown portion 134 disposed above the first doped portion 131 and the second doped portion 132. According to another implementation, the gate trench 111 may be etched to a depth less than the thickness of the epitaxially grown portion 134, so that a portion of the epitaxially grown portion 134 is retained below the gate trench 111.

[0144] Afterwards, as in Figure 9H As shown in FIG. 1 , an inclined ion implantation process may be performed to form a second conductivity type doped portion 120 and a first conductivity type doped portion 121. During the inclined ion implantation process 136, the implantation angle and energy may be appropriately set to provide the first doped portion 120 and the second doped portion 121. Figure 9HAn example of a resulting workpiece 15 is shown. Thereafter, further processing for defining elements of the semiconductor device may be performed.

[0145] According to the replacement method, from Fig.9F Starting with the structure shown in FIG. 1 , a further ion implantation process 133 may be performed in order to define the channel region 122. Thereafter, the gate trench 111 may be etched, resulting in the definition of the ridge 114. Figure 9J An example of a resulting workpiece 15 is shown. Thereafter, further processing for defining elements of the semiconductor device may be performed.

[0146] According to another example, an epitaxial process may be performed to form an epitaxial growth portion 134, such as a SiC body. Fig. 10B As shown in FIG. 1 , various blanket, eg, unmasked, ion implantation processes 133 may be performed to define current spreading regions 126, channel regions 122, and source regions 124. In particular, various implantation processes with dopants of different conductivity types may be performed.

[0147] Afterwards, refer to Fig. 10C , trenches 135 may be etched into the surface of the resulting workpiece. Fig. 10C An example of a resulting workpiece 15 is shown. Thereafter, an angled ion implantation process 136 may be performed in order to provide doped sidewall portions. Fig. 10D An example of a workpiece including doped sidewall portions 138 of the second conductivity type is shown.

[0148] Afterwards, refer to Fig.10E , a further implantation process 136 may be performed so as to define a doped sidewall portion 137 of the first conductivity type. According to another example, the order of the processes may be reversed. Thereafter, a dielectric material 139 is formed. For example, the dielectric material 139 may include silicon oxide. The dielectric material 139 may be formed so as to cover the sidewalls of the trench 135. Furthermore, a filling of the dielectric material 139 is formed in the upper trench portion.

[0149] Reference Figure 10G , etching the gate trench 111, thereby defining the ridge 114. Then, referring to Fig. 10H A gate dielectric layer 112 is formed adjacent to the sidewalls of the gate trench 111. Furthermore, a conductive material is filled to form the gate electrode 110. Thereafter, the workpiece 15 may be further processed to provide additional components of the semiconductor device.

[0150] According to another example, first, the epitaxially grown portion 134 may be formed, as in Fig.11A Thereafter, as in Fig. 11BAs shown in FIG. 1 , an ion implantation process 133 may be performed to form a source region 124 of the first conductivity type. Fig. 11C , a groove 135 may be formed in the workpiece 15. Thereafter, referring to Fig.11D , an inclined ion implantation process 126 may be performed. As a result, a first doped sidewall portion 138 of the second conductivity type may be formed directly adjacent to the sidewall. Fig.11E , a first conductivity type doped sidewall portion 137 may be formed. Fig.11F As shown in FIG. 1 , thereafter, a further tilted ion implantation process 136 may be performed in order to form a doped portion 120 of the second conductivity type of the channel region.

[0151] Then, as in Fig.11G As shown in FIG. 1 , an additional tilted ion implantation process 136 may be performed to form a doped portion 121 of the first conductivity type in the central portion of the ridge 114. Fig.11H As shown in FIG. 1 , a dielectric material 135 is formed on the sidewalls of the extended trench portion 113. In addition, a dielectric material 135 for forming a gate dielectric layer 112 is formed in the upper trench portion. In addition, a conductive material for forming a gate electrode 110 is filled in the trench. Fig.11D and Fig.11E The implantation process shown in FIG. 1 is performed so that the implanted portions 138, 135 reach down to the bottom of the trench. Fig.11F and Fig.11G In the process described, Fig.11D and Fig.11E The tilt angle is larger than that in the process shown in FIG. The tilt angle is adjusted so as to set the desired length of the channel region 122 .

[0152] Although embodiments of the present invention have been described above, it is apparent that other embodiments may be implemented. For example, other embodiments may include any subcombination of the features recited in the claims or any subcombination of the elements described in the examples given above. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

Claims

1. A semiconductor device (10), comprising a transistor, the transistor comprising: A plurality of gate trenches (111) are formed in the semiconductor substrate (100), the gate trenches (111) patterning the semiconductor substrate (100) into ridges (114) extending in a first horizontal direction, the ridges (114) being arranged between two adjacent gate trenches (111); a gate electrode (110) disposed in at least one of the gate trenches (111); A source region (124) of a first conductivity type and electrically coupled to a source terminal (130), a channel region (122) including a doped portion (120) of a second conductivity type, a current diffusion region (126) of the first conductivity type, and a drain region (125) electrically coupled to a drain terminal (129), the source region (124), the channel region (122) and a portion of the current diffusion region (126) being arranged in a ridge (114), the gate electrode (110) being insulated from the channel region (122) and the current diffusion region (126), wherein the source region (124) is arranged at least in a central portion of the ridge (114); The semiconductor device (10) further comprises a super junction structure (117) which is arranged at a greater distance from the source region (124) than the channel region (122), comprising: a first compensation region (118) of a first conductivity type, the first compensation region (118) being electrically coupled to a drain terminal (129); and The second compensation region (119) of the second conductivity type, the first compensation region (118) and the second compensation region (119) are adjacent to each other, The doping concentration of the second conductivity type doping portion (120) of the channel region (122) decreases from a region close to the gate electrode (110) to a central portion of the ridge (114) in a second horizontal direction intersecting the first horizontal direction.

2. The semiconductor device (10) of claim 1, wherein the channel region (122) further comprises a doped portion (121) of the first conductivity type in a central portion of the ridge (114).

3. The semiconductor device (10) of claim 2, wherein the first compensation region (118) is electrically coupled to a doped portion (121) of the first conductivity type in a central portion of the ridge (114).

4. The semiconductor device (10) as described in any one of claims 1 to 3, further comprising a shielding portion (116) of the second conductivity type, which is correspondingly arranged below the gate trench (111), the shielding portion (116) having a higher doping concentration than the second compensation region (119), wherein the second compensation region (119) is electrically coupled to the shielding portion (116).

5. The semiconductor device (10) as claimed in any one of the preceding claims, wherein the super junction structure (117) extends in a first horizontal direction.

6. The semiconductor device (10) according to any one of claims 1 to 4, wherein the super junction structure (117) extends in a second horizontal direction intersecting the first horizontal direction.

7. The semiconductor device (10) as claimed in any one of the preceding claims, wherein the source region (124) extends continuously along the first horizontal direction.

8. A semiconductor device (10) as claimed in any one of claims 1 to 6, wherein the source region (124) is segmented into source region segments (109) along a first horizontal direction, wherein the semiconductor device further comprises a body contact portion (123) between adjacent source region segments (109), the body contact portion (123) being electrically coupled to a source terminal (130).

9. The semiconductor device (10) as claimed in any one of the preceding claims, further comprising a drift region (127) of the first conductivity type arranged between the super junction structure (117) and the drain region (125).

10. The semiconductor device (10) as claimed in any one of the preceding claims, wherein the gate trench (111) extends continuously in the first horizontal direction.

11. The semiconductor device (10) according to claim 10, further comprising: a contact recess (106) running in a first horizontal direction and extending through the gate trench (111); A metal layer is arranged in the contact recess (106), which is electrically coupled to the source terminal (130) and the second compensation region (119) of the second conductivity type.

12. The semiconductor device (10) of claim 11, wherein the contact recess (106) extends continuously in the first horizontal direction.

13. The semiconductor device (10) of claim 11, wherein the contact recess (106) is segmented into recess contact islands (108).

14. The semiconductor device (10) according to any one of claims 1 to 10, wherein the gate trench (111) comprises a plurality of trench segments (107), which are arranged along a first horizontal direction.

15. A semiconductor device (10) as claimed in claim 14, further comprising a metal layer which is electrically coupled to the source terminal (130), the metal layer being arranged to contact the source region (124) between adjacent trench segments (107) and to contact the doped portion (120) of the second conductivity type (120) of the channel region (121).

16. A semiconductor device (10), comprising a transistor, the transistor comprising: A plurality of gate trenches (111) are formed in the SiC substrate (100), the gate trenches (111) patterning the SiC substrate (100) into ridges (114) extending in a first horizontal direction, the ridges (114) being arranged between two adjacent gate trenches (111); a gate electrode (110) disposed in at least one of the gate trenches (111); A source region (124) of a first conductivity type and electrically coupled to a source terminal (130), a channel region (122) including a doped portion (120) of a second conductivity type, a current diffusion region (126) of the first conductivity type, and a drain region (125) electrically coupled to a drain terminal (129), the source region (124), the channel region (122) and a portion of the current diffusion region (126) being arranged in a ridge (114), the gate electrode (110) being insulated from the channel region (122) and the current diffusion region (126), wherein a width of the source region (124) corresponds to a width of the ridge (114); The semiconductor device (10) further comprises a super junction structure (117) which is arranged at a greater distance from the source region (124) than the channel region (122), the super junction structure (117) comprising: a first compensation region (118) of a first conductivity type, the first compensation region (118) being electrically coupled to a drain terminal (129); and A second compensation region (119) of the second conductivity type is electrically coupled to a doped portion (121) of the second conductivity type of the channel region (122), and the first compensation region (118) and the second compensation region (119) are adjacent to each other.

17. The semiconductor device (10) of claim 16, wherein the first compensation region (118) is electrically coupled to the current spreading region (126).

18. A semiconductor device (10) as described in any one of claims 16 or 17, wherein the doping concentration of the second conductivity type doped portion (120) of the channel region (122) decreases from a region close to the gate electrode (110) to a central portion of the ridge (114) in a second horizontal direction intersecting the first horizontal direction.

19. The semiconductor device (10) of claim 18, wherein the channel region (122) further comprises a doped portion (121) of the first conductivity type in a central portion of the ridge (114).

20. The semiconductor device (10) of claim 19, wherein the first compensation region (118) is electrically coupled to a doped portion (121) of the first conductivity type in a central portion of the ridge (122).

21. A semiconductor device (10) as claimed in any one of claims 16 to 20, further comprising a contact groove (106) which runs in a first horizontal direction and extends from a bottom portion of the gate trench (111) in a depth direction, the metal layer arranged in the contact groove (106) being electrically coupled to the source terminal (130).

22. The semiconductor device (10) of any one of claims 16 to 10, wherein the gate trench (111) comprises a plurality of trench segments (107) arranged along the first horizontal direction.

23. The semiconductor device (10) of claim 22, further comprising a metal layer electrically coupled to the source terminal (130), the metal layer being arranged to contact the source region (124) between adjacent trench segments (107).

Images