Stress testing for growing bad blocks

Abstract

Techniques for detecting growing bad blocks in a non-volatile storage system are disclosed herein. Stress testing can accelerate stress conditions on memory cells and thereby provide early detection of growing bad blocks. The stress test may include applying a program voltage to a selected word line and applying a stress voltage less than a nominal boost voltage to a word line adjacent to one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than that would be generated in a normal program operation, thereby accelerating stress on the memory cells. The stress testing may also include programming all of the memory cells to a relatively high threshold voltage that may create an additional stress on the memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 17 / 886,155, filed on August 11, 2022, entitled “STRESS TEST FOR GROWN BAD BLOCKS” and is hereby incorporated by reference in its entirety for all purposes. Background Art

[0003] The present disclosure relates to non-volatile memory.

[0004] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0005] The memory structure in the memory system usually contains many memory cells and various control lines. The memory structure can be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged as vertical NAND strings. The memory structure can be arranged into units commonly referred to as blocks. For example, a block in a NAND memory system contains many NAND strings. The NAND string includes memory cell transistors connected in series, a drain side selection gate at one end, and a source side selection gate at the other end. Each NAND string is associated with a bit line. The block usually has many word lines, which provide voltage to the control gate of the memory cell transistor. In some architectures, each word line is connected to the control gate of a memory cell on each corresponding NAND string in the block.

[0006] Non-volatile memory cells can be programmed to store data. Typically, memory cells are programmed to multiple data states. Using two data states to store a single bit per cell is referred to herein as SLC programming. Using a greater number of data states allows more bits to be stored per memory cell. Using additional data states to store two or more bits per cell is referred to herein as MLC programming. For example, four data states can be used to store two bits per memory cell, eight data states can be used to store three bits per memory cell, 16 data states can be used to store four bits per memory cell, etc. Some memory cells can be programmed to data states by storing charge within the memory cell. For example, the threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming the charge into a charge storage region such as a charge trapping layer. The amount of charge stored in the charge trapping layer determines the Vt of the memory cell.

[0007] During a programming operation, a series of programming voltage pulses are applied to the control gate of the memory cell. Each voltage pulse may be stepped in amplitude by one step size from the previous programming pulse in the process, which is referred to as incremental step pulse programming. Each programming voltage may be followed by a verification operation to determine whether the corresponding memory cell has been programmed to the desired memory state. Therefore, a programming operation may include multiple programming / verification cycles. The word line connected to the memory cell being verified is referred to as the "selected word line" in this article. The remaining word lines connected to other memory cells on the NAND string are referred to as "unselected word lines" in this article.

[0008] The following manufacturing defects may exist in the memory structure. For example, there may be a short circuit between a word line and a NAND string. There may be a short circuit between a word line and a conductive line such as a source line. Such defects may cause malfunction of memory operations such as erase, program and / or read. Such defects may potentially cause data loss. Therefore, the memory structure is usually tested after manufacturing to detect such defects. The area of ​​the memory structure with defects can be retired. For example, a block of memory cells containing defects can be marked as a bad block so that the block is not used in the field.

[0009] Normal memory operation in the field creates a small amount of stress on the memory structure. Over time, the accumulated stress from many memory operations may create defects. In this article, the term "growing bad blocks" refers to blocks of memory cells that have developed defects in the field. Some memory systems will test for growing bad blocks and disable the growing bad blocks. For example, some systems may test for defects during programming operations. However, testing for defects during programming operations may affect performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Like numbered elements refer to common parts in different drawings.

[0011] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0012] Figure 2A is a block diagram of one embodiment of a memory die.

[0013] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0014] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0015] Figure 4 is a perspective view of a portion of an example embodiment of a monolithic three dimensional memory structure.

[0016] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0017] Figure 4B is a block diagram depicting a top view of a portion of a block of memory cells.

[0018] Figure 4C Depicted is an embodiment of a stack showing the Figure 4B Sectional view along line AA.

[0019] Figure 4D Depicted Figure 4C View of area 445.

[0020] Figure 4E is a schematic diagram of a portion of one embodiment of a block, depicting several NAND strings.

[0021] Figure 5A , Figure 5B and Figure 5C The threshold voltage distribution is depicted.

[0022] Figure 6 is a flow chart describing one embodiment of a process for programming a memory cell.

[0023] Figure 7 is a flow chart of one embodiment of a process for detecting growing bad blocks in a non-volatile storage system.

[0024] Figure 8 is a schematic diagram of a NAND string depicting voltages applied during an embodiment of a stress test.

[0025] Fig. 9is a flow chart of one implementation of a process for performing stress testing on a group of memory cells.

[0026] Fig.10 is a flow chart of one implementation of a process for post-stress testing health check.

[0027] Fig.11 is a flow chart of one embodiment of a normal programming process.

[0028] Fig.12 is a flow chart of one embodiment of a process for programming during stress testing.

[0029] Fig.13 is a block level diagram of one embodiment of components used in a fast search for leaky word lines.

[0030] Fig.14 is a flow chart of one embodiment of a process for locating a leaky word line.

[0031] Fig.15A and Fig. 15B An example is provided to illustrate a divide-and-conquer search for leaky word lines.

[0032] Fig.16 is a flow chart of one embodiment of a process of repeatedly dividing a group of word lines into smaller sub-groups and selecting the smaller sub-groups for short testing until a word line involved in a short is located.

[0033] Fig.17A is a flow chart of one embodiment of a process for determining whether a block of word lines contains a leaky word line.

[0034] Fig. 17B is provided in Fig.17A A table with further details of the voltages applied during embodiments of the process.

[0035] Fig.18A is a flow chart of one embodiment of a process of determining whether a subgroup of word lines contains a leaky word line.

[0036] Fig.18B is provided in Fig.18A A table with further details of the voltages applied during embodiments of the process.

[0037] Fig.19 is a flow chart of one embodiment of a process for performing a leaky wordline test in a particular set of wordlines. DETAILED DESCRIPTION

[0038] Disclosed herein are techniques for detecting growing bad blocks in non-volatile memory systems. In an embodiment, a stress test is performed on a group of memory cells. The stress test can accelerate the stress condition on the memory cells and thereby provide early detection of growing bad blocks. In addition, the number of growing bad blocks that escape detection is kept low. In an embodiment, the stress test involves generating an electric field (e-field) near the junction between the word line and the NAND string. Growing bad blocks can be detected during a built-in self test (BIST). For example, electronic circuits within a memory system can test for and locate growing bad blocks.

[0039] In an embodiment, the stress test includes applying a programming voltage to a selected word line and applying a stress voltage less than a nominal boost voltage to a word line adjacent to one side of the selected word line. The combination of the programming voltage and the stress voltage can generate an e-field stronger than that which would be generated in a normal programming operation, thereby accelerating the stress on the memory cells. In an embodiment, the stress test also includes programming all memory cells to a relatively high threshold voltage that can generate additional stress on the memory cells.

[0040] Disclosed herein are techniques for detecting short circuits involving word lines in non-volatile memory systems. Word lines involved in short circuits (or more briefly "shorts") are referred to herein as "leaky word lines," which refers to current leakage that occurs due to the short circuit. Short circuits may include, but are not limited to, word line to NAND channel shorts, word line to conductive line shorts, and / or word line to source line shorts. Leaky word lines may be detected during built-in self-test (BIST). For example, electronic circuitry within a memory system may test for and locate leaky word lines.

[0041] In an embodiment, a divide and conquer method is used to very quickly locate the exact word line involved in the short circuit. In an embodiment, it is first determined whether at least one word line in a group (such as any of the word lines in a block) is involved in the short circuit. This initial determination can be made very quickly. If no word line in the group is involved in the short circuit, the search can end. However, in response to a determination that at least one word line in the group is involved in the short circuit, a divide and conquer search can be performed in which the group of word lines is repeatedly divided into smaller sub-groups, with the smaller sub-groups selected for the short circuit test until the word line involved in the short circuit is located.

[0042] Determining the exact word lines that are leaking provides feedback that can be used to improve the design and manufacture of future memory systems. For example, if it is determined that word lines located in a particular area of ​​a block are more likely to fail, changes can be made in the design and / or manufacture to improve such word lines. Additionally, operational changes can be made to account for certain word lines that are more likely to become leaky word lines in the field.

[0043] Figure 11 is a block diagram of one embodiment of a storage system 100 that implements the technology described herein. In one embodiment, the storage system 100 is a solid state drive ("SSD"). The storage system 100 can also be a memory card, a USB drive, or other types of storage systems. The technology of the present invention is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses a memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0044] Figure 1 The components of the storage system 100 depicted in are electronic circuits. The storage system 100 includes a memory controller 120 (or storage device controller) that is connected to a non-volatile storage device 130 and a local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local memory 140 is a non-volatile memory that may include volatile memory or non-volatile memory. The memory controller 120 uses the local high-speed memory 140 to perform certain operations. For example, the local high-speed memory 140 may store a logical to physical address translation table ("L2P table").

[0045] The memory controller 120 includes a host interface 152, which is connected to the host 102 and communicates with it. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use clockless asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of system on chip (SoC) and the power efficiency of complex SoC. The wires and links of NOC are shared by many signals. Since all links in NOC can operate on different data packets at the same time, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and local memory controller 164 are connected to and communicate with NOC 154. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0046] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0047] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom and dedicated hardware circuit without any software. Processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store data between the locations of one or more memory dies as it wishes. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An example implementation is to maintain a table (i.e., the above-mentioned L2P table) identifying the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they do not have to be tables in the literal sense. Instead, logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all of the L2P tables. In this case, the entire set of L2P tables is stored in the storage device 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed memory 140.

[0048] The memory interface 160 communicates with the non-volatile storage device 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for sending data to one or more memory dies and receiving data from one or more memory dies.

[0049] In one embodiment, non-volatile storage 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including a non-volatile storage device 130. Each of the one or more memory dies of the non-volatile storage device 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory structure 202 (e.g., a memory array), which may include non-volatile memory cells (also referred to as non-volatile storage device cells), as described in more detail below. The array terminal lines of the memory structure 202 include various word line layers organized into rows and various bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output of which is connected to the corresponding word lines of the memory structure 202. The row control circuit 220 receives a group M row address signal and one or more various control signals from the system control logic circuit 260, and may generally include circuits such as a row decoder 222, an array driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a read / write circuit 225. The read / write circuit 225 may contain a sense amplifier and a data latch. The sense amplifier inputs / outputs are connected to corresponding bit lines of the memory structure 202. Although only a single block is shown for the structure 202, the memory die may include multiple arrays that may be individually addressed. The column control circuit 210 receives a group of N column address signals and one or more various control signals from the system control logic 260, and may generally include circuits such as a column decoder 212, array terminal receivers or driver circuits 214, and read / write circuits 225 and I / O multiplexers.

[0050] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is fully implemented in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 260 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operations. The system control logic 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory structure 202.

[0051] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0052] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, part or all of system control logic 260 may be formed on a different die than the die containing memory structure 202.

[0053] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0054] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR type flash memory) may also be used.

[0055] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the new claimed embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0056] An example of a ReRAM crosspoint memory includes reversible resistive shear elements arranged in a crosspoint array accessed by X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element may be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, resulting in a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0057] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by an external field. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through the pair of write lines, an induced magnetic field is generated. MRAM-based memory embodiments will be discussed in more detail below.

[0058] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of current, voltage, light or other waves. These memory elements within a single selectable memory cell or bit may include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0059] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0060] Figure 2A The components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuits. This can place quite severe limitations on these elements of the peripheral circuits. For example, the need to fit the sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a basic trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuits.

[0061] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs in implementing the different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic component 260 often employ PMOS devices. The processing operations used to manufacture a CMOS die will differ in many respects from processing operations optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, e.g., Figure 4 ) can particularly benefit from specialized processing operations.

[0062] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 are separated into separately formed dies, and then the dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the circuits in the peripheral circuits (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each memory die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, which can now be combined with additional capabilities that may not be easily combined if the peripheral elements are confined to the edge of the same die that houses the memory cell array. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to peripheral elements on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments may use more dies, such as, for example, two memory dies and one control die.

[0063] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile storage device 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory structure die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory structure die 201. In some embodiments, the memory structure die 201 and the control die 211 are bonded together.

[0064] Figure 2B An example of peripheral circuits including control circuits formed in a peripheral circuit or control die 211 is shown, which is coupled to a memory structure 202 formed in a memory structure die 201. Common components are shown in a similar manner to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory structure die 201. In some embodiments, a portion of the circuitry in system control logic 260 is located on memory structure die 201.

[0065] The system control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by conventional processes (e.g., CMOS processes), such that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while removing such circuitry from a die such as the memory structure die 201 may reduce the number of steps required to manufacture such a die, adding such circuitry to a die such as the control die 211 may not require many additional process steps. Since some or all of the control circuitry 260, 210, 220 is implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0066] Figure 2B Column control circuitry 210 including read / write circuitry 225 on control die 211 is shown coupled to memory structure 202 on memory structure die 201 via electrical path 206. For example, electrical path 206 may provide electrical connections between column decoder 212, driver circuitry 214, R / W circuitry 225, and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory structure die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 206 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each electrical path 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory structure die 201 .

[0067] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read / write circuitry 225, sense amplifiers, microcontrollers, microprocessors, and / or other circuits of similar function. The control circuitry may include hardware alone or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuitry.

[0068] For purposes of this document, the term “device” may include, but is not limited to, one or more of the memory system 100 , the memory controller 120 , the memory device 130 , the memory die 200 , the integrated memory component 207 , and / or the control die 211 .

[0069] In some embodiments, there is more than one control die 211 and more than one memory structure die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201. Figure 3A A side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory structure dies) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are more than three memory structure dies 201 and more than three control dies 211. Figure 3A In the embodiment, there are equal numbers of memory structure dies 201 and control dies 211; however, in one embodiment, there are more memory structure dies 201 than control dies 211. For example, one control die 211 can control multiple memory structure dies 201.

[0070] Each control die 211 is attached (e.g., bonded) to at least one of the memory structure dies 201. Some of the bonding pads 282 / 284 are depicted. There may be many more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials may be used as the solid layer 280, but in an embodiment, the material may be a Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0071] The integrated memory components 207 may be stacked, for example, with a stepped offset so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may span the width of each control die 211 (i.e., toward the substrate 271). Figure 3A ) is formed in the page.

[0072] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier layer that prevents metal diffusion. The barrier layer, in turn, may be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0073] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory assembly 207 and memory controller 120.

[0074] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3BThe integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are far more than three memory structure dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory structure die 201. Optionally, the control die 211 can be bonded to two or more memory structure dies 201.

[0075] Some of the bonding pads 282, 284 are depicted. There may be many more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211.

[0076] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0077] As briefly discussed above, the control die 211 and the memory structure die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu to Cu bonding process, the bonding pads are directly bonded to each other without solder or other added materials. In the Cu to Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles that may have settled on the bonding pads and prevented tight bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu to Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu to Cu bonding in this article, the term may also be applicable even when the bonding pads are formed by materials other than copper.

[0078] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size of the bonding pad and the spacing between the bonding pads can be further reduced. The film layer is disposed around the bonding pad. When the dies are put together, the bonding pads can be bonded to each other, and the film layers on the corresponding dies can be bonded to each other. This bonding technique may be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads may be approximately 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. A bonding technique that provides bonding pads with smaller sizes and spacings may be used.

[0079] Some embodiments may include a film on the surface of the dies 201, 211. In the case where such a film is not initially provided, the space between the dies may be underfilled with epoxy or other resins or polymers. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfill step protects the electrical connection between the dies 201, 211 and further secures the dies together. A variety of materials may be used as the underfill material.

[0080] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4 A portion 400 of a block of memory is shown. The depicted structure includes a set of bit lines BL located above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as word line layers) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. In one embodiment, the alternating dielectric and conductive layers are divided into four (or a different number of) regions (e.g., sub-blocks) by isolation regions IR. Figure 4 An isolation region IR is shown separating two sub-blocks. The source line layer SL is located below the alternating dielectric layer and word line layer. The memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that Figure 4 2, the dielectric layers are depicted as being in perspective so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0081] Figure 4A403 and 405. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes may also be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, a block may be divided into sub-blocks, and the sub-blocks may be the unit of erase. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 403 / 405 are shown, but more or less than two planes may be implemented. In some embodiments, memory structure 202 includes four planes. In some embodiments, memory structure 202 includes eight planes. In some embodiments, programming can be performed in parallel in a first selected block in plane 403 and a second selected block in plane 405.

[0082] FIG. 4B to FIG. 4E An example three-dimensional ("3D") NAND structure is depicted, corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of a portion 407 of block 2. Figure 4B It can be seen that Figure 4B The blocks depicted in FIG. extend in the direction of arrow 433. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0083] Figure 4B A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, 452, and 453 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. Vertical column 453 implements NAND string 489. More details of these vertical columns are provided below. Figure 4B The block depicted in FIG. 4 extends in the direction of arrow 433, so the block includes Figure 4BMore vertical columns are depicted in the figure.

[0084] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of a block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each of the circles representing the vertical columns has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, 452, and 453.

[0085] Figure 4B The block depicted in FIG. 4 includes a set of isolation regions 402, 404, 406, 408, 410, and 424 formed of SiO2; however, other dielectric materials may also be used. Isolation regions 402, 404, 406, 408, 410, and 424 are used to divide the top layer of the block into five regions; for example, Figure 4B The top layer depicted in FIG. 1 is divided into regions 420, 430, 440, 450, and 460, all of which are referred to as sub-blocks. In one embodiment, isolation regions 402 and 424 separate a block from an adjacent block. Thus, isolation regions 402 and 424 may extend down to the substrate. In one embodiment, isolation regions 404, 406, 408, and 410 divide only the layer used to implement the select gates so that NAND strings in different sub-blocks can be independently selected. Back to Reference Figure 4 , the IR region may correspond to any of the isolation regions 404, 406, 408, or 410. In one example implementation, the bit lines are connected to only one vertical column / NAND string in each of the regions (sub-blocks) 420, 430, 440, 450, and 460. In this implementation, each block has twenty rows of active columns, and each bit line is connected to five vertical columns / NAND strings in each block. In one embodiment, all five vertical columns / NAND strings connected to a common bit line are connected to the same word line (or the same set of word lines); therefore, the system uses drain-side select lines to select one (or another subset) of the four for which a memory operation (program, verify, read, and / or erase) is to be performed.

[0086] although Figure 4B It is shown that each region has four rows of vertical columns in a block, and five regions have twenty rows of vertical columns, but these exact numbers are example implementations. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0087] Figure 4C A portion of one embodiment of a three-dimensional memory structure 202 is depicted showing the Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 422 and 434 of region 420 (see Figure 4B ). Figure 4C The structure includes three drain side select gate layers (SGD0, SGD1 and SGD2). Figure 4C The structure also includes three drain side select gate layers (SGS0, SGS1 and SGS2). Figure 4C The structure also includes five dummy word line layers DD0, DD1, WLIFDU, WLIDDL, DDS; one hundred and sixty-two word line layers WL0 to WL161, which are used to connect to the data memory cells. The dielectric layer is depicted between the conductive layers just described. Other embodiments may implement more or less than the above for Figure 4C In one embodiment, SGD0, SGD1 and SGD2 are electrically connected together; and SGS0, SGS1 and SGS2 are electrically connected together.

[0088] Figure 4C An embodiment of a stack with two tiers is depicted. The two-tier stack includes an upper tier 421 and a lower tier 423. Two-tier or other multi-tier stacks can be used to form a relatively high stack while maintaining a relatively narrow memory hole width (or diameter). After forming the layers of the lower tier, a memory hole portion is formed in the lower tier. Subsequently, after forming the layers of the upper tier, a memory hole portion is formed in the upper tier, which is aligned with the memory hole portion in the lower tier to form a continuous memory hole from the bottom to the top of the stack. Compared with etching holes from the top to the bottom of the stack instead of separately in each tier, the resulting memory hole is narrower. An interface (IF) region is generated at the location connecting the two tiers. The IF region is typically thicker than other dielectric layers. Due to the presence of the IF region, adjacent word line layers are affected by edge effects, such as programming or erasing difficulties. Therefore, these adjacent word line layers can be set to dummy word lines (WLIFDL, WLIFDU). In some embodiments, the upper tier 421 and the lower tier 423 are erased independently of each other. Therefore, after erasing the upper stack 421, data may be maintained in the lower stack 423. Likewise, after erasing the lower stack 423, data may be maintained in the upper stack 421.

[0089] Vertical columns 432 and 434 are depicted as protruding through the drain side selection layer, source side selection layer, IF layer, dummy word line layer, and word line layer. In one embodiment, each vertical column includes a vertical NAND string. Substrate 457, insulating film 454 on the substrate, and source line SL are located below the vertical columns and layers listed below. The NAND string of vertical column 432 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4C Vertical columns 432 connected to bit lines 414 via connectors 417 are shown.

[0090] One of the isolation regions 402 is depicted adjacent to the stack, which corresponds to Figure 4B 499. The isolation region 402 has a conductive region 499 surrounded by an insulating material 497. The conductive region 499 extends downward to the source line (SL) and provides an operating voltage to the SL. The conductive region 499 may be formed of, for example, tungsten. The insulating material 497 may be formed of, for example, silicon oxide. A short circuit may occur between the word line and the conductive region 499. An example defect 495 is depicted that causes a short circuit between WL159 and the conductive region 499. The conductive region 499 may be referred to herein as a local interconnect (LI). In one embodiment, such a word line to LI short circuit is detected. Defects such as defect 495 may exist when the memory structure is manufactured, or may develop due to normal memory operation.

[0091] Another type of short that can be detected is a word line to memory hole short. Defect 493 can cause a short between WL158 and memory hole 422. In one embodiment, such a word line to memory hole short is detected. Defects such as defect 493 can exist when the memory structure is manufactured, or can develop due to normal memory operation.

[0092] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, and the data word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals such as tungsten, or metal silicide. In some embodiments, different conductive layers may be formed of different materials. A dielectric layer is located between the conductive layers. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0093] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in a NAND string. The word line layers WL0 to W161 are connected to the memory cells (also referred to as data memory cells). The dummy word line layers DD0, DD1, and DDS are connected to the dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from the host, such as data from a host user), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain side selection layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect (or cut off) the channels of the corresponding NAND strings with the bit lines. The source side selection layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect (or cut off) the channels of the corresponding NAND strings with the source lines SL.

[0094] Figure 4D Depicted Figure 4C 445. Included are WL156 to WL160 and dielectric layers DL164 to DL168. Data memory cell transistors 570, 571, 572, 573 and 574 are indicated by dashed lines. Multiple layers may be deposited, for example, along the sidewalls (SW) of the memory hole 422 using atomic layer deposition and / or within each word line layer. For example, each column (e.g., a column formed by the material within the memory hole) may include a blocking oxide / block high-k material 470, a charge trapping layer or film 463 (such as SiN or other nitrides), a tunnel layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layer may include a conductive metal 462 such as tungsten as a control gate. For example, control gates 490, 491, 492, 493 and 494 are provided. In this example, all layers except the metal are provided in the memory hole. In other methods, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes.The pillars may form a pillar-shaped active area (AA) of a NAND string.

[0095] As described above, one type of short that can be detected is a word line to memory hole short. Defect 493 can cause a short between WL158 and one or more of the layers in memory hole 422, such as, for example, charge trapping layer 463 and / or polysilicon body 465. In one embodiment, such a word line to memory hole short is detected.

[0096] When programming the data memory cell transistor, electrons are stored in a portion of the charge trapping layer associated with the data memory cell transistor. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the data memory cell transistor increases in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0097] Each of the memory holes may be filled with a plurality of annular layers (also referred to as memory film layers) including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and the WLL in each of the memory holes. In some cases, the tunnel layer 464 may include a plurality of layers, such as in an oxide-nitride-oxide configuration.

[0098] Figure 4E yes Figures 4 to 4D A schematic diagram of a portion of a memory is depicted in FIG. Figure 4E Physical word lines WL0 to WL161 are shown extending across the entire block. Figure 4E The structure corresponds to FIG. 4A to FIG. 4B 4, 419. Within a block, each bit line is connected to four NAND strings. Drain side select lines SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are used to determine which of the five NAND strings (NS0, NS1, NS2, NS3, NS4) is connected to the associated bit line. Figure 4E s0. The first sub-block corresponds to those vertical NAND strings controlled by SGD-s0. The second sub-block corresponds to those vertical NAND strings controlled by SGD-s1. The third sub-block corresponds to those vertical NAND strings controlled by SGD-s2. The fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s3. The fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s4. There may be more or less than five sub-blocks in a block.

[0099] The source side select line SGS connects / disconnects the NAND strings to / from the common source line. In some embodiments, there is a source side select line for each sub-block (similar to the five SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4). It is also contemplated that the block may be divided into five sub-blocks SB0, SB1, SB2, SB3, and SB4. Sub-block SB0 corresponds to those vertical NAND strings controlled by SGD-s0, sub-block SB1 corresponds to those vertical NAND strings controlled by SGD-s1, sub-block SB2 corresponds to those vertical NAND strings controlled by SGD-s2, sub-block SB3 corresponds to those vertical NAND strings controlled by SGD-s3, and sub-block SB4 corresponds to those vertical NAND strings controlled by SGD-s4.

[0100] Although Figures 4 to 4E An example memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0101] The memory system discussed above can be erased, programmed, and read. Each memory cell can be associated with a memory state according to the write data in the program command. Based on the memory state of the memory cell, the memory cell will remain in the erased state or be programmed to a memory state different from the erased state (programmed memory state).

[0102] For example, in a two-bit per cell memory device (sometimes referred to as a multi-level cell (MLC)), there are four memory states, including an erased state and three programmed memory states, which are referred to as A, B, and C memory states. In a three-bit per cell memory device (sometimes referred to as a three-level cell (TLC)), there are eight memory states, including an erased state and seven programmed memory states, which are referred to as A, B, C, D, E, F, and G memory states. In a four-bit per cell memory device (sometimes referred to as a quad-level cell (QLC)), there are sixteen memory states, including an erased state and fifteen programmed memory states, which are referred to as Er, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 memory states.

[0103] Figure 5ADepicted is an embodiment of a threshold voltage Vth distribution of a four-state memory device in which each memory cell stores two bits of data. A first threshold voltage Vth distribution 500 is provided for an erased (Er state) storage element. Three threshold voltage Vth distributions 502, 504, and 506 represent programming memory states A, B, and C, respectively. A 2-bit code with a lower bit and a higher bit can be used to represent each of the four memory states. In an embodiment, the "Er", "A", "B", and "C" memory states are represented by "11", "01", "00", and "10", respectively.

[0104] Figure 5B An embodiment of the threshold voltage Vth distribution of an eight-state memory device is depicted, in which each memory cell stores three bits of data. A first threshold voltage Vth distribution 510 is provided for the Er state storage element. Seven threshold voltage Vth distributions 512, 514, 516, 518, 520, 522, and 524 represent programming memory states A, B, C, D, E, F, and G, respectively. A 3-bit code with a lower page bit, a middle page bit, and an upper page bit can be used to represent each of the eight memory states. In an embodiment, the "Er", "A", "B", "C", "D", "E", "F", and "G" memory states are represented by "111", "011", "001", "000", "010", "110", "100", and "101", respectively.

[0105] Figure 5C An embodiment of a threshold voltage Vth distribution for a sixteen-state memory device is depicted in which each memory cell stores four bits of data. A first threshold voltage Vth distribution 530 is provided for erasing Er state storage elements. Fifteen threshold voltage Vth distributions 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558, and 560 represent programmed memory states S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, respectively.

[0106] A 4-bit code with a lower page bit, a middle page bit, an upper page bit, and a top page bit may be used to represent each of the sixteen memory states. In an implementation, the S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 memory states are represented by "1111", "1110", "1100", "1101", "1001", "0001", "0101", "0100", "0110", "0010", "0000", "1000", "1010", "1011", "0011", and "0111", respectively.

[0107] In addition to full sequence programming, the techniques described herein may also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In some embodiments, the programming states (e.g., S1 to S15) may overlap, where the controller 120 ( Figure 1 ) relies on error correction to identify the correct data being stored.

[0108] Figure 6 2 is a flow chart describing one embodiment of a process for programming memory cells. For the purposes of this document, the terms program / programming are synonymous with write / writing. In an example embodiment, the memory structure 202 is executed using one or more of the control circuits discussed above (e.g., the system control logic unit 260, the column control circuit 210, the row control circuit 220). Figure 6 In one example embodiment, Figure 6 The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory structure die 201. The process includes multiple cycles, each cycle including a programming phase and a verification phase. Figure 6 process to achieve full sequence programming and other programming schemes including multi-level programming. When implementing multi-level programming, Figure 6 The process is used to implement any / each stage of the multi-level programming process.

[0109] Typically, the programming voltage applied to the control gate (via the selected data word line) during a programming operation is applied as a series of programming pulses (e.g., voltage pulses). Between programming pulses, a set of verify pulses (e.g., voltage pulses) may be used to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6In step 602, the programming voltage signal (Vpgm) is initialized to a starting amplitude (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their expected target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) including memory cells connected to the selected word line that will be prohibited from programming have their channels boosted to prohibit programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die will precharge the channels of the NAND strings including memory cells connected to the selected word line that will be prohibited from programming. In step 606, the NAND strings including memory cells connected to the selected word lines that are to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to perform the boosting scheme. A program inhibit voltage is applied to the bit lines coupling the unselected NAND strings.

[0110] In step 608, a programming voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If the memory cell on the NAND string should be programmed, the corresponding bit line is biased to be at a programming enable voltage. In step 608, a programming pulse is applied to all memory cells connected to the selected word line simultaneously, so that all memory cells connected to the selected word line are programmed at the same time (unless the memory cell is prohibited from programming). That is, the memory cells are programmed at the same time or during overlapping times (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changed at the same time unless the memory cell is prohibited from programming.

[0111] In step 610, program verification is performed and memory cells that have reached their target state are locked out by the control die from further programming. Step 610 includes performing verification of programming by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached an appropriate verification reference voltage. In step 610, the memory cell may be locked out after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state. For example, if the memory cell reaches the verification reference voltage, the memory cell may be locked out.

[0112] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 614, a "PASS" status is reported. Otherwise, if, in step 612, it is determined that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 616.

[0113] In step 616, the number of memory cells that have not yet reached their corresponding target threshold voltage distribution is counted. That is, the number of memory cells that have so far been unable to reach their target state is counted. This counting can be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0114] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can be stopped and a "pass" condition is reported in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0115] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 620 and checks the programming counter PC against a programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failed" condition is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude that is a step size ΔVpgm larger than the previous pulse (e.g., a step size of 0.1 volts to 1.0 volts). After step 626, the process loops back to step 604 and another programming pulse is applied to the selected word line so that execution is performed. Figure 6 Another iteration of the programming process (steps 604 to 626).

[0116] In one embodiment, the memory cells are erased prior to programming, and erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. Figure 5A The state A to C changes to state E, from Figure 5B A to G to state Er, or from Figure 5C States S1 to S15 are changed to state Er.

[0117] Disclosed herein are techniques for detecting growing bad blocks in non-volatile storage systems. In an embodiment, a stress test is performed on a group of memory cells. The stress test can accelerate the stress condition on the memory cells and thereby provide early detection of growing bad blocks. In addition, the number of growing bad blocks that escape detection is kept low. In an embodiment, the stress test involves generating an electric field (e-field) near the junction between the word line and the NAND string.

[0118] Figure 7 700 is a flow chart of one embodiment of a process 700 for detecting a growing bad block in a non-volatile storage system. The process 700 may be performed by one or more control circuits in the storage system 100. The process 700 describes detecting a growing bad block in the context of garbage collection. Garbage collection may include data compression, in which valid data from one or more source blocks is copied to one or more destination blocks. When the amount of valid data drops below a threshold percentage, the source blocks may be identified for data compression. It should be noted that detecting a growing bad block may be performed without garbage collection. In an alternative embodiment, detecting a growing bad block is performed in response to a special command sequence. For example, the memory controller 120 may issue a command sequence to the die (memory die 200, control die 211) to detect a growing bad block.

[0119] Step 702 includes: identifying an available free block to transfer valid data. In an embodiment, the memory controller 120 identifies one or more free blocks in the storage device 130. Step 704 includes: copying valid data from the selected block to the free block. The copying may include data compression. Step 706 includes: erasing the selected block after the valid data has been successfully transferred. At this point, a stress test may be performed on the selected block. However, it is not necessary to perform a stress test each time the selected block is erased. In one embodiment, a stress test is performed once every n program / erase cycles. The value of n may be, for example, 10, 20, or some other value. If the stress test will not be performed (step 708 is no), then in step 712, the selected block is allocated to a free block pool. Alternatively, a stress test may be performed in step 710. The stress test may accelerate stress conditions on the memory cell and thereby provide early detection of growing bad blocks. In addition, the number of growing bad blocks that escape detection is kept low. Further details of the embodiment of the stress test are described below. Step 714 includes: determining whether the block passes the stress test. If the block passes the stress test, the block is allocated to a free block pool in step 712. If the block fails the stress test, the block is deactivated in step 716. The block may be deactivated by adding the block to a list of growing bad blocks. In an embodiment, the memory controller 120 maintains a list of free blocks and growing bad blocks.

[0120] Figure 8 is a schematic diagram of a NAND string depicting voltages applied during an embodiment of a stress test. The NAND string 802 is connected between the bit line 411 and the source line (SL). Only a few of the memory cells on the NAND string 802 are depicted. The top transistor on the NAND string is a select transistor having a control gate connected to the select line SGD. The bottom transistor on the NAND string is a select transistor having a control gate connected to the select line SGS. The select voltage Vsgd is applied to the select line SGD. The select voltage Vsgs is applied to the select line SGS. The programming voltage Vpgm is applied to the selected word line WLn. The stress voltage Vstress is applied to WLn-1. WLn-1 is adjacent to one side of the selected word line. The boost voltage Vpass is applied to other unselected word lines (WL0, WLn+1, WLn+2 are depicted, but there are many other unselected word lines).

[0121] The selected memory cell connected to WLn is being programmed to high Vt. High Vt may correspond to the highest data state of a normal programming algorithm. Figure 5A In the MLC example, the highest data state is the C state; Figure 5B In the MLC example in , the highest data state is the G state; and about Figure 5C In the MLC example in, the highest data state is the S15 state. In an embodiment, the memory cells are programmed one word line at a time from the source line to the bit line. Therefore, the memory cells from WL0 to WLn-1 have been programmed to high Vt. However, the memory cells between WLn and the bit line are still in the erased state.

[0122] These voltages will generate one or more electric fields that can stress the memory cells. An electric field 810 is depicted due to Vpgm being applied to WLn and Vstress being applied to WLn-1. An electric field 820 is depicted due to Vpgm being applied to WLn and Vpass being applied to WLn+1. In an embodiment, Vpgm may be between about 12V and 20V and may increase from one programming / verification cycle to the next programming / verification cycle. In an embodiment, Vpass may be about 8V to 10V. In an embodiment, Vstress may be about 3V to 5V. Note that all Vpgm, Vpass, and Vstress may be different from these examples. However, Vstress has a lower magnitude than Vpass, so that e-field 810 may be stronger than e-field 820. An e-field 830 is also depicted due to Vpgm being applied to the control gate of a selected memory cell at a given memory cell's Vt. The e-field 830 may be stronger than the typical e-field in normal programming. That is, normal programming may program one eighth of the memory cells to Figure 5B Each of the eight data states in . However, programming all memory cells to the highest Vt may result in an e-field 830 that is stronger than in normal programming, at least for later programming / verification cycles. Therefore, the e-field 810 and / or the e-field 830 may be an enhanced e-field that generates stress on a group of memory cells. For example, the e-field 810 and / or the e-field 830 may be greater than the corresponding e-field in normal programming. In addition, the amount of stress generated by the e-field 810 may be controlled by selecting the amplitude of Vstress. If the e-field 810 generates too much stress, some blocks that would not fail without any stress may fail due to stress testing. On the other hand, if the e-field 810 does not generate enough stress, some blocks that would fail without any stress may escape detection using stress testing. Therefore, the amplitude of Vstress may be selected to generate a certain amount of stress, the amount of which will cause most of the blocks that would fail without stress testing to be detected, but without damaging other blocks that would not fail without stress testing.

[0123] Fig. 9 Flow chart of one embodiment of process 900 for performing stress testing on a group of memory cells. In one embodiment, process 900 is performed on a block of memory cells. The block may store user data or system data. The process may be performed in step 708 of process 700. Process 900 may be performed during garbage collection, but need not be part of garbage collection. Step 902 includes: initializing a WL number, which is an identifier of the currently selected word line. In an embodiment, the process sequentially passes through each word line in the block. Therefore, in step 902, the word line may be initialized to WL0. Process 900 will be described with respect to the selected word line being WLn. Step 904 includes: initializing the magnitude of the programming voltage (Vpgm). In one embodiment, Vpgm may be initialized to approximately 12V. However, Vpgm may be initialized to be at a higher or lower voltage.

[0124] Step 906 includes applying a program enable voltage (Venable) to the bit lines associated with the memory cells to receive programming. For example, Venable may be 0V. These bit lines are referred to herein as selected bit lines. Step 908 includes applying a program inhibit voltage (Vinhibit) to the bit lines associated with the memory cells to be inhibited from programming. For example, Vinhibit may be about 2V. In one embodiment, all memory cells will be programmed to high Vt. Therefore, the first programming loop may enable all bit lines.

[0125] Step 910 includes applying Vstress to WLn-1, which is the last word line to be programmed. Step 912 includes applying Vpass to other unselected word lines. Step 914 includes applying Vpgm to the selected word line (WLn). Steps 906, 908, 910, 912, and 914 are performed together.

[0126] Step 916 includes a verify operation. In process 900, all memory cells may be programmed to a high Vt data state. Figure 5B , all memory cells can be programmed to the G state. Therefore, all memory cells can be tested relative to VvG. If a memory cell has a Vt higher than VvG, the memory cell can be inhibited from further programming by applying a program inhibit voltage to its bit line in the next programming cycle. Step 918 is to determine whether the currently selected word line has completed its stress test portion. This determination can be based on whether a sufficient number of memory cells have passed the verification test. For example, if all memory cells except a few memory cells have passed the verification of the high Vt state, the portion of the stress test for the word line can end. If the word line has not completed the stress test, then in step 920, Vpgm is incremented. Then, the process repeats steps 906 to 918. When the stress test for the currently selected word line is completed, in step 922, a determination is made as to whether there is another word line for which memory cells should be programmed. If so, then in step 924, the word line number is incremented. Then, in step 904, the programming voltage Vpgm is initialized to its starting value again. Then, steps 906 to 920 are performed for that word line. When all memory cells in the block have been programmed, the status of the block is verified in step 926. There are a number of ways to verify the status of a block.

[0127] Fig.10 1 is a flow chart of one embodiment of a process 1000 for verifying status after stress testing. Process 1000 may be used in an embodiment of step 926 of process 900. Step 1002 includes: erasing a block after stress testing. Step 1004 includes: programming a dummy pattern into the block. Step 1006 includes: verifying the status of programming the dummy pattern. Figure 6 As an example, the dummy pattern may have an equal number of memory cells programmed to each state from the Er state to the G state (see Figure 5B Step 1008 is to determine whether the condition for programming the dummy mode has passed. The criteria for passing programming may vary. In one embodiment, according to Figure 6614. The dummy pattern is programmed according to the process in step 615, wherein the passed condition is indicated in step 614 and the failed condition is indicated in step 624. If the dummy pattern is programmed to fail, then in step 1010, the block is added to the list of growing bad blocks. If the dummy pattern is programmed to pass, then in step 1012, the data can be read back. In step 1014, the read condition is checked. The criteria for passing the read operation can vary. In one embodiment, the read data is compared with the dummy pattern. The number of bits that are different from the dummy pattern can be counted. If the number exceeds the allowed number, a failure is indicated. In one embodiment, the data is provided to an ECC decoder, which detects errors and is able to correct them. Pass or fail can be based on the result of the decoding operation. For example, pass or fail can be based on a fail bit count (FBC), which is the number of bits in the ECC codeword that have errors. If the read condition is pass (step 1016), then in step 1018, the block is added to the free block pool. If the read condition is fail, the block is added to the list of growing bad blocks. Note that process 1000 is one embodiment of health check after stress testing. However, other techniques are possible for health check.

[0128] In some embodiments, programming performed in a stress test generates one or more e-fields that are enhanced relative to normal programming. Fig.11 is a flow chart of one embodiment of a process 1100 for normal programming. Fig.12 is a flow chart of one embodiment of a process 1200 for programming during stress testing. Processes 1100 and 1200 will be compared to facilitate explanation of embodiments of generating one or more enhanced e-fields during stress testing.

[0129] refer to Fig.11 , step 1102 includes: applying a programming voltage to the selected word line WLn. Step 1104 includes: applying a boost voltage Vpass to the unselected word lines. This includes applying Vpass to WLn-1. Step 1106 includes: verifying whether the memory cell is programmed to at least four Vt distributions. Process 1100 can be used to program memory cells to two bits per cell (four Vt distributions), three bits per cell (eight Vt distributions), four bits per cell (sixteen Vt distributions), etc. In each case, there is a highest Vt distribution. Step 1108 includes: determining whether programming is complete. If complete, process 1100 ends. Step 1110 is to increase the programming voltage if programming has not yet been completed. The process then repeats steps 1102 to 1106 until programming is complete.

[0130] refer to Fig.12, step 1202 includes: applying a programming voltage to the selected word line WLn. Step 1204 includes: applying a voltage lower than Vpass to WLn-1. For example, Vpass may be about 8V and Vstress may be about 3V to 5V. However, Vstress may be greater than 5V or less than 3V. In addition, Vpass may be lower or higher than 8V. Step 1206 includes: applying Vpass to other unselected word lines. This includes applying Vpass to WLn+1. Step 1208 includes: verifying whether the memory cell is programmed to the highest Vt distribution used in step 1106 of process 1100. If process 1100 uses four Vt distributions, step 1208 tests all memory cells for the highest of the four Vt distributions. If process 1100 uses eight Vt distributions, step 1208 tests all memory cells for the highest of the eight Vt distributions. If process 1100 uses sixteen Vt distributions, then step 1208 tests all memory cells for the highest of the sixteen Vt distributions. Step 1210 includes determining whether programming is complete. If complete, process 1200 ends. Step 1212 is to increase the programming voltage if programming is not complete. The process then repeats steps 1202 to 1208 until programming is complete.

[0131] In some embodiments, a fast search for leaky word lines is performed. A leaky word line can be, for example, a word line to memory hole short, a word line to source line short, etc. In an embodiment, a divide and conquer search is used to very quickly locate the exact word line involved in the short.

[0132] Fig.13 is a block level diagram of one embodiment of components used in a fast search for leaky word lines. Fig.13 The components in are circuits. The automatic navigation module 1302 controls the search for the leakage word line. The automatic navigation module 1302 controls which group of word lines are searched for the leakage word line. The word line can be searched at different granularity levels. For example, the entire block of word lines can be searched for the leakage word line, a stack of blocks can be searched for the leakage word line, a group of word lines specifically identified can be searched for the leakage word line, or a specific word line can be tested to see if it is a leakage word line. In one embodiment, the automatic navigation module 1302 performs a divide-and-conquer search for the leakage word line, wherein the word line is repeatedly divided into smaller sub-groups, wherein only the selected smaller sub-groups are tested for short circuits until the leakage word line is located. Examples of divide-and-conquer searches include, but are not limited to, binary searches, tri-search searches, and quad-search searches. However, divide-and-conquer searches are not limited to these examples. As will be described in more detail below, each step of the divide-and-conquer search is not required to divide the word line into the same number of sub-groups. The automatic navigation module 1302 transmits a WL selection signal to the control gate decoder 1304 to control which group of one or more word lines are tested to see if they are leakage word lines.

[0133] In one embodiment, the word line being tested for leakage has a high voltage (e.g., Vpgmu) applied thereto, and the word line not currently being tested has a medium voltage (e.g., Vpass) applied thereto. The first charge pump 1306(1) generates a high voltage (e.g., Vpgmu) and provides the high voltage to the leakage detection circuit 1308. As mentioned above, the magnitude of Vpgm may increase from one programming cycle to the next. The voltage Vpgmu may be the highest programming voltage that would normally be used. However, Vpgmu may even be higher than the highest programming voltage that would normally be used. Furthermore, Vpgmu may be lower than the highest programming voltage that would normally be used. The second charge pump 1306(2) generates a medium voltage (e.g., Vpass) and provides the medium voltage to the control gate decoder 1304. The voltage Vpass is a boost voltage used during programming. The leakage current detection circuit 1308 provides the high voltage (e.g., Vpgmu) to the control gate decoder 1304. The leakage current detection circuit 1308 can detect whether a leakage current is generated due to the application of voltage to the memory structure 202 .

[0134] The high voltage (HV) switch 1310 may contain a high voltage switch (e.g., a transistor) for each word line in the selected block in the memory structure 202. Based on the WL select signal from the autopilot 1302, the control gate decoder 1304 passes a high voltage (e.g., Vpgmu) or a medium voltage (e.g., Vpass) to the appropriate HV switch. The HV switch 1310 passes these voltages to the transmission circuit 1312, which provides the high voltage (e.g., Vpgmu) or the medium voltage (e.g., Vpass) to the appropriate word line in the selected block. The transmission circuit 1312 may contain a transistor that passes the voltage. In some embodiments, a low voltage (e.g., Vss or 0V) is applied to a certain area of ​​the memory structure to set up a condition for possible leakage current. For example, a low voltage (e.g., Vss) may be applied to the source line (through the LI 499) to test for a word line to LI short. As another example, a low voltage (e.g., Vss) may be applied to the bit line and source line to test for word line to memory hole shorts. As mentioned above, the leakage current detection circuit 1308 is capable of detecting whether leakage current is generated due to applying high and low voltages to the memory structure 202.

[0135] The automatic navigation module 1302 communicates with the leakage current detection circuit 1308 to instruct the circuit 1308 to perform a leakage test and receive the status of the leakage detection test. The automatic navigation module 1302 can control the leakage test under the guidance of the state machine 262, and can report the status to the state machine 262. In one embodiment, the automatic navigation module 1302 reports the address of the leakage word line. The automatic navigation module 1302 can be implemented in hardware (e.g., circuit). In one embodiment, the automatic navigation module 1302 can be programmed by software. In one embodiment, the automatic navigation module 1302 is implemented by a microcontroller or microprocessor, which is on or outside the memory chip. The state machine 262 can report the address of the leakage word line to the off-chip circuit. When the leakage test is performed on site, the off-chip circuit can be the memory controller 120, or when the leakage test is performed in the factory, the off-chip circuit can be a test circuit.

[0136] Fig.14 1 is a flow chart of one embodiment of a process 1400 for locating a leaky word line. In other words, the process 1400 looks for word lines involved in short circuits. Short circuits may include, but are not limited to, word line to memory hole short circuits and word line to source line short circuits. The process 1400 may be performed in a BIST. Fig.13 The circuit depicted in may perform process 1400. In one embodiment, a die (e.g., memory die 200, control die 211) performs process 1400 in response to commands received on interface 268. The commands may be provided by memory controller 120, but in some environments, memory controller 120 may not be present. For example, if process 1400 is performed in a test environment, memory controller 120 may not be present.

[0137] Step 1402 includes selecting a group of word lines to be tested for shorts. In one embodiment, a block of NAND strings is selected. A block may have multiple stacks (e.g., see Figure 4C ), but this is not required.

[0138] Step 1404 includes determining whether at least one word line in the group is involved in a short circuit. If no word lines in the group are involved in a short circuit (no short circuit at step 1406), then the testing of the group of word lines can end. Then, in step 1410, the memory system determines whether to test another group of word lines. If so, the process returns to step 1402. However, if a leaky word line is detected (yes at step 1406), then in step 1408, the leaky word line is searched for and located.

[0139] Step 1408 performs an efficient search for leaky word lines. In an embodiment, the system performs a divide-and-conquer search in which groups of word lines are repeatedly divided into smaller subgroups that are tested for word lines involved in the short until the word line involved in the short is located. After the leaky word line is located, the address of the leaky word line can be reported. In one embodiment, the die (e.g., memory die 200, control die 211) reports the address of the leaky word line via, for example, interface 268.

[0140] Fig.15A and Fig. 15B An example is provided to illustrate a divide and conquer search for a leaky word line. In this example, the divide and conquer search has four steps 1502, 1504, 1506, and 1508. In step 1502, the entire block is searched for a leaky word line. Fig.15A The cross-hatching in indicates that there is a leaky word line somewhere in the block. However, at step 1502, it is not known which word line is leaking. In an embodiment, step 1502 applies a test voltage to each word line in the block in a single test. Therefore, step 1502 quickly determines whether there is a leaky word line somewhere in the block.

[0141] In step 1504, the upper stack 421 and the lower stack 423 of the selected block are individually tested for leakage word lines (for examples of the upper stack 421 and the lower stack 423, see Figure 4C ). In this example, the test shows that there is no leaky word line in the upper stack 421. However, there is a leaky word line somewhere in the lower stack 423. Therefore, in a later step, only the word lines in the lower stack 423 are tested.

[0142] In step 1506, multiple subgroups of word lines in the lower stack 423 are tested. Fig.15A , ten subgroups are depicted in the lower stack, with one subgroup 1510 being referenced by an arrow. Each of the ten subgroups in the lower stack 423 may be tested. In this example, only subgroup 1510 has a leaky word line, as indicated by the black shading.

[0143] In step 1508, each individual word line in subgroup 1510 is tested for leakage. In this example, there are four word lines in subgroup 1510. Word line 1512 is shaded black to indicate that it is a leaky word line.

[0144] Fig. 15BA similar divide-and-conquer search for leaky word lines is depicted. However, in this example, there are two leaky word lines 1512, 1522 in the block. Therefore, in this example, the first two steps (1542, 1544) are performed as described above with respect to steps 1502 and 1504. However, in step 1546, two subgroups 1510 and 1520 have leaky word lines. Leaky word line 1512 is found in step 1548, as described above in step 1508. However, leaky word line 1522 is also found in step 1548 by testing all word lines in subgroup 1520.

[0145] therefore, Fig.15A and Fig. 15B Each depicts an example of a divide and conquer search in which a block of word lines is repeatedly divided into smaller subgroups, and the smaller subgroups are tested for leaky word lines until the leaky word line is located. For example, in step 1504, the block is divided into a first subgroup of word lines in the upper stack 421 and a second subgroup of word lines in the lower stack 423. In step 1506, the word lines of the lower stack 423 are divided into 10 subgroups in the lower stack 423. In step 1508, the word lines of subgroup 510 are divided into four subgroups, each containing a single word line. Note that at each step in this divide and conquer search, the subgroups become smaller. In other words, the number of word lines per subgroup becomes smaller with each step. The number of word lines in the subgroups in each step may be different Fig.15A and Fig. 15B In the example above, the total number of steps in a divide-and-conquer search can be more or less than four. Also, note that Fig.15A and Fig. 15B In the example of , a block has 80 word lines. However, a block may have more or less than 80 word lines. However, 80 word lines are selected for ease of illustration. In one embodiment, a block has 160 word lines, and in step 1506 (or 1546), each stack is divided into 20 subgroups.

[0146] Please note that Fig.15AIn the example of step 1502, the term "group" may be used to describe the entire set of word lines in the block in step 1502. However, the term "subgroup" may be used for the unit tested in each of steps 1504, 1506, and 1508, because each unit tested in step 1504, 1506, or 1508 is a "subgroup" of the group in step 1502. The terms "parent-subgroup" and "sub-subgroup" may also be used, where the term "sub-subgroup" refers to the entire set of subgroups formed by one parent-subgroup. For example, there are ten sub-subgroups formed by the parent low-stack subgroup. Therefore, each word line in the parent subgroup is in one of its sub-subgroups. The terms "parent" and "child" may also be used to refer to moving from step 1506 to step 1508. For example, subgroup 1510 may be referred to as a parent-subgroup with four sub-subgroups (in which case each sub-subgroup has a single word line).

[0147] Fig.16 is a flow chart of one embodiment of a process 1600 of repeatedly dividing a group of word lines into smaller subgroups and testing selected smaller subgroups for shorts until a word line involved in a short is located. Process 1600 provides further details of one embodiment of a divide-and-conquer search for leaky word lines that may be used in step 1408 of process 1400. Thus, prior to process 1600, it has been determined that there is at least one leaky word line in a group (e.g., block) of word lines.

[0148] Step 1602 includes dividing a block having a leaky word line into a plurality of subgroups of word lines. Fig.15A and Fig. 15B In the example of , the block is divided into an upper stack 421 and a lower stack 423, but this is only an example. In step 1602, the block may be divided into more than two subgroups.

[0149] In step 1604, one of the subgroups is tested for leaky WLs. Fig.18A Further details of an embodiment of a test for leaky word lines are shown and described. Fig.16 In step 1606, a condition of the subgroup is recorded. The condition may be recorded as a single bit having one value for a leaky word line and another value for a non-leaky word line. The condition may be recorded in a register, a data latch, etc. Step 1608 includes determining whether there is another subgroup to test. In Fig.15A / Fig. 15B In the example of , two stacks can be tested. When all subgroups formed in step 1602 are tested, in step 1610, a determination is made whether a leaky word line has been located. Assuming that a leaky word line has not been located, the subgroup with the leaky word line is divided into multiple subgroups. Fig.15AIn the example of FIG. 1 , the lower stack 423 is divided into ten subgroups. However, the lower stack 423 may be divided into more or less than ten subgroups. The process 1600 then loops through steps 1604 to 1608 to test each of these subgroups for leaky word lines. Fig.15A , step 1612 will be performed again to divide subgroup 1510 into multiple subgroups (in this example, each subgroup has a single word line). Then, process 1600 loops through steps 1604 to 1608 to test each of these word lines. Leaking word line 1512 will be reported in step 1614. Leaking word line 1512 can be efficiently reported by state machine 262 by, for example, transmitting eight bits of information reporting the status of eight word lines. Therefore, a single bit can specify which word line is leaking. In one embodiment, the die (e.g., memory die 200, control die 211) reports the status of eight word lines in each cycle within multiple cycles. Therefore, the pass / fail status of each word line can be reported. In one embodiment, the die only reports the pass / fail status of certain word lines identified in the test command to the die.

[0150] Please note that Fig. 15B In the example of FIG. 1 , step 1612 further divides subgroup 1510 into multiple subgroups to locate leaky word line 1522. In addition, it should be noted that process 1600 is not limited to Fig.15A and Fig. 15B Thus, process 1600 is not limited to Fig.15A Additionally, steps 1602 and 1612 of process 1600 are not limited to dividing the set of word lines having leaky word lines into any particular number of sub-groups for further testing.

[0151] Fig.17A1 is a flow chart of one embodiment of a process 1700 for determining whether a block of word lines contains a leaky word line. The process 1700 may be used in step 1404 in the process 1400. Step 1702 includes: applying a high voltage (e.g., Vpgmu) to all word lines in the block. It should be noted that the programming voltage used during the programming operation may vary according to the programming cycle. The voltage Vpgmu may be the highest voltage of these programming voltages, or even higher than the highest programming voltage typically used during the programming operation. As an example, Vpgmu may be 25V. However, Vpgmu may be higher or lower than 25V. In one embodiment, the automatic navigation module 1302 instructs the control gate decoder 1304 to apply a high voltage to all word lines in the block. Step 1704 includes: applying a low voltage to a region of the memory structure. In one embodiment, a low voltage is applied to the source line to test for a word line to source line short circuit. In one embodiment, a low voltage is applied to the bit line to test for a word line to a memory hole short circuit. In one embodiment, a low voltage is applied to both the bit line and the source line to test for a word line to memory hole short or a word line to memory hole short. Step 1706 includes determining whether a leakage current is detected. In one embodiment, the leakage current detection circuit 1308 monitors for leakage current. In one embodiment, if there is a short between any word line and the source line in the word line of the block, the leakage current may flow. In one embodiment, if there is a short between any word line and the memory hole (e.g., NAND string channel) in the word line of the block, the leakage current may flow.

[0152] Fig. 17B is a table that provides further details of the voltages applied during an embodiment of process 1700. In this example, a high voltage (eg, Vpgmu) is applied to all data word lines, but a lower voltage (eg, Vpass) may be applied to all dummy word lines. Fig. 17B The data word lines in are WL0 to WL80 in the lower stack and WL81 to WL161 in the upper stack. Fig. 17B The dummy word lines in include one or more source side dummy WL (DS), a dummy word line (WLIFDL) adjacent to IF at the top of the lower stack, a dummy word line (WLIFDU) adjacent to IF at the bottom of the upper stack, and one or more drain side dummy WL (DD). A low voltage (e.g., Vss or 0V) is applied to both the bit line (BL) and the source line (SL). The bit line and source line are examples of conductive lines connected to the ends of the NAND string. The voltage Vsgd applied to one or more SGD lines can be a selection voltage that turns on the drain side selection gate. The voltage Vsgs applied to one or more SGS lines can be a selection voltage that turns on the source side selection gate. In one embodiment, as Fig. 17BThe voltages applied as depicted in FIG. 1 will produce a high voltage on the word line and a low voltage on the NAND channel to test for a word line to memory hole short. In one embodiment, as Fig. 17B The voltages applied as depicted in FIG. 8 will produce a high voltage on the word line and a low voltage on the source line to test for a word line to L1 short.

[0153] Fig.18A 1 is a flow chart of one embodiment of a process 1800 for determining whether a subgroup of word lines contains a leaky word line. Process 1800 may be used in step 1408 of process 1400. Process 1800 may be used in step 1604 of process 1600. Step 1802 includes: applying a high voltage (e.g., Vpgmu) to all word lines in the subgroup. This may be the same Vpmgu used in process 1700. In one embodiment, autopilot module 1302 instructs control gate decoder 1304 to apply a high voltage to all word lines in the subgroup. Step 1804 includes: applying a medium voltage (e.g., Vpass) to all word lines in the block that are not in the subgroup. For example, if it is test subgroup 1510 (see Fig.15A ) is being tested, a high voltage is applied only to those word lines in the subgroup 1510, and a medium voltage (e.g., Vpass) is applied to all other word lines in the block. The medium voltage may be between a high voltage (e.g., Vpgmu) and a low voltage (e.g., Vss), but need not be intermediate between the two. For example, Vpass may be approximately 8V, but may be higher or lower. Step 1806 includes: applying a low voltage (e.g., Vss) to an area of ​​the memory structure. In one embodiment, a low voltage is applied to a source line to test for a word line to source line short. In one embodiment, a low voltage is applied to a bit line to test for a word line to memory hole short. Step 1808 includes: determining whether a leakage current is detected. In one embodiment, the leakage current detection circuit 1308 monitors for leakage current. In one embodiment, if there is a short circuit between any word line and a source line in a subgroup, a leakage current may flow. In one embodiment, if there is a short circuit between any word line and a memory hole in a subgroup, a leakage current may flow.

[0154] Fig.18B is a table providing further details of the voltages applied during an embodiment of process 1800 . Fig.18BThe example in has a single word line (WLn) in the upper stack being tested. A high voltage (e.g., Vpgmu) is applied only to WLn. A medium voltage (Vpass) is applied to all other word lines (both data WL and dummy WL). A low voltage (e.g., Vss or 0V) is applied to both the bit line (BL) and the source line (SL). The voltage Vsgd applied to one or more SGD lines can be a selection voltage that turns on the drain side selection gate. The voltage Vsgs applied to one or more SGS lines can be a selection voltage that turns on the source side selection gate. In the case of testing more than one word line, Vpgmu can be applied to those additional word lines being tested. In one embodiment, the word lines being tested are continuous. That is, in one embodiment, the group of word lines being tested are adjacent to each other. For example, if four word lines are tested, these may be WL4, WL5, WL6, and WL7, which will each have Vpgmu applied to them (with Vpass being applied to all other word lines).

[0155] As described herein, testing for leaky word lines may be performed at various levels of granularity. Fig.19 1 is a flow chart of one embodiment of a process 1900 for performing a leaky wordline test in a particular set of wordlines. In some embodiments, the state machine 262 instructs the autopilot module 1302 as to which set of wordlines should be tested for leaky wordlines. However, the instructions as to which set of wordlines to test may be sent off-chip to the die. For example, the memory controller 120 or external test circuitry may transmit a set of instructions to the die (e.g., the memory die 200, the control die 211) requesting that certain wordlines be tested.

[0156] Step 1902 includes receiving a request to test a group of one or more word lines for a leaky word line. Step 1904 is a branch with four branches according to the test scope. One branch is to test all word lines in the block for a leaky word line. In step 1906, a high voltage (e.g., Vpgmu) is applied to all word lines in the block. Step 1906 can be similar to process 1700. In one embodiment, the only condition reported after step 1906 is whether there is a leaky word line somewhere in the block. Therefore, it is not necessary to locate the leaky word line in step 1906.

[0157] The second branch is to test all word lines in one stack of the block for leaky word lines. In step 1908, a high voltage (e.g., Vpgmu) is applied to all word lines in the stack. In step 1910, a medium voltage (e.g., Vpass) is applied to all word lines in the other stacks of the block. In one embodiment, the only condition reported after step 1910 is whether there is a leaky word line somewhere in the stack. Therefore, there is no need to locate the leaky word line in the second branch.

[0158] The third branch is to test all word lines in one WL group of the block for leaky word lines. The WL group can be any convenient size. For example, the WL group can include 4, 8, 12, 16, or some other number of word lines. In step 1912, a high voltage (e.g., Vpgmu) is applied to all word lines in the WL group. In step 1914, a medium voltage (e.g., Vpass) is applied to all other word lines in the block. In one embodiment, the only condition reported after step 1914 is whether there is a leaky word line somewhere in the WL group. Therefore, there is no need to locate the leaky word line in the third branch.

[0159] The fourth branch is to test a single word line in the block for leaky word lines. In step 1916, a high voltage (e.g., Vpgmu) is applied to the single word line. In step 1918, a medium voltage (e.g., Vpass) is applied to all other word lines in the block. In one embodiment, the condition reported after step 1918 is whether the word line is leaky.

[0160] In view of the foregoing, a first embodiment includes a device comprising a memory structure including non-volatile memory cells and word lines associated with the memory cells. The device includes one or more control circuits that communicate with the memory structure. The one or more control circuits are configured to erase groups of the memory cells. The one or more control circuits are configured to: for one or more selected word lines, generate an enhanced e-field between a currently selected word line connected to a memory cell currently being programmed and an adjacent word line connected to a memory cell that has been programmed and adjacent to the currently selected word line, to generate stress in the group of memory cells. The enhanced e-field is greater than the e-field generated in a normal programming operation for programming user data. The one or more control circuits determine whether the group of memory cells passes a test criterion after the stress.

[0161] In a second embodiment, as an advancement of the first embodiment, the one or more control circuits are further configured to disable the group of memory cells in response to the group of memory cells failing the test criterion.

[0162] In a third embodiment, as an advancement of the first embodiment or the second embodiment, the one or more control circuits are further configured to: in response to the group of memory cells passing the test criteria, continue to use the group of memory cells for memory operations.

[0163] In a fourth embodiment, as an advancement of any one of the first to third embodiments, the one or more control circuits are further configured to: program all memory cells connected to the one or more selected word lines to the same threshold voltage while generating the enhanced e-field between the currently selected word line and the already programmed word line to generate further stress in the group of memory cells.

[0164] In a fifth embodiment, as an advancement of any one of the first to fourth embodiments, the one or more control circuits are further configured to: program the memory cells connected to the one or more selected word lines in the normal programming operation, the programming comprising: applying a programming voltage to the currently selected word line of the one or more selected word lines; and applying a boost voltage to unselected word lines while applying the programming voltage to the currently selected word line. The boost voltage is applied to word lines adjacent to the selected word line. The programming voltage applied to the currently selected word line and the boost voltage applied to the word line adjacent to the currently selected word line generate the e-field in the normal programming operation.

[0165] In a sixth embodiment, as an advancement of the fifth embodiment, the one or more control circuits are further configured to: program the memory cells connected to the one or more selected word lines to generate the stress, the programming comprising: applying a programming voltage to the currently selected word line; and applying a stress voltage having a magnitude lower than the boosting voltage to the word line adjacent to the currently selected word line. The programming voltage applied to the currently selected word line and the stress voltage applied to the word line adjacent to the currently selected word line generate the enhanced e-field.

[0166] In a seventh embodiment, as an advancement of any one of the first to sixth embodiments, the one or more control circuits are further configured to: erase the group of memory cells after stressing the memory cells, and determine whether the group of memory cells passes the test criteria based on the results of the erasure.

[0167] In an eighth embodiment, as an advancement of any one of the first to seventh embodiments, the one or more control circuits are further configured to: erase the group of memory cells after stressing the memory cells, program a dummy pattern into the group of memory cells, and determine whether the group of memory cells passes the test criterion based on the results of programming the dummy pattern.

[0168] In a ninth embodiment, as an advancement of any of the first to eighth embodiments, the memory structure is three-dimensional.

[0169] In a tenth embodiment, as an advancement of the ninth embodiment, the memory cells are arranged in the memory structure as NAND strings.

[0170] In an eleventh embodiment, as an advancement of any of the first to tenth embodiments, the group of memory cells comprises a block having NAND strings, and the one or more selected word lines comprises a plurality of word lines associated with the NAND strings.

[0171] In a twelfth embodiment, as an advancement of any one of the first to eleventh embodiments, the one or more control circuits are further configured to: generate stress in the group of memory cells during garbage collection.

[0172] One embodiment includes a method for operating a non-volatile memory device. The method includes erasing a block of NAND memory cells, and applying stress to the block of memory cells. Applying stress to the block of memory cells includes performing the following operations for a plurality of consecutively programmed word lines in the block: i) applying a programming voltage to a currently selected word line in the block; ii) applying a nominal boosting voltage to a group of unselected word lines in the block; iii) applying a stress voltage to unselected word lines adjacent to the selected word line for which memory cells have been programmed, wherein the stress voltage has a lower magnitude than the nominal boosting voltage. The method also includes determining whether the block of memory cells passes a test criterion after applying the stress voltage, and marking the block of memory cells as a growing bad block (GBB) in response to the block of memory cells failing the test criterion.

[0173] One embodiment includes a non-volatile memory system. The system includes a memory structure including a three-dimensional memory structure including a NAND string having memory cells. The system includes means for programming the memory cells in a normal mode, wherein a programming voltage is applied to a selected word line and a boost voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have been programmed. The system includes means for stressing the memory cells, wherein a programming voltage is applied to the selected word line while a stress voltage having a magnitude lower than the boost voltage is applied to the unselected word lines adjacent to the selected word line for which memory cells have been programmed. The system includes means for disabling the memory cells in response to the memory cells failing a stress test criterion after the stress voltage is applied.

[0174] In an embodiment, the means for programming the memory cells in the normal mode includes one or more of the following: memory controller 120, state machine 262, power control 264, column decoder 212, driver circuit 214, R / W circuit 225, row decoder 222, array driver 224, block selector 226, processor, FPGA, ASIC and / or integrated circuit, wherein a programming voltage is applied to a selected word line and a boost voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have been programmed. In an embodiment, the means for programming the memory cells in the normal mode performs Figure 6 A process in which a programming voltage is applied to a selected word line and a boosting voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have already been programmed. In an embodiment, the means for programming these memory cells in a normal mode performs Fig.11 A process 1100 is provided in which a program voltage is applied to a selected word line and a boost voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have already been programmed.

[0175] In an embodiment, the means for stressing the memory cells includes one or more of the following: memory controller 120, state machine 262, power control 264, column decoder 212, driver circuit 214, R / W circuit 225, row decoder 222, array driver 224, block selector 226, processor, FPGA, ASIC and / or integrated circuit, wherein a programming voltage is applied to a selected word line, while a stress voltage having a magnitude lower than the boost voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have been programmed. In an embodiment, the means for stressing the memory cells performs Fig. 9 A process 900 is provided in which a programming voltage is applied to a selected word line, while a stress voltage having a magnitude lower than the boost voltage is applied to the unselected word lines adjacent to the selected word line for which memory cells have been programmed. In an embodiment, the means for stressing the memory cells performs Fig.12 The process 1200 includes applying a program voltage to the selected word line while applying a stress voltage having a magnitude lower than the boosting voltage to the unselected word lines adjacent to the selected word line for which memory cells have been programmed.

[0176] In an embodiment, the means for disabling the memory cells in response to the memory cells failing the stress test criteria after the stress voltage is applied comprises one or more of: a memory controller 120, a state machine 262, a processor, an FPGA, an ASIC, and / or an integrated circuit. In an embodiment, the means for disabling the memory cells in response to the memory cells failing the stress test criteria after the stress voltage is applied performs Fig.10 of process 1000.

[0177] In an embodiment, the garbage collection means for identifying blocks for garbage collection includes one or more of the following: memory controller 120, state machine 262, power control 264, column decoder 212, driver circuit 214, R / W circuit 225, row decoder 222, array driver 224, block selector 226, processor, FPGA, ASIC, and the garbage collection means for identifying blocks for garbage collection performs Figure 7 Process 700.

[0178] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0179] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected such that they are able to communicate electronic signals between them.

[0180] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0181] For the purposes of this document, the use of numerical terms such as a "first," "second," and "third" object without additional context may not imply an ordering of the objects but may be used for identification purposes to identify different objects.

[0182] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0183] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: a memory structure comprising nonvolatile memory cells and word lines associated with the memory cells; and one or more control circuits in communication with the memory structure, wherein the one or more control circuits are configured to: erasing the group of memory cells; generating, for one or more selected word lines, an enhanced e-field between a currently selected word line connected to a memory cell currently being programmed and a neighboring word line adjacent to the currently selected word line connected to a memory cell already programmed to produce stress in the group of memory cells, wherein the enhanced e-field is greater than an e-field generated in a normal programming operation for programming user data; as well as A determination is made as to whether the group of memory cells passes a test criterion after the stress.

2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: The group of memory cells is disabled in response to the group of memory cells failing the test criteria.

3. The apparatus of claim 2, wherein the one or more control circuits are further configured to: Memory operations are continued using the group of memory cells in response to the group of memory cells passing the test criteria.

4. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: All of the memory cells connected to the one or more selected word lines are programmed to the same threshold voltage while generating the enhanced e-field between the currently selected word line and an already programmed word line to generate further stress in the group of memory cells.

5. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: Programming the memory cells connected to the one or more selected word lines in the normal programming operation, the programming comprising: applying a program voltage to the currently selected word line of the one or more selected word lines; as well as A boost voltage is applied to unselected word lines while the programming voltage is applied to the currently selected word line, wherein the boost voltage is applied to the word lines adjacent to the selected word line, wherein the programming voltage applied to the currently selected word line and the boost voltage applied to the word lines adjacent to the currently selected word line generate the e-field in the normal programming operation.

6. The apparatus of claim 5, wherein the one or more control circuits are further configured to: Programming the memory cells connected to the one or more selected word lines to generate the stress, the programming comprising: applying a programming voltage to the currently selected word line; as well as A stress voltage having a magnitude lower than the boosting voltage is applied to the word line adjacent to the currently selected word line, wherein the program voltage applied to the currently selected word line and the stress voltage applied to the word line adjacent to the currently selected word line generate the enhanced e-field.

7. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: erasing the group of memory cells after stressing the memory cells; and A determination is made based on a result of the erasing whether the group of memory cells passes the test criteria.

8. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: erasing the group of memory cells after stressing the memory cells; programming a dummy pattern into the group of memory cells; and A determination is made whether the group of memory cells passes the test criteria based on a result of programming the dummy pattern.

9. The apparatus of claim 1, wherein the memory structure is three-dimensional.

10. The device of claim 9, wherein the memory cells are arranged as NAND strings in the memory structure.

11. The device according to claim 1, wherein: The group of memory cells comprises a block having NAND strings; and The one or more selected word lines include a plurality of word lines associated with the NAND strings.

12. The apparatus of claim 1 , wherein the one or more control circuits are further configured to: Stress is created in the group of memory cells during garbage collection.

13. A method for operating a non-volatile memory device, the method comprising: Erasing blocks of NAND memory cells; Applying stress to the block of memory cells, the applying comprising performing the following operations for a plurality of consecutively programmed word lines in the block: i) applying a program voltage to a currently selected word line in the block; ii) applying a nominal boost voltage to a group of unselected word lines in the block; as well as iii) applying a stress voltage to unselected word lines adjacent to the selected word line for which memory cells have been programmed, wherein the stress voltage has a lower magnitude than the nominal boosting voltage; determining whether the block of memory cells passes a test criterion after applying the stress voltage; as well as The block of memory cells is marked as a growing bad block (GBB) in response to the block of memory cells failing the test criteria.

14. The method of claim 13, wherein applying stress to the block of memory cells further comprises: Programming the block of memory cells in a normal mode to at least four threshold voltage distributions including a highest threshold voltage distribution, the programming comprising: applying a program voltage to the currently selected word line; and The nominal boosting voltage is applied to unselected word lines while the program voltage is applied to the currently selected word line, wherein the nominal boosting voltage is applied to the word lines adjacent to the selected word line for which memory cells have been programmed.

15. The method of claim 14, wherein applying stress to the group of memory cells further comprises: All memory cells in the block are programmed to the highest threshold voltage distribution.

16. A non-volatile storage system, comprising: a memory structure comprising a three-dimensional memory structure including a NAND string having memory cells; means for programming the memory cells in a normal mode, wherein a program voltage is applied to a selected word line and a boost voltage is applied to unselected word lines adjacent to the selected word line for which memory cells have been programmed; means for stressing the memory cell, wherein a programming voltage is applied to a selected word line, while a stress voltage having a magnitude lower than the boosting voltage is applied to the unselected word lines adjacent to the selected word line for which memory has been programmed; and Means for disabling the memory cell in response to the memory cell failing a stress test criterion after applying the stress voltage.

17. The non-volatile storage system according to claim 16, wherein: The means for programming the memory cell in the normal mode is further for programming the memory cell to at least four threshold voltage distributions including a highest threshold voltage distribution; and The means for stressing the memory cells is further for programming all of the memory cells to a highest threshold voltage distribution.

18. The nonvolatile storage system of claim 16, wherein the means for stressing the memory cells applies the boosting voltage to unselected word lines adjacent to the selected word line for which memory cells have not been programmed, while applying the programming voltage to the selected word line.

19. The non-volatile storage system of claim 16, wherein the NAND strings are arranged in erase blocks, and the non-volatile storage system further comprises: Garbage collection means for identifying blocks for garbage collection, wherein the memory cells that are stressed include those memory cells in the blocks identified for garbage collection.

20. The non-volatile storage system of claim 19, wherein the memory cell is stressed after a predetermined number of erasures.

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