Semiconductor device package with coupled substrate

Abstract

A semiconductor device package includes a first substrate and a receiving port electrically connected to the first substrate. A first semiconductor die is electrically connected to and directly mounted on the first substrate. A second substrate is electrically connected to the first substrate via a corresponding receiving port and is oriented substantially perpendicular to the first substrate. A second semiconductor die is electrically connected to and directly mounted on the second substrate. A housing substantially encloses each of the above components. The receiving port allows an additional substrate carrying a semiconductor memory die to be connected to the first substrate, thereby increasing the total storage capacity of the semiconductor device package while conforming to a predefined form factor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 361,118, entitled “Semiconductor Device Package with Coupled Substrates,” filed in the U.S. Patent and Trademark Office on July 28, 2023, and is hereby incorporated by reference in its entirety for all purposes, which non-provisional application claims priority to U.S. Provisional Application No. 63 / 387,328, filed on December 14, 2022. Background Art

[0003] The present invention relates generally to semiconductor devices, and more particularly to semiconductor device packages having one or more substrates directly coupled to a main substrate to increase storage capacity within a predetermined form factor.

[0004] Semiconductor device packages typically include multiple semiconductor dies and other electrical components coupled to a substrate such as a printed circuit board (PCB), which is enclosed in an external housing structure. For solid-state drive type (SSD) packages, there are typically one or more storage devices (e.g., NAND dies) electrically connected to the PCB, and the amount of storage provided by each storage device is at least a portion of the total storage capacity of the semiconductor device package. The size of the semiconductor device package is typically constrained by an industry standard form factor based on the intended use of the semiconductor device package. Some such form factors may be enterprise and data center standard form factors (EDSFF), such as the E1.S standard form factor, which each define the length, width, and thickness of the package. The E1.S standard form factor typically includes the following: E1.S bare PCB 5.9mm, E1.S with heat sink 8mm, E1.S with symmetrical housing 9.5mm, E1.S with asymmetric housing 15mm, and E1.S with asymmetric housing 25mm.

[0005] Each of the above-mentioned form factors has different advantages and disadvantages. For example, within a single server rack (e.g., a storage server rack), the number of bare PCB 5.9mm and symmetrical housing 9.5mm form factor semiconductor device packages that can be included is greater than the number of asymmetrical housing 15mm and / or 25mm form factor semiconductor device packages that can be included. Therefore, by including conventional 5.9mm and 9.5mm form factor semiconductor device packages, the total storage capacity provided by a single storage server rack can be increased when compared to including conventional 15mm and 25mm form factor packages. However, when compared to 5.9mm and 9.5mm packages, 15mm and 25mm form factor packages generally provide better power and performance per package. For example, the cooling requirements (e.g., via airflow) of 15mm and 25mm packages are less than the cooling requirements of 5.9mm and 9.5mm packages. Therefore, there is a need to increase the total amount of storage capacity provided by E1.S 15 mm and 25 mm form factor semiconductor device packages while conforming to the form factor dimensions and maintaining its power and performance benefits. Summary of the invention

[0006] In one embodiment, there is a semiconductor device package, which includes: a first substrate having a top flat surface and a bottom flat surface; one or more receiving ports mounted on the top flat surface and electrically connected to the first substrate; one or more first semiconductor dies electrically connected to the first substrate and directly mounted on the first substrate; a second substrate having a top flat surface and a bottom flat surface, the second substrate electrically connected to corresponding receiving ports of the one or more receiving ports, the top flat surface of the second substrate being oriented to be approximately perpendicular to the top flat surface of the first substrate; one or more second semiconductor dies electrically connected to the second substrate and directly mounted on the second substrate; and a housing that substantially encapsulates each of the first substrate, the second substrate, the one or more receiving ports, the one or more first semiconductor dies, and the one or more second semiconductor dies.

[0007] In some embodiments, the housing has a width of about 33.75 mm, a length of about 118.75 mm, and a height of about 25.00 mm. In some embodiments, the one or more first semiconductor dies and the one or more second semiconductor dies include a NAND die. In some embodiments, the second semiconductor die is at least twice the size of the first semiconductor die. In some embodiments, the one or more receiving ports include a first receiving port and a second receiving port, each of which is electrically connected to the first substrate and spaced apart from each other. In some embodiments, the semiconductor device package further includes a third substrate, wherein the second substrate is electrically connected to the first receiving port, and the third substrate is electrically connected to the second receiving port.

[0008] In some embodiments, the one or more second semiconductor dies are electrically connected to the second substrate and mounted directly on the second substrate, and the semiconductor device package further includes one or more third semiconductor dies electrically connected to the third substrate and mounted directly on the third substrate. In some embodiments, the housing substantially encapsulates each of the first substrate, the second substrate, and the third substrate and each of the one or more first semiconductor dies, the second semiconductor dies, and the third semiconductor dies, and the housing includes a bottom surface and a top surface, the first substrate is positioned between the bottom surface and the top surface of the housing, the first hollow protrusion extends upward from the top surface of the housing near the first receiving port, the second substrate and the one or more second semiconductor dies are at least partially positioned within the first hollow protrusion, and the second hollow protrusion extends upward from the top surface of the housing near the second receiving port, and the third substrate and the one or more third semiconductor dies are at least partially positioned within the second hollow protrusion.

[0009] In some embodiments, the semiconductor device package also includes a heat sink mounted on the top surface of the housing and including a plurality of fins, each of the plurality of fins being positioned between the first hollow protrusion and the second hollow protrusion of the housing. In some embodiments, the heat sink is integrally formed with the housing. In some embodiments, the semiconductor device package also includes a thermally conductive layer, each of the one or more thermally conductive layers being directly mounted on the surface of the corresponding semiconductor die in the one or more first semiconductor dies, the second semiconductor die, and the third semiconductor die. Each thermally conductive layer may extend between the surface of the corresponding semiconductor die and the adjacent internal surface of the housing. In some embodiments, each of the plurality of fins extends upward from the top surface of the housing and is substantially perpendicular to the top surface of the housing. In some embodiments, the second substrate and the third substrate are detachably coupled to the first substrate through one or more receiving ports.

[0010] In some embodiments, the first hollow protrusion and the second hollow protrusion each have a width greater than the width of a single fin in the plurality of fins. In some embodiments, the semiconductor device package further comprises one or more first fasteners connected to the second substrate and the first hollow protrusion, the one or more first fasteners being connected to the second substrate opposite to the position at which the second substrate is electrically connected to the first receiving port; and one or more second fasteners connected to the third substrate and the second hollow protrusion, the one or more second fasteners being connected to the third substrate opposite to the position at which the third substrate is electrically connected to the second receiving port. In some embodiments, the one or more first fasteners and the one or more second fasteners comprise a biasing element configured to maintain the orientation of the second substrate and the third substrate relative to the first substrate. In some embodiments, the one or more receiving ports are each a through-hole mount electrically connected to the first substrate.

[0011] In another embodiment, there is a semiconductor device package, which includes: a first substrate device, which is used to provide electrical connectivity with one or more electrical components coupled to the first substrate device; one or more receiving devices, which are electrically connected to the first substrate device and used to provide electrical connectivity between the first substrate device and one or more other substrate devices; one or more first storage devices, each of which is used to store a certain amount of charge, each of the one or more first storage devices is electrically connected to the first substrate device through a corresponding electrical connection device; a second substrate device, which is used to electrically connect with one or more electrical components coupled to the second substrate device, the second substrate device is electrically connected to the one or more receiving devices and is oriented to be approximately perpendicular to the first substrate device; one or more second storage devices, each of which is used to store a certain amount of charge, each of the one or more second storage devices is electrically connected to the second substrate device through a corresponding electrical connection device; and a shell device, which is used to substantially enclose each of the first substrate device, the second substrate device, the one or more receiving devices, the one or more first storage devices and the one or more second storage devices.

[0012] In some embodiments, the semiconductor device package also includes: a third substrate device, which is used to provide electrical connectivity with one or more electrical components coupled to the third substrate device, the third substrate device is electrically connected to one or more receiving devices and is oriented to be approximately perpendicular to the first substrate device and separated from the second substrate device; and one or more third storage devices, each of which is used to store a certain amount of charge, each of the one or more third storage devices is electrically connected to the third substrate device via a corresponding electrical connection device.

[0013] In another embodiment, there is a semiconductor device package, which includes: a first substrate having a top flat surface and a bottom flat surface approximately parallel to the top flat surface; a first receiving port electrically connected to the first substrate; a second receiving port spaced apart from the first receiving port and electrically connected to the first substrate; one or more first NAND dies electrically connected to the first substrate and directly mounted on the first substrate; a second substrate having a top flat surface and a bottom flat surface, the second substrate electrically connected to the first receiving port so that the top flat surface of the second substrate is approximately perpendicular to the top flat surface of the first substrate; one or more second NAND dies electrically connected to the second substrate and directly mounted on the second substrate; a third substrate having a top flat surface and a bottom flat surface, the third substrate electrically connected to the second receiving port so that the top flat surface of the third substrate is approximately perpendicular to the top flat surface of the first substrate; one or more third NAND dies electrically connected to the third substrate and directly mounted on the third substrate; and a housing substantially encapsulating each of the first, second and third substrates and each of the one or more first, second and third NAND dies.

[0014] The housing includes a bottom surface and a top surface, a first substrate is positioned between the bottom surface and the top surface of the housing, a first hollow protrusion extends upward from the top surface of the housing near the first receiving port, a second substrate is at least partially positioned in the first hollow protrusion, and a second hollow protrusion extends upward from the top surface of the housing near the second receiving port, and a third substrate is at least partially positioned in the second hollow protrusion. A heat sink is mounted on the top surface of the housing and includes a plurality of fins, each of the plurality of fins being positioned between the first hollow protrusion and the second hollow protrusion of the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] When read in conjunction with the accompanying drawings, the above-described content of the invention and the following specific embodiments will be better understood. For the purpose of illustrating the present disclosure, currently preferred embodiments are shown in the accompanying drawings, wherein similar reference numerals indicate similar elements throughout the text. However, it should be noted that various aspects of the present disclosure may be embodied in different forms and therefore should not be construed as being limited to the illustrated embodiments set forth herein. The elements shown in the accompanying drawings may not necessarily be drawn to scale, but may have been exaggerated to highlight the important features of the subject matter therein. In addition, the drawings may be simplified by omitting elements that are not necessarily required for understanding the disclosed embodiments.

[0016] In the attached picture:

[0017] Figure 1 is a cross-sectional view of a semiconductor device package according to an exemplary embodiment of the present disclosure;

[0018] Figure 2 yes Figure 1 A perspective view of a first substrate, a second substrate, and a third substrate of a semiconductor device package;

[0019] Figure 3 is of the dimensions shown Figure 1 a cross-sectional view of a semiconductor device package;

[0020] Figure 4 yes Figure 1 A perspective view of a semiconductor device package;

[0021] Figure 5A yes Figure 1 a top plan view of a first substrate of a semiconductor device package; and

[0022] Figure 5B yes Figure 1 A top elevation view of a second substrate of a semiconductor device package. DETAILED DESCRIPTION

[0023] The present subject matter will now be described more fully below with reference to the accompanying drawings, in which representative embodiments are shown. However, the present subject matter may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided for description and to enable those skilled in the art.

[0024] See also Figures 1 to 5B , a semiconductor device package, generally designated 100, according to an exemplary embodiment of the present disclosure is shown. Semiconductor device package 100 (or simply package 100) can be configured to provide increased storage capacity while following the same industry standard form factor when compared to conventional semiconductor device packages that follow one or more industry standard form factors. For simplicity, semiconductor device package 100 is described herein with reference to the E1.S25mm industry standard form factor dimensions. However, it should be understood that the inventive concepts discussed herein can be applied to other industry standard form factors to provide increased total storage capacity.

[0025] See also Figure 1 to Figure 2, the semiconductor device package 100 may include a first substrate 102, one or more receiving ports 104, one or more first semiconductor dies 106, a second substrate 108, a third substrate 110, one or more second semiconductor dies 112, one or more third semiconductor dies 113, and a housing 114 that substantially encapsulates each. In some embodiments, one or more of the first substrate 102, the second substrate 108, and the third substrate 110 are used to provide a storage device, a processing device, and / or a control device. For example, the first substrate 102 may be used to provide a storage device, a processing device, and a control device, and the second substrate 108 and the third substrate 110 may be used to provide an additional storage device. The first substrate 102 may have a top planar surface 102t and a bottom planar surface 102b substantially parallel to the top planar surface 102t. In some embodiments, the one or more first semiconductor dies 106 may be a first group of semiconductor dies 106. Similarly, the one or more second semiconductor dies 112 and the one or more third semiconductor dies 113 may be a second group of semiconductor dies 112 and a third group of semiconductor dies 113, respectively. Each of the first group of semiconductor dies 106, the second group of semiconductor dies 112, and the third group of semiconductor dies 113 may refer to semiconductor dies mounted on the corresponding first substrate 102, the second substrate 108, and the third substrate 110. In some embodiments, one or more groups of semiconductor dies 106, 112, 113 are included in a NAND package mounted on a surface of the corresponding substrate 102, 108, 110.

[0026] The first substrate 102 may include a mechanical base support for connecting to the electrical components thereon and an electrical interface (or circuit) providing access to the electrical components. In some embodiments, the first substrate 102 may include a circuit (not shown) having a plurality of metal layers and / or traces disposed within the first substrate 102, including one or more layers for routing signals (such as but not limited to input / output signals, power signals, and ground signals) using conductive (e.g., copper) traces. In some embodiments, the first substrate 102 includes, for example, up to sixteen layers for routing signals. In some embodiments, the first substrate 102 is a first printed circuit board (PCB). In some embodiments, the first substrate is a high density interconnect (HDI) PCB. In some embodiments, the second substrate 108 and / or the third substrate 110 are substantially the same as the first substrate 102. In some embodiments, the second substrate 108 and the third substrate 110 have a thickness less than the first substrate 102. For example, the second substrate 108 and the third substrate 110 may each have a thickness of about half the thickness of the first substrate 102. In some embodiments, the second substrate 108 and / or the third substrate 110 has a thickness less than or equal to about 1 mm.

[0027] In some embodiments, one or more receiving ports 104 include a first receiving port 104a and a second receiving port 104b, which are configured to electrically connect the second substrate 108 and the third substrate 110 to the first substrate 102, respectively. The first receiving port 104a and / or the second receiving port 104b may be electrically connected to the first substrate 102 and mounted directly on the first substrate. For example, the first receiving port 104a and the second receiving port 104b may be electrically connected to the top flat surface 102t of the first substrate 102 and mounted directly on the top flat surface. In some embodiments, the first substrate 102 includes one or more surface mount technology (SMT) or through hole (TH) sockets to which the first receiving port 104a and the second receiving port 104b are electrically connected. In some embodiments, there may be one or more through hole (TH) mounting supports connected to the first receiving port 104a and the second receiving port 104b, respectively. For example, the receiving ports 104a, 104b may be TH mounting members electrically connected to the first substrate 102. In some embodiments, the first substrate 102 includes two on-board SMT sockets with TH mounting supports to route electrical signals to and from the first substrate 102 (e.g., electrical signals from and to the second and third substrates 108 and 110). In some embodiments, each of the first receiving port 104a and the second receiving port 104b includes a female electrical connector and a mechanical connector configured to receive corresponding male connectors of the second and third substrates 108 and 110, respectively. The receiving ports 104a, 104b are configured to allow electrical signals to be transmitted between components on the first substrate 102 (e.g., the first semiconductor die 106) and components of the second and third substrates 108 and 110 (e.g., the second and third semiconductor dies 112 and 113).

[0028] In some embodiments, the second substrate 108 and the third substrate 110 are oriented approximately perpendicular to the first substrate 102. The second substrate 108 may include a top planar surface 108t and a bottom planar surface 108b, which in some embodiments may be oriented approximately perpendicular to the top planar surface 102t of the first substrate 102. For example, one or more of the top planar surface 108t and the bottom planar surface 108b may extend along a plane that is approximately perpendicular to the plane along which the top planar surface 102t of the first substrate extends. Similarly, the third substrate 110 may include a top planar surface 110t and a bottom planar surface 110b, at least one of which may be oriented approximately perpendicular to the top planar surface 102t of the first substrate 102. In some embodiments, the second substrate 108 and / or the third substrate 110 are removably coupled to the first substrate 102 through the corresponding receiving ports 104a, 104b.

[0029] The housing 114 may include one or more inner surfaces defining an inner cavity or recess of the housing, in which at least a portion of the first substrate 102, one or more receiving ports 104a or 104b, one or more first semiconductor dies 106, the second substrate 108, the third substrate 110, and one or more second semiconductor dies 112 and the third semiconductor die 113 may be positioned. Thus, the housing 114 may be configured to protect the above-mentioned components from external forces and / or prevent debris from entering the housing 114. In some embodiments, the housing 114 is composed of one or more of a polymer, a metal, a metal alloy, a plastic, and / or a composite material. The housing 114 may substantially encapsulate the first substrate 102, the second substrate 108, and the third substrate 110, while allowing the first substrate 102 to be electrically connected to one or more external devices. For example, a portion of the first substrate 102 configured to be electrically connected to an external device may partially extend out of the housing 114. The housing 114 may substantially encapsulate each of the first substrate 102 , the second substrate 108 , the third substrate 110 , the receiving ports 104 a , 104 b , the one or more first semiconductor dies 106 , and the one or more second semiconductor dies 112 and / or third semiconductor dies 113 .

[0030] In some embodiments, the housing 114 includes a bottom surface 114b and a top surface 114t, which is substantially parallel to and spaced apart from the top surface 114t. In some embodiments, the bottom surface 114b and the top surface 114t at least partially define a first inner chamber, in which one or more components of the semiconductor device package 100 can be positioned. The first substrate 102 can be positioned in the housing 114, at least partially between the top surface 114t and the bottom surface 114b. In some embodiments, one or more semiconductor dies in the first semiconductor die 106 are positioned between the top surface 114t and the bottom surface 114b of the housing 114. The housing 114 can be configured to encapsulate the second substrate 108 and the third substrate 110 when the second substrate 108 and the third substrate 110 are electrically connected to the first substrate 102 (e.g., when the second substrate 108 and the third substrate 110 are connected to the receiving ports 104a, 104b). The housing 114 may include a first protrusion 116a and / or a second protrusion 116b extending upward from a top surface 114t of the housing 114 and configured to enclose the second substrate 108 and the third substrate 110. The first protrusion 116a may be positioned near the first receiving port 104a, and the second protrusion 116b may be positioned near the second receiving port 104b. In some embodiments, the first protrusion 116a and / or the second protrusion 116b extend substantially vertically from the top surface 114t of the housing 114. For example, the side surfaces of the first protrusion 116a and / or the second protrusion 116b may be oriented on respective planes substantially perpendicular to the plane in which the top surface 114t of the housing 114 is oriented.

[0031] By including a second substrate 108 and / or a third substrate 110 and orienting the second substrate 108 and / or the third substrate 110 to be approximately perpendicular to the first substrate 102, the semiconductor device package 100 of the present disclosure can increase the amount of available space to which memory dies can be connected when compared to a conventional semiconductor device package of approximately the same size. For example, in a conventional semiconductor device package conforming to an E1.S25mm form factor, a single substrate positioned within a housing in substantially the same manner as the first substrate 102 is provided. All dies and other semiconductor dies are electrically connected and mounted to a single substrate of a conventional semiconductor device package. The number and / or placement of memory dies mounted thereon is based on maximizing the number of memory dies that can be directly mounted on a single substrate together with other necessary dies and / or electrical components. For example, in a conventional substrate included in an E1.S25mm form factor semiconductor device package, the number of memory dies mounted thereon can be up to about eight.

[0032] However, in the semiconductor device package 100 of the present invention, the number of memory dies mounted on the first substrate 102 may be less than the number conventionally included (e.g., less than eight), so that the receiving ports 104a, 104b may be mounted on the first substrate 102. In this way, the second substrate 108 and / or the third substrate 110 may be electrically connected to the first substrate 102 and positioned within the protrusions 116a, 116b of the housing 114. Therefore, the second substrate 108 and / or the third substrate 110 may provide additional mounting surfaces (e.g., top surfaces 108t, 110t and bottom surfaces 108b, 110b) on which memory dies (e.g., the second semiconductor die 112 and the third semiconductor die 113) may be mounted. Therefore, in some embodiments, even though the number of memory dies on the first substrate 102 may be less than the number of memory dies that may be positioned on a single substrate of certain conventional devices, the total number of memory dies in the semiconductor device package of the present invention may be larger due to the additional memory devices on the second substrate 108 and the third substrate 110. In addition to the above examples, there may be eight memory dies mounted to each of the second substrate 108 and the third substrate 110 and four memory dies mounted to the first substrate 102. Thus, when compared to a conventional semiconductor device package of the same form factor (e.g., E1.S25mm), the total storage capacity and / or number of memory dies is increased by at least about 150% (e.g., eight dies in a conventional package versus twenty dies in package 100). Where asymmetric die loading is achieved, the total storage capacity may be increased by at least about 350% when compared to a conventional semiconductor device package of the same form factor. In this way, the semiconductor device package 100 of the present disclosure may provide increased storage capacity when compared to a conventional semiconductor device package of the same or similar industry standard form factor.

[0033] In some embodiments, the semiconductor device package 100 includes a heat sink 118 mounted on the top surface 114t of the housing 114 and configured to dissipate heat generated by the electrical components of the semiconductor device 100 during use. The heat sink 118 may be a finned heat sink including a plurality of fins. Figure 1In the embodiment of the present invention, the heat sink 118 includes four fins positioned between the first protrusion 116a and the second protrusion 116b of the housing 114. In some embodiments, the fins of the heat sink 118 may be substantially parallel to the first protrusion 116a and the second protrusion 116b. In addition, in some embodiments, the fins of the heat sink 118 may have a height substantially the same as the first protrusion 116a and the second protrusion 116b. In some embodiments, the heat sink 118 may include any number of fins. For example, the heat sink 118 may include one fin, two fins, three fins, four fins, five fins, six fins, seven fins, eight fins or more than eight fins. In some embodiments, each of the first protrusion 116a and the second protrusion 116b may serve as an additional fin to help dissipate heat together with the heat sink 118. In some embodiments, although the first protrusion and the second protrusion each have an inner cavity for holding the second substrate 108 and the third substrate 110, the fins of the heat sink 118 may be solid. In some embodiments, each fin of the heat sink 118 is oriented substantially perpendicular to the top surface 114t of the housing 114. In some embodiments, the heat sink 118 is integrally formed with the housing 114. For example, each fin included in the heat sink 118 may be integrally formed with the housing 114. In some embodiments, the first protrusion 116a and the second protrusion 116b are integrally formed with the top surface 114t of the housing 114.

[0034] In some embodiments, the first protrusion 116a and / or the second protrusion 116b are hollow, so that one or more of the second substrate 108 and the third substrate 110 and the components connected thereto can be at least partially positioned within the corresponding first protrusion 116a and the second protrusion 116b. For example, the first substrate 108 can be at least partially positioned within the hollow recess defined by the first protrusion 116a, and the second substrate 110 can be at least partially positioned within the hollow recess defined by the second protrusion 116b.

[0035] One or more first semiconductor dies 106, second semiconductor die 112, and / or third semiconductor die 113 may be any type of semiconductor die, such as, but not limited to, a memory die (e.g., a NAND die), an application specific integrated circuit (ASIC) die, a controller die, or other integrated circuit (IC) die. For example, in some embodiments, there is at least one controller and one or more NAND dies directly coupled to the first substrate 102. In some embodiments, the plurality of first semiconductor dies 106 may include different types of dies. For example, the semiconductor die may include a plurality of memory dies and one or more control dies electrically connected to the first substrate 102. In some embodiments, the one or more first semiconductor dies 106 are NAND packages including a plurality of memory dies, which may be electrically connected to the package via any conventional method known to those skilled in the art (e.g., wire bonding, flip chip mounting). The NAND package may be electrically connected to the first substrate 102 via welding. In some embodiments, the one or more second semiconductor dies 112 and / or third semiconductor die 113 are NAND dies.

[0036] Still see Figure 1 to Figure 2 , in some embodiments, one or more of the first semiconductor dies 106 are directly mounted on the first substrate 102. At least one of the first semiconductor dies 106 may be electrically connected to the first substrate 102 and mounted on the top planar surface 102t. In some embodiments, at least one of the first semiconductor dies 106 is electrically connected to the first substrate 102 and mounted on the bottom planar surface 102b. In some embodiments, at least one of the first semiconductor dies 106 is mounted on the top planar surface 102t, and at least one or more other first semiconductor dies 106 are mounted on the bottom planar surface 102b. In some embodiments, one or more of the first semiconductor dies 106 are positioned on the first substrate 102 between the first receiving port 104a and the second receiving port 104b. In some embodiments, there are between one and six first semiconductor dies 106 (e.g., memory dies, NAND dies) electrically connected to the first substrate 102 and mounted directly on the first substrate. In some embodiments, there are four first semiconductor dies 106 (e.g., memory dies, NAND dies) electrically connected to and mounted directly on the first substrate 102. There may be other electrical components such as, but not limited to, ASIC dies, controllers, dynamic random access memory (DRAM), capacitors, and / or other control circuits electrically connected to the first substrate 102. The specific number and / or type of other electrical components connected thereto may vary based on the architecture of the package 100.

[0037] In some embodiments, one or more second semiconductor dies 112 are directly mounted on the second substrate 108. At least one of the second semiconductor dies 112 may be electrically connected to the second substrate 108 and directly mounted on the top planar surface 108t and / or the bottom surface 108b. In some embodiments, there are one or more second semiconductor dies 112 mounted on the top planar surface 108t and the bottom planar surface 108b of the second substrate 108. For example, there may be four second semiconductor dies 112a-112d mounted on the top planar surface 108t, and there may be four second semiconductor dies 112 mounted on the bottom planar surface 108b. In some embodiments, the number of second semiconductor dies 112 included in the semiconductor device package 100 is greater than the number of first semiconductor dies 106 included. In some embodiments, the second semiconductor die 112 is at least twice the first semiconductor die 106. For example, there may be four first semiconductor dies 106 (e.g., four first NAND dies) mounted on the first substrate 102 and eight second semiconductor dies 112 (e.g., eight second NAND dies) mounted on the second substrate 108. In some embodiments, there are at least four second semiconductor dies 112 mounted to and electrically connected to the second substrate 108.

[0038] In some embodiments, one or more third semiconductor dies 113 are mounted directly on the third substrate 110. The number and / or mounting position of the third semiconductor dies 113 relative to the third substrate 110 may be substantially the same as described in the previous paragraph with reference to the second semiconductor die 112 and the second substrate 108, and will not be described again for the sake of brevity. The third semiconductor die 113 may be at least twice the number of the first semiconductor die 106. For example, there may be four first semiconductor dies 106 (e.g., four first NAND dies) mounted on the first substrate 102 and eight third semiconductor dies 113 (e.g., eight third NAND dies) mounted on the third substrate 108. For example, there may be at least four third semiconductor dies 113a-113d mounted on the top surface 110t of the third substrate 110 and four third semiconductor dies 113 mounted on the bottom surface 110b. In some embodiments, the number of second semiconductor dies 112 and third semiconductor dies 113 mounted to the respective second substrate 108 and the third substrate 110 is substantially the same. In some embodiments, the second semiconductor die 112 is symmetrically arranged on the second substrate 108 with respect to the top planar surface 108t and the bottom planar surface 108b. The third semiconductor die 113 can be symmetrically arranged on the third substrate 108 with respect to the top planar surface 110t and the bottom planar surface 110b.

[0039] In some embodiments, there may be one or more thermally conductive layers 120 mounted on the surface of one or more of the first semiconductor die 106, the second semiconductor die 112, and / or the third semiconductor die 113. The thermally conductive layer 120 may be composed of a thermally conductive material having a thermal conductivity of at least 0.01 W / cm*K. In some embodiments, the thermally conductive layer 120 is a thermal interface material (TIM). In some embodiments, the thermally conductive layer 120 is a thermally conductive adhesive applied to the surface of one or more of the first semiconductor die 106, the second semiconductor die 112, and / or the third semiconductor die 113. In some embodiments, the thermally conductive layer 120 is composed of a silicone polymer. In other embodiments, the thermally conductive layer 120 is composed of a metal or a metal alloy (e.g., copper, aluminum). In some embodiments, the thermally conductive layer 120 extends between the surface of the corresponding semiconductor die 106, 112, 113 to which it is mounted and the adjacent surface of the housing 114. For example, Figure 1 The thermally conductive layer 120 mounted on the first semiconductor die 106 is shown to extend from the top surface of the first semiconductor die 106 to an adjacent inner surface of the housing 114 near the top flat surface 114t. Similarly, the thermally conductive layers 120 mounted on the second and third semiconductor dies 112 and 113, respectively, extend from the outer surfaces of the semiconductor dies 112, 113 to the inner surfaces of the corresponding first and second protrusions 116a, 116b.

[0040] In some embodiments, there may be one or more fasteners 122a, 122b connected to the second substrate 108 and the third substrate 110, respectively, and configured to maintain the positioning of the second substrate 108 and the third substrate 110 relative to the housing 114. There may be one or more first fasteners 122a connected to the second substrate 108 and the first protrusion 116a. The fasteners 122a, 122b may be connected to the inner surface of the protrusions 116a, 116b. The one or more first fasteners 122a may be connected to the second substrate 108 at a location substantially opposite to the location where the second substrate 108 is electrically connected to the first receiving port 104a. For example, and as Figure 1As shown, the first fastener 122a is positioned near the side of the second substrate 108 opposite to the side of the second substrate 108 connected to the first receiving port 104a. In some embodiments, one or more first fasteners 122a are connected to the first protrusion 116a. In this way, one or more first fasteners 122a can help maintain the interval between the second substrate 108 and the inner surface of the first protrusion 116a. In some embodiments, one or more first fasteners 122a are used as electrical grounding. In some embodiments, there are one to four first fasteners 122a connected to the second substrate 108 and / or the first protrusion 116a. In some embodiments, there are two fasteners 122a connected to the second substrate 108 and / or the first protrusion 116a. In some embodiments, one or more first fasteners 122a are biasing elements. For example, one or more first fasteners 122a can each include a spring to help couple the first fastener 122a to the second substrate 108. For example, each fastener may include a spring positioned between an inner surface of the protrusion and at least one of the top and bottom surfaces of the respective substrate 108, 110. Thus, the spring-biased fastener may provide a degree of vibration and / or shock absorption, thereby reducing the risk of damaging the substrate 108, 110.

[0041] There may be one or more second fasteners 122b connected to the third substrate 110 and / or the second protrusion 116b in substantially the same manner as described above with reference to the first fastener 122a, the second substrate 106, and the first protrusion 116a. Therefore, for the sake of brevity and so as not to obscure the relevant aspects of the present disclosure, the one or more second fasteners 112b will not be described in detail.

[0042] See also Figures 3 to 5B , the dimensions of the semiconductor device package 100 and its components are set to conform to one or more industry standard form factors, such as but not limited to the E1.S25mm form factor. The housing 114 can have an overall width W of about 33.75mm, an overall height H of about 25.00mm, and an overall length L of about 118.75mm. In some embodiments, the height H from the top surface 114t of the housing 114 to the top surface of the first protrusion 116a and / or the second protrusion 116b is about 1.5mm. P In some embodiments, the height H of the protrusion is about 15.5 mm. P The height of the first protrusion 116a and / or the second protrusion 116b is approximately equal to the height of the fins included in the heat sink 118. In some embodiments, the first protrusion 116a and / or the second protrusion 116b are spaced apart from the corresponding side surface of the housing 114 by a distance W. S In some embodiments, the spacing distance W SIn some embodiments, the first protrusion 116a and the second protrusion 116b have a width W P , which is greater than the width W of each fin included in the heat sink 118 F In some embodiments, the width W P is about 6.00 mm, and the width W F In some embodiments, the width W F Between about 0.50 mm and about 1.00 mm.

[0043] In some embodiments, each fin included in the heat sink 118 is spaced apart from each adjacent fin by a distance W. G In some embodiments, the distance between each fin of the heat sink 118 is between about 0.50 mm and about 2.00 mm. In some embodiments, the distance W between the protrusions 116a, 116b is about 0.50 mm and about 2.00 mm. H In some embodiments, the thickness between the inner wall and the outer wall of each protrusion 116a, 116b is between about 0.50 mm and about 1.00 mm. In some embodiments, the protrusions 116a, 116b and / or fins included in the heat sink 118 may have a length equal to or less than the length L of the housing 114.

[0044] The first substrate 102 may have a length L of about 111.50 mm. S1 and a width W of about 31.50 mm S1 In some embodiments, receiving ports 104a and / or 104b can be spaced apart from the front surface of first substrate 102 by a distance D1. In some embodiments, each of receiving ports 104a and 104b can be spaced apart from the front surface of first substrate 102 by approximately the same distance D1. Distance D1 can be less than or equal to 23.00 mm. Each of receiving ports 104a, 104b can have approximately the same length L R The length of each of the receiving ports 104a, 104b may be between about 75.00 mm and about 79.00 mm. In some implementations, each of the receiving ports 104a, 104b has a width W of about 6.00 mm. R In some implementations, each of the receiving ports 104a, 104b is spaced less than 1.00 mm from a corresponding adjacent side surface of the first substrate 102. The second substrate 108 can have an overall length L of approximately 75.00 mm. S2 and an overall width W equal to or less than 17.00 mm S2In some embodiments, the male electrical connector of the second substrate 108 configured to electrically and mechanically connect to the corresponding receiving ports 104a, 104b has a width W between about 3.00 mm and about 4.00 mm. M The third substrate 110 may have substantially the same size as the second substrate 108 .

[0045] In some embodiments, there may be a plurality of power, ground and input / output (IO) pins electrically connected to the first substrate 102 and configured to facilitate electrical communication with the second substrate 108 and the third substrate 110 coupled thereto. For example, the receiving ports 104a, 104b may be configured to electrically connect the second substrate 108 and the third substrate 110 to the first substrate 102 via pins (not shown). In some embodiments, for each semiconductor die 112, 113 and / or memory die package (e.g., NAND package) that is connected to the substrate 102 via the receiving ports 104a, 104b, the corresponding receiving port includes about 64 pins. For each NAND channel, about 32 pins may be required, and the total pin count of each of the receiving ports 104a, 104b may be a multiple of 32. The total number of required pins can be reduced by sharing channels between different memory dies (e.g., NAND dies). In some embodiments, for two NAND channels, there are about 56 pins for IO and electrical grounding and about eight power pins for each receiving port 104a, 104b. In some embodiments, there are two NANDIO voltage (VCC) pins, two NAND core voltage pins (VCCQ), two NAND Vpp pins (Vpp) and two Vref pins (e.g., one for the first channel and one for the second channel). In some embodiments, there is an eight-pin data bus for the first channel (e.g., channel 0, CH0). In some embodiments, there is a control bus with sixteen pins for the first channel (e.g., the control bus of channel 0). In some embodiments, there is an eight-pin data bus for the second channel (e.g., channel 1, CH1). In some embodiments, there is a control bus with sixteen pins for the second channel. In some embodiments, there are eight ground pins. In some embodiments, the size of the receiving port 104a, 104b depends on the number of required pins. For example, the dimensions of the receiving ports 104a, 104b outlined above are based on a 64-pin count, as discussed in this paragraph. However, as the pin count decreases, the dimensions of the receiving ports 104a, 104b may also be reduced, thereby providing additional space on the first substrate 102 to position additional memory dies and / or NAND packages containing multiple memory dies.

[0046] It will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the broad inventive concept of the exemplary embodiments shown and described above. Therefore, it should be understood that the present invention is not limited to the exemplary embodiments shown and described, but is intended to cover modifications within the spirit and scope of the present invention as defined in the claims. For example, the specific features of the exemplary embodiments may or may not be part of the claimed invention, and the various features of the disclosed embodiments may be combined. The words "right", "left", "lower" and "upper" specify directions in the accompanying drawings to which reference is made. Unless expressly set forth herein, the terms "one", "a kind" and "the" are not limited to one element, but should be interpreted as meaning "at least one". As used herein, the term "about" may refer to ±10% of the referenced value. For example, "about 9" is understood to include 8.1 and 9.9.

[0047] It should be understood that at least some of the figures and descriptions of the present invention have been simplified to focus on elements relevant to a clear understanding of the present invention, while other elements that should be understood by those of ordinary skill in the art and omitted for clarity may also constitute a part of the present invention. However, because such elements are well known in the art and because they are not necessarily conducive to a better understanding of the present invention, a description of such elements is not provided herein.

[0048] In addition, where the method of the present invention does not rely on a specific order of steps described herein, the specific order of steps should not be construed as a limitation on the claims. Any claim directed to the method of the present invention should not be limited to performing its steps in the order written, and those skilled in the art can readily understand that these steps can be changed and still remain within the spirit and scope of the present invention.

Claims

1. A semiconductor device package, comprising: a first substrate having a top planar surface and a bottom planar surface; one or more receiving ports mounted on the top planar surface and electrically connected to the first substrate; one or more first semiconductor dies electrically connected to and mounted directly on the first substrate; a second substrate having a top planar surface and a bottom planar surface, the second substrate being electrically connected to a corresponding one of the one or more receiving ports, the top planar surface of the second substrate being oriented substantially perpendicular to the top planar surface of the first substrate; one or more second semiconductor dies electrically connected to and mounted directly on the second substrate; and a housing that substantially encapsulates each of the first substrate, the second substrate, the one or more receiving ports, the one or more first semiconductor dies, and the one or more second semiconductor dies, the housing comprising: a bottom surface and a top surface, the first substrate being positioned between the bottom surface and the top surface of the housing; A first hollow protrusion extends upward from the top surface of the housing proximate one of the one or more receiving ports, the second substrate and the one or more second semiconductor dies being at least partially positioned within the first hollow protrusion. 2 . The semiconductor device package of claim 1 , wherein the housing has a width of about 33.75 mm, a length of about 118.75 mm, and a height of about 25.00 mm. 3 . The semiconductor device package of claim 1 , wherein the one or more first semiconductor dies comprise a first group of NAND dies, and the one or more second semiconductor dies comprise a second group of NAND dies. 4 . The semiconductor device package of claim 3 , wherein the second group of NAND dies includes at least twice as many NAND dies as the first group of NAND dies. 5 . The semiconductor device package of claim 1 , wherein the one or more receiving ports include a first receiving port and a second receiving port, the first receiving port and the second receiving port being each electrically connected to the first substrate and spaced apart from each other.

6. The semiconductor device package according to claim 5, further comprising: a third substrate, wherein the second substrate is electrically connected to the first receiving port and the third substrate is electrically connected to the second receiving port; and One or more third semiconductor dies are electrically connected to and directly mounted on the third substrate. 7 . The semiconductor device package of claim 6 , wherein the one or more first semiconductor dies comprise a first group of NAND dies, the one or more second semiconductor dies comprise a second group of NAND dies, and the one or more third semiconductor dies comprise a third group of NAND dies. 8 . The semiconductor device package of claim 7 , wherein each of the second group of NAND dies and the third group of NAND dies includes at least twice as many NAND dies as the first group of NAND dies.

9. The semiconductor device package of claim 6, wherein the housing substantially encapsulates each of the first, second, and third substrates and each of the one or more first, second, and third semiconductor dies, wherein the first hollow protrusion is proximate to the first receiving port, and The housing further comprises: A second hollow protrusion extends upward from the top surface of the housing proximate the second receiving port, the third substrate and the one or more third semiconductor dies being at least partially positioned within the second hollow protrusion.

10. The semiconductor device package according to claim 9, further comprising: A heat sink is mounted on the top surface of the housing and includes a plurality of fins, each of the plurality of fins being positioned between the first hollow protrusion and the second hollow protrusion of the housing. The semiconductor device package according to claim 10 , wherein the heat sink is integrally formed with the housing.

12. The semiconductor device package according to claim 10, further comprising: one or more thermally conductive layers, each of the one or more thermally conductive layers being mounted directly on a surface of a corresponding semiconductor die of the one or more first semiconductor dies, second semiconductor die, and third semiconductor die, Each thermally conductive layer extends between the surface of the corresponding semiconductor die and an adjacent interior surface of the housing. 13 . The semiconductor device package of claim 10 , wherein each of the plurality of fins extends upward from the top surface of the housing and is substantially perpendicular to the top surface of the housing. 14 . The semiconductor device package of claim 10 , wherein the first hollow protrusion and the second hollow protrusion each have a width greater than a width of a single fin among the plurality of fins.

15. The semiconductor device package according to claim 9, further comprising: one or more first fasteners, the one or more first fasteners connected to the second substrate and the first hollow protrusion, the one or more first fasteners connected to the second substrate opposite the location where the second substrate is electrically connected to the first receiving port; and One or more second fasteners are connected to the third substrate and the second hollow protrusion, the one or more second fasteners are connected to the third substrate opposite to where the third substrate is electrically connected to the second receiving port. 16 . The semiconductor device package of claim 15 , wherein the one or more first fasteners and the one or more second fasteners include biasing elements configured to maintain an orientation of the second substrate and the third substrate relative to the first substrate. 17 . The semiconductor device package of claim 1 , wherein the one or more receiving ports are each a through-hole mount electrically connected to the first substrate.

18. A semiconductor device package, comprising: a first substrate arrangement for providing electrical communication with one or more electrical components coupled to the first substrate arrangement; one or more receiving devices electrically connected to the first substrate device and configured to provide electrical communication between the first substrate device and one or more other substrate devices; One or more first storage devices, each of the one or more first storage devices is used to store a certain amount of charge, and each of the one or more first storage devices is electrically connected to the first substrate device through a corresponding electrical connection device; a second substrate device for providing electrical communication with one or more electrical components coupled to the second substrate device, the second substrate device being electrically connected to the one or more receiving devices and being oriented generally perpendicular to the first substrate device; One or more second storage devices, each of the one or more second storage devices is used to store a certain amount of charge, and each of the one or more second storage devices is electrically connected to the second substrate device through a corresponding electrical connection device; | A housing device for substantially enclosing each of the first substrate device, the second substrate device, the one or more receiving devices, the one or more first storage devices, and the one or more second storage devices, the housing device comprising: a bottom surface and a top surface, the first substrate device being positioned between the bottom surface and the top surface of the housing; a first hollow protrusion extending upwardly from the top surface of the housing device proximate one of the one or more receiving devices, the second substrate device and the one or more second storage devices being at least partially positioned within the first hollow protrusion.

19. The semiconductor device package according to claim 18, further comprising: a third substrate device for providing electrical communication with one or more electrical components coupled to the third substrate device, the third substrate device being electrically connected to the one or more receiving devices and being oriented generally perpendicular to the first substrate device and spaced apart from the second substrate device; and One or more third storage devices, each of the one or more third storage devices is used to store a certain amount of charge, and each of the one or more third storage devices is electrically connected to the third substrate device through a corresponding electrical connection device.

20. A semiconductor device package, comprising: a first substrate having a top planar surface and a bottom planar surface substantially parallel to the top planar surface; a first receiving port, the first receiving port being electrically connected to the first substrate; a second receiving port spaced apart from the first receiving port and electrically connected to the first substrate; one or more first NAND dies electrically connected to and mounted directly on the first substrate; a second substrate having a top planar surface and a bottom planar surface, the second substrate being electrically connected to the first receiving port such that the top planar surface of the second substrate is substantially perpendicular to the top planar surface of the first substrate; one or more second NAND dies electrically connected to and mounted directly on the second substrate; a third substrate having a top planar surface and a bottom planar surface, the third substrate being electrically connected to the second receiving port such that the top planar surface of the third substrate is substantially perpendicular to the top planar surface of the first substrate; one or more third NAND dies electrically connected to and mounted directly on the third substrate; a housing that substantially encapsulates each of the first, second, and third substrates and each of the one or more first, second, and third NAND dies, the housing comprising: a bottom surface and a top surface, the first substrate being positioned between the bottom surface and the top surface of the housing; a first hollow protrusion extending upward from the top surface of the housing proximate the first receiving port, the second substrate being at least partially positioned within the first hollow protrusion; and a second hollow protrusion extending upward from the top surface of the housing proximate the second receiving port, the third substrate being at least partially positioned within the second hollow protrusion; and A heat sink is mounted on the top surface of the housing and includes a plurality of fins, each of the plurality of fins being positioned between the first hollow protrusion and the second hollow protrusion of the housing.

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