Semiconductor device and electronic device

Abstract

The purpose of the present invention is to increase the yield. This semiconductor device is provided with: a base member having a first bonding surface; and a semiconductor chip having a rectangular second bonding surface; the second bonding surface of the semiconductor chip and the first bonding surface of the base member are directly bonded to each other. The semiconductor chip has: a multilayer wiring layer including a second bonding surface; and a semiconductor layer disposed on a surface of the multilayer wiring layer opposite to the second bonding surface side. The multilayer wiring layer includes a warpage suppression layer that extends along at least one side of the second bonding surface and suppresses warpage of the semiconductor chip.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device and an electronic device, and particularly to a technology effective when applied to a semiconductor device having a semiconductor chip directly bonded to a base member and an electronic device including the semiconductor device. Background Art

[0002] As a semiconductor device, a light detection device such as a solid-state imaging device or a distance measuring device is known. In the light detection device, a three-dimensional structure is adopted to achieve miniaturization and high density of pixels. As a method for realizing the three-dimensional structure, a method of directly bonding two semiconductor wafers is known.

[0003] On the other hand, Patent Document 1 discloses a technique for suppressing warpage caused by bonding of substrates.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-001681 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] In addition, as a method for realizing a three-dimensional structure, a method of directly bonding a rectangular semiconductor chip to a base member (bonding member) such as a semiconductor wafer or a semiconductor chip (chip bonding method) is also known. In this chip bonding method, due to the warping of the semiconductor chip, the peripheral edge of the semiconductor chip sometimes floats from the base member, which easily causes defects such as cracks and chipping of the semiconductor chip, resulting in a decrease in the manufacturing yield of the semiconductor device.

[0009] In particular, in order to reduce the thickness of the semiconductor device, the thickness of the substrate of the semiconductor chip can be reduced after the semiconductor chip is directly bonded to the base member. In this case, the rigidity of the semiconductor chip becomes weak, and the floating of the semiconductor chip easily occurs.

[0010] The purpose of this technology is to increase manufacturing yields.

[0011] Solution to the problem

[0012] (1) A semiconductor device according to one aspect of the present technology includes a base member having a first bonding surface and a semiconductor chip having a second bonding surface having a quadrilateral shape.

[0013] Then, the second bonding surface of the semiconductor chip and the first bonding surface of the base member are bonded by direct bonding.

[0014] Then, the semiconductor chip includes: a multilayer wiring layer including a second bonding surface; and a semiconductor layer provided on a side of the multilayer wiring layer opposite to a side of the second bonding surface.

[0015] Furthermore, the multilayer wiring layer has a warp suppression film extending along at least one side of the second bonding surface to suppress warping of the semiconductor chip.

[0016] (2) A semiconductor device according to another aspect of the present technology includes:

[0017] a base member having a first engaging surface; and

[0018] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0019] Semiconductor chips include:

[0020] a multilayer wiring layer including a second bonding surface,

[0021] a semiconductor layer provided on the opposite side to one side of the second bonding surface of the multilayer wiring layer, and

[0022] a warpage suppressing portion which is provided in the multilayer wiring layer and suppresses warpage of the semiconductor chip, and

[0023] The warpage suppressing portion is selectively provided on the peripheral edge portion side of the second joint surface in a plan view.

[0024] (3) A semiconductor device according to another aspect of the present technology includes:

[0025] a base member having a first engaging surface; and

[0026] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0027] Semiconductor chips include:

[0028] a multilayer wiring layer including a second bonding surface,

[0029] a semiconductor layer provided on the opposite side of one side of the second bonding surface of the multilayer wiring layer and having a back surface having a quadrilateral shape on the opposite side of one side of the multilayer wiring layer, and

[0030] a warpage suppressing portion provided in the semiconductor layer and suppressing warpage of the semiconductor chip, and

[0031] The warpage suppression portion is selectively provided on the peripheral edge portion side of the rear surface of the semiconductor layer in a plan view.

[0032] (4) A semiconductor device according to another aspect of the present technology includes:

[0033] a base member having a first engaging surface; and

[0034] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0035] Semiconductor chips include:

[0036] a multilayer wiring layer including a second bonding surface, and

[0037] a semiconductor layer provided on a side opposite to a side of the second bonding surface of the multilayer wiring layer,

[0038] The second joint surface includes: an insulating layer included in the multi-layer wiring layer; and a weak joint portion having a weaker joint force with the first joint surface than the insulating layer; and

[0039] The weak joining portion is provided on the peripheral edge portion side of the second joining surface. (5)

[0041] A semiconductor device according to another aspect of the present technology includes:

[0042] a base member having a first joint surface having a quadrilateral shape; and

[0043] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0044] At least one of the first joint surface or the second joint surface includes a weak joint area and a strong joint area having a relatively different joint force from the other joint surface, and one weak joint area is provided on the peripheral portion side of one joint surface.

[0045] (6) An electronic device according to another aspect of the present technology includes: a semiconductor device; an optical system that forms an image of image light from a subject on the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 : is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology.

[0047] Figure 2 : is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit of the solid-state imaging device according to the first embodiment of the present technology.

[0048] Figure 3 is a plan layout diagram schematically showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology.

[0049] Figure 4 is a schematic diagram showing the Figure 1 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a3-a3 in FIG.

[0050] Figure 5 yes Figure 4 The expanded diagram of .

[0051] Figure 6 It is schematically shown Figure 3 A bottom view of the bottom surface side of the solid-state imaging device in FIG.

[0052] Figure 7 : is a plan view schematically showing a state in which the second semiconductor chip is bonded to the first semiconductor chip when viewed from the second semiconductor chip side, in which illustration of the sealing body is omitted.

[0053] Figure 8 is schematically shown along Figure 7 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a7-a7 in FIG.

[0054] Fig. 9 is schematically shown along Figure 7 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b7-b7 in FIG.

[0055] Fig.10 is a plan view schematically showing the bonding surface side of the first semiconductor chip.

[0056] Fig.11 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0057] Fig. 12A is schematically shown along Fig.11 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a11 - a11 in FIG.

[0058] Fig. 12B yes Fig. 12A A partial enlarged longitudinal section view.

[0059] Fig.13 is schematically shown along Fig.11 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b11-b11 in FIG.

[0060] Fig.14: is a plan view schematically showing a semiconductor wafer for describing a method of manufacturing the second semiconductor chip included in the solid-state imaging device according to the first embodiment of the present technology.

[0061] Fig.15 It is shown in Fig.14 2 is a diagram showing the configuration of the chip forming area by enlarging the area A.

[0062] Fig.16 is schematically shown along Fig.15 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a15-a15 in FIG.

[0063] Fig.17 It is a plan view schematically showing a state where a dicing process is performed on a semiconductor wafer in the second semiconductor chip manufacturing method.

[0064] Fig.18 is schematically shown along Fig.17 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a17-a17 in FIG.

[0065] Fig.19 is a longitudinal cross-sectional view schematically showing a state in which a ring CMP process is performed in the method of manufacturing the second semiconductor chip.

[0066] Fig. 20 It is a cross-sectional view schematically showing a process of forming a warpage suppression film and a bonding metal pad in the manufacturing method of the second semiconductor chip.

[0067] Fig.21 It is a cross-sectional view schematically showing a process of forming a warpage suppression film and a bonding metal pad in the manufacturing method of the second semiconductor chip.

[0068] Fig. 22 : is a plan view schematically showing a wafer stack for describing a method of manufacturing a first semiconductor chip included in the solid-state imaging device according to the first embodiment of the present technology.

[0069] Fig.23 It indicates schematically Fig. 22 A longitudinal cross-sectional view of the longitudinal cross-sectional structure of a wafer stack.

[0070] Fig.24 It is shown Fig. 22 2 is a diagram showing the configuration of the chip forming area by enlarging the area B.

[0071] Fig.25 It is a plan view schematically showing the process of the method of manufacturing the solid-state imaging device according to the first embodiment of the present technology.

[0072] Fig.26 is schematically shown along Fig.25 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a25-a25.

[0073] Fig. 27 is a schematic diagram showing the Fig.25 Floor plan of the after process.

[0074] Fig.28 is schematically shown along Fig. 27 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a27-a27 in FIG.

[0075] Fig.29 yes Fig.28 A partial enlarged longitudinal section view.

[0076] Fig.30 is a schematic diagram showing the Fig. 27 Longitudinal cross-section of the process followed.

[0077] Fig.31 is a schematic diagram showing the Fig. 27 Floor plan of the after process.

[0078] Fig.32 is schematically shown along Fig.31 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a31 - a31 in FIG.

[0079] Fig.33 is a schematic diagram showing the Fig.31 Longitudinal cross-section of the process followed.

[0080] Fig.34 It is schematically shown Fig.33 Floor plan of the after process.

[0081] Fig.35 1 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-1 of the first embodiment of the present technology.

[0082] Fig.36 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-2 of the first embodiment of the present technology.

[0083] Fig.37 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-3 of the first embodiment of the present technology.

[0084] Fig.38 : is a plan view schematically showing the configuration of the second semiconductor chip according to Modification 1-4 of the first embodiment of the present technology.

[0085] Fig.39 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-5 of the first embodiment of the present technology.

[0086] Fig.40 : is a plan view schematically showing the configuration of the second semiconductor chip according to Modification 1-6 of the first embodiment of the present technology.

[0087] Fig.41 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-7 of the first embodiment of the present technology.

[0088] Fig.42 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-8 of the first embodiment of the present technology.

[0089] Fig.43 : is a plan view schematically showing the configuration of the second semiconductor chip according to Modification 1-9 of the first embodiment of the present technology.

[0090] Fig.44 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-10 of the first embodiment of the present technology.

[0091] Fig.45 It is a diagram schematically showing the film state of the warpage suppression film according to Modification 1-11 of the first embodiment of the present technique.

[0092] Fig.46 It is a diagram schematically showing the film state of the warpage suppression film according to Modification 1-12 of the first embodiment of the present technology.

[0093] Fig.47 It is a diagram schematically showing the film state of the warpage suppression film according to Modification 1-13 of the first embodiment of the present technique.

[0094] Fig.48 It is a diagram schematically showing the film state of the warpage suppression film according to Modification 1-14 of the first embodiment of the present technique.

[0095] Fig.49 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-15 of the first embodiment of the present technology.

[0096] Fig.50 It is a plan view schematically showing the configuration of the second semiconductor chip according to Modification 1-16 of the first embodiment of the present technology.

[0097] Fig.51It is a plan view schematically showing a main part of the configuration of the second semiconductor chip according to Modification 1-17 of the first embodiment of the present technology.

[0098] Fig.52 1 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-18 of the first embodiment of the present technology.

[0099] Fig.53 is a cross-sectional view schematically showing the configuration of the second semiconductor chip according to Modification 1-18 of the first embodiment of the present technology ( Fig.53 (a) schematically shows the Fig.52 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a52-a52 in FIG. Fig.53 (b) schematically shows the Fig.52 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b52-b52 in FIG.

[0100] Fig.54 is a schematic diagram showing a second semiconductor chip according to a modification 1-19 of the first embodiment of the present technology. Fig.52 A longitudinal sectional view of the longitudinal sectional structure in which the cutting line b52 - b52 shown in FIG. 1 is at the same position.

[0101] Fig.55 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a second embodiment of the present technology.

[0102] Fig.56 is schematically shown along Fig.55 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a55-a55.

[0103] Fig.57 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0104] Fig.58A is schematically shown along Fig.57 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a57-a57.

[0105] Fig.58B yes Fig.58A A partial enlarged longitudinal section view.

[0106] Fig.59 It is a plan view schematically showing the planar shape of a warp suppression film provided in an inner layer of a multilayer wiring layer of a second semiconductor chip.

[0107] Fig.60AIt is a plan view schematically showing a plan pattern of a warp suppressing film provided on a bonding surface of a multilayer wiring layer in a second semiconductor chip according to a modification 2-1 of the second embodiment of the present technology.

[0108] Fig.60B This is a plan view schematically showing a plan pattern of a warp suppression film provided in an inner layer of a multilayer wiring layer in a second semiconductor chip according to Modification 2-1 of the second embodiment of the present technology.

[0109] Fig.61A It is a plan view schematically showing a plan pattern of a warp suppression film provided on a bonding surface of a multilayer wiring layer in a second semiconductor chip according to Modification 2-2 of the second embodiment of the present technology.

[0110] Fig.61B 2 is a plan view schematically showing a plan pattern of a warpage suppression film provided in an inner layer of a multilayer wiring layer in a second semiconductor chip according to Modification 2-2 of the second embodiment of the present technology.

[0111] Fig.62 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a third embodiment of the present technology.

[0112] Fig.63 is schematically shown along Fig.62 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a62-a62 in FIG.

[0113] Fig.64 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0114] Fig.65A is schematically shown along Fig.62 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a62-a62 in FIG.

[0115] Fig.65B yes Fig.65A A partial enlarged longitudinal section view.

[0116] Fig.66 3 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a second semiconductor chip according to Modification 3-1 of the third embodiment of the present technology.

[0117] Fig.67 is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to a fourth embodiment of the present technology.

[0118] Fig.68 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0119] Fig.69 is a plan view schematically showing the bonding surface side of the first semiconductor chip.

[0120] Fig.70 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0121] Fig.71 is schematically shown along Fig.70 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a70-a70 in FIG.

[0122] Fig.72 is schematically shown along Fig.70 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b70-b70 in FIG.

[0123] Fig.73 5 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to Modification 5-1 of the fifth embodiment of the present technology.

[0124] Fig.74 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a sixth embodiment of the present technology.

[0125] Fig.75 is schematically shown along Fig.75 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a75-a75.

[0126] Fig.76 is schematically shown along Fig.75 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b75-b75.

[0127] Fig.77A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-1 of the sixth embodiment of the present technology.

[0128] Fig.77B is schematically shown along Fig.77A The longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b77-b77 in FIG.

[0129] Fig.78A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-2 of the sixth embodiment of the present technology.

[0130] Fig.78B is schematically shown along Fig.78A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a78-a78 in FIG.

[0131] Fig.78C is schematically shown along Fig.78A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b78-b78 in FIG.

[0132] Fig.79A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-3 of the sixth embodiment of the present technology.

[0133] Fig.79B is schematically shown along Fig.79A The longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b79-b79 in FIG.

[0134] Fig.80A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-4 of the sixth embodiment of the present technology.

[0135] Fig.80B is schematically shown along Fig.80A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b80-b80 in FIG.

[0136] Fig.81A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-5 of the sixth embodiment of the present technology.

[0137] Fig.81B is schematically shown along Fig.81A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a81 - a81 in FIG.

[0138] Fig.82 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a seventh embodiment of the present technology.

[0139] Fig.83 is schematically shown along Fig.82 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a82 - a782 in FIG.

[0140] Fig.84 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0141] Fig.85A : is a plan view schematically showing the bonding surface side of the second semiconductor chip according to Modification 7-1 of the seventh embodiment of the present technology.

[0142] Fig.85B: is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to Modification 7-2 of the seventh embodiment of the present technology.

[0143] Fig.86 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to an eighth embodiment of the present technology.

[0144] Fig.87A is schematically shown along Fig.86 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a86a-a86a in FIG.

[0145] Fig.87B is schematically shown along Fig.86 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a86b-a86b in FIG.

[0146] Fig.88 1 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0147] Fig.89 : is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to Modification 8-1 of the eighth embodiment of the present technology.

[0148] Fig.90 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a ninth embodiment of the present technology.

[0149] Fig.91A is a schematic diagram showing the Fig.90 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a90a-a90a in FIG.

[0150] Fig.91B is schematically shown along Fig.90 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a90b-a90b in FIG.

[0151] Fig.92 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0152] Fig.93 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a tenth embodiment of the present technology.

[0153] Fig.94 is schematically shown along Fig.93 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a93-a93.

[0154] Fig.95is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0155] Fig.96 is schematically shown along Fig.95 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b95-b95.

[0156] Fig.97 is a plan view schematically showing the bonding surface side of the first semiconductor chip.

[0157] Fig.98 It is a diagram showing types of arrangement patterns of weak bonding regions in Modification 10-1 of the tenth embodiment of the present technology.

[0158] Fig.99 It is a longitudinal cross-sectional view schematically showing a modification example 10-2 of the tenth embodiment of the present technology.

[0159] Fig.100 It is a longitudinal cross-sectional view schematically showing a modification 10-3 of the tenth embodiment of the present technology.

[0160] Fig.101 It is a longitudinal cross-sectional view schematically showing a modification example 10-4 of the tenth embodiment of the present technology.

[0161] Fig.102 It is a longitudinal cross-sectional view schematically showing a modification example 10-5 of the tenth embodiment of the present technology.

[0162] Fig.103 It is a longitudinal cross-sectional view schematically showing a modification example 10-6 of the tenth embodiment of the present technology.

[0163] Fig.104 It is a longitudinal cross-sectional view schematically showing a modification example 10-7 of the tenth embodiment of the present technology.

[0164] Fig.105 It is a longitudinal cross-sectional view schematically showing a modification example 10-8 of the tenth embodiment of the present technology.

[0165] Fig.106 It is a longitudinal cross-sectional view schematically showing a modification example 10-9 of the tenth embodiment of the present technology.

[0166] Fig.107 It is a longitudinal cross-sectional view schematically showing a modification 10-10 of the tenth embodiment of the present technology.

[0167] Fig.108 It is a longitudinal cross-sectional view schematically showing a modification 10-11 of the tenth embodiment of the present technology.

[0168] Fig.109 It is a longitudinal cross-sectional view schematically showing a modification 10-12 of the tenth embodiment of the present technology.

[0169] Fig.110 It is a longitudinal cross-sectional view schematically showing a modification 10-13 of the tenth embodiment of the present technology.

[0170] Fig.111 It is a longitudinal cross-sectional view schematically showing a modification 10-14 of the tenth embodiment of the present technology.

[0171] Fig.112 It is a longitudinal cross-sectional view schematically showing a modification 10-15 of the tenth embodiment of the present technology.

[0172] Fig.113 It is a longitudinal cross-sectional view schematically showing a modification 10-16 of the tenth embodiment of the present technology.

[0173] Fig.114 It is a longitudinal cross-sectional view schematically showing a modification 10-17 of the tenth embodiment of the present technology.

[0174] Fig.115 is a diagram illustrating a schematic configuration of an electronic device according to an eleventh embodiment of the present technology. DETAILED DESCRIPTION

[0175] Hereinafter, embodiments of the present technology will be described in detail with reference to the accompanying drawings.

[0176] Note that in the illustrations of the drawings referred to in the following description, the same or similar parts are represented by the same or similar reference numerals. In addition, the drawings are schematic, and the relationship between thickness and plane size, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and size should be determined in consideration of the following description.

[0177] In addition, the dimensional relationships and ratios between the drawings are of course different. In addition, the effects described herein are merely examples and are not limiting, and other effects may be provided.

[0178] In addition, the following embodiments illustrate devices and methods for embodying the technical concept of the present technology, and do not specify the following configurations. That is, various modifications can be made to the technical concept of the present technology within the technical scope described in the claims.

[0179] In addition, the definition of directions (such as up and down directions) in the following description is defined only for the convenience of description and does not limit the technical concept of the present technology. Obviously, for example, when the object is rotated 90° and observed, the vertical direction is converted and read as the horizontal direction, and when the object is rotated 180° and observed, the top side is read as the bottom side, and the bottom side is read as the top side.

[0180] Furthermore, in the following embodiments, a case where the first conductivity type is p type and the second conductivity type is n type will be exemplarily described, but the relationship between the conductivity types may be reversed, that is, the first conductivity type may be n type and the second conductivity type may be p type.

[0181] In addition, in the following embodiments, among the three directions orthogonal to each other in space, the first direction and the second direction orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to the first direction and the second direction is defined as the Z direction. Furthermore, in the following embodiments, the thickness direction of the first semiconductor chip 20 and the second semiconductor chip 40 described below is described as the Z direction.

[0182] [First embodiment]

[0183] In the first embodiment, an example in which the present technology is applied to a solid-state imaging device 1A called a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor as a semiconductor device is described.

[0184] Furthermore, in this embodiment, an example in which a warpage suppressing film is provided on the multilayer wiring layer of the second semiconductor chip as a warpage suppressing portion suppressing the warpage of the second semiconductor chip is described.

[0185] <<Overall Configuration of Solid-State Imaging Device>>

[0186] First, the overall configuration of the solid-state imaging device 1A will be described.

[0187] like Figures 3 to 6 As shown, the solid-state imaging device 1A according to the first embodiment of the present technology includes: a first semiconductor chip 20 having a bonding surface 20a as an example of a base member; and a second semiconductor chip 40 having a quadrilateral bonding surface 40a. Then, the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding.

[0188] In addition, in the first embodiment, although two second semiconductor chips 40, 40 having a planar size smaller than the planar size of the first semiconductor chip 20 are provided, the present invention is not limited thereto. The two second semiconductor chips 40 are separately arranged within the two-dimensional surface of the first semiconductor chip 20. The top view shape of the first semiconductor chip 20 and the second semiconductor chip 40 is a quadrilateral two-dimensional planar shape. As a direct bonding of the second semiconductor chip 40, for example, surface activated bonding can be used. The direct bonding of the second semiconductor chip 40 is performed in the state of the wafer stack 60 before the first semiconductor chip 20 is formed (see Fig. 22 and Fig.23), by forming the chip into region 65 (see Fig.24 ) is divided into small pieces to obtain a wafer stack 60.

[0189] In addition, the solid-state imaging device 1A according to the first embodiment of the present technology further includes a sealing body 51 provided on one side of the bonding surface 20a of the first semiconductor chip 20 to cover the second semiconductor chip 40. As the sealing body 51, for example, an epoxy-based thermosetting insulating resin or a polyimide-based thermoplastic insulating resin can be used. Figure 6 As shown, the sealing body 51 has a quadrangular planar shape in a plan view, and has, for example, a rectangular shape similar to the first semiconductor chip 20 in the first embodiment.

[0190] Here, in the first embodiment, the first semiconductor chip 20 corresponds to a specific example of the “base member” of the present technology. In addition, the second semiconductor chip 40 corresponds to a specific example of the “semiconductor chip” of the present technology.

[0191] Furthermore, the bonding surface 20 a of the first semiconductor chip 20 corresponds to a specific example of “first bonding surface” of the present technology, and the bonding surface 40 a of the second semiconductor chip 40 corresponds to a specific example of “second bonding surface” of the present technology.

[0192] In addition, the plan view refers to the case where the semiconductor chip 20, 40 is observed from the direction along the thickness direction (Z direction). In addition, the cross-sectional view refers to the case where the cross section along the thickness direction (Z direction) of the semiconductor chip 20, 40 is observed from the direction (X direction or Y direction) orthogonal to the thickness direction (Z direction) of the semiconductor chip 20, 40.

[0193] like Fig.39 As shown, the solid-state imaging device 1A (101) according to the first embodiment receives image light (incident light 106) from an object through an optical lens 102, converts the amount of incident light 106 of an image formed on an imaging surface into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal (image signal).

[0194] like Figure 3 As shown, the first semiconductor chip 20 includes a quadrilateral pixel array unit 2A provided in a central portion and a peripheral portion 2B provided outside the pixel array unit 2A to surround the pixel array unit 2A in a two-dimensional plane including X and Y directions orthogonal to each other.

[0195] The pixel array unit 2A is, for example, a receiving Fig.39The optical receiving surface of the light focused by the optical lens (optical system) 102 shown in FIG. Then, in the pixel array unit 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane including an X direction and a Y direction. In other words, the pixels 3 are repeatedly arranged in the X direction and the Y direction orthogonal to each other in the two-dimensional plane.

[0196] like Figure 3 As shown, a plurality of pads 14 are arranged in the periphery 2B. For example, each of the plurality of pads 14 is provided along each of the four sides of the two-dimensional plane of the first semiconductor chip 20. Each of the plurality of pads 14 functions as an input / output terminal that electrically connects the first semiconductor chip 20 and an external device to each other.

[0197] <Logic Circuit>

[0198] The first semiconductor chip 20 includes Figure 1 The logic circuit 13 shown. Figure 1 As shown, the logic circuit 13 includes a vertical driving circuit 4, a column signal processing circuit 5, a horizontal driving circuit 6, an output circuit 7, a control circuit 8, etc. The logic circuit 13 includes, for example, a complementary MOS (CMOS) circuit including an n-channel conductive metal oxide semiconductor field effect transistor (MOSFET) and a p-channel conductive MOSFET as field effect transistors.

[0199] The vertical drive circuit 4 includes, for example, a shift register. The vertical drive circuit 4 sequentially selects a desired pixel drive line 10 and supplies a pulse for driving the pixel 3 to the selected pixel drive line 10 to drive each pixel 3 on a row-by-row basis. That is, the vertical drive circuit 4 selectively scans the individual pixels 3 in the pixel array unit 2A sequentially in the vertical direction row by row and supplies a pixel signal from each pixel 3 to the column signal processing circuit 5 based on a signal charge generated by a photoelectric conversion unit (photoelectric conversion element) of the pixel 3 according to the amount of light received through the vertical signal line 11.

[0200] For example, the column signal processing circuit 5 is provided for each column of pixels 3, and performs signal processing such as noise removal on the signals output from the pixels 3 of one row for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion for removing pixel-specific fixed pattern noise.

[0201] The horizontal drive circuit 6 includes, for example, a shift register and sequentially outputs horizontal scanning pulses to the column signal processing circuits 5 to sequentially select the column signal processing circuits 5 and causes each column signal processing circuit 5 to output a pixel signal having undergone signal processing to the horizontal signal line 12 .

[0202] The output circuit 7 performs signal processing on pixel signals sequentially supplied from the individual column signal processing circuits 5 through the horizontal signal line 12 and outputs the pixel signals. As the signal processing, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc. can be used.

[0203] The control circuit 8 generates a clock signal and a control signal as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal. Then, the control circuit 8 then outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0204] <Circuit Configuration of Pixel>

[0205] like Figure 2 As shown, each of the plurality of pixels 3 includes a photoelectric conversion region 35 and a pixel circuit (readout circuit) 15. The photoelectric conversion region 35 includes a photoelectric conversion unit 16, a transfer transistor TR, and a charge holding region (floating diffusion) FD. The pixel circuit 15 is electrically connected to the charge holding region FD of the photoelectric conversion region 35. For example, the first embodiment has a circuit configuration in which one pixel circuit 15 is assigned to one pixel 3, but the circuit configuration is not limited thereto, and a circuit configuration in which one pixel circuit 15 is shared by a plurality of pixels 3 may be adopted. For example, a circuit configuration in which one pixel circuit 15 is shared by four pixels 3 (one pixel block) arranged in a 2×2 layout (i.e., two pixels 3 are arranged in the X direction and two pixels 3 are arranged in the Y direction) may be adopted.

[0206] Figure 2 The photoelectric conversion unit 16 shown in FIG. 1 includes, for example, a pn junction photodiode (PD) and generates signal charge according to the amount of light received. The photoelectric conversion unit 16 has a cathode side electrically connected to the source region of the transfer transistor TR and an anode side electrically connected to a reference potential line (eg, ground).

[0207] Figure 2 The transfer transistor TR shown in FIG. transfers the signal charge generated by the photoelectric conversion of the photoelectric conversion unit 16 to the charge holding region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 16, and the drain region of the transfer transistor TR is electrically connected to the charge holding region FD. Then, the gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line among the pixel drive lines 10 (see FIG. Figure 1 ).

[0208] Figure 2 The charge holding region FD shown in FIG. 1 temporarily holds (accumulates) signal charges transferred from the photoelectric conversion unit 16 via the transfer transistor TR.

[0209] The photoelectric conversion region 35 including the photoelectric conversion unit 16, the transfer transistor TR, and the charge holding region FD is provided in the semiconductor layer 32 (see Figure 5 ). In addition, for example, the pixel transistor (AMP, SEL, RST, FDG) included in the pixel circuit 15 is also provided in the semiconductor layer 32, but is not limited to this structure.

[0210] Figure 2 The pixel circuit 15 shown in reads the signal charge held in the charge holding area FD, converts the read signal charge into a pixel signal, and outputs the pixel signal. In other words, the pixel circuit 15 converts the photoelectrically converted signal charge generated by the photoelectric conversion unit 16 (photoelectric conversion element PD) into a pixel signal based on the signal charge and outputs the pixel signal. For example, the pixel circuit 15 includes, but is not limited to, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and a switch transistor FDG as pixel transistors. For example, such pixel transistors (AMP, SEL, RST, and FDG) and the transfer transistor TR each include a MOSFET as a field effect transistor. Alternatively, these transistors may be MISFETs.

[0211] Among the pixel transistors included in the pixel circuit 15 , each of the selection transistor SEL, the reset transistor RST, and the switching transistor FDG functions as a switching element, and the amplification transistor AMP functions as an amplification element.

[0212] like Figure 2 As shown, the amplifier transistor AMP has a source region electrically connected to the drain region of the selection transistor SEL and a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. Then, the gate electrode of the amplifier transistor AMP is electrically connected to the charge holding region FD and the source region of the switching transistor FDG.

[0213] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL) and a drain region electrically connected to the source region of the amplifier transistor AMP. In addition, the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line among the pixel drive lines 10 (see Figure 1 ).

[0214] The source region of the reset transistor RST is electrically connected to the drain region of the switch transistor FDG, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. Then, the gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line among the pixel drive lines 10 (see Figure 1 ).

[0215] The switching transistor FDG has a source region electrically connected to the charge holding region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. In addition, the gate electrode of the switching transistor FDG is electrically connected to the switching transistor driving line of the pixel driving line 10 (see Figure 1 ).

[0216] It should be noted that the selection transistor SEL and the switch transistor FDG can be omitted as needed. It should be noted that in the case where the selection transistor SEL is omitted, the source region of the amplifier transistor AMP is electrically connected to the vertical signal line 11 (VSL). In addition, in the case where the switch transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode of the amplifier transistor AMP and the charge holding region FD.

[0217] when Figure 2 When the transfer transistor TR shown is turned on, the transfer transistor TR transfers the signal charge generated by the photoelectric conversion unit 16 to the charge holding region FD.

[0218] when Figure 2 When the reset transistor RST shown is turned on, the reset transistor RST resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 15.

[0219] The amplifier transistor AMP generates a signal of a voltage corresponding to the level of the signal charge held in the charge holding region FD as a pixel signal. The amplifier transistor AMP constitutes a source follower amplifier and outputs a pixel signal of a voltage corresponding to the level of the signal charge generated by the photoelectric conversion unit 16. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the charge holding region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line (VSL) 11.

[0220] Figure 2 The switching transistor FDG shown in FIG. 1 controls charge retention of the charge retention region FD, and adjusts the amplification rate of the voltage according to the potential amplified by the amplifier transistor AMP.

[0221] If you will refer to Figure 2As described, during the operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 16 of the pixel 3 is held (accumulated) in the charge holding region FD via the transfer transistor TR of the pixel 3. Then, the signal charge held in the charge holding region FD is read out by the pixel circuit 15 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 15. The vertical shift register supplies the horizontal line selection control signal to the gate electrode of the selection transistor SEL of the pixel circuit 15. Then, the selection control signal is set to a high (H) level to turn on the selection transistor SEL to allow a current corresponding to the potential of the charge holding region FD that has been amplified by the amplifier transistor AMP to flow in the vertical signal line 11. In addition, the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 is set to a high (H) level to turn on the reset transistor RST to reset the signal charge accumulated in the charge holding region FD.

[0222] like Figure 1 As shown, the second semiconductor chip 40 includes an internal circuit 17 electrically connected to the logic circuit 13 of the first semiconductor chip 20. Examples of the internal circuit 17 include a memory circuit such as a DRAM or a flash memory, and a control circuit.

[0223] <<Specific configuration of the solid-state imaging device>>

[0224] Next, we will refer to Figures 3 to 13 A specific configuration of the solid-state imaging device 1A is described.

[0225] It should be noted that Figure 8 and Fig. 9 and Figure 4 and Figure 5 Invert vertically. In addition, Fig. 12A , Fig. 12B and Fig.13 and Figure 8 and Fig. 9 Vertical inversion.

[0226] like Figures 3 to 6 As shown, the solid-state imaging device 1A has a chip stack structure in which the first semiconductor chip 20 and the second semiconductor chip 40 are stacked with their bonding surfaces facing each other. That is, the solid-state imaging device 1A includes a chip stack body including the first semiconductor chip 20 and the second semiconductor chip 40.

[0227] <First Semiconductor Chip>

[0228] like Figure 4 and Figure 5As shown, the first semiconductor chip 20 includes a first substrate unit 21 and a second substrate unit 31 stacked facing each other in the thickness direction (Z direction) of the substrate unit. The first substrate unit 21 is provided with a logic circuit 13, etc. The second substrate unit 31 is provided with a pixel array unit 2A, a peripheral portion 2B, a pixel transistor included in a pixel circuit 15, a pad 14, etc. Each of the first substrate unit 21 and the second substrate unit 31 can also be represented as a semiconductor chip.

[0229] <Second Substrate Unit>

[0230] like Figure 4 and Figure 5 As shown, the second substrate unit 31 includes: a semiconductor layer 32 having a first surface (element forming surface or main surface) and a second surface (light incident surface or back surface) located on opposite sides to each other in the thickness direction (Z); and a multilayer wiring layer 33 provided on the first surface side of the semiconductor layer 32. In addition, the second substrate unit 31 includes an optical filter layer 36 and a microlens 37 provided on the light incident surface side (second surface side) of the semiconductor layer 32 in order from the side surface of the semiconductor layer 32, and the light incident surface side (second surface side) of the semiconductor layer 32 is located on the side opposite to the side surface (first surface side) of the multilayer wiring layer 33. As shown in FIG. Figure 3 and Figure 6 As shown, the first semiconductor chip 20 has a quadrangular planar shape in a plan view, and is formed in a rectangular shape in the first embodiment, for example.

[0231] <Semiconductor Layer>

[0232] like Figure 4 and Figure 5 As shown in , the semiconductor layer 32 extends two-dimensionally above the pixel array unit 2A and the periphery 2B, and overlaps with the pixel array unit 2A and the periphery 2B in a plan view. As the semiconductor layer 32, a Si substrate, a SiGe substrate, an InGaAs substrate, etc. can be used. Although not limited to this configuration, in the first embodiment, a semiconductor substrate is used for the semiconductor layer 32, wherein silicon (Si) is used as a semiconductor material, for example, single crystal is used as the crystallinity, for example, and P type is used as the conductivity type.

[0233] like Figure 4 and Figure 5 As shown, the photoelectric conversion region 35 is provided in the semiconductor layer 32. Although not shown in detail, the photoelectric conversion region 35 is repeatedly arranged for each pixel 3 in each of the X direction and the Y direction orthogonal to each other in a two-dimensional plane, for example. Figure 3As described above, the charge holding region FD that holds the signal charge photoelectrically converted by the photoelectric conversion unit 16 and the transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion unit 16 to the charge holding region are arranged in the surface layer portion of the semiconductor layer 32 on the side opposite to the multilayer wiring layer 33 side. The photoelectric conversion unit 16, the charge holding region FD, and the transfer transistor TR are arranged in the semiconductor layer 32 (photoelectric conversion region 35) of each pixel 3.

[0234] <Multi-layer wiring layer>

[0235] Although not shown in detail, as shown in reference Figure 4 and Figure 5 As described, the multilayer wiring layer 33 has a stacked structure in which the insulating layer and the wiring layer are alternately stacked in multiple stages. Then, the multilayer wiring layer 33 includes wiring and bonding metal pads 34 arranged in each wiring layer. As the material of the insulating layer, for example, silicon oxide (SiO2) can be used. As the material of the wiring layer and the bonding metal pad 34, for example, a metal such as aluminum (Al) or copper (Cu), an alloy mainly containing Al or Cu, etc. can be used.

[0236] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 33 is covered by the uppermost insulating layer. The bonding metal pad 34 is provided on the surface layer portion of the multilayer wiring layer 33 on the side opposite to the semiconductor layer 32 side, and is provided in the insulating layer in a state where the surface is exposed from the uppermost insulating layer. The bonding metal pad 34 is electrically connected to the wiring in the layer lower than the bonding metal pad 34. Then, the wiring in the lower layer is electrically connected to the charge holding region FD and the transfer transistor TR.

[0237] <Optical filter and microlens>

[0238] The optical filter layer 36 separates the colors of incident light incident from the light incident surface side (back side) of the first semiconductor chip 20. For example, the optical filter layer 36 includes a red (R) first color filter, a green (G) second color filter, and a blue (B) third color filter.

[0239] On the optical filter layer 36 on the side opposite to the semiconductor layer 32 side (light incident surface side), a microlens 37 is provided for each photoelectric conversion region 35. The microlens 37 condenses the irradiated light and allows the condensed light to enter the photoelectric conversion unit 16 efficiently.

[0240] <First Substrate Unit>

[0241] like Figure 4 and Figure 5As shown, the first substrate unit 21 includes: a semiconductor layer 22 having a first surface (element forming surface) and a second surface (back surface) located on opposite sides in the thickness direction (Z direction); a multilayer wiring layer 23 arranged on the first surface side of the semiconductor layer 22; and a multilayer wiring layer 25 arranged on the second surface side of the semiconductor layer 22.

[0242] <Semiconductor Layer>

[0243] The semiconductor layer 22 extends two-dimensionally above the pixel array unit 2A and the periphery 2B, and overlaps with the pixel array unit 2A and the periphery 2B in a plan view. As the semiconductor layer 22, a Si substrate, a SiGe substrate, an InGaAs substrate, etc. can be used. Although not limited to this configuration, in the first embodiment, a semiconductor substrate is used for the semiconductor layer 22, wherein silicon (Si) is used as a semiconductor material, for example, a single crystal is used as the crystallinity, for example, a p-type is used as the conductivity type.

[0244] Despite Figure 4 and Figure 5 Although not shown in detail, for example, a metal oxide semiconductor field effect transistor (MOSFET) is provided on the first surface (element shape surface) of the semiconductor layer 22 as a transistor element constituting the logic circuit 13 (see Figure 1 ).

[0245] <Multi-layer wiring layer>

[0246] Although not shown in detail, the multilayer wiring layer 23 has a stacked structure in which the insulating layer and the wiring layer are alternately stacked in multiple stages. Then, the multilayer wiring layer 23 includes wiring and a bonding metal pad 24 arranged in each wiring layer. As the material of the insulating layer, for example, silicon oxide (SiO2) can be used. As the material of the wiring layer and the bonding metal pad 24, for example, a metal such as aluminum (Al) or copper (Cu), an alloy mainly containing Al or Cu, etc. can be used.

[0247] The wiring provided in the uppermost wiring layer of the multilayer wiring layer 23 is covered by the uppermost insulating layer. The bonding metal pad 24 is provided on a surface layer portion on the side opposite to the semiconductor layer 22 of the multilayer wiring layer 23, and the surface of the bonding metal pad 24 is exposed from the uppermost insulating layer. The bonding metal pad 24 is electrically connected to the wiring in the layer lower than the bonding metal pad 24.

[0248] <Multi-layer wiring layer>

[0249] Although not shown in detail, the multilayer wiring layer 25 has a stacked structure in which the insulating layer and the wiring layer are alternately stacked in multiple stages. Then, the multilayer wiring layer 25 includes wiring and a bonding metal pad 27 provided in each wiring layer. As a material for the insulating layer, for example, silicon oxide (SiO2) can be used. As a material for the wiring layer and the bonding metal pad 27, for example, a metal such as aluminum (Al) or copper (Cu), an alloy mainly containing Al or Cu, etc. can be used.

[0250] The wirings arranged in the uppermost wiring layer of the multilayer wiring layer 25 are covered by the uppermost insulating layer 26 (see Figure 8 and Fig. 9 Then, the bonding metal pad 27 is provided on the surface layer portion of the multilayer wiring layer 25 on the side opposite to the semiconductor layer 22 side, and is provided in the insulating layer 26 in a state where the surface is exposed from the uppermost insulating layer 26. The bonding metal pad 27 is electrically connected to the wiring in the layer lower than the bonding metal pad 27.

[0251] The wiring of the multilayer wiring layer 25 is via Figure 4 and Figure 5 The contact electrode 28 shown is electrically connected to the wiring of the multilayer wiring layer 23. The contact electrode 28 penetrates the semiconductor layer 22 in the thickness direction of the semiconductor layer 22 and extends over the multilayer wiring layer 23, the semiconductor layer 22, and the multilayer wiring layer 25. As a material of the contact electrode 28, for example, a high melting point metal such as titanium (Ti) or tungsten (W) can be used.

[0252] <Bonding Pad and Bonding Opening>

[0253] like Figure 4 and Figure 5 As shown, the bonding pad 14 is provided in the multilayer wiring layer 33 on the semiconductor layer 32 side. Specifically, the bonding pad 14 is provided in, for example, a first wiring layer of the multilayer wiring layer 33.

[0254] like Figure 4 and Figure 5 As shown, the first semiconductor chip 20 is provided with a bonding opening 38 exposing the surface of the bonding pad 14. The bonding opening 38 penetrates the semiconductor layer 32 in the thickness direction (Z direction) of the semiconductor layer 32 and extends over the semiconductor layer 32 and the multilayer wiring layer 33. A connection member such as a bonding wire and a bump electrode is electrically and mechanically connected to the bonding pad 14 through the bonding opening 38.

[0255] <Joining of First Substrate Unit and Second Substrate Unit>

[0256] like Figure 4 and Figure 5As shown, in the first substrate unit 21, the bonding metal pad 24 is provided in the surface layer portion of the multilayer wiring layer 23 opposite to the semiconductor layer 22 side. The bonding metal pad 24 is provided in the uppermost insulating layer of the multilayer wiring layer 23 in a state where the bonding surface is exposed.

[0257] As described above, in the second substrate unit 31, the bonding metal pad 34 is provided in the surface layer portion of the multilayer wiring layer 33 opposite to the semiconductor layer 32 side. The bonding metal pad 34 is provided in the uppermost insulating layer of the multilayer wiring layer 33 in a state where the bonding surface is exposed.

[0258] Then, the bonding metal pads 24 of the substrate unit 21 and the bonding metal pads 34 of the second substrate unit 31 are electrically and mechanically connected by metal-to-metal bonding with their respective bonding surfaces facing each other. Then, the metal-to-metal bonding between the bonding metal pads 24 and the bonding metal pads 34 makes the wiring of the multilayer wiring layer 23 of the first substrate unit 21 and the wiring of the multilayer wiring layer 33 of the second substrate unit 31 conductive.

[0259] The bonding metal pad 24 of the first substrate unit 21 and the bonding metal pad 34 of the second substrate unit 31 are bonded to each other at their bonding surfaces by direct bonding. In addition, the uppermost insulating layer of the multi-layer wiring layer of the first substrate unit 21 and the uppermost insulating layer of the multi-layer wiring layer of the second substrate unit 31 are bonded to each other at their bonding surfaces by direct bonding. As direct bonding, for example, surface activated bonding can be used.

[0260] <Bonding Surface of First Semiconductor Chip>

[0261] like Figure 4 and Figure 5 As shown, the bonding surface 20a of the first semiconductor chip 20 is disposed on the multilayer wiring layer 25 on the insulating layer 26 side. Figures 7 to 10 As shown, the bonding surface 20 a of the first semiconductor chip 20 includes an insulating layer 26 located at the uppermost layer of the multi-layer wiring layer 25 of the first semiconductor chip 20 , and further includes bonding metal pads 27 interspersed with the insulating layer 26 .

[0262] like Fig.10 As shown, the chip mounting region Cm having the bonding surface 20a dotted with the bonding metal pads 27. Then, the second semiconductor chip 40 is mounted on the chip mounting region Cm, and the bonding surface 40a of the second semiconductor chip 40 is directly bonded.

[0263] Here, in the first embodiment, the insulating layer 26 of the multilayer wiring layer 25 corresponds to a specific example of the “first insulating layer” of the present technology, and the bonding metal pad 27 of the multilayer wiring layer 25 corresponds to a specific example of the “first bonding metal pad” of the present technology.

[0264] <Second Semiconductor Chip>

[0265] like Figure 4 and Figure 5 As shown, the two second semiconductor chips 40 include: a semiconductor layer 42 having a first surface (element forming surface or main surface) and a second surface (back surface) on one side opposite to each other in the thickness direction (Z); and a multilayer wiring layer 45 provided on the first surface side of the semiconductor layer 42. That is, each of the two second semiconductor chips 40 includes a multilayer wiring layer 45 having a second bonding surface 40a, and a semiconductor layer 42 provided on the multilayer wiring layer 45 on a side opposite to the second bonding surface 40a side.

[0266] <Semiconductor Layer>

[0267] As the semiconductor layer 42, a Si substrate, a SiGe substrate, an InGaAs substrate, etc. can be used. Although not limited to this configuration, in the first embodiment, a semiconductor substrate is used for the semiconductor layer 42, wherein silicon (Si) is used as a semiconductor material, for example, single crystal is used as crystallinity, and for example, p type is used as conductivity type.

[0268] For example, a metal oxide semiconductor field effect transistor (MOSFET) is provided on the first surface (element forming surface) of the semiconductor layer 42 as a transistor element constituting the internal circuit 17 (see Figure 2 ).

[0269] <Multi-layer wiring layer>

[0270] like Figure 8 and Fig. 9As shown, the multilayer wiring layer 45 includes: a multi-stage stacking portion 45a in which insulating layers and wiring layers are alternately stacked in multiple layers; and a warpage suppression film 45b provided as a warpage suppression portion on the side opposite to the semiconductor layer 42 side of the multi-stage stacking portion 45a. In addition, the multilayer wiring layer 45 includes: an insulating layer 46 provided on the multi-stage stacking portion 45a on the side opposite to the semiconductor layer 42 side to cover the warpage suppression film 45b; and a bonding metal pad 47 which is dispersed in a surface layer portion of the insulating layer 46 on the side opposite to the side of the multi-stage stacking portion 45a and has a surface exposed from the insulating layer 46. The insulating layer 46 is the uppermost insulating layer of the multilayer wiring layer 45, and the surface of the insulating layer 46 is the bonding surface 40a of the second semiconductor chip 40. That is, the bonding surface 40a of the second semiconductor chip 40 includes the uppermost insulating layer 46 of the multilayer wiring layer 45 and the bonding metal pad 47 dispersed with the insulating layer 46. The bonding metal pad 47 is provided in the insulating layer 46 of the multilayer wiring layer 45 in a state where the bonding surface is exposed. Then, the bonding surface 40a is substantially flat with a step between the bonding metal pad 47 and the insulating layer 46 as small as possible.

[0271] For example, a silicon oxide (SiO2) film can be used as a material of the insulating layer of the multi-stage stacked portion 45a and the uppermost insulating layer 46. In addition, as a material of the wiring layer and the bonding metal pad 47 of the multi-stage stacked portion 45a, for example, a metal such as aluminum (Al) or copper (Cu), an alloy mainly containing Al or Cu, or the like can be used.

[0272] The bonding metal pad 47 is electrically connected to a wiring in a layer lower than the bonding metal pad 47. Then, the wiring in the lower layer is electrically connected to the transistor provided on the first surface side of the semiconductor layer 42.

[0273] like Fig.11 As shown, the second semiconductor chip 40 has a quadrilateral planar shape in a plan view, and is formed into a rectangular shape, for example, in the first embodiment. Fig.11 As shown, the bonding surface 40 a of the second semiconductor chip 40 is also in a rectangular shape which is an example of a quadrilateral.

[0274] <Bonding Surface of Second Semiconductor Chip and Warpage Suppressing Film>

[0275] Next, refer to Figures 11 to 13 The bonding surface 40 a of the second semiconductor chip 40 and the warpage suppressing film 45 b are described.

[0276] Fig.11 , Fig. 12A , Fig. 12B , Fig.13Indicates the state before the second semiconductor chip 40 is directly bonded to the wafer stack described later. In addition, since the first semiconductor chip 20 is formed by dividing the chip forming area 65 of the wafer stack 60 to be described below into small pieces, for convenience, the description of "second semiconductor chip" can be given instead of "wafer stack".

[0277] like Figures 11 to 13 As shown, the bonding surface 40a of the second semiconductor chip 40 is provided on the multilayer wiring layer 45 on the insulating layer 46 side. Fig.11 As shown, the joint surface 40a has two sides 40a1 and 40a2 located on opposite sides to each other in the X direction and two sides 40a3 and 40a4 located on opposite sides to each other in the Y direction. The two sides 40a1 and 40a2 extend in the Y direction. The two sides 40a3 and 40a4 extend in the X direction.

[0278] Here, the two sides 40a1 and 40a2 may be referred to as long sides. In addition, the two sides 40a3 and 40a4 may be referred to as short sides.

[0279] like Figures 11 to 13 As shown, the second semiconductor chip 40 has a peripheral portion Cs including four sides 40a1, 40a2, 40a3, and 40a4 of the bonding surface 40a. Moreover, the peripheral portion Cs is in a curved shape that is curved between the bonding surface 40a and the side surface of the second semiconductor chip 40. The curved peripheral portion Cs is formed by performing ring CMP on the bonding surface 40a of the second semiconductor chip 40 in the manufacturing process of the second semiconductor chip 40 described later.

[0280] like Fig.11 As shown, the warpage suppression film 45b of the multilayer wiring layer 45 extends along at least one side of the bonding surface 40a of the second semiconductor chip 40. Fig.11 As shown, in the bonding surface 40a of the second semiconductor chip 40, a warpage suppression film 45b is provided on the sides of four sides (40a1, 40a2, 40a3, 40a4), and the warpage suppression film 45b has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4). The warpage suppression film 45b overlaps the side surfaces (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view and is exposed from the side surfaces of the second semiconductor chip 40.

[0281] By disposing the warp suppressing film 45 b on the peripheral portion (on the peripheral portion Cs side) of the second semiconductor chip 40 , it is possible to control the local film stress of the second semiconductor chip 40 and suppress the warping of the second semiconductor chip 40 .

[0282] Specifically, as will be described in detail below, the process of manufacturing the solid-state imaging device 1A according to the first embodiment includes the following steps. Figure 27 to Figure 29 As shown, after the bonding surface 40a of the second semiconductor chip 40 is directly bonded to the bonding surface 20a (bonding surface 20a of the first semiconductor chip) in the chip forming region 65 of the wafer stack 60, a thinning process is performed to reduce the thickness of the second semiconductor chip 40 in the Z direction. In this thinning process, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 in the Z direction is reduced, thereby reducing the rigidity of the second semiconductor chip 40. In addition, since the rigidity of the second semiconductor chip 40 is reduced, in the second semiconductor chip 40, there is a warp that separates the peripheral portion (the peripheral portion Cs side of the second semiconductor chip 40) from the bonding surface 20a in the chip forming region 65 (bonding surface 20a of the first semiconductor chip) of the wafer stack 60, that is, a warp that sets the bonding surface 40a of the second semiconductor chip 40 as a convex surface. The warp suppression film 45b suppresses such warping of the second semiconductor chip 40.

[0283] For the warpage suppression film 45b, a material having a linear expansion coefficient different from that of the surrounding multi-stage stacked portion 45a and the insulating layer 46 is used. In addition, the rigidity is improved by using a dense film with a low shrinkage rate for the warpage suppression film 45b. As a result, the warpage of the peripheral portion of the semiconductor chip 40 caused by the difference in linear expansion coefficient can be suppressed.

[0284] like Fig. 12B As shown, the warpage suppression film 45b is provided between the multi-stage stacking portion 45a and the insulating layer 46. The thickness t1 of the warpage suppression film 45b is greater than the thickness t2 of the wiring 45a1 of the multi-layer wiring layer 45 (t1>t2) so as to be able to control the local film stress of the second semiconductor chip 40. Moreover, the thickness t1 of the warpage suppression film 45b is preferably greater than the thickness t3 of the bonding metal pad 47 of the multi-layer wiring layer 45.

[0285] The warpage suppression film 45b is preferably composed of a material different from the insulating layer of the multi-stage stacked portion 45a of the multi-layer wiring layer 45 or the uppermost insulating layer 46 of the multi-layer wiring layer 45. For example, as the warpage suppression film 45b, an insulating film such as a SiO film, a SiCO film, a SiO film, a SiCN film, a silicon nitride (SiN) film, an aluminum (Al) film, a copper (Cu) film, a tungsten (W) film, a titanium (Ti) film, a tantalum (Ta) film, a zirconium (Zr) film, a hafnium (Hf) film, a lanthanum (La) film, a metal film such as an alloy film thereof, an oxide film or a nitride film thereof, or a resin film thereof can be used. In the case where the insulating layer 46 is a silicon oxide layer, a silicon nitride film, an aluminum nitride film, or a hafnium nitride film is preferred because a processing selectivity ratio with a silicon oxide layer can be obtained more advantageously. In the first embodiment, the warpage suppression film 45b is composed of, for example, a silicon nitride film.

[0286] <Joining of First Semiconductor Chip and Second Semiconductor Chip>

[0287] like Figure 8 As shown, the bonding metal pads 27 of the first semiconductor chip 20 and the bonding metal pads 47 of the second semiconductor chip 40 are electrically and mechanically connected by metal-to-metal bonding in a state where their respective bonding surfaces face each other. Then, through the metal-to-metal bonding between the bonding metal pads 27 and the bonding metal pads 47, the wiring of the multi-layer wiring layer 25 of the first semiconductor chip 20 and the wiring of the multi-layer wiring layer 45 of the second semiconductor chip 40 are electrically connected.

[0288] like Figure 8 As shown, the bonding metal pad 27 of the first semiconductor chip 20 and the bonding metal pad 47 of the second semiconductor chip 40 are directly bonded at the bonding surfaces in a state where the bonding surfaces face each other.

[0289] In addition, if Figure 8 and Fig. 9 As shown, the insulating layer 26 of the first semiconductor chip 20 and the insulating layer 46 of the second semiconductor chip 40 are bonded by direct bonding in a state where the insulating layers face each other.

[0290] That is, the bonding surface 20a of the first semiconductor chip 20 including the insulating layer 26 and the bonding metal pad 27 and the bonding surface 40a of the second semiconductor chip 40 including the insulating layer 46 and the bonding metal pad 47 are bonded by direct bonding. As direct bonding, for example, surface activated bonding can be used.

[0291] <<Method of Manufacturing Second Semiconductor Chip>>

[0292] Next, we will refer to Figures 14 to 21 A method of manufacturing the second semiconductor chip 40 included in the solid-state imaging device 1A is described.

[0293] Fig.14 is a schematic plan view of a semiconductor wafer 70 for describing a method of manufacturing the second semiconductor chip 40 included in the solid-state imaging device 1A according to the first embodiment of the present technology,

[0294] Fig.15 is shown by enlarging Fig.14 FIG. 7 is a diagram showing the configuration of the chip forming region 75 in region A;

[0295] Fig.16 is a schematic diagram showing the Fig.15 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a15-a15 in FIG.

[0296] Fig.174 is a plan view schematically showing a state where a semiconductor wafer 70 is subjected to a dicing process in a method for manufacturing a second semiconductor chip 40.

[0297] Fig.18 is a schematic diagram showing the Fig.17 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a17-a17 in FIG. 1 , and

[0298] Fig.19 It is a longitudinal cross-sectional view schematically showing a state where a ring CMP process is performed in the method for manufacturing the second semiconductor chip 40 .

[0299] also, Fig. 20 and Fig.21 4 is a cross-sectional view schematically showing a process of forming the multilayer wiring layer 45 including the warpage suppression film 45 b and the bonding surface 40 a in the method of manufacturing the second semiconductor chip 40 .

[0300] The second semiconductor chip 40 included in the solid-state imaging device 1A is formed on Fig.15 1 and 2. The chip forming region 75 of the semiconductor wafer 70 shown in FIG. The chip forming region 75 is divided by scribe lines 76 extending in each of the X direction and the Y direction, and a plurality of chip forming regions are arranged in a matrix. Fig.15 Four chip forming regions 75 are shown, which are arranged around intersections 76 a where scribe lines 76 extending in the X direction intersect with scribe lines 76 extending in the Y direction.

[0301] Then, the chip forming region 75 is divided into small pieces (individually divided) along the scribe line 76 to form the second semiconductor chip 40. The chip forming region 75 has a quadrangular planar shape in a plan view, and has a rectangular shape in the first embodiment. Note that the scribe line 76 is not physically formed.

[0302] exist Fig.14 In the semiconductor wafer 70 shown in FIG. 1 , pre-processing for forming transistors, multilayer wiring layers 45, etc. in the semiconductor layer 42 has been performed (see FIG. 1 ). Fig.16 ), and Fig.15 The chip forming region 75 shown is formed Fig.16 The semiconductor layer 42, the multilayer wiring layer 45, the bonding surface 40a, etc. are shown. The bonding surface 40a includes the insulating layer 46 of the multilayer wiring layer 45 and the bonding metal pad 47. Hereinafter, the processing after the pre-processing is performed will be described.

[0303] like Fig.17 and Fig.18As shown, the semiconductor wafer 70 on which the preprocessing has been performed is cut along the scribe line 76, and the plurality of chip forming regions 65 of the semiconductor wafer 70 are individually divided into small pieces to form the second semiconductor chips 40. The slicing of the semiconductor wafer 70 is performed in a state where the semiconductor wafer 70 is bonded and fixed on a dicing sheet (dicing tape) 79. The second semiconductor chip 40 includes a bonding surface 40a and a warpage suppression film 45b, and the bonding surface 40a includes an insulating layer 46 and a bonding metal pad 47.

[0304] Next, in a state where the plurality of second semiconductor chips 40 are bonded and fixed to the dicing sheet 79 , ring CMP is performed on the bonding surfaces 40 a of the plurality of second semiconductor chips 40 .

[0305] At this time, the peripheral edge portion Cs on the bonding surface side of the second semiconductor chip 40 is over-polished, as shown in FIG. Fig.19 As shown, the peripheral edge portion Cs including four sides ( 40 a 1 , 40 a 2 , 40 a 3 , 40 a 4 ) of the bonding surface 40 a of the second semiconductor chip 40 is in a curved shape that curves over the bonding surface 40 a and the side surfaces of the second semiconductor chip 40 . Fig.19 In the cross section of the second semiconductor chip 40 in the X direction, peripheral edge portions Cs on both sides 40 a 1 , 40 a 2 of the bonding surface 40 a are shown.

[0306] Next, after performing the surface modification process of activating the bonding surface 40 a of the second semiconductor chip 40 , the second semiconductor chip 40 is transferred to a die bonding process during a process of manufacturing the solid-state imaging device 1A described below.

[0307] <Formation of Multilayer Wiring Layers>

[0308] Next, refer to Fig. 20 and Fig.21 The formation of the multilayer wiring layer 45 including the warpage suppression film 45b and the bonding surface 40a is described. The multilayer wiring layer 45 is formed in a wafer state before the plurality of chip formation regions 65 of the semiconductor wafer 70 are divided into small pieces to form the second semiconductor chips 40.

[0309] First, if Fig. 20 As shown in (a) of FIG. 1 , a multi-stage stacked portion 45 a in which insulating layers and wiring layers are alternately stacked in multiple layers is formed on the semiconductor layer 42 on the element formation surface side.

[0310] Then, if Fig. 20As shown in (b), a warpage suppression film 45b is formed on the entire surface of the multi-stage stacked portion 45a on the side opposite to the semiconductor layer 42. As the warpage suppression film 45b, for example, an insulating film such as a silicon nitride (SiN) film, a metal film such as an aluminum (Al) film, a copper (Cu) film or an alloy film thereof, or a resin film can be used. In the first embodiment, a silicon nitride film is formed as the warpage suppression film 45b by, for example, a CVD method.

[0311] Next, the warpage suppression film 45b is patterned into a predetermined shape, such as Fig. 20 As shown in (c), a warpage suppression film 45b having a prescribed shape is formed on the multi-stage stacked portion 45a. Patterning of the warpage suppression film 45b is performed using known photolithography technology and anisotropic dry etching technology.

[0312] Although not shown in detail, the warpage suppression film 45b is formed in a shape extending in a plan view along at least one of the four sides of the chip forming region 75. In the first embodiment, the warpage suppression film 45b is formed in a ring-shaped pattern extending continuously along the four sides of the chip forming region 75 in a plan view, for example, but is not limited thereto.

[0313] Then, if Fig. 20 As shown in (d), the insulating layer 46 covering the warpage suppression film 45b is formed on the entire surface of the multi-stage stacked portion 45a on the side opposite to the semiconductor layer 42. The insulating layer 46 can be formed by forming a silicon oxide film by CVD method, for example.

[0314] Then, if Fig.21 As shown in (e), a recessed portion 46a is formed in the surface layer portion of the insulating layer 46 on the side opposite to the multilayer buildup portion 45a. The recessed portion 46a is formed using known photolithography technology and anisotropic dry etching technology.

[0315] Then, if Fig.21 As shown in (f), a metal film 47A that buries the recessed portion 46a is formed on the entire surface of the insulating layer 46 on the side opposite to the multilayer laminated portion 45a. As the metal film 47A, for example, a metal film of aluminum (Al), copper (Cu), or an alloy film mainly containing an alloy of Al or Cu can be used. These metal films and alloy films can be formed by, for example, sputtering.

[0316] Next, the metal film 47A on the insulating layer 46 is selectively removed so that the metal film 47A remains in the concave portion 46a of the insulating layer 46, and Fig.21 As shown in (g) of FIG. 4 , a bonding metal pad 47 is formed in the recess 46a of the insulating layer 46. For example, the selective removal of the metal film 47A is performed by a CMP method.

[0317] Through this process, a bonding surface 40 a including the insulating layer 46 and the bonding metal pads 47 interspersed with the insulating layer 46 is formed in the chip formation region 75 .

[0318] In addition, through this process, the multilayer wiring layer 45 including the multi-stage stacked portion 45 a , the warp suppressing film 45 b , and the bonding surface 40 a is formed.

[0319] <<Method for manufacturing a solid-state imaging device>>

[0320] Next, we will refer to Figures 22 to 34 A method of manufacturing the solid-state imaging device 1A is described.

[0321] Fig. 22 It is a diagram showing a planar structure of a wafer stack. Fig.23 2 is a longitudinal sectional view schematically showing the longitudinal sectional structure of the wafer stack 60 . Fig.24 is schematically shown by enlarging Fig.23 Schematic diagram of the configuration of the chip formation region 65 in region B.

[0322] also, Fig.25 , Fig. 27 , Fig.31 and Fig.34 is a plan view schematically showing the process of a method of manufacturing the solid-state imaging device 1A,

[0323] Fig.26 is a schematic diagram showing the Fig.25 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a25-a25 in FIG.

[0324] Fig.28 is a schematic diagram showing the Fig. 27 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a27-a27 in FIG.

[0325] Fig.29 yes Fig.28 A partially enlarged longitudinal cross-sectional view of

[0326] Fig.30 is a schematic diagram showing the Fig. 27 A longitudinal cross-section of the process followed;

[0327] Fig.33 is a schematic diagram showing the Fig.31 A longitudinal cross-section of the subsequent process; and

[0328] Fig.34 It is schematically shown Fig.33 Floor plan of the after process.

[0329] Here, the first semiconductor chip 20 included in the solid-state imaging device 1A is Fig.24 The chip forming regions 65 of the wafer stack 60 shown in FIG. The chip forming regions 65 are divided by scribe lines (dicing lines) 66 extending in each of the X direction and the Y direction, and a plurality of chip forming regions are arranged in a matrix. Fig.24 An example of nine chip formation regions 65 arranged in a three-by-three matrix in the X direction and the Y direction is shown. Then, the plurality of chip formation regions 65 are divided into small pieces along the scribe lines 66, thereby forming the first semiconductor chip 20. The chip formation region 65 is divided into small pieces after performing the manufacturing process described below.

[0330] Note that scribe line 66 is not physically formed.

[0331] like Fig. 22 and Fig.23 As shown, the wafer stack 60 includes two semiconductor wafers 61 and 62 stacked on each other.

[0332] The semiconductor wafer 61 includes a semiconductor layer 22 , a multilayer wiring layer 23 stacked on the semiconductor layer 22 on the element forming surface side, and a multilayer wiring layer 25 stacked on the semiconductor layer 22 on the opposite side to one side of the multilayer wiring layer 23 .

[0333] The semiconductor wafer 62 includes a semiconductor layer 32 and a multilayer wiring layer 33 stacked on the semiconductor layer 32 on the element forming surface side. Then, the semiconductor wafers 61 and 62 are bonded in a state where the multilayer wiring layer 23 side of the semiconductor wafer 61 is opposed to the multilayer wiring layer 33 side of the semiconductor wafer 62.

[0334] Figures 25 to 34 2 is a diagram illustrating a chip forming region 65 of the wafer stack 60. Fig.25 and Fig.26 A state in which a wafer stacking process is performed to form a wafer stacked body 60 in the process of manufacturing the solid-state imaging device 1A is shown.

[0335] like Fig.26As shown, the chip forming region 65 includes a multilayer wiring layer 25, a semiconductor layer 22, a multilayer wiring layer 23, a multilayer wiring layer 33, and a semiconductor layer 32. Then, the bonding metal pad 24 of the multilayer wiring layer 23 and the bonding metal pad 34 of the multilayer wiring layer 33 are bonded by direct bonding, and conduction is established between the multilayer wiring layer 23 and the multilayer wiring layer 33. Then, the uppermost insulating layer 26 of the multilayer wiring layer 23 and the uppermost insulating layer of the multilayer wiring layer 23 are directly bonded. Moreover, the chip forming region 65 has a bonding surface 20a on the multilayer wiring layer 25 on the side opposite to the semiconductor layer 22 side. Then, the bonding surface 20a includes the uppermost insulating layer 26 of the multilayer wiring layer 25 and a bonding metal pad 27 provided in the insulating layer 26 in a state where the surface (bonding surface) is exposed from the insulating layer 26. The bonding metal pad 27 is provided in the chip mounting region Cm. Then, in the chip forming region 65, a Figure 3 The pixel array unit 2A shown in Figure 1 and Figure 2 The logic circuit 13, pads (input / output terminals) 14, pixel circuits 15, etc. shown in FIG. Next, a process after the wafer stack 60 is formed (a process after the wafer stacking process) will be described.

[0336] Note that in the first embodiment, the case where the photoelectric conversion region 35, the optical filter layer 36, and the microlens 37 are also formed will be described, but the photoelectric conversion region 35, the optical filter layer 36, and the microlens 37 may be formed after the sealing body forming process to be described below.

[0337] In the formation Fig.25 and Fig.26 After the wafer stack 60 is formed, Fig. 27 and Fig.28 As shown, the second semiconductor chip 40 is mounted in the chip forming region 65 of the wafer stack 60. The second semiconductor chip 40 is mounted by directly bonding the bonding surface 40a of the second semiconductor chip 40 and the bonding surface 20a of the wafer stack 60 (bonding surface 20a of the first semiconductor chip 20).

[0338] Specifically, first, the bonding surface 20a of the wafer stack 60 is subjected to an activated surface modification process. In this surface modification process, for example, the bonding surface 20a of the wafer stack 60 is irradiated with plasma to remove oxides and adsorbents and generate dangling bonds of atoms. In addition, in the above-mentioned surface modification process for activating the bonding surface 40a of the second semiconductor chip 40, dangling bonds of atoms are generated, for example, by plasma irradiation.

[0339] In this process, the surface improvement process is performed on the surfaces of the insulating layer 26 and the bonding metal pad 27 included in the bonding surface 20a of the wafer stack body 60. In addition, in the second semiconductor chip 40, the surface of each of the insulating layer 46 and the bonding metal pad 47 included in the bonding surface 40a is subjected to the surface improvement process.

[0340] Then, if Fig.29 As shown, the second semiconductor chip 40 is placed on the chip forming area 65 (chip mounting area Cm) of the wafer stack 60 while the bonding surface 20a and the bonding metal pad 27 of the wafer stack 60 that have undergone surface improvement treatment, and the bonding surface 40a and the bonding metal pad 47 of the second semiconductor chip 40 that have undergone surface improvement treatment are relative to each other.

[0341] Next, Fig.29 In the state shown, the bonding surface 40 a of the second semiconductor chip 40 is press-bonded (compressed) to the bonding surface 20 a of the wafer stack 60 , and a bonding wave is generated from the center portion toward the periphery within the two-dimensional surface of the second semiconductor chip 40 .

[0342] Through this treatment, the dangling bonds of the bonding surface 20a of the wafer stack 60 and the dangling bonds of the bonding surface 40a of the second semiconductor chip 40 are bonded, and the bonding surface 20a of the wafer stack 60 and the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activation bonding. Specifically, the insulating layer 26 included in the bonding surface 20a of the wafer stack 60 and the insulating layer 46 included in the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activation bonding, and the bonding metal pad 27 included in the bonding surface 20a of the wafer stack 60 and the bonding metal pad 47 included in the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activation bonding.

[0343] In addition, in this process, Fig.29 As shown, since the peripheral portion Cs on the bonding surface 40a side of the second semiconductor chip 40 is a curved surface, the peripheral portion Cs on the bonding surface 40a side of the second semiconductor chip 40 can also be separated from the bonding surface 20a of the wafer stack 60 (first semiconductor chip 20).

[0344] Then, if Fig.30 As shown, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 in the Z direction is reduced to make the second semiconductor chip 40 thinner. The thinning of the second semiconductor chip 40 is a process for thinning the solid-state imaging device 1A. For example, by grinding the surface layer portion of the semiconductor layer 42 on the side opposite to the multilayer wiring layer 45 side by the CMP method, the thickness of the semiconductor layer 42 in the Z direction can be reduced.

[0345] Here, the rigidity of the second semiconductor chip 40 is reduced by reducing the thickness of the semiconductor layer 42. Due to the reduction in rigidity, in conventional semiconductor chips, such as Fig.30 As shown, in the chip forming area 65 (the bonding surface 20a of the first semiconductor chip 20) of the wafer stack 60, a bending is performed so that the peripheral portion of the second semiconductor chip 40 (the peripheral portion Cs side of the second semiconductor chip 40) is peeled off from the bonding surface 20a, that is, warping with the bonding surface 40a of the second semiconductor chip 40 as a convex surface can occur in the second semiconductor chip 40.

[0346] In contrast, Fig.30 As shown, the second semiconductor chip 40 of the first embodiment includes the warping suppression film 45 b for suppressing the warping of the second semiconductor chip 40 , and can suppress the bending of the second semiconductor chip 40 due to the reduction in the rigidity of the second semiconductor chip 40 .

[0347] Then, if Fig.31 , Fig.32 As shown, a sealing body 51 covering the two second semiconductor chips 40 is formed on the bonding surface 20a side of the wafer stack 60, and a flattened surface portion is provided in the chip forming region 65 on the side opposite to the bonding surface 20a side. The sealing body 51 can be formed, for example, as follows: a sealing material is formed in the chip forming region 65 in a manner covering the entire second semiconductor chip 40, and then, for example, the surface of the sealing material is flattened by a chemical mechanical polishing (CMP) method. As a sealing material, for example, an epoxy-based thermosetting insulating resin or a polyimide-based thermoplastic insulating resin can be used. In addition, as a sealing material, a silicon oxide-based material with high fluidity, such as phosphosilicate glass (PSG), can also be used.

[0348] At this time, the two second semiconductor chips 40 are sealed by the sealing body 51 .

[0349] Note that the sealing body 51 may be formed by selectively forming a sealing material outside the second semiconductor chip 40 by spin coating or the like in the chip formation region 65 to expose the upper surface side of the semiconductor layer 42 of the second semiconductor chip 40 .

[0350] Next, if Fig.33 As shown, a bonding opening 38 is formed that penetrates the semiconductor layer 32 and exposes the surface of the bonding pad 14 .

[0351] Then, thereafter, the plurality of chip forming regions 65 of the wafer stack 60 are respectively divided into small pieces along the scribe lines 66, so that Fig.34As shown, the first semiconductor chip 20 including the first substrate unit 21 and the second substrate unit 31 is formed, and a chip stack body is formed in which the bonding surface 40a of the second semiconductor chip 40 is bonded to the bonding surface 20a of the first semiconductor chip 20 by direct bonding. Then, the solid-state imaging device 1A including the first semiconductor chip 20, the second semiconductor chip 40 and the sealing body 51 is almost completed.

[0352] <<Main Effects of First Embodiment>>

[0353] The second semiconductor chip 40 of the solid-state imaging device 1A according to the first embodiment of the present technology includes: a multilayer wiring layer 45 including a second bonding surface; and a semiconductor layer 42 provided on the multilayer wiring layer 45 on the side opposite to the second bonding surface 40a side. And, the multilayer wiring layer 45 has a warpage suppression film 45b that extends in a ring shape along four sides (40a1, 40a2, 40a3, 40a4) of the second bonding surface 40a and suppresses the second semiconductor chip 40.

[0354] Therefore, in the process of manufacturing the solid-state imaging device 1A, even after the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 is reduced, the bending of the second semiconductor chip 40 caused by the reduction in the rigidity of the second semiconductor chip 40 can be suppressed, cracks, peeling of the second semiconductor chip 40, etc. can be suppressed, which leads to a reduction in the manufacturing yield of the solid-state imaging device 1A. Therefore, the solid-state imaging device 1A according to the first embodiment can improve the manufacturing yield.

[0355] In addition, since the warp suppression film 45b extends along the sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, by changing the length in the long side direction, the width or thickness in the short side direction, it is possible to control the local film stress of the second semiconductor chip 40 in accordance with the stress strain causing the warping of the second semiconductor chip 40. Therefore, in order to control the local film stress of the second semiconductor chip 40, the thickness t1 of the warp suppression film 45b is thicker than the thickness t2 of the wiring 45a1 of the multilayer wiring layer 45 (t1>t2). Moreover, the thickness t1 of the warp suppression film 45b is preferably greater than the thickness t3 of the bonding metal pad 47 of the multilayer wiring layer 45.

[0356] <<Modification of the first embodiment>>

[0357] Next, a modification of the first embodiment will be described.

[0358] <Variation 1-1>

[0359] In the first embodiment, the case where the warpage suppression film 45b overlaps the side surfaces (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view is described. However, the warpage suppression film 45b is not limited to the first embodiment.

[0360] For example, as a variation 1-1, Fig.35 As shown, when viewed from above, the warp suppression film 45b is arranged on the inner side of the side surfaces (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40. In this case, the warp suppression film 45b is peeled off from the side surfaces of the second semiconductor chip 40 (the side surfaces of the multilayer wiring layer 42) toward the inner side.

[0361] <Variation 1-2>

[0362] In the first embodiment, the warping suppression film 45b is described as extending in a ring shape along four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40. However, the warping suppression film 45b is not limited to the ring pattern of the first embodiment.

[0363] For example, as a variation 1-2, Fig.36 As shown, the warpage suppression film 45 b is spread along four sides ( 40 a 1 , 40 a 2 , 40 a 3 , 40 a 4 ) of the bonding surface 40 a of the second semiconductor chip 40 .

[0364] <Variation 1-3>

[0365] Furthermore, as a variation 1-3, it is also possible to Fig.37 As shown, among the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, the warp suppression film 45b is independently arranged on the two long sides (40a1, 40a2) opposite to each other in the X direction. In this case, the warp suppression film 45b extends along the two long sides 40a1, 40a2.

[0366] <Variation 1-4>

[0367] Furthermore, as a modification 1-4, it is also possible to Fig.38 As shown, among the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, the warp suppression film 45b is independently arranged on the two short sides (40a3, 40a4) located opposite to each other in the Y direction. In this case, the warp suppression film 45b extends along the two long sides 40a1, 40a2.

[0368] In short, the warpage suppression film 45b only needs to extend along at least one of the four sides of the bonding surface of the second semiconductor chip 40. That is, the warpage suppression film 45b only needs to exist on at least a portion of the bonding surface on the peripheral portion Cs side of the second semiconductor chip in a plan view.

[0369] In addition, in the first to fourth modified examples, the same effects as those of the above-mentioned first embodiment can be obtained.

[0370] <Variation 1-5>

[0371] Fig.39 : is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-5 of the first embodiment of the present technology.

[0372] Modification 1-5 is an example of a case where the warping of the corner portion Cr side of the second semiconductor chip 40 is selectively suppressed.

[0373] Reference Fig.39 Since the planar shape of the second semiconductor chip 40 is a quadrilateral, the stress caused by the difference in linear expansion coefficient between the semiconductor layer 21 and the multilayer wiring layer 45 is easily concentrated on the corner Cr where the two sides of the bonding surface 40a intersect when viewed from above, and floating (warping) is most likely to occur at the corner Cr. Therefore, the warping suppression film 45 can be selectively provided near the corner Cr where two sides with different extension directions (specifically, the side 40a1 or 40a2 extending in the Y direction and the side 40a3 or 40a4 extending in the X direction) intersect at the bonding surface 40a of the second semiconductor chip 40, and the warping of the bonding surface 40a on the corner Cr side can be selectively suppressed.

[0374] For example, Fig.39 As shown, the warpage suppression film 45a may be formed into a shape that selectively extends in a plan view at least on both sides of the corner Cr of the bonding surface 40a including the second semiconductor chip 40. Specifically, on the bonding surface 40a, a warpage suppression film 45b extending on both sides 40a1 and 40a4 including the corner Cr1, a warpage suppression film 45b extending on both sides 40a1 and 40a3 including the corner Cr2, a warpage suppression film 45b extending on both sides 40a2 and 40a4 including the corner Cr3, or a warpage suppression film 45b extending on both sides 40a2 and 40a3 including the corner Cr4 may be selectively provided.

[0375] In this case, if Fig.39As shown, a warpage suppression film 45b may be selectively provided for each of the four corners Cr (Cr1, Cr2, Cr3, and Cr4) of the bonding surface 40a. In addition, although not shown, even in the four corners Cr (Cr1, Cr2, Cr3, Cr4), since the degree of bending varies depending on the structure of the chip, a warpage suppression film may be selectively provided for at least one of the four corners Cr (Cr1, Cr2, Cr3, Cr4). In this case, the warpage suppression film 45b has an L-shaped plane shape.

[0376] Note that the corner portion Cr of the joint surface 40 a is included in the peripheral edge portion Cs of the joint surface 40 a .

[0377] <Variation 1-6>

[0378] Fig.40 : is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-6 of the first embodiment of the present technology.

[0379] Modification 1-6 is an example in which the countermeasure against the warping of the second semiconductor chip 40 on the corner portion Cr side is further strengthened.

[0380] like Fig.40 As shown, the warping suppression film 45b can be configured so that a first width W1 on the outer side (corner side) and the inner side of a first portion 45b1 adjacent to a corner Cr (Cr1, Cr2, Cr3 or Cr4) connecting the joining surface 40a in a plan view is wider than a second width W2 on the outer side (side) and the inner side of a second portion 45b2 adjacent to a side surface (40a1, 40a2, 40a3 or 40a4) connecting the joining surface 40a in a plan view.

[0381] Specifically, for example, the description Fig.40 The corner portion Cr1 shown in FIG. 4 is taken as an example. In the plan view, in the warpage suppression film 45b selectively extending along the two sides 40a1 and 40a4 of the corner portion Cr1 including the bonding surface 40a, in the plan view, the first width W1 connecting the outer end portion located on the corner portion Cr1 side and the inner end portion located on the opposite side (bonding metal pad 47 side) of the outer end portion (corner portion Cr1 side) in the first portion 45b1 adjacent to the corner portion Cr1 of the bonding surface 40a is wider than the second width W2 connecting the outer end portion located on the side of the side 40a1 or 40a4 and the inner end portion located on the opposite side (side 40a1 or 40a4 side) of the outer end portion (side 40a1 or 40a4 side) in the second portion 45b2 adjacent to the side 40a1 or 40a4 of the bonding surface 40a.

[0382] In the case of the warpage suppression film 45b of Modification 1-6, the area at the corner portion Cr of the bonding surface 40 can be selectively increased. Therefore, compared with the warpage suppression film 45b of Modification 1-5, the protection against warpage of the bonding surface 40a on the corner portion Cr side can be further enhanced.

[0383] Note that in a plan view, by tilting the inner end of the first portion 45b1 relative to the side (40a1, 40a2, 40a3 or 40a4) of the joining surface 40a, the first width W1 of the first portion 45b1 can be made wider than the second width W2 of the second portion 45b2.

[0384] <Variation 1-7>

[0385] Fig.41 : is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-7 of the first embodiment of the present technology.

[0386] like Fig.41 As shown, in variation 1-7, Fig.40 The corner expansion technique of the modification 1-6 shown is applied to the warp suppression film 45 b of the above-mentioned first embodiment.

[0387] That is, Fig.41 As shown, the warpage suppression film 45b of modification example 1-7 is provided on the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, and has an annular planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4). Then, in the warping suppression film 45b having a ring-shaped planar pattern, a first width W1 connecting the outer end portion on the corner Cr1 side and the inner end portion on the opposite side (the bonding metal pad 47 side) to the outer end portion (corner Cr1 side) in the first portion 45b1 adjacent to the corner Cr1 of the bonding surface 40a in a plan view is wider than a second width W2 connecting the outer end portion on the edge 40a1 or 40a4 side and the inner end portion on the opposite side (the bonding metal pad 47 side) to the outer end portion (edge ​​40a1 or 40a4 side) in the second portion 45b2 adjacent to the edge 40a1 or 40a4 of the bonding surface 40a.

[0388] In the case of the warpage suppression film 45b of Modification 1-7, the area of ​​the corner Cr of the bonding surface 40a can also be selectively increased. Therefore, compared with the warpage suppression film 45b of the first embodiment, the protection of the bonding surface 40a against warpage on the corner Cr side can be further strengthened.

[0389] <Variation 1-8>

[0390] Fig.42: is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-8 of the first embodiment of the present technology.

[0391] In Modification 1-8, the planar shape of the first portion 45b1 of the warpage suppression film 45b is a quadrilateral, and the first width W1 of the first portion 45b1 is wider than the second width W2 of the second portion 45b2. That is, in Modification 1-8, each of the outer end and the inner end of the first portion 45b1 has a corner.

[0392] In the warp suppression film 45b of Modification 1-8, the area of ​​the corner Cr of the bonding surface 40 can also be selectively increased. Therefore, compared with the warp suppression film 45b of the first embodiment, the protection against warping of the bonding surface 40a on the corner Cr side can be further strengthened.

[0393] <Variation 1-9>

[0394] Fig.43 : is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-9 of the first embodiment of the present technology.

[0395] In Modification 1-9, in the first portion 45b1 of the warpage suppression film 45b, the planar shape of the inner end portion is made arc-shaped, and the first width W1 of the first portion 45b1 is made wider than the second width W2 of the second portion 45b2.

[0396] In the warp suppression film 45b of Modification 1-9, the area of ​​the corner Cr of the bonding surface 40 can also be selectively increased. Therefore, compared with the warp suppression film 45b of the first embodiment, the protection against warping of the bonding surface 40a on the corner Cr side can be further enhanced.

[0397] <Variation 1-10>

[0398] Fig.44 is a plan view schematically showing the configuration of a second semiconductor chip according to Modification 1-10 of the first embodiment of the present technology.

[0399] In Modification 1-10, the planar shape of the inner end of the warpage suppression film 45 b is made elliptical, and the first width W1 of the first portion 45 b 1 is made wider than the second width W2 of the second portion 45 b 2 .

[0400] In the warp suppression film 45b of Modification 1-9, the area of ​​the corner Cr of the bonding surface 40 can also be selectively increased. Therefore, compared with the warp suppression film 45b of the first embodiment, the protection against warping of the bonding surface 40a on the corner Cr side can be further enhanced.

[0401] <Variations 1-11 to 1-14>

[0402] Figures 45 to 48 It is a diagram schematically showing a mesh pattern of film quality of the warpage suppression film 45 b according to Modifications 1-11 to 1-14 of the first embodiment of the present invention.

[0403] As for its own film quality (film state), the warpage suppression film 45b may be composed of a normal solid film or may be composed of a Figures 45 to 48 The mesh plane pattern shown.

[0404] Fig.45 The mesh planar pattern of the modification 1-11 shown in FIG. 1 has a checkered pattern, wherein the openings 45b 11 and membrane portion 45b 12 Arranged alternately and repeatedly in each of the X direction and the Y direction.

[0405] also, Fig.46 The mesh planar pattern of the modification 1-12 shown in FIG. 1 has a checkered pattern, wherein the openings 51 b 11 and membrane portion 45b 12 The arrangement is alternately and repeatedly in an oblique direction with respect to the X direction and the Y direction.

[0406] also, Fig.47 The mesh planar pattern of the modification 1-13 shown in FIG. 1 is a lattice planar pattern in which a plurality of first thin film portions 51 b extending in the X direction and arranged at predetermined intervals in the Y direction 13 and a plurality of second thin film portions 51 b extending in the Y direction and arranged at predetermined intervals in the X direction 14 intersect in the same plane.

[0407] also, Fig.48 The mesh planar pattern of the modification 1-14 shown in FIG. 1 is the first film portion 45b in a different layer in the plan view. 15 and the second membrane portion 45b 16 A mesh-like flat pattern that crisscrosses in a lattice-like manner.

[0408] In addition, in Modifications 1-11 to 1-14, the same effects as those of the above-described first embodiment can be obtained.

[0409] Furthermore, the mesh patterns of Modifications 1-11 to 1-14 can also be applied to the warpage suppression films 45 b of Modifications 1-2 to 1-10 described above.

[0410] <Variation 1-15>

[0411] Fig.491 is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-15 of the first embodiment of the present technology.

[0412] In Modification 1-15, unlike the warp suppression film 45b of the first embodiment described above, a warp suppression film 45c is selectively provided near the corner Cr of the bonding surface 42a in plan view. The warp suppression film 45c is separated from the warp suppression film 45b in plan view.

[0413] The warp suppression film 45c is not limited thereto, and may be, for example, a quadrilateral planar shape and arranged inside the warp suppression film 45b. The warp suppression film 45c is formed, for example, on the same layer as the warp suppression film 45c in the inner layer of the multilayer wiring layer 45.

[0414] As the warpage suppression film 45c, similar to the warpage suppression film 45b, an insulating film such as a silicon nitride (SiN) film, a metal film such as an aluminum (Al) film, a copper (Cu) film or an alloy film thereof, or a resin film can be used. In Modification 1-15, the warpage suppression film 45b is also composed of, for example, a silicon nitride film.

[0415] The planar size of the warpage suppression film 45c is preferably larger than the planar size of the bonding metal pad 47. In addition, the warpage suppression film 45c is preferably provided on the outside of the bonding metal pad 47, that is, on the side (40a1, 40a2, 40a3 or 40a4) of the bonding surface 40a relative to the bonding metal pad 47, and on the inside of the warpage suppression film 45c.

[0416] In modification 1-15, a warp suppression film 45c different from the tangential warp suppression film 45b is provided near the corner Cr of the joining surface 40a in a plan view, so that protection against warping of the joining surface 40a on the corner Cr side can be further enhanced compared with the above-mentioned first embodiment.

[0417] <Variation 1-16>

[0418] Fig.50 It is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-16 of the first embodiment of the present technology.

[0419] like Fig.50 As shown, in Modification 1-16, unlike the warpage suppression film 45b of the first embodiment described above, a plurality of warpage suppression films 45c are selectively provided near the corner Cr of the bonding surface 42a in a plan view. In addition, in Modification 1-16, similar to Modification 1-15, protection against warpage of the bonding surface 40a on the corner Cr side can be further enhanced compared to the first embodiment described above.

[0420] <Variation 1-17>

[0421] Fig.51 1 is a plan view schematically showing a main part of the configuration of the second semiconductor chip 40 according to Modification 1-17 of the first embodiment of the present technology.

[0422] like Fig.51 As shown, in Modification 1-17, as the film quality state of the warpage suppression film 45b, the warpage suppression film 45b is composed of a general solid film, and the warpage suppression film 45c is composed of a mesh plane pattern. In addition, in Modification 1-17, similar to Modification 1-15, compared with the above-mentioned first embodiment, the protection against warpage of the bonding surface 40a on the corner Cr side can be further strengthened.

[0423] Note that, in contrast to Modification 1-17, the warp suppression film 45b may be formed as a mesh planar pattern, and the warp suppression film 45c may be formed as a general solid film. In addition, the warp suppression films 45b and 45c may also be formed of a general solid film, or the warp suppression films 45b and 45c may also be formed of a mesh pattern.

[0424] <Variation 1-18>

[0425] Fig.52 1 is a plan view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-18 of the first embodiment of the present technology.

[0426] Fig.53 is a cross-sectional view schematically showing the configuration of the second semiconductor chip 40 according to Modification 1-18 of the first embodiment of the present technology ( Fig.53 (a) schematically shows the Fig.52 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a52-a52 in FIG. Fig.53 (b) schematically shows the Fig.52 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b52-b52 in FIG.

[0427] like Fig.52 and Fig.53 As shown in (a) and (b) of FIG. 1 , in Modification 1-18, the film thickness of the warpage suppression film 45b is different between the first portion 45b1 and the second portion 45b2. That is, in the warpage suppression film 45b of Modification 1-18, the film thickness of the first portion 45b1 adjacent to the corner Cr1 of the bonding surface 40a in a plan view is greater than the film thickness of the second portion 45b2 adjacent to the side surface of the bonding surface 40a in a plan view.

[0428] In addition, in Modification 1-18, compared with the above-described first embodiment, protection against warping of the joining surface 40 a on the corner Cr side can be further enhanced.

[0429] <Variation 1-19>

[0430] Fig.54 is a schematic diagram showing the modification 1-19 of the first embodiment of the present technology. Fig.52 A longitudinal cross-sectional view of the longitudinal cross-sectional structure at the same position of the cutting line b52 - b52 shown.

[0431] like Fig.54 As shown, in Modification 1-19, the warpage suppression film 45b is composed of a stacked film in which a plurality of films are stacked in multiple stages. As the film, films of the same substance may be stacked in multiple layers, or films of different substances may be stacked in multiple layers.

[0432] In the modification 1-18, the same effects as those of the above-mentioned first embodiment can be obtained.

[0433] It should be noted that, although not shown, Modification 1-19 can be combined with each of the above-described Modifications 1-1 to 1-18.

[0434] [Second Embodiment]

[0435] In the second embodiment, an example in which a warpage suppressing film is provided on the bonding surface 40 a of the second semiconductor chip 40 and each inner layer of the multilayer wiring layer 45 will be described.

[0436] Fig.55 1 is a plan view schematically showing a main part of a configuration example of a solid-state imaging device 1B according to a second embodiment of the present technology.

[0437] Fig.56 is schematically shown along Fig.55 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a55-a55.

[0438] Fig.57 2 is a plan view schematically showing the bonding surface side of the second semiconductor chip 40 .

[0439] Fig.58A is schematically shown along Fig.57 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a57-a57.

[0440] Fig.58B yes Fig.58A A partial enlarged longitudinal section view.

[0441] Fig.591 is a plan view schematically showing the planar shape of a warp suppression film 45 b provided in an inner layer of the multilayer wiring layer 45 of the second semiconductor chip 40 .

[0442] It should be noted that Fig.55 Corresponding to the first embodiment described above Figure 7 .

[0443] like Fig.55 and Fig.56 As shown, the solid-state imaging device 1B according to the second embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0444] That is, Fig.56 and Fig.57 As shown in FIG. 1 , the second semiconductor chip 40 of the second embodiment further includes a warpage suppressing film 45 d as a warpage suppressing portion on the bonding surface 40 a. The other structures are substantially the same as those of the first embodiment described above.

[0445] like Fig.56 , Fig.57 , Fig.58A As shown, a warpage suppression film 45d is provided on the multilayer wiring layer 45. That is, the multilayer wiring layer 45 of the second embodiment includes a multi-stage stacked portion 45a, a warpage suppression film 45b, an insulating layer 46, and a bonding metal pad 47, and further includes the warpage suppression film 45d.

[0446] As described above, the insulating layer 46 is the uppermost insulating layer of the multilayer wiring layer 45, and the surface of the insulating layer 46 is the bonding surface 40a of the second semiconductor chip 40. That is, the bonding surface 40a of the second semiconductor chip 40 of the second embodiment includes the uppermost insulating layer 46 of the multilayer wiring layer 45, the bonding metal pad 47 sandwiching the insulating layer 46, and the warpage suppression film 45d. That is, the semiconductor chip 40 of the second embodiment has the warpage suppression film 45b provided in the inner layer of the multilayer wiring layer 45 and the warpage suppression film 45d provided on the bonding surface 40a of the multilayer wiring layer 45.

[0447] Like the bonding metal pad 47, the warpage suppression film 45d is provided on the insulating layer 46 of the multilayer wiring layer 45 in a state where the bonding surface side is exposed. Then, the bonding surface 40a is substantially flat with the steps between the warpage suppression film 45d and the bonding metal pad 47 and the insulating layer 46 as small as possible.

[0448] The warpage suppression film 45 d is not limited thereto, and is, for example, formed in the same process as the bonding metal pad 47 and is composed of the same metal material as the bonding metal pad 47 .

[0449] like Fig.57As shown, the warpage suppression film 45d is provided on at least a portion of the peripheral portion Cs side of the bonding surface 40a of the second semiconductor chip 40. In the second embodiment, similarly to the warpage suppression film 45b of the first embodiment, Fig.57 As shown, the warpage suppression film 45d is provided in the second semiconductor chip 40 on the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a, and has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4). Moreover, the warpage suppression film 45d overlaps with the side (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view, and is exposed from the side of the second semiconductor chip 40, that is, the side of the multilayer wiring layer 45. That is, the warpage suppression film 45d is provided on the side of the bonding surface 40a and the multilayer wiring layer 45.

[0450] The warp suppression film 45d is also arranged at the peripheral portion (peripheral portion Cs side) of the second semiconductor chip 40 in the same manner as the warp suppression film 45b, thereby controlling the local film stress of the second semiconductor chip 40 and suppressing the warping of the second semiconductor chip 40. For the warp suppression film 45d, a material having a linear expansion coefficient different from that of the surrounding multi-stage stacked portion 45a and the insulating layer 46 is used. In addition, the rigidity is increased by using a dense film with a low shrinkage rate for the warp suppression film 45d. As a result, the warping of the peripheral portion of the semiconductor chip 40 caused by the difference in linear expansion coefficient can be suppressed.

[0451] like Fig.58B As shown, in the warpage suppression film 40d, the portion located on the bonding surface 40a side ( Fig.58B The outer end portion 40d of the side 40a1 side) 11 The thickness t4 is greater than that at the outer end 40d. 11 The inner end portion 40d on the opposite side 12 The thickness t5 is thin. (t4<t5). In the second embodiment, the bonding surface ( Fig.58B The upper surface in the figure is a curved surface, but may be a flat surface or a stepped surface. Regarding the structure of the thickness (t4<t5) of the warpage suppression film 40d, as shown in FIG. Fig.29 As shown, this is to suppress the generation of gaps on the bonding surface 40a on the peripheral portion Cs side of the second semiconductor chip 40 due to the gradual change of the bonding wave when the bonding surface 40a of the second semiconductor chip 40 is pressed (crimped) onto the bonding surface 20a of the wafer stack 60, thereby generating a bonding wave from the central portion toward the peripheral portion of the second semiconductor chip 40 in a two-dimensional plane.

[0452] In addition, if Fig.58BAs shown, in order to control the local film stress of the second semiconductor chip 40, the outer end portion 40d is preferably 11 and inner end 40d 12 At least the inner end 40d 12 The thickness t5 of the warp suppression film 45d is greater than the thickness t2 of the wiring 45a1 of the multilayer wiring layer 45 (t4>t2). 12 The thickness t5 of the multilayer wiring layer 45 is thicker than the thickness t3 of the bonding metal pad 47 .

[0453] like Fig.59 As shown, the warpage suppression film 45a of the second embodiment is also provided on the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, similarly to the first embodiment, and has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4). Therefore, the warpage suppression films 45d and 45b of the second embodiment extend along the peripheral portion Cs of the semiconductor chip 40 in a state of overlapping in a plan view.

[0454] <<Effects of the Second Embodiment>>

[0455] The second semiconductor chip 40 of the second embodiment is provided with two warpage suppression films 45d, 45b. Therefore, in the process of manufacturing the solid-state imaging device 1B, even after the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 is reduced, and in addition, the bending of the second semiconductor chip 40 caused by the reduction of the rigidity of the second semiconductor chip 40 can be further suppressed, and cracks, debris of the second semiconductor chip 40, etc. can be suppressed, which leads to a reduction in the manufacturing yield of the solid-state imaging device 1B. Therefore, the solid-state imaging device 1B according to the first embodiment can further improve the manufacturing yield.

[0456] Furthermore, in the warpage suppression film 45d according to the second embodiment, the Fig.58B The outer end portion 40d of the side surface 40a1 side) of the joint surface 40a 11 The thickness t4 is greater than that at the outer end 40d. 11 The inner end portion 40d on the opposite side 12 The thickness t5 is thin. (t4 <t5)。

[0457] Therefore, in the process of manufacturing the solid-state imaging device 1B, when the bonding surface 20a of the wafer stack 60 and the bonding surface 40a of the second semiconductor chip 40 are bonded by surface activation bonding, even if the bonding wave reaching the side (40a1, 40a2, 40a3 or 40a4) of the bonding surface 40a is before the corner Cr (Cr1, Cr2, Cr3 or Cr4) of the bonding surface 40a, as the arrival position where the bonding wave expands into a circle, a blank space 68 formed by the warpage suppression film 45d is formed in the bonding surface 40a on the corner Cr side, so that a gas such as an inert gas or air in the atmosphere can be released. Therefore, according to the solid-state imaging device 1B of the second embodiment, the generation of voids can be suppressed.

[0458] Furthermore, since the generation of voids can be suppressed, the manufacturing yield and reliability of the solid-state imaging device 1B can be further improved.

[0459] Note that in the above-mentioned second embodiment, the case where the warpage suppression film 45d is composed of the same material as the metal pad 47 has been described, but the warpage suppression film may be composed of other materials. In addition, the warpage suppression film 45d is preferably composed of a material different from the insulating layer of the multi-stage stacked portion 45a of the multi-layer wiring layer 45 or the uppermost insulating layer 46 of the multi-layer wiring layer 45, as is the case with the warpage suppression film 45b. For example, as the warpage suppression film 45d, an insulating film such as a silicon nitride (SiN) film, a metal film such as an aluminum (Al) film, a copper (Cu) film or an alloy film thereof, or a resin film can be used. In the first embodiment, the warpage suppression film 45d is composed of, for example, a silicon nitride film.

[0460] <<Modification of Second Embodiment>>

[0461] <Modification 2-1>

[0462] Fig.60A It is a plan view schematically showing a plan pattern of the warpage suppression film 45 d included in the bonding surface 45 a of the second semiconductor chip 40 in the modification 2-1 of the second embodiment of the present technology.

[0463] Fig.60B It is a plan view schematically showing a plan pattern of a warp suppression film included in an inner layer of the multilayer wiring layer 45 of the second semiconductor chip 40 in Modification 2-1 of the second embodiment of the present technology.

[0464] like Fig.60A and Fig.60B As shown, in the present modification 2-1, in the semiconductor chip 40, each of the warpage suppression films 45d, 45b is selectively provided near the corner Cr of the bonding surface 42a in a plan view.

[0465] In the present modification 2-1, compared with the above-described second embodiment, it is possible to more selectively strengthen the countermeasure against the warping of the bonding surface 40 a of the semiconductor chip 40 on the corner portion Cr side.

[0466] <Modification 2-2>

[0467] Fig.61A This is a plan view schematically showing a planar pattern of a warpage suppression film included in the bonding surface of the second semiconductor chip according to Modification 2-2 of the second embodiment of the present technique.

[0468] Fig.61B It is a plan view schematically showing a plan pattern of a warpage suppression film included in an inner layer of a multilayer wiring layer of a second semiconductor chip according to Modification 2-2 of the second embodiment of the present technology.

[0469] like Fig.61A and Fig.61B As shown, in Modification 2-2, each of the warpage suppression films 45d and 45c is configured as a mesh-shaped planar pattern as shown in Modification 1-11 described above.

[0470] In the modification 2-2, compared with the above-described second embodiment, it is possible to more selectively strengthen the protection against the warping of the bonding surface 40 a of the semiconductor chip 40 on the corner portion Cr side.

[0471] <Other Modifications>

[0472] In the second embodiment described above, the case where the warpage suppression films 45d and 45c have an annular planar shape has been described. However, the modification of the first embodiment described above may also be applied to the warpage suppression films 45d and 45c.

[0473] [Third Embodiment]

[0474] In the third embodiment, an example in which a warpage suppressing film is provided on the bonding surface 40 a and the side surface of the semiconductor chip 40 will be described.

[0475] Fig.62 1 is a plan view schematically showing a main part of a configuration example of a solid-state imaging device 1C according to a third embodiment of the present technology.

[0476] Fig.63 is schematically shown along Fig.62 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a62-a62 in FIG.

[0477] Fig.64 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0478] Fig.65A is schematically shown along Fig.64 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a64-a64.

[0479] Fig.65B yes Fig.65A A partial enlarged longitudinal section view.

[0480] It should be noted that Fig.62 Corresponding to the first embodiment described above Figure 7 .

[0481] like Figures 62 to 65B As shown, the solid-state imaging device 1C according to the third embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0482] That is, the second semiconductor chip 40 according to the third embodiment is as follows: Figures 62 to 65B As shown, instead of the first embodiment described above Figure 8 The warpage suppression portion shown, namely the warpage suppression film 45b, includes a warpage suppression film 45e provided on the second bonding surface 45b and the side surface of the multilayer wiring layer 45. The other structures are substantially the same as those of the first embodiment described above.

[0483] like Figures 62 to 65B As shown, the warpage suppression film 45e is provided on the bonding surface 40a and the side surface of the multilayer wiring layer 45, that is, the bonding surface 40a and the side surface of the second semiconductor chip 40. Next, the multilayer wiring layer 45 of the third embodiment includes the multilayer wiring layer 45a, the warpage suppression film 45e, the insulating layer 46 and the bonding metal pad 47.

[0484] Like the bonding metal pad 47, the warpage suppression film 45e is provided in the multilayer wiring layer 45 with the bonding surface side exposed. Then, the bonding surface 40a is substantially flat with the step between the warpage suppression film 45e and the bonding metal pad 47 and the insulating layer 46 as small as possible.

[0485] like Figures 62 to 65B As shown, the warpage suppression film 45e is selectively provided on the peripheral edge portion Cs side of the bonding surface 40a of the second semiconductor chip 40 when viewed from above. Although not shown, in the third embodiment, for example Figures 62 to 65BAs shown, the warpage suppression film 45e is provided on the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, and has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4) similarly to the warpage suppression film 45b of the first embodiment described above. Moreover, the warpage suppression film 45e overlaps with the side surfaces (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view, and is exposed from the side surfaces of the second semiconductor chip 40.

[0486] As with the above-mentioned warpage suppression film 45b, by configuring the warpage suppression film 45e at the peripheral portion (peripheral portion Cs side) of the second semiconductor chip 40, the local film stress of the second semiconductor chip 40 is controlled, and the warpage of the second semiconductor chip 40 is suppressed. For the warpage suppression film 45e, a material having a linear expansion coefficient different from that of the surrounding multi-stage stacking portion 45a and the insulating layer 46 is used. In addition, the rigidity is increased by using a dense film with a low shrinkage rate for the warpage suppression film 45d. As a result, the warpage of the peripheral side (peripheral Cs side) of the semiconductor chip 40 caused by the difference in linear expansion coefficient can be suppressed.

[0487] The warp suppression film 45e is bonded to the bonding surface 20a of the first semiconductor chip 20 (the bonding surface 20a of the chip forming region 65 of the wafer stack 60) by direct bonding. Here, in the case where the bonding surface 20a of the second semiconductor chip 20 is composed of a silicon oxide film, by using silicon nitride to constitute the warp suppression film 45e, the bonding strength between the bonding surface 20a of the base member 10 and the warp suppression film 45e can be improved. On the other hand, as a warp suppression film 45e for suppressing the warp of the second semiconductor chip 40, a silicon nitride film is useful. Therefore, by providing a warp suppression film 45e composed of a silicon nitride film on the peripheral portion Cs side of the bonding surface 40a of the second semiconductor chip 40, the warp suppression film 45e is directly bonded to the bonding surface 20a of the first semiconductor chip 20, thereby suppressing the warping of the second semiconductor chip 40 and improving the bonding strength between the first semiconductor chip 20 and the peripheral portion Cs side of the second semiconductor chip 40. Therefore, defects such as peeling of the second semiconductor chip 40 from the first semiconductor chip 20 can be suppressed, and thus the manufacturing yield of the solid-state imaging device 1C can be improved.

[0488] like Fig.65B As shown, the thickness t5 of the warpage suppression film 45e is larger than the width W3 (t5>W3). Thus, the internal stress of the second semiconductor chip 40 can be further increased compared to the first embodiment, and the warpage suppression effect can be further improved.

[0489] In addition, in the third embodiment, the case where the warpage suppression film 45e composed of a silicon nitride film is used is described. However, as long as it can suppress the warpage of the second semiconductor chip 40 and improve the bonding strength between the bonding surface 20a of the first semiconductor chip 20 and the bonding surface 40a of the second semiconductor chip 40, it is not limited to the silicon nitride film.

[0490] <<Modification of the Third Embodiment>>

[0491] <Variation 3-1>

[0492] Fig.66 3 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a second semiconductor chip according to Modification 3-1 of the third embodiment of the present technology.

[0493] like Fig.66 As shown, in Modification 3-1, the warpage suppression film 45 e extends over the bonding surface 40 a of the semiconductor chip 40 and the back surface opposite to the bonding surface 40 a , covering the side surfaces of the multilayer wiring layer 45 and the semiconductor layer 42 .

[0494] In the case of the modification 3-1, the countermeasure against the warping of the second semiconductor chip 40 can be further improved compared with the above-mentioned first embodiment.

[0495] <Other Modifications>

[0496] In the third embodiment described above, the case where the warp suppressing film 45 e has a ring-shaped planar pattern has been described. However, the warp suppressing film 45 e can also be applied to the modified example of the first embodiment described above.

[0497] [Fourth Embodiment]

[0498] In the fourth embodiment, an example in which the warpage suppression film 45 f is formed in the same process as the bonding metal pad 47 will be described.

[0499] Fig.67 : is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device 1D according to a fourth embodiment of the present technology.

[0500] Fig.68 2 is a plan view schematically showing the bonding surface 40 a side of the second semiconductor chip 40 .

[0501] Fig.69 2 is a plan view schematically showing the bonding surface 20 a side of the first semiconductor chip 20 .

[0502] like Figure 67 to Figure 69As shown, the solid-state imaging device 1D according to the fourth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0503] That is, Fig.67 and Fig.68 As shown, the second semiconductor chip 40 of the fourth embodiment replaces the semiconductor chip 40 of the first embodiment. Figure 8 The warpage suppression portion shown has a warpage suppression film 45f provided on the side surfaces of the second bonding surface 45b and the multilayer wiring layer 45. The other structures are substantially the same as those of the first embodiment described above.

[0504] like Fig.67 and Fig.68 As shown, like the bonding metal pad 47, a warpage suppression film 45f is provided in the multilayer wiring layer 45 in a state where the bonding surface side is exposed. Then, the bonding surface 40a is substantially flat with the step between the warpage suppression film 45f and the bonding metal pad 47 and the insulating layer 46 as small as possible.

[0505] The warpage suppression film 45f in the fourth embodiment is not limited to this, and for example, it can also be formed in the same process as the bonding metal pad 47 and made of the same metal material as the bonding metal pad 47. Also, without limitation to this, similarly to the warpage suppression film 45e in the third embodiment, the warpage suppression film 45f is provided on the four sides (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40, and has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4). Moreover, the warpage suppression film 45e overlaps with the side surfaces (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view, and is exposed from the side surfaces of the second semiconductor chip 40.

[0506] like Fig.69 As shown, the first semiconductor chip 20 of the fourth embodiment has a dummy pad 27f corresponding to the warpage suppression film 45f of the second semiconductor chip 40 on the bonding surface 20a. The dummy pad 27f is provided on the bonding surface 20 of the first semiconductor chip 20 in a manner overlapping with the warpage suppression film in a plan view, and is formed into a ring-shaped planar pattern similar to the warpage suppression film. The dummy pad 27f is formed in the same process as the bonding metal pad 27, for example, and is made of the same metal material as the bonding metal pad 27. Unlike the metal pad 27, the dummy pad 27f is not electrically connected, for example, no potential is supplied.

[0507] like Fig.67As shown, the dummy pads 27f of the first semiconductor chip 20 and the warpage suppression film 45f of the second semiconductor chip 40 are bonded to the bonding surfaces 20a and 40a of the first semiconductor chip 20 and the second semiconductor chip 40 by direct bonding, as well.

[0508] Furthermore, in the solid-state imaging device 1D of the fourth embodiment, similarly to the third embodiment described above, the bonding strength between the first semiconductor chip 20 and the peripheral edge portion Cs side of the second semiconductor chip 40 can be increased while suppressing the bending of the second semiconductor chip 40, and defects such as the second semiconductor chip 40 peeling off from the first semiconductor chip 20 can be suppressed. Therefore, the solid-state imaging device 1D according to the fourth embodiment can improve manufacturing yield.

[0509] <<Modification of the Fourth Embodiment>>

[0510] In the fourth embodiment described above, the case where the warp suppression film 45 f has a ring-shaped planar shape has been described. However, the warp suppression film 45 f may also be applied to the modified example of the first embodiment described above.

[0511] [Fifth Embodiment]

[0512] In the first to fourth embodiments described above, the case where the warpage suppression films 45b, 45c, 45d, 45e, and 45f are provided in the multilayer wiring layer 45 of the second semiconductor chip 40 as the warpage suppression portion for suppressing the warpage of the second semiconductor chip 40 is described. In the present embodiment, the case where the warpage suppression portion is provided on the semiconductor layer 42 of the second semiconductor chip 40 is described. Next, in the present embodiment, the modified layer 81 with disordered crystallinity is described as the warpage suppression portion provided on the semiconductor layer 42 of the second semiconductor chip 40.

[0513] Fig.70 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology.

[0514] Fig.71 is schematically shown along Fig.70 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a70-a70 in FIG.

[0515] Fig.72 is schematically shown along Fig.70 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b70-b70 in FIG.

[0516] like Figure 70 to Figure 72As shown, the solid-state imaging device 1E according to the fifth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0517] That is, Figure 70 to Figure 72 As shown, the second semiconductor chip 40 according to the fifth embodiment replaces the semiconductor chip 40 of the first embodiment. Figure 8 The warpage suppression film 45b of the warpage suppression portion shown in the figure has a modified layer 81 provided on the semiconductor layer 42. The other structures are substantially the same as those of the first embodiment described above.

[0518] As mentioned above, Figure 70 to Figure 72 The second semiconductor chip 40 shown includes: a semiconductor layer 42 having a first surface (element forming surface or main surface) and a second surface (back surface 42b) on one side opposite to each other in the thickness direction (Z); and a multilayer wiring layer 45 provided on the first surface side of the semiconductor layer 42. That is, the second semiconductor chip 40 of the fifth embodiment includes: a multilayer wiring layer 45 having a second bonding surface 40a, a semiconductor layer 42 having a quadrilateral back surface 42b on the side opposite to the side of the multilayer wiring layer 45, and a modified layer 81 as a warpage suppression portion provided on the second semiconductor layer 42 and suppressing the bending of the second semiconductor chip 40.

[0519] Here, in the present embodiment, the back surface 42 b of the semiconductor layer 42 may be referred to as a back surface located on the opposite side to the bonding surface 40 a of the second semiconductor chip 40 .

[0520] like Figure 70 to Figure 72 As shown, in the semiconductor chip 40 involved in the fifth embodiment, the back side 42b of the semiconductor layer 42 is formed into a quadrilateral in the same manner as the bonding surface 40a. Then, the back side 42b of the semiconductor layer 42 has two sides 42b1 and 42ba2 located on both sides opposite to each other in the X direction and two sides 42ba3 and 42b4 located on both sides opposite to each other in the Y direction. The two sides 42b1 and 42b2 extend in the Y direction. The two sides 42b3 and 42b4 extend in the X direction.

[0521] Here, the two sides 42b1 and 42b2 may be referred to as long sides, and the two sides 42ba3 and 42ba4 may be referred to as short sides.

[0522] like Figure 70 to Figure 72 As shown, the second semiconductor chip 40 has a peripheral portion Cv including four sides 42b1, 42b2, 42b3, and 42b4 of the back surface 42b.

[0523] like Figure 70 to Figure 72As shown, the modified layer 81 is selectively provided on the peripheral portion Cv side of the back surface 42b of the semiconductor layer 42 in a plan view. Fig.70 As shown, the modified layer 81 is provided on the sides of the four sides (42b1, 42b2, 42b3, and 42b4) in the back side 42b of the semiconductor layer 42, and has a ring-shaped planar pattern extending continuously along the four sides (42b1, 42b2, 42b3, and 42b4). Then, the modified layer 81 overlaps the sides (42b1, 42b2, 42b3, and 42b4) of the back side 42b of the semiconductor layer 42 in a plan view, and is exposed from the sides of the semiconductor layer 42.

[0524] Similar to the above-mentioned warping suppression film 45b, by configuring a modified layer 81 on the peripheral portion (peripheral portion Cs side) of the second semiconductor chip 40, that is, the peripheral portion (peripheral portion Cv side) of the semiconductor layer 42, the local film stress of the second semiconductor chip 40 is controlled and the warping of the second semiconductor chip 40 is suppressed.

[0525] Unlike the single crystal of the semiconductor layer 42, the modified layer 81 is in a state where crystallinity is disturbed. The modified layer 81 can be formed, for example, by converging a laser beam having a wavelength with transparency into the semiconductor layer 42. When the condensation energy is high, the material is locally evaporated inside the semiconductor layer 42 to form a hole, so that the modified layer 81 having disturbed crystallinity can be formed. Note that the modified layer 81 includes, for example, a polycrystalline or amorphous region.

[0526] The modified layer 81 formed in this manner is in a lower density state than the surrounding single crystals in the semiconductor layer, thereby causing compressive stress.

[0527] The modified layer 81 may be composed of strip-shaped holes having a predetermined width, and may be configured as a pattern in which a plurality of holes exist in a dotted manner. In addition, the modified layer 81 may also be configured as a pattern in which a plurality of linear holes exist. Compressive stress is inherent in any modified layer 81.

[0528] The second semiconductor chip 40 of the fifth embodiment has a modified layer 81 provided on the semiconductor layer 42 as a warpage suppression portion for suppressing the warpage of the second semiconductor chip 40. Therefore, in the process of manufacturing the solid-state imaging device 1E, even after the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 is reduced, the bending of the second semiconductor chip 40 caused by the reduction in the rigidity of the second semiconductor chip 40 can be suppressed, cracks, chipping of the second semiconductor chip 40, etc. can be suppressed, which leads to a reduction in the manufacturing yield of the solid-state imaging device 1F. Therefore, the solid-state imaging device 1E according to the fifth embodiment can further improve the manufacturing yield.

[0529] Note that the modified layer 81 is preferably formed at a depth position that remains even after the thickness of the semiconductor layer 42 of the second semiconductor chip is reduced.

[0530] <<Modification of the Fifth Embodiment>>

[0531] <Variation 5-1>

[0532] Fig.73 5 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to Modification 5-1 of the fifth embodiment of the present technology.

[0533] like Fig.73 As shown, the fifth embodiment described above is combined with the warp suppression film 45 b of the first embodiment described above to obtain a modification 5-1. According to the modification 5-1, the warping of the second semiconductor chip 40 can be suppressed more effectively than in the fifth embodiment described above.

[0534] <Other Modifications>

[0535] In the above-described fifth embodiment, the case where the modified layer 81 is configured in the annular planar pattern has been described, but the modification of the above-described first embodiment can also be applied to the modified layer 81 .

[0536] [Sixth Embodiment]

[0537] In the fifth embodiment described above, the case where the modified layer 81 is a warpage suppression portion provided on the semiconductor layer 42 of the second semiconductor chip 40 is described. In the sixth embodiment, the thick portion (second portion) 82a included in the semiconductor layer 42 is described as a warpage suppression portion provided in the semiconductor layer 42 of the second semiconductor chip 40.

[0538] Fig.74 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a sixth embodiment of the present technology.

[0539] Fig.75 is schematically shown along Fig.75 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a75-a75.

[0540] Fig.76 is schematically shown along Fig.75 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b75-b75.

[0541] like Figure 74 to Figure 76As shown, the solid-state imaging device 1F according to the sixth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1E according to the above-described fifth embodiment, and the configuration of the second semiconductor chip 40 is different.

[0542] That is, the second semiconductor chip 40 according to the sixth embodiment is as follows: Figure 74 to Figure 76 As shown, instead of the modified layer 81, a thick portion 82a included in the back surface 42b of the semiconductor layer 42 is provided as the fifth embodiment. Figure 70 to Figure 72 The other structures are substantially the same as those of the fifth embodiment.

[0543] like Figure 74 to Figure 76 As shown, the back side 42b of the semiconductor chip 40 of the sixth embodiment includes a thin portion (first portion) having a first thickness and a thick portion (second portion) having a second thickness thicker than the first thickness. Furthermore, a thick portion is provided on the peripheral portion Cv side of the back side 42b of the semiconductor chip 40. In the sixth embodiment, as Fig.74 As shown, the thick portion 82a is disposed on (but not limited to) four side surfaces (42b1, 42b2, 42b3, and 42b4) in the back surface 42b of the semiconductor layer 42, and has a ring-shaped planar pattern extending continuously along the four side surfaces (42b1, 42b2, 42b3, and 42b4). Then, the thick portion 82a overlaps with the side surfaces (42b1, 42b2, 42b3, and 42b4) of the back surface 42b of the semiconductor layer 42 in a plan view, and is included in the side surfaces of the semiconductor layer 42.

[0544] like Figure 74 to Figure 76 As shown, a thin portion 82b is provided in the central area of ​​the back side 42 of the second semiconductor chip 40, and the thin portion 82b is recessed from the thick portion 82a toward the multilayer wiring layer 45 side. In addition, the thick portion 82a is provided in the peripheral area of ​​the back side 42 of the second semiconductor chip 40, and protrudes from the thin portion 82b to the side opposite to the multilayer wiring layer 45 side. That is, the back side 42b of the second semiconductor chip 40 of the sixth embodiment has a step portion 82 formed by a thin portion (first portion) 82b and a thick portion (second portion) 82a having relatively different thicknesses.

[0545] As described above, by providing the step portion 82 formed of the thin portion (first portion) 82b and the thick portion (second portion) 82a having relatively different thicknesses on the back surface 42 of the second semiconductor chip 40, the bending rigidity of the second semiconductor chip 40 in the Z direction can be improved.

[0546] Therefore, in the process of manufacturing the solid-state imaging device 1F, even after the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding, the thickness of the semiconductor layer 42 of the second semiconductor chip 40 is reduced, the bending of the second semiconductor chip 40 caused by the reduction in the rigidity of the second semiconductor chip 40 can be suppressed, and cracks, chipping of the second semiconductor chip 40, etc. can be suppressed, which leads to a reduction in the manufacturing yield of the solid-state imaging device 1F. Therefore, the solid-state imaging device 1F according to the sixth embodiment can improve the manufacturing yield.

[0547] <<Modification of Sixth Embodiment>>

[0548] In the sixth embodiment described above, the thick portion 82a in the annular planar pattern extending continuously along the four sides (42b1, 42b2, 42b3 and 42b4) of the back surface 42b of the second semiconductor chip 40 is described as the thick portion 82a of the semiconductor layer 45. However, the thick portion 82a is not limited to the annular planar pattern of the sixth embodiment described above.

[0549] <Variation 6-1>

[0550] Fig.77A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification 2-1 of the sixth embodiment of the present technology.

[0551] Fig.77B is schematically shown along Fig.77A The longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b77-b77 in FIG.

[0552] like Fig.77A and Fig.77B As shown, in Modification 6-1, the thick portion 82a is provided on the four corners Cw (Cw1, Cw2, Cw3, Cw4) of the back surface 42b of the second semiconductor chip 40. Moreover, the thick portion 82a of Modification 6-1 overlaps the corners Cw (Cw1, Cw2, Cw3, Cw4) in a plan view.

[0553] In Modification 6-1, as in the sixth embodiment, the second semiconductor chip 40 can be prevented from warping. In Modification 6-1 in particular, the semiconductor layer 42 of the second semiconductor chip 40 can be prevented from warping on the corner Cw side (corner Cr side of the bonding surface 40a).

[0554] <Variation 6-2>

[0555] Fig.78A: is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-2 of the sixth embodiment of the present technology.

[0556] Fig.78B is schematically shown along Fig.78A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a78-a78 in FIG.

[0557] Fig.78C is schematically shown along Fig.78A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b78-b78 in FIG.

[0558] like Figures 78A to 78C As shown, in the modification 6-2, the thick portion 82a is configured as an X-shaped plane pattern extending from the sides of the four corners Cw (Cw1, Cw2, Cw3, Cw4) of the back surface 42b of the semiconductor layer 42 of the second semiconductor chip 40 toward the central portion. The X-shaped thick portion 82a extends inward from the sides of the corners Cw (Cw1, Cw2, Cw3, Cw4) included in the peripheral portion Cv of the back surface 42b of the semiconductor layer 42.

[0559] In Modification 6-2, as in the sixth embodiment, the second semiconductor chip 40 can be prevented from warping. Furthermore, in Modification 6-2, the warping of the corner Cw side (corner Cr side of the bonding surface 40a) of the semiconductor layer 42 of the second semiconductor chip 40 can also be prevented.

[0560] <Variation 6-3>

[0561] Fig.79A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-3 of the sixth embodiment of the present technology.

[0562] Fig.79B is schematically shown along Fig.79A The longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b79-b79 in FIG.

[0563] like Fig.79A and Fig.79B As shown, in the modification 6-3, the thick portion 82a is configured as a cross-shaped plane shape where a first portion extending in the X direction and a second portion extending in the Y direction intersect at the central portion of the back surface 42b of the semiconductor layer 42 of the second semiconductor chip 40. The cross-shaped thick portion 82a extends inward from the sides (42b1, 42b2, 42b3, 42b4) included in the peripheral portion Cv of the back surface 42b of the semiconductor layer 42.

[0564] In the modification 6-3 as well, similarly to the sixth embodiment, the warping of the second semiconductor chip 40 can be suppressed.

[0565] <Variation 6-4>

[0566] Fig.80A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-4 of the sixth embodiment of the present technology.

[0567] Fig.80B is schematically shown along Fig.80A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b80-b80 in FIG.

[0568] like Fig.80A as well as Fig.80B As shown, in the modification 6-4, a thick portion 82a having an inclined shape extending obliquely on both sides with different extension directions is provided near the corner Cw of the back surface 42b of the semiconductor layer 42 of the second semiconductor chip 40. The thick portion 82a having an inclined shape extends inward from the edge (42b1, 42b2, 42b3, 42b4) included in the peripheral portion Cv of the back surface 42b of the semiconductor layer 42.

[0569] In Modification 6-4, as in the sixth embodiment, the second semiconductor chip 40 can be prevented from bending. Furthermore, in Modification 6-4, the warping of the corner Cw side (corner Cr side of the bonding surface 40a) of the semiconductor layer 42 of the second semiconductor chip 40 can also be prevented.

[0570] <Variation 6-5>

[0571] Fig.81A : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a modification example 6-5 of the sixth embodiment of the present technology.

[0572] Fig.81B is schematically shown along Fig.81A A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a81 - a81 in FIG.

[0573] like Fig.81A and Fig.81B As shown, Modification 6-5 is obtained by combining the warpage suppression films 45 b of the sixth embodiment and the first embodiment. According to Modification 6-5, the warpage of the second semiconductor chip 40 can be suppressed more effectively than in the sixth embodiment.

[0574] [Seventh Embodiment]

[0575] In the seventh embodiment, a technique for suppressing the generation of voids caused by a joining wave will be described.

[0576] Fig.82 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a seventh embodiment of the present technology.

[0577] Fig.83 is schematically shown along Fig.82 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a82-a782 in FIG.

[0578] Fig.84 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0579] It should be noted that Fig.82 Corresponding to the first embodiment described above Figure 7 .

[0580] like Figure 82 to Figure 84 As shown, the solid-state imaging device 1G according to the seventh embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0581] That is, Fig.83 and Fig.84 As shown, the semiconductor chip 40 of the seventh embodiment replaces the semiconductor chip 40 of the first embodiment. Figure 8 The warpage suppression film 45b shown in the figure has a weak joint portion 85. The other structures are substantially the same as those of the first embodiment described above.

[0582] like Figure 83 to Figure 84 As shown, a weak bonding portion 85 is included in the bonding surface 40a of the second semiconductor chip 40 together with the insulating layer 46 of the multilayer wiring layer 45 and the bonding metal pad 47. Then, the weak bonding portion 85 is composed of a material whose bonding force to the bonding surface 20a of the first semiconductor chip 20 is weaker than the bonding force of the insulating layer 46 of the multilayer wiring layer 45. That is, the second bonding surface 40a of the second semiconductor chip 40 of the seventh embodiment includes: an insulating layer 46 included in the multilayer wiring layer 45; and a weak bonding portion 85, which has a bonding force weaker than the insulating layer 46 relative to the bonding surface 20a of the first semiconductor chip 20. The weak bonding portion 85 is, for example, composed of a porous film (porous film). Since the porous film includes a plurality of holes, the bonding force with the counterpart is weaker than the bonding force of the film formed by a film forming method such as a CVD method.

[0583] The bonding wave when the second semiconductor chip is directly bonded to the bonding surface of the first semiconductor chip affects the bonding force between the bonding surface of the first semiconductor chip and the bonding surface of the second semiconductor chip, and the travel speed of the bonding wave is reduced in the portion where the bonding force is weak. That is, in the bonding surface of the second semiconductor chip, the travel speed of the bonding wave in the weak bonding portion is slower than the travel speed of the bonding wave in the insulating layer between the insulating layer and the weak bonding portion.

[0584] Similar to the bonding metal pad 47, the weak bonding portion 85 is provided in the insulating layer 46 of the multilayer wiring layer 45 in a state where the bonding surface side is exposed from the bonding surface 40a. Then, the bonding surface 40a is substantially flat with the step between the weak bonding portion 85 and the bonding metal pad 47 and the insulating layer 46 as small as possible. The weak bonding portion 85 and the insulating layer 46 are bonded to the bonding surface 20a of the first semiconductor chip 20 by direct bonding.

[0585] like Fig.83 and Fig.84 As shown, a weak bonding portion 85 is provided on the peripheral portion Cs side of the bonding surface 40a of the second semiconductor chip 40. In addition, in the seventh embodiment, for example, in the bonding surface 40a of the second semiconductor chip 40, a weak bonding portion is provided on the sides of four sides (40a1, 40a2, 40a3, 40a4), and the weak bonding portion has a ring-shaped planar pattern extending continuously along the four sides (40a1, 40a2, 40a3, 40a4), but is not limited to this. Moreover, the weak bonding portion 85 overlaps with the side (40a1, 40a2, 40a3, 40a4) of the bonding surface 40a of the second semiconductor chip 40 in a plan view, and is exposed from the side of the second semiconductor chip 40, that is, the side of the multilayer wiring layer 45.

[0586] Here, in the manufacturing process, as in the first embodiment described above, Fig.29 As shown, the bonding surface 40a of the second semiconductor chip 40 is directly bonded to the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) of the wafer stack 60. In this direct bonding, the bonding surface 40a of the second semiconductor chip 40 is pressed (crimped) onto the bonding surface 20a (bonding surface 20a of the first semiconductor chip 20) of the wafer stack 60, so that a bonding wave is generated radially from the central portion toward the periphery within the two-dimensional surface of the second semiconductor chip 40.

[0587] At this time, in the case of the conventional second semiconductor chip, as described with reference to the seventh embodiment Fig.84As will be described, the bonding wave reaches the side (40a1, 40a2, 40a3 and 40a4) of the bonding surface 40a of the second semiconductor chip 40. Then, the traveling speed of the bonding wave that has reached the bonding surface 40a side increases, traveling along the bonding surface 40a side, and before the corner Cr of the bonding surface 40a, which is the arrival position of the radially expanded bonding wave. Therefore, in the existing second semiconductor chip, gaps are easily generated at the corners of the bonding surface. In the quadrilateral second semiconductor chip, in a plan view, there is a difference between the distance from the center of the semiconductor chip to the side and the distance from the center to the corner of the semiconductor chip, so that the generation of gaps at the corners of the second semiconductor chip becomes significant.

[0588] On the contrary, Fig.84 As shown, the bonding surface 40a of the second semiconductor chip 40 of the seventh embodiment includes: an insulating layer 46 included in the multilayer wiring layer 45; and a weak bonding portion 85 having a bonding force weaker than the insulating layer 46 relative to the bonding surface 20a of the first semiconductor chip 20. Then, the weak bonding portion 85 is arranged on the peripheral portion Cs side of the bonding surface 40a (on the side 40a1 side, the side 40a2 side, the side 40a3 side and the side 40a4 side). Therefore, the bonding wave can be delayed to reach the peripheral portion Cs of the bonding surface 40a. In addition, the weak bonding portion 85 extends along the side (40a1, 40a2, 40a3 and 40a4) of the bonding surface 40a. Therefore, the travel speed of the bonding wave traveling along the side of the bonding surface 40a can be reduced. As a result, during the manufacturing process, it is possible to suppress the generation of voids at the corners Cr of the second semiconductor chip 40 due to the arrival time difference between the bonding wave advancing along the sides ( 40 a 1 , 40 a 2 , 40 a 3 , 40 a 4 ) of the bonding surface 40 and the bonding wave spreading radially.

[0589] Therefore, the solid-state imaging device 1G according to the seventh embodiment can improve manufacturing yield.

[0590] <<Modification of Seventh Embodiment>>

[0591] <Variation 7-1>

[0592] Fig.85A : is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to Modification 7-1 of the seventh embodiment of the present technology.

[0593] like Fig.85A As shown, in Modification 7-1, weak bonding portions 85 are scattered along the bonding surface side of the second semiconductor chip. In Modification 7-1, the same effects as those of the seventh embodiment can also be obtained.

[0594] <Variation 7-2>

[0595] Fig.85B : is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to Modification 7-2 of the seventh embodiment of the present technology.

[0596] like Fig.85B As shown, Modification 7-2 is obtained by combining the seventh embodiment with the warpage suppression film 45b of the first embodiment. According to Modification 2, compared with the seventh embodiment, the warpage of the second semiconductor chip 40 can be suppressed, and the generation of voids caused by the bonding wave can be suppressed.

[0597] <<Other Modifications>>

[0598] In the seventh embodiment described above, the case where the porous weak bonding portion 85 is provided on the peripheral portion Cs side of the bonding surface 40a of the second semiconductor chip 40 is described, but a dummy pad may be used as the weak bonding portion 85. In this case, a material (e.g., Cu, etc.) whose bonding force with the bonding surface 20a of the first semiconductor chip 20 is weaker than that with the insulating layer 46 of the second semiconductor chip 40 is selected as the dummy pad.

[0599] [Eighth Embodiment]

[0600] In an eighth embodiment, a technique for suppressing the generation of voids caused by a junction wave will be described.

[0601] Fig.86 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to an eighth embodiment of the present technology.

[0602] Fig.87A is schematically shown along Fig.86 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a86a-a86a in FIG.

[0603] Fig.87B is schematically shown along Fig.86 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a86b-a86b in FIG.

[0604] Fig.88 1 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0605] It should be noted that Fig.86 Corresponding to the first embodiment described above Figure 7 .

[0606] In addition, Fig.88 In order to make the figure easier to see, dotted hatching is applied to the area of ​​the bonding surface.

[0607] like Figure 86 to Figure 88As shown, the solid-state imaging device 1H according to the eighth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1G according to the seventh embodiment described above, and the configuration of the second semiconductor chip 40 is different.

[0608] That is, Figure 86 to Figure 88 As shown, in the semiconductor chip 40 of the eighth embodiment, the peripheral edge portion Cs (side 40a1, side 40a2, side 40a3, side 40a4) of the bonding surface 40a is curved. In addition, the semiconductor chip 40 of the eighth embodiment does not have the seventh embodiment described above. Fig.88 The weak joint 85 is shown. In addition, the semiconductor chip 40 of the twenty-eighth embodiment has a recess 86 extending inward from the side surface thereof.

[0609] In the semiconductor chip 40 of the eighth embodiment, as Fig.88 As shown, the peripheral edge portion Cs has a meandering shape in which a first peripheral edge portion Cs1 and a second outer edge portion Cs2 located inside the first peripheral edge portion Cs1 are repeatedly arranged in one direction in a plan view. Then, the peripheral edge portion Cs of the joint surface 40a reflects the planar shape of the recess.

[0610] like Fig.88 As shown, the recesses 86 of the second semiconductor chip 40 are repeatedly arranged in the extending direction of the peripheral edge portion Cs of the bonding surface 40a in a plan view. Fig.87A and Fig.87B As shown, the recess 86 of the semiconductor chip 40 extends from the bonding surface 40a to the back surface 42b of the semiconductor chip 40. In the eighth embodiment, one end of the recess 86 is included in the bonding surface 40a of the semiconductor chip 40, and the other end is separated from the back surface 42b of the semiconductor chip 40. The recess 86 is, for example, formed in a hexahedral shape, and the surface on the bonding surface 40a side and the side surface of the semiconductor chip 40 are open surfaces among the six surfaces, and the remaining four surfaces are surrounded by the insulating layer 45.

[0611] In the semiconductor chip 40 of the eighth embodiment, the peripheral edge Cs of the bonding surface 40a is curved. Therefore, without increasing the planar size of the second semiconductor chip 40, the actual length of the peripheral edge can be made greater than the distance obtained by connecting two corners on the opposite side of one bonding surface with a straight line.

[0612] Thus, in the manufacturing process, by pressing (compressing) the bonding surface 40a of the second semiconductor chip 40 to the bonding surface 20a of the wafer stack 60, a bonding wave from the central portion toward the peripheral portion is generated within the two-dimensional surface of the second semiconductor chip 40, such as Fig.29As shown, the bonding wave propagates along the edges (40a1, 40a2, 40a3 and 40a4) of the bonding surface 40a of the second semiconductor chip 40, and the arrival of the bonding wave at the corner of the bonding surface can be delayed. And the gap generated in the corner Cr of the second semiconductor chip 40 due to the arrival time difference between the bonding waves traveling along the edges (40a1, 40a2, 40a3 and 40a4) of the bonding surface 40 and the radial expansion of the bonding wave can be suppressed.

[0613] Therefore, similar to the solid-state imaging device 1F according to the above-described seventh embodiment, the solid-state imaging device 1G according to the eighth embodiment can improve manufacturing yield.

[0614] <Variation of the Eighth Embodiment>

[0615] <Variation 8-1>

[0616] Fig.89 : is a longitudinal sectional view schematically showing a configuration example of a solid-state imaging device according to Modification 8-1 of the eighth embodiment of the present technology.

[0617] like Fig.89 As shown, in the modification 8-1, the recess 86 is filled with an insulating material 87. As the insulating material 87, an organic material such as a silicon oxide film or a silicon nitride film, or an organic material such as a resin can be used. After the bonding surface 20a of the wafer stack 60 (the bonding surface 20a of the first semiconductor chip 20) and the bonding surface 40a of the second semiconductor chip 40 are bonded by direct bonding, the insulating material 87 is formed in the recess 86. In the modification 8-1, the same effect as the above-mentioned eighth embodiment can also be obtained.

[0618] [Ninth Embodiment]

[0619] Fig.90 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a ninth embodiment of the present technology.

[0620] Fig.91A is schematically shown along Fig.90 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a90a-a90a in FIG.

[0621] Fig.91B is schematically shown along Fig.90 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along line a90b-a90b in FIG.

[0622] Fig.92 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0623] It should be noted that Fig.90Compared with the first embodiment described above Figure 7 correspond.

[0624] like Figure 90 to Figure 92 As shown, the solid-state imaging device 1I according to the ninth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1H according to the eighth embodiment described above, and the configuration of the groove 86 of the second semiconductor chip 40 is different.

[0625] That is, Figure 90 to Figure 92 As shown, the recess 86 of the ninth embodiment extends from the bonding surface 40 a of the second semiconductor chip 40 to the back surface 42 b and is included in the bonding surface 40 a and the back surface 42 b .

[0626] The solid-state imaging device 1I according to the ninth embodiment can also produce effects similar to those produced by the solid-state imaging device 1H according to the above-described eighth embodiment.

[0627] [Tenth embodiment]

[0628] In the tenth embodiment, a technique for suppressing the generation of voids by providing a weak bonding region having a weak bonding force and a strong bonding region having a strong bonding force on a bonding surface and controlling a bonding wave will be described.

[0629] Fig.93 : is a plan view schematically showing a main part of a configuration example of a solid-state imaging device according to a tenth embodiment of the present technology.

[0630] Fig.94 is schematically shown along Fig.93 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line a93-a93.

[0631] Fig.95 is a plan view schematically showing the bonding surface side of the second semiconductor chip.

[0632] Fig.96 is schematically shown along Fig.95 A longitudinal cross-sectional view of the longitudinal cross-sectional structure taken along the cutting line b95-b95.

[0633] Fig.97 is a plan view schematically showing the bonding surface side of the first semiconductor chip.

[0634] like Figures 93 to 97 As shown, the solid-state imaging device 1J according to the tenth embodiment of the present technology basically has a configuration similar to that of the solid-state imaging device 1A according to the above-described first embodiment, and the configuration of the second semiconductor chip 40 is different.

[0635] That is, at least one of the bonding surface 20a of the first semiconductor chip 20 or the bonding surface 40a of the second semiconductor chip 40 includes a weak bonding surface 91 and a strong bonding surface 92 having a bonding force different from that of the other bonding surfaces, and the one weak bonding surface 91 is provided on one bonding surface on the peripheral portion side. Figure 93 to Figure 97 As shown, the bonding surface 40 of the second semiconductor chip 40 includes a weak bonding surface 91 and a strong bonding surface 92 .

[0636] Then, if Fig.95 As shown, the weak bonding area 91 is arranged on two long sides (40a1 and 40a2) located on the side opposite to each other in the X direction among the four sides (40a1, 40a2, 40a3 and 40a4) of the bonding surface 40a of the second semiconductor chip 40, and extends along the corresponding long sides (40a1 and 40a2).

[0637] Notice, Fig.95 An example is shown in which the weakly joined region 91 is not in contact with the peripheral portion Cs in a plan view, but the present embodiment is not limited thereto. For example, the weakly joined region 91 may be in contact with the peripheral portion Cs in a plan view.

[0638] Then, the weak bonding region 91 includes a solid conductive film 91a extending continuously. The conductive film 91a is composed of metal materials such as Cu, W, Al, Ru, etc., and has a hydrophobic bonding surface (surface). The bonding force between the conductive film 91a having a hydrophobic bonding surface and the bonding surface 20a of the first semiconductor chip 20 is weaker than the bonding force between the insulating layer 46 of the multilayer wiring layer 45. The strong bonding region 92 includes an insulating layer 46 and a bonding metal pad 47. That is, the bonding force between the weak bonding region 91 and the bonding surface of the first semiconductor chip 20 is weaker than the bonding force between the strong bonding region 92.

[0639] As described above, the bonding surface 40a of the second semiconductor chip 40 includes a weak bonding area 91 and a strong bonding area 92 having relatively different bonding forces from the bonding surface 20a of the first semiconductor chip 20, and the weak bonding area 91 is arranged on the side of the side (42a1 and 42a2) in the bonding surface 40a of the first semiconductor chip 40, so that the bonding wave can be delayed to reach the peripheral edge Cs (side 42a1 and side 42a2) of the bonding surface 40a. In addition, the weak bonding area 91 extends along the side (40a1 and 40a2) of the bonding surface 40a. Therefore, the travel speed of the bonding wave traveling along the side of the bonding surface 40a can be reduced. As a result, in the manufacturing process, the gap generated in the corner Cr of the second semiconductor chip 40 due to the arrival time difference between the bonding wave traveling along the edge (40a1, 40a2) of the bonding surface 40 and the radially extended bonding wave can be suppressed.

[0640] Therefore, the solid-state imaging device 1J according to the tenth embodiment can improve the manufacturing yield.

[0641] <<Modification of the Tenth Embodiment>>

[0642] <Variation 10-1>

[0643] Fig.98 1 is a diagram showing a type of arrangement pattern of weak bonding areas 91 and 93 arranged on respective bonding surfaces 20a and 40a of the first semiconductor chip 20 and the second semiconductor chip 40. In Modification 10-1, the bonding surface 20a of the first semiconductor chip 20 includes a weak bonding area 93 and a strong bonding area 94 having relatively different bonding forces with the bonding surface 40a of the second semiconductor chip 40. In addition, the bonding surface 40a of the second semiconductor chip 40 includes a weak bonding surface 91 and a strong bonding surface 92 having relatively different bonding forces with the bonding surface 20a of the first semiconductor chip 20.

[0644] Fig.98 (a) shows an example in which, in the first semiconductor chip 20 and the second semiconductor chip 40 , weak bonding regions 91 and 93 are arranged in the bonding surfaces 20 a and 40 a on both long sides, respectively.

[0645] Fig.98 (b) shows an example in which, in the first semiconductor chip 20 and the second semiconductor chip 40 , the weak bonding regions 91 and 93 are arranged on the sides of the two long sides and the two short sides of the bonding surfaces 20 a and 40 a , respectively.

[0646] Fig.98 (c) shows an example in which weak bonding areas 91 and 93 are arranged in the bonding surfaces 20a and 40a on both long sides, respectively, in the first semiconductor chip 20 and the second semiconductor chip 40. In this example, the weak bonding areas 91 and 93 are planar patterns having portions in which the width along the side gradually increases from the center toward the side of the bonding surfaces 20a and 40a.

[0647] Moreover, in Fig.98 (a) Fig.98 (b) and Fig.98 In the modification 10-1 shown in (c) of FIG. 1 , effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0648] <Variation 10-2>

[0649] Fig.99 2 is a diagram showing a type of arrangement pattern in which the weak bonding regions 91 in the first semiconductor chip 20 and the second semiconductor chip 40 are arranged on the bonding surface 40 a of the second semiconductor chip 40 .

[0650] Fig.99 (a) Fig.99 (b) and Fig.99 The arrangement pattern of the weak bonding area 91 in (c) is similar to that in the above Fig.98 (a) Fig.98 (b) and Fig.98 The arrangement pattern in (c) is similar.

[0651] Moreover, in Fig.99 (a) Fig.99 (b) and Fig.99 In the modification 10-2 shown in (c) of FIG. 10 , effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0652] <Variation 10-3>

[0653] Fig.100 1 is a diagram showing a type of arrangement pattern in which the weak bonding regions 93 in the first semiconductor chip 20 and the second semiconductor chip 40 are arranged on the bonding surface 20 a of the first semiconductor chip 20 .

[0654] Fig.100 (a) Fig.100 (b) and Fig.100 The arrangement pattern of the weak bonding area 93 in (c) is similar to that in the above Fig.98 (a) Fig.98 (b) and Fig.98 The arrangement pattern in (c) is similar.

[0655] Moreover, in Fig.100 (a) Fig.100 (b) and Fig.100 In the modification 10-3 shown in (c) of FIG. 10 , effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0656] <Variation 10-4>

[0657] exist Fig.101 In the modification 10-4 shown, similarly to the tenth embodiment described above, the weak bonding surfaces 91 and 93 of the first semiconductor chip 20 and the second semiconductor chip 40 are formed of a solid conductive film 91a. Also in this modification 10-4, effects similar to those of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0658] <Variation 10-5>

[0659] exist Fig.102In the modification 10-5 shown, the weak bonding regions 91 and 93 of both the first semiconductor chip 20 and the second semiconductor chip 40 include a plurality of conductive films 91b repeatedly arranged at predetermined intervals in the extending direction of the side surfaces of the bonding surfaces 20a and 40a. Also in this modification 10-5, an effect similar to that of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0660] <Variation 10-6>

[0661] exist Fig.103 In the modification 10-6 shown, the surface roughness of the weak bonding regions 91 and 93 of the first semiconductor chip 20 and the second semiconductor chip 40 is made rougher than the surface roughness of the strong bonding regions 92 and 93. In the modification 10-6, the entire surface roughness of each of the weak bonding regions 91 and 93 is rougher than the entire surface roughness of the strong bonding regions 92 and 94. The bonding force of the bonding surfaces 20a and 40a depends on the surface roughness, and the bonding force of the rougher bonding surface is smaller. Also in this modification 10-5, an effect similar to that of the solid-state imaging device 1J according to the above-mentioned tenth embodiment can be obtained.

[0662] <Variation 10-7>

[0663] exist Fig.104 In the illustrated modification 10-7, the surface roughness of the weak bonding regions 91 and 93 of the first semiconductor chip 20 and the second semiconductor chip 40 is made rougher than the surface roughness of the strong bonding regions 92 and 93. In the modification 10-7, a portion of the surface roughness of each of the weak bonding regions 91 and 93 is rougher than the surface roughness of the strong bonding regions 92 and 94.

[0664] <Variation 10-8>

[0665] exist Fig.105 In the illustrated modification 10-8, a recess 93a extending in the extension direction of the side surface is provided in the bonding surface 20a of the first semiconductor chip 20 of the first semiconductor chip 20 and the second semiconductor chip 40 to configure a weak bonding area 93 in the bonding surface 20a of the first semiconductor chip 20. Also in this modification 10-7, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0666] Note that in Modification 10-8, the recess 93a is provided in the bonding surface 20a of the first semiconductor chip 20, but the recess 93a may be provided in the bonding surface 40a of the second semiconductor chip 40 to form a weak bonding region in the second semiconductor chip 40. In addition, the recess 93a may be formed in each of the bonding surfaces 20a and 40a of the first semiconductor chip 20 and the second semiconductor chip 40 to form a weak bonding region in each of the bonding surfaces 20a and 40.

[0667] <Variation 10-9>

[0668] exist Fig.106 In the illustrated modification 10-9, recesses 93b extending in the extension direction of the bonding surface side are repeatedly arranged at predetermined intervals in the bonding surface 20a of the first semiconductor chip 20 of the first semiconductor chip 20 and the second semiconductor chip 40 to construct a weak bonding area in the bonding surface 20a of the first semiconductor chip 20. Also, in the modification 10-8, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0669] Note that in Modification 10-9, the recess 93b is provided in the bonding surface 20a of the first semiconductor chip 20, but the recess 93b may be provided in the bonding surface 40a of the second semiconductor chip 40 to form a weak bonding region in the second semiconductor chip 40. In addition, the recess 93b may be formed in each of the bonding surfaces 20a and 40a of the first semiconductor chip 20 and the second semiconductor chip 40 to form a weak bonding region in each of the bonding surfaces 20a and 40.

[0670] <Variation 10-10>

[0671] exist Fig.107 In the modification 10-10 shown, the bonding surfaces 20a and 20b of the first semiconductor chip 20 and the second semiconductor chip 40 are made hydrophobic, and weak bonding surfaces 91 and 93 are formed on the bonding surfaces 20a and 40a in the hydrophobic region 95a extending in the extending direction of each side. Also in this modification 10-10, an effect similar to that of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0672] Note that the hydrophobic weak bonding region may be formed in any one of the bonding surfaces 20 a and 40 a of the first semiconductor chip 20 and the second semiconductor chip 40 .

[0673] <Variation 10-11>

[0674] exist Fig.108In the illustrated modification 10-9, the respective bonding surfaces 20a and 20b of the first semiconductor chip 20 and the second semiconductor chip 40 are made hydrophobic, and weak bonding areas 91 and 93 are formed in the respective bonding surfaces 20a and 40a in the hydrophobic area 95b spread in the extending direction of the side surface. Also in this modification 10-11, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0675] Note that the hydrophobic weak bonding region may be formed in any one of the bonding surfaces 20 a and 40 a of the first semiconductor chip 20 and the second semiconductor chip 40 .

[0676] <Variation 10-12>

[0677] exist Fig.109 In the modification 10-12 shown, in the modification 10-5 described above, an empty space is provided between the conductive film 91b on the first semiconductor chip 20 side and the conductive film 91b on the second semiconductor chip 40 side. Also in this modification 10-10, effects similar to those of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0678] <Variation 10-13>

[0679] exist Fig.110 In the modification 10-13 shown, weak bonding surfaces 91, 93 and strong bonding surfaces 92, 94 are formed by changing the density of the island-shaped conductive film 91b of the bonding surfaces 20a, 20b of the first semiconductor chip 20 and the second semiconductor chip 40. Also in this modification 10-13, effects similar to those of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0680] <Variation 10-14>

[0681] exist Fig.111 In the variation 10-14 shown, Fig.102 The modified examples 10-5 and Fig.104 The modification 10-7 shown is combined to form weak bonding surfaces and strong bonding surfaces on the bonding surfaces 20a and 20b of the first semiconductor chip 20 and the second semiconductor chip 40. Also in this modification 10-13, effects similar to those of the solid-state imaging device 1J according to the tenth embodiment described above can be obtained.

[0682] <Variation 10-15>

[0683] exist Fig.112In the illustrated modification 10-15, the island-shaped conductive films 91b are arranged in two rows to form weak bonding regions 91 and 93. Also in this modification 10-15, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0684] <Variation 10-16>

[0685] exist Fig.113 In the illustrated modification 10-16, the number of rows of the island-shaped conductive film 91b varies on the long side and the short side. Also in this modification 10-16, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0686] <Variation 10-17>

[0687] exist Fig.114 In the variants 10-17 shown, Fig.98 The weak bonding region in (c) is configured by arranging the island-shaped conductive films into a plurality of lines. Also in this modification 10-17, effects similar to those of the solid-state imaging device 1J according to the above-described tenth embodiment can be obtained.

[0688] [Eleventh Embodiment]

[0689] <<Application examples of electronic devices>>

[0690] For example, the present technology (technology of the present disclosure) can be applied to various electronic devices including an imaging device such as a digital camera or a digital video camera, a mobile phone with an imaging function, or other devices with an imaging function.

[0691] Fig.115 is a diagram illustrating a schematic configuration of an electronic device (for example, a camera) according to a second embodiment of the present technology.

[0692] like Fig.115 As shown, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is an embodiment in the case where the solid-state imaging device 1A according to the first embodiment of the present technology is used for an electronic device (for example, a camera) as the solid-state imaging device 101.

[0693] The optical lens 102 forms an image of the image light (incident light 106) from the object on the imaging surface of the solid-state imaging device 101. As a result, the signal charge is accumulated in the solid-state imaging device 101 for a certain period. The shutter device 103 controls the light irradiation period and the light shielding period for the solid-state imaging device 101. The drive circuit 104 provides a drive signal for controlling the transmission operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The signal of the solid-state imaging device 101 is transmitted by the drive signal (timing signal) provided from the drive circuit 104. The signal processing circuit 105 performs various types of signal processing on the signal (pixel signal) output from the solid-state imaging device 101. The image signal that has been subjected to signal processing is stored in a storage medium such as a memory, or is output to a monitor.

[0694] With this configuration, in the electronic device 100 according to the second embodiment, the manufacturing yield is improved in the solid-state imaging device 101, and therefore, the cost can be reduced.

[0695] It should be noted that the electronic device 100 to which the solid-state imaging device of each embodiment described above can be applied is not limited to a camera, and the solid-state imaging device can also be applied to other electronic devices. For example, the solid-state imaging device can be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0696] In addition, the present technology can be applied to any light detection device including not only the above-mentioned solid-state imaging device as an image sensor but also a distance measuring sensor (also called a time-of-flight (ToF) sensor and measuring distance, etc.). The distance measuring sensor is a sensor that emits irradiation light toward an object, detects reflected light as the irradiation light reflected from the surface of the object, and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. The above-mentioned structure of the second semiconductor chip can be adopted as the structure of the second semiconductor chip of the distance measuring sensor.

[0697] [Other embodiments]

[0698] In the above-described embodiment, an example has been described in which the present technology is applied to the solid-state imaging device 1A called a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor. However, the present technology can also be applied to a front-illuminated image sensor and other semiconductor devices.

[0699] In addition, in the above-mentioned first embodiment, the case where the bonding surface 20a of the second semiconductor chip 40 is bonded to the bonding surface 20a of the wafer stack 60 in the process of manufacturing the solid-state imaging device 1A has been described. However, the present technology is not limited to the above-mentioned first embodiment. For example, in the process of manufacturing the solid-state imaging device 1A, the present technology can also be applied to the case where the bonding surface 40a of the second semiconductor chip 40 is bonded to the bonding surface 20a of the divided first semiconductor chip 20 by surface activation bonding.

[0700] Furthermore, in the above-described first embodiment, the case where the first semiconductor chip 20 provided with the two semiconductor layers 22 and 32 is used has been described, but the present technology can also be applied to the case where the first semiconductor chip provided with a single semiconductor layer is used.

[0701] In the first embodiment, two second semiconductor chips 40 are bonded, but the present technology can also be applied to bonding one or three or more second semiconductor chips 40. In addition, the present technology can also be applied to bonding second semiconductor chips having different planar sizes.

[0702] It should be noted that the present technology can also have the following configurations. (1)

[0704] A semiconductor device comprises: a base member having a first bonding surface; and a semiconductor chip having a second bonding surface having a quadrilateral shape, wherein

[0705] The second bonding surface of the semiconductor chip and the first bonding surface of the base member are bonded by direct bonding,

[0706] The semiconductor chip includes: a multilayer wiring layer including a second bonding surface; and a semiconductor layer provided on an opposite side to one side of the second bonding surface of the multilayer wiring layer, and

[0707] The multilayer wiring layer includes a warp suppression film that extends along at least one side of the second bonding surface and suppresses warping of the semiconductor chip. (2)

[0709] According to the semiconductor device of (2), the warp suppression film suppresses warping in which the second bonding surface side of the semiconductor chip is convex. (3)

[0711] The semiconductor device according to (2) or (2), wherein the warpage suppression film is thicker than the wirings of the multilayer wiring layer. (4)

[0713] The semiconductor device according to any one of (1) to (3), wherein the warpage suppression film is provided on each of both sides located on opposite sides of the second bonding surface, respectively. (5)

[0715] The semiconductor device according to any one of (1) to (3), wherein the warpage suppression films are provided on four side surfaces of the second bonding surface. (6)

[0717] The semiconductor device according to any one of (1) to (5), wherein the warpage suppression film is composed of any one of a silicon nitride film, a metal film, an alloy film, or a resin film. (7)

[0719] The semiconductor device according to any one of (1) to (6), wherein

[0720] The first bonding surface includes a first insulating layer included in the multi-layer wiring layer and first bonding metal pads dispersed in the first insulating layer.

[0721] The second bonding surface includes a second insulating layer and a second bonding metal pad interspersed with the second insulating layer, and

[0722] The first bonding metal pad and the second bonding metal pad are bonded by direct bonding. (8)

[0724] The semiconductor device according to (7), wherein the warpage suppression film is arranged outside the second metal pad in a plan view. (9)

[0726] The semiconductor device according to any one of (1) to (8), wherein the base member includes a semiconductor layer provided with the photoelectric conversion unit. (10)

[0728] The semiconductor device according to any one of (1) to (9), wherein

[0729] the base member is a first semiconductor chip,

[0730] The semiconductor chip is a second semiconductor chip, and

[0731] The planar size of the first semiconductor chip is larger than the planar size of the second semiconductor chip. (11)

[0733] A semiconductor device comprising:

[0734] a base member having a first engaging surface; and

[0735] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0736] Semiconductor chips include:

[0737] a multilayer wiring layer including a second bonding surface,

[0738] a semiconductor layer provided on the opposite side to one side of the second bonding surface of the multilayer wiring layer, and

[0739] a warpage suppressing portion which is provided in the multilayer wiring layer and suppresses warpage of the semiconductor chip, and

[0740] The warpage suppression portion is selectively provided on a peripheral edge portion side of the second joint surface in a plan view. (12)

[0742] The semiconductor device according to (11), wherein the warpage suppression portion extends along both sides of a corner portion including at least the second bonding surface in a plan view. (13)

[0744] A semiconductor device according to (12), wherein, in the warping suppression portion, a first width of an inner side of a first portion connecting one side of the corner and a side adjacent to the second bonding surface in a plan view is wider than a second width of an inner side of a second portion connecting one side of the corner and a side adjacent to the second bonding surface in a plan view. (14)

[0746] The light detecting device according to (11) or (12), wherein the warpage suppressing portion is selectively provided on a corner side of the second joint surface in a plan view. (15)

[0748] The light detecting device according to any one of (11) to (14), wherein the warpage suppressing portion is exposed from a side surface of the multilayer wiring layer. (16)

[0750] The semiconductor device according to any one of (11) to (14), wherein the warpage suppression film is provided over the second bonding surface and the side surface of the multilayer wiring layer. (17)

[0752] The semiconductor device according to any one of (11) to (15), wherein the warpage suppression portion is provided at least one of an inner layer of the multilayer wiring layer or the second bonding surface. (18)

[0754] According to the semiconductor device of (11), the warpage suppression portion is provided on the second bonding surface of the multilayer wiring layer and is directly bonded to the first bonding surface of the base member. (19)

[0756] The semiconductor device according to any one of (11) to (18), wherein

[0757] The first bonding surface includes a first insulating layer included in the wiring layer and a first bonding metal pad interspersed with the first insulating layer,

[0758] The second bonding surface includes a second insulating layer and a second bonding metal pad interspersed with the second insulating layer, and

[0759] The first bonding metal pad and the second bonding metal pad are bonded by direct bonding. (20)

[0761] A semiconductor device according to (19), wherein the warpage suppression portion is arranged outside the second metal pad in a plan view. (twenty one)

[0763] The semiconductor device according to any one of (11) to (20), wherein the base member includes a semiconductor layer provided with the photoelectric conversion unit. (twenty two)

[0765] A semiconductor device comprising:

[0766] a base member having a first engaging surface; and

[0767] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0768] Semiconductor chips include:

[0769] a multilayer wiring layer including a second bonding surface,

[0770] a semiconductor layer provided on the opposite side of one side of the second bonding surface of the multilayer wiring layer and having a back surface having a quadrilateral shape on the opposite side of one side of the multilayer wiring layer, and

[0771] a warpage suppressing portion provided in the semiconductor layer and suppressing warpage of the semiconductor chip, and

[0772] The warpage suppression portion is selectively provided on a peripheral edge portion side of a rear surface of the semiconductor layer in a plan view. (twenty three)

[0774] The semiconductor device according to (22), wherein the warpage suppression portion is a modified layer having disturbed crystallinity. (twenty four)

[0776] A semiconductor device according to any one of (22) to (25), wherein the modified layer extends inward from a peripheral portion side of a rear surface of the semiconductor layer in a plan view. (25)

[0778] The semiconductor device according to (22), wherein

[0779] The back side of the semiconductor layer includes a first portion having a first thickness and a second portion having a second thickness thicker than the first thickness, and

[0780] The warpage suppression portion is the second portion. (26)

[0782] A semiconductor device according to (27), wherein the second portion extends inward from a peripheral portion side of a rear surface of the semiconductor layer in a plan view. (27)

[0784] A semiconductor device comprising:

[0785] a base member having a first engaging surface; and

[0786] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0787] Semiconductor chips include:

[0788] a multilayer wiring layer including a second bonding surface, and

[0789] a semiconductor layer provided on a side opposite to a side of the second bonding surface of the multilayer wiring layer,

[0790] The second joint surface includes: an insulating layer included in the multi-layer wiring layer; and a weak joint portion having a weaker joint force with the first joint surface than the insulating layer; and

[0791] The weak joining portion is provided on the peripheral edge portion side of the second joining surface. (28)

[0793] The semiconductor device according to (27), wherein the weak bonding portion extends along one side of the second bonding surface. (29)

[0795] The semiconductor device according to (27), wherein the weak bonding portions are dispersed along one side of the second bonding surface. (30)

[0797] The semiconductor device according to any one of (27) to (29), wherein the weak bonding portion includes a porous film. (31)

[0799] A semiconductor device comprising:

[0800] a base member having a first engaging surface; and

[0801] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0802] The peripheral edge portion of the second joint surface is curved. (32)

[0804] The semiconductor device according to (31), wherein the peripheral portion of the second bonding surface has a planar shape in which a first peripheral portion and a second peripheral portion located inside the first peripheral portion are repeatedly arranged in one direction in a plan view. (33)

[0806] The semiconductor device according to any one of (31) or (32), wherein

[0807] The semiconductor chip has a recess extending inwardly from a side surface of the semiconductor chip, and

[0808] The planar shape of the recessed portion is reflected in the peripheral portion of the second joint surface. (34)

[0810] A semiconductor device according to (33), wherein the recess is embedded with an insulating material. (35)

[0812] The semiconductor device according to any one of (30) to (33), wherein

[0813] The semiconductor chip has a back surface on the side opposite to the second bonding surface, and

[0814] The recess extends from the second bonding surface to one side of the back surface of the semiconductor chip. (36)

[0816] A semiconductor device comprising:

[0817] a base member having a first joint surface having a quadrilateral shape; and

[0818] A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein

[0819] At least one of the first joint surface or the second joint surface includes a weak joint area and a strong joint area having a relatively different joint force from the other joint surface, and one weak joint area is provided on the peripheral portion side of one joint surface. (37)

[0821] An electronic device, comprising:

[0822] Semiconductor devices;

[0823] an optical lens configured to form an image of image light from a subject on an imaging surface of the semiconductor device; and

[0824] A signal processing circuit is configured to perform signal processing on a signal output from the semiconductor layer, wherein

[0825] Semiconductor devices include:

[0826] a base member having a first bonding surface; and a semiconductor chip having a second bonding surface having a quadrilateral shape,

[0827] The second bonding surface of the semiconductor chip and the first bonding surface of the base member are bonded by direct bonding,

[0828] The semiconductor chip includes: a multilayer wiring layer including a second bonding surface; and a semiconductor layer provided on an opposite side to one side of the second bonding surface of the multilayer wiring layer, and

[0829] The multilayer wiring layer includes a warp suppression film that extends along at least one side of the second bonding surface and suppresses warping of the semiconductor chip.

[0830] The scope of the present technology is not limited to the exemplary embodiments shown in the drawings and described above, but also includes all embodiments that produce effects equivalent to the effects that the present technology is intended to produce. In addition, the scope of the present technology is not limited to the combination of the features of the present invention defined by the claims, and may be defined by any desired combination of specific features among all the features disclosed.

[0831] Reference Symbols List

[0832] 1A Solid-state imaging device

[0833] 2 chip stack

[0834] 2A pixel array unit

[0835] 2B Periphery

[0836] 3 pixels

[0837] 4 Vertical drive circuit

[0838] 5 columns of signal processing circuits

[0839] 6 Horizontal drive circuit

[0840] 7 Output Circuit

[0841] 8 Control circuit

[0842] 10 pixel drive lines

[0843] 11 Vertical signal line

[0844] 13 Logic Circuits

[0845] 14 Bonding pads

[0846] 15 Pixel circuit (readout circuit)

[0847] 16 photoelectric conversion units

[0848] 20 first semiconductor chip (base member)

[0849] 20a: Joining surface (first joining surface)

[0850] 21. First substrate unit

[0851] 22 Semiconductor layer

[0852] 23 Multi-layer wiring layer

[0853] 24 Bonding metal pad

[0854] 25 multi-layer wiring layer

[0855] 26 Insulation layer (first insulation layer)

[0856] 27 bonding metal pad (first bonding metal pad)

[0857] 27f Dummy pad

[0858] 28 Contact electrode

[0859] 31 Second base unit

[0860] 32 Semiconductor layer

[0861] 33 Multi-layer wiring layer

[0862] 34 Bonding metal pad

[0863] 35 Photoelectric conversion area

[0864] 36 optical filter layers

[0865] 37 Microlens

[0866] 38 Joint opening

[0867] 40 Second semiconductor chip

[0868] 40a: Joining surface (second joining surface)

[0869] 40a1,40a2,40a3,40a4 side

[0870] 42 Semiconductor layer

[0871] 42b Back

[0872] 45 multi-layer wiring layer

[0873] 45a Multi-stage stacking unit

[0874] 45a1 wiring

[0875] 45b,45c,45d,45e,45f Warp suppression film

[0876] 45b1 Part 1

[0877] 45b 11 Opening

[0878] 45b 12 Membrane

[0879] 45b2 Part 2

[0880] 46 insulation layer (second insulation layer)

[0881] 47 Bonding metal pad

[0882] 51 Sealing body

[0883] 60 Wafer Stack

[0884] 61,62 Semiconductor wafer

[0885] 64 marking lines (cutting lines)

[0886] 65 Chip formation area

[0887] 68 Blank Space

[0888] 79 Slice

[0889] 81 Modified layer

[0890] 82 Steps

[0891] 82a Thick part (second part)

[0892] 82b thin part (first part)

[0893] 85 Weak joint

[0894] 86 recess

[0895] 87 Insulation Materials

[0896] 100 Electronic devices

[0897] 101 Solid-state imaging device

[0898] 102 Optical lens

[0899] 103 Shutter device

[0900] 104 Driving Circuit

[0901] 105 Signal Processing Circuit

[0902] 106 Incident Light

[0903] AMP Amplifier Transistor

[0904] FD Charge Retention Region

[0905] FDG Switching Transistor

[0906] PD Photoelectric conversion element

[0907] RST Reset transistor

[0908] SEL select transistor

[0909] TR Transfer Transistor

[0910] Cm Chip mounting area

[0911] Cs, Cv peripheral part

[0912] Cs1 First peripheral part

[0913] Cs2 Second peripheral part

[0914] Cr, Cw corner

Claims

1. A semiconductor device comprising: a base member having a first engagement surface; and a semiconductor chip having a second bonding surface having a quadrilateral shape, wherein the second bonding surface of the semiconductor chip and the first bonding surface of the base member are bonded by direct bonding, The semiconductor chip includes: a multilayer wiring layer including the second bonding surface; and a semiconductor layer provided on an opposite side of one side of the second bonding surface of the multilayer wiring layer, and The multilayer wiring layer includes a warp suppression film that extends along at least one side of the second bonding surface and suppresses warping of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein The warpage suppression film suppresses warpage of a convex side of the second bonding surface of the semiconductor chip.

3. The semiconductor device according to claim 1, wherein The warpage suppression film is thicker than wirings of the multilayer wiring layer.

4. The semiconductor device according to claim 1, wherein The warpage suppression films are respectively provided on each of both sides located on opposite sides of the second joint surface.

5. The semiconductor device according to claim 1, wherein The warpage suppression films are provided on four sides of the second bonding surface.

6. The semiconductor device according to claim 1, wherein The warpage suppression film is configured of any one of a silicon nitride film, a metal film, an alloy film, or a resin film.

7. The semiconductor device according to claim 1, wherein The first bonding surface includes a first insulating layer included in the wiring layer and a first bonding metal pad interspersed with the first insulating layer, The second bonding surface includes a second insulating layer and a second bonding metal pad interspersed with the second insulating layer, and The first bonding metal pad and the second bonding metal pad are bonded by direct bonding.

8. The semiconductor device according to claim 7, wherein: The warpage suppression film is arranged outside the second metal pad in a plan view.

9. The semiconductor device according to claim 1, wherein: The base member includes the semiconductor layer provided with a photoelectric conversion unit.

10. The semiconductor device according to claim 1, wherein The base member is a first semiconductor chip, The semiconductor chip is a second semiconductor chip, and A planar size of the first semiconductor chip is larger than a planar size of the second semiconductor chip.

11. A semiconductor device comprising: a base member having a first engagement surface; as well as A semiconductor chip having a second bonding surface in a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein The semiconductor chip comprises: a multilayer wiring layer including the second bonding surface, a semiconductor layer provided on the opposite side to one side of the second bonding surface of the multilayer wiring layer, and a warpage suppressing portion provided in the multilayer wiring layer and suppressing warpage of the semiconductor chip, and The warpage suppressing portion is selectively provided on a peripheral edge portion side of the second joint surface in a plan view.

12. The semiconductor device according to claim 11, wherein The warpage suppressing portion extends along both sides of a corner portion including at least the second joint surface in a plan view.

13. The semiconductor device according to claim 12, wherein: In the warping suppression portion, a first width of an inner side of a first portion connecting one side of the corner and the side adjacent to the second joining surface in a plan view is wider than a second width of an inner side of a second portion connecting one side of the side and the side adjacent to the second joining surface in a plan view.

14. The light detection device according to claim 11, wherein The warpage suppression portion is selectively provided on a corner side of the second joint surface in a plan view.

15. The light detection device according to claim 11, wherein The warpage suppression portion is exposed from a side surface of the multilayer wiring layer.

16. The semiconductor device according to claim 11, wherein A warpage suppression film is provided on the second bonding surface and the side surfaces of the multilayer wiring layer.

17. The semiconductor device according to claim 11, wherein The warpage suppression portion is provided at least one of an inner layer of the multilayer wiring layer or the second bonding surface.

18. The semiconductor device according to claim 11, wherein The warpage suppression portion is provided on the second joining surface of the multilayer wiring layer and is directly joined to the first joining surface of the base member.

19. The semiconductor device according to claim 11, wherein The first bonding surface includes a first insulating layer included in the wiring layer and a first bonding metal pad interspersed with the first insulating layer, The second bonding surface includes a second insulating layer and a second bonding metal pad interspersed with the second insulating layer, and The first bonding metal pad and the second bonding metal pad are bonded by direct bonding.

20. The semiconductor device according to claim 19, wherein The warpage suppression portion is arranged outside the second metal pad in a plan view.

21. The semiconductor device according to claim 11, wherein The base member includes the semiconductor layer provided with a photoelectric conversion unit.

22. A semiconductor device comprising: a base member having a first engagement surface; as well as a semiconductor chip having a second bonding surface of a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein The semiconductor chip comprises: a multilayer wiring layer including the second bonding surface, a semiconductor layer provided on the opposite side to one side of the second bonding surface of the multilayer wiring layer and having a back surface in a quadrilateral shape on the opposite side to one side of the multilayer wiring layer, and a warpage suppressing portion provided in the semiconductor layer and suppressing warpage of the semiconductor chip, and The warpage suppression portion is selectively provided on a peripheral portion side of a rear surface of the semiconductor layer in a plan view.

23. The semiconductor device according to claim 22, wherein: The warpage suppression portion is a modified layer having disordered crystallinity.

24. The semiconductor device according to claim 22, wherein: The modified layer has a lower density than the semiconductor layer.

25. The semiconductor device according to claim 22, wherein: The back side of the semiconductor layer includes a first portion having a first thickness and a second portion having a second thickness thicker than the first thickness, and The warpage suppression portion is the second portion.

26. The semiconductor device according to claim 25, wherein The second portion extends inward from the peripheral edge portion side of the rear surface of the semiconductor layer in a plan view.

27. A semiconductor device comprising: a base member having a first engagement surface; as well as a semiconductor chip having a second bonding surface of a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein The semiconductor chip comprises: a multilayer wiring layer including the second bonding surface, and a semiconductor layer provided on a side opposite to a side of the second bonding surface of the multilayer wiring layer, The second joint surface includes: an insulating layer included in the multi-layer wiring layer; and a weak joint portion having a weaker joint force with the first joint surface than the insulating layer; and The weak engagement portion is provided on the peripheral edge portion side of the second engagement surface.

28. The semiconductor device according to claim 27, wherein: The weak engagement portion extends along one side of the second engagement surface.

29. The semiconductor device according to claim 27, wherein: The weak engagement portions are distributed along one side of the second engagement surface.

30. The semiconductor device according to claim 27, wherein The weak joining portion includes a porous film.

31. A semiconductor device comprising: a base member having a first engagement surface; as well as a semiconductor chip having a second bonding surface of a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein A peripheral portion of the second joint surface is curved.

32. The semiconductor device according to claim 31, wherein The peripheral portion of the second joint surface has a curved shape in which a first peripheral portion and a second peripheral portion located inside the first peripheral portion are repeatedly arranged in one direction in a plan view.

33. The semiconductor device according to claim 31, wherein The semiconductor chip has a recess extending inwardly from a side surface of the semiconductor chip, and The planar shape of the recessed portion is reflected in the peripheral edge portion of the second joint surface.

34. The semiconductor device according to claim 33, wherein: The recess is embedded with an insulating material.

35. The semiconductor device according to claim 31, wherein The semiconductor chip has a back surface on an opposite side of the second bonding surface, and The recess extends from the second bonding surface to one side of the back surface of the semiconductor chip.

36. A semiconductor device comprising: a base member having a first engaging surface having a quadrilateral shape; as well as a semiconductor chip having a second bonding surface of a quadrilateral shape, the second bonding surface being directly bonded to the first bonding surface of the base member, wherein At least one of the first joint surface or the second joint surface includes a weak joint area and a strong joint area having a relatively different joint force from the other joint surface, and one weak joint area is provided in one joint surface on the peripheral portion side.

37. An electronic device comprising: Semiconductor devices; an optical lens configured to form an image of image light from a subject on an imaging surface of the semiconductor device; as well as A signal processing circuit is configured to perform signal processing on a signal output from the semiconductor layer, wherein The semiconductor device comprises: a base member having a first bonding surface; and a semiconductor chip having a second bonding surface having a quadrilateral shape, the second bonding surface of the semiconductor chip and the first bonding surface of the base member are bonded by direct bonding, The semiconductor chip includes: a multilayer wiring layer including the second bonding surface; and a semiconductor layer provided on an opposite side of one side of the second bonding surface of the multilayer wiring layer, and The multilayer wiring layer includes a warp suppression film that extends along at least one side of the second bonding surface and suppresses warping of the semiconductor chip.

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