Wide-input-range low-power-consumption PWM controller

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a circuit of a PWM (Pulse Width Modulation) controller with a wide input range and low power consumption. The PWM controller circuit comprises a reference circuit, an error amplifier, a current mode comparator, a clock circuit, a protection circuit and a digital logic circuit module. The frequency of the clock circuit is controlled by applying a capacitor outside a chip, and the duty ratio is controlled by detecting an external current, so that the output power is controlled, and finally the output voltage is controlled. According to the invention, the voltage within a relatively large input range can be controlled to be 20-100V.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, in particular to a power management chip circuit. Background Art

[0002] The power supply is the core part of various electronic products, and the performance of the power supply directly affects the performance of electronic products. Nowadays, power management chips are developing in the direction of high integration, high efficiency, and portability, and have been developing in depth in terms of small size, low power consumption, and high integration. In power management chips, analog circuit modules and digital logic modules are often contained inside, and a stable internal power supply is required to achieve normal functions. The power efficiency of DCDC power management chips is extremely high. Compared with the management chip efficiency of LDO, it can reach more than 90%. The key components inside the switching power supply work in a high-frequency switching state, and the energy consumed itself is extremely low. According to the number of active power devices, isolated DCDC converters can be divided into three categories: single-tube active forward, flyback, and Cuk, and dual-tube forward, dual-tube flyback, push-pull, and half-bridge. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention provides a low-offset, low-noise, high-precision rail-to-rail operational amplifier circuit.

[0004] The present invention is achieved through the following scheme:

[0005] A circuit of a PWM controller with wide input range and low power consumption is characterized in that the circuit comprises a reference module, an error amplifier module, a current analog comparator module, a power supply module, a clock circuit module, a protection circuit, and a digital logic module.

[0006] Further, the reference module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, and a first voltage regulator tube M1;

[0007] The emitter of the first NPN tube Q1 of the reference module is grounded, and the base is connected to the collector. The emitter of the second NPN tube Q2 is connected to the collector of the first NPN tube Q1, and the base is connected to the collector. The emitter of the third NPN tube Q3 is connected to the collector of the second NPN tube Q2, and the base is connected to the collector. One end of the first resistor R1 is connected to the third NPN tube Q3. The second resistor R2 is connected to the first resistor R1. The third resistor R3 is connected to the second resistor R2. The fourth resistor R4 is connected to the third resistor R3. The fifth resistor R5 is connected to the sixth resistor R6, the seventh resistor R7 is connected to the sixth resistor R6, the eighth resistor R8 is connected to the seventh resistor R7, the emitter of the fourth NPN tube Q4 is connected to the first resistor R8, the collector of the fourth NPN tube Q4 is connected to the power supply VCC, the base is connected to the output end of the first voltage regulator tube M1 and the drain end of the first PMOS tube P1, the input end of the first voltage regulator tube M1 is connected to the ground line, the gate terminal of the first PMOS tube P1 is connected to the bias voltage BISE, and the source terminal of the first PMOS tube is connected to the power supply VCC.

[0008] Further, the error amplifier module includes a fifth NPN tube Q5, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a ninth resistor R9, a tenth resistor R10, and a first capacitor C1;

[0009] The emitter of the fifth NPN tube Q5 of the error amplifier module is grounded, connected to the emitter of the sixth NPN tube Q6, the emitter of the seventh NPN tube Q7, and the emitter of the ninth NPN tube Q9, the base of the fifth NPN tube Q5 is connected to the collector and the base of the sixth NPN tube, the drain of the second PMOS tube P2 is connected to the collector of the fifth NPN tube Q5, the gate of the second PMOS tube P2 is connected to the bias voltage VBF, the source of the second PMOS tube P2 is connected to the source P3 of the third PMOS tube and the drain of the fourth PMOS tube P4, the source of the fourth PMOS tube P4 is connected to the source of the fifth PMOS tube and the collector of the eighth NPN tube Q8, and connected to the power supply VCC, the The gate of the fourth PMOS tube P4 is connected to the gate of the fifth PMOS tube, the gate of the third PMOS tube is connected to the reference voltage VREF, the drain is connected to the collector of the sixth NPN tube Q6 and the base of the seventh NPN tube Q7, the collector of the seventh NPN tube is connected to the drain of the fifth PMOS tube P5 and the base of the eighth NPN tube Q8, the two ends of the first capacitor C1 are connected between the base and the collector of the seventh NPN tube Q7, the emitter of the eighth NPN tube Q8 is connected to the ninth resistor R9, the ninth resistor R9 is connected to the tenth resistor R10 and the collector of the ninth NPN tube Q9, the other end of the tenth resistor R10 is connected to the COMP output, and the base of the ninth NPN tube is connected to the bias voltage VBN.

[0010] Further, the current mode comparator includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a tenth NPN tube Q10, an eleventh resistor R11, and a twelfth resistor R12;

[0011] The source of the first NMOS tube N1 of the current mode comparator module is connected to the source of the second NMOS tube, and is externally connected to an external current source. The gate of the first NMOS tube N1 is connected to COMP, and the drain is connected to the drain of the sixth PMOS tube P6. The source of the sixth PMOS tube P6 is connected to the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube, and is connected to the power supply VCC. The gate of the sixth PMOS tube P6 is connected to the gate of the seventh PMOS tube P7 and the gate of the eighth PMOS tube. The drain of the seventh PMOS tube P7 is connected to The drain of the second NMOS tube N2 is connected, the gate of the second NMOS tube N2 is connected to the gate of the third NMOS tube N3, the drain of the eighth PMOS tube P8 is connected to the drain of the third NMOS tube N3, the gate and the drain of the third NMOS tube N3 are connected, the source of the third NMOS tube N3 is connected to the collector of the tenth NPN tube Q10, the base and the collector are connected, the emitter of the tenth NPN tube Q10 is connected to the eleventh resistor R11, the eleventh resistor R11 is connected to the twelfth resistor R12, and the twelfth resistor R12 is grounded.

[0012] Further, the power module includes a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, an eleventh NPN tube Q11, and a thirteenth resistor R13;

[0013] One end of the thirteenth resistor R13 of the power module is connected to the bias voltage BIAS, and the other end is connected to the drain of the ninth PMOS tube P9. The source of the ninth PMOS tube P9 is connected to the source of the tenth PMOS tube P10 and the source of the eleventh PMOS tube P11, and is externally connected to VCC. The gate and drain of the ninth PMOS tube P9 are connected, and the gate is connected to the gate of the tenth PMOS tube P10, and the output voltage VBP is output. The gate of the tenth PMOS tube P10 is connected to the gate of the eleventh PMOS tube P11, the drain of the tenth PMOS tube is connected to the collector of the eleventh NPN tube Q11, the base of the eleventh NPN tube Q11 is connected to the collector, and the output voltage VBN is output. The emitter of the eleventh NPN tube Q11 is connected to the drain of the eleventh PMOS tube P11, and is externally grounded.

[0014] Further, the clock module includes a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a second capacitor C2, a third capacitor C3, a fourteenth resistor R14, and a fifteenth resistor R15;

[0015] One end of the second capacitor C2 of the clock module is connected to the fourteenth resistor R14, the third capacitor C3, the gate of the sixth NMOS tube N6, the gate of the twelfth PMOS tube, and the gate of the fifth NMOS tube N5, and the other end is connected to GND!, the fourteenth resistor R14 is connected to the drain of the fourth NMOS tube N4, the source of the fourth NMOS tube N4 is connected to the fifteenth resistor R15, the fifteenth resistor R15 is connected to the discharge port DISCHARGE, the gate of the fourth NMOS tube is connected to the third capacitor C3, the drain of the thirteenth PMOS tube P13, the drain of the seventh NMOS tube N7, the drain of the eighth NMOS tube N8, the gate of the fourteenth PMOS tube P14, the gate of the eighth NMOS tube N8, the source of the fifth NMOS tube N5 is connected to the source of the seventh NMOS tube N7, and the external GND! The drain of the fifth NMOS tube N5 is connected to the source of the sixth NMOS tube N6, the drain of the sixth NMOS tube N6 is connected to the drain of the twelfth PMOS tube P12, the gate of the seventh NMOS tube N7, and the gate of the thirteenth PMOS tube P13, the source of the twelfth PMOS tube P12 is connected to the source of the thirteenth PMOS tube P13, and is externally connected to the power supply VCC, the drain of the eighth NMOS tube N8 is connected to the drain of the fourteenth PMOS tube P14, and is connected to the output OSCOUT, the source of the eighth NMOS tube N8 is connected to GND!, and the source of the fourteenth PMOS tube P14 is connected to the power supply VCC.

[0016] Further, the protection module 1 includes a twelfth NPN tube Q12, a thirteenth NPN tube Q13, a fourteenth NPN tube Q14, a fifteenth NPN tube Q15, a sixteenth NPN tube Q16, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, and a second voltage regulator tube M2;

[0017] The emitter of the twelfth NPN tube Q12 of the protection module 1 is connected to the emitter of the thirteenth NPN tube Q13 and is externally grounded, the base of the twelfth NPN tube Q12 is connected to the base of the thirteenth NPN tube Q13, the collector of the twelfth NPN tube Q12 is connected to the drain of the fifteenth PMOS tube P15, the gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube P16, the source of the fifteenth PMOS tube P15 is connected to the source of the sixteenth PMOS tube P16 and is externally connected to VCC, the drain of the sixteenth PMOS tube is connected to the output end of the second voltage regulator tube M2, and the second The output end of the Zener tube M2 is connected to the collector of the sixteenth NPN tube Q16, the base of the sixteenth NPN tube Q16 is connected to the collector, the emitter of the sixteenth NPN tube Q16 is connected to the collector of the fifteenth NPN tube Q15, the base of the fifteenth NPN tube Q15 is connected to the collector, the emitter of the fifteenth NPN tube Q15 is connected to the collector of the fourteenth NPN tube Q14, the base of the fourteenth NPN tube Q14 is connected to the collector, the emitter of the fourteenth NPN tube Q14 is connected to the collector of the thirteenth NPN tube Q13, and the base of the thirteenth NPN tube Q13 is connected to the collector.

[0018] Further, the protection module 2 includes a seventeenth NPN tube Q17, an eighteenth NPN tube Q18, a nineteenth NPN tube Q19, a twentieth NPN tube Q20, a third voltage regulator tube M3, a seventeenth PMOS tube P17, and an eighteenth PMOS tube P18;

[0019] The emitter of the seventeenth NPN tube Q17 of the protection module 2 is connected to the emitter of the eighteenth NPN tube Q18 and to the ground, the base of the seventeenth NPN tube Q17 is connected to the base of the eighteenth NPN tube Q18, the base of the seventeenth NPN tube Q17 is connected to the collector, the collector is connected to the emitter of the nineteenth NPN tube Q19, the base of the nineteenth NPN tube Q19 is connected to the collector, the collector of the nineteenth NPN tube Q19 is connected to the emitter of the twentieth NPN tube Q20, and the twentieth NPN The base of the tube Q20 is connected to the collector, the collector of the twentieth NPN tube Q20 is connected to the input electrode of the third voltage regulator tube M3, the output stage of the third voltage regulator tube M3 is connected to the drain of the seventeenth PMOS tube P17, the gate P17 of the seventeenth PMOS tube P17 is connected to the gate of the eighteenth PMOS tube P18, the bias voltage VBP is connected, the source is connected to the source of the eighteenth PMOS tube P18 and connected to VCC, and the drain of the eighteenth PMOS tube P18 is connected to the collector of the eighteenth NPN tube Q18.

[0020] The advantages and positive effects of the present invention are: the present invention designs a wide-input low-power PWM controller, the overall input is controlled at 20-100V to achieve a wide range of input. The efficiency is up to 90%, and the maximum load is 50W, which meets most of the market demand for power management chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a circuit diagram of a reference module in the present invention;

[0022] Figure 2 This is a circuit diagram of the error amplifier module in the present invention;

[0023] Figure 3 This is a module diagram of a current mode comparator in the present invention;

[0024] Figure 4 This is a diagram of a power module in the present invention;

[0025] Figure 5 This is a clock module diagram in the present invention;

[0026] Figure 6 This is a diagram of a protection module in the present invention;

[0027] Figure 7 This is the second diagram of the protection module in the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0029] In an embodiment of the present invention, a circuit of a PWM controller with wide input range and low power consumption includes a reference module, an error amplifier module, a current mode comparator module, a power supply module, a clock circuit module, a protection circuit, and a digital logic module.

[0030] like Figure 1 As shown, the reference module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, and a first voltage regulator tube M1;

[0031] The emitter of the first NPN tube Q1 of the reference module is grounded, and the base is connected to the collector. The emitter of the second NPN tube Q2 is connected to the collector of the first NPN tube Q1, and the base is connected to the collector. The emitter of the third NPN tube Q3 is connected to the collector of the second NPN tube Q2, and the base is connected to the collector. One end of the first resistor R1 is connected to the third NPN tube Q3. The second resistor R2 is connected to the first resistor R1. The third resistor R3 is connected to the second resistor R2. The fourth resistor R4 is connected to the third resistor R3. The fifth resistor R5 is connected to the sixth resistor R6, the seventh resistor R7 is connected to the sixth resistor R6, the eighth resistor R8 is connected to the seventh resistor R7, the emitter of the fourth NPN tube Q4 is connected to the first resistor R8, the collector of the fourth NPN tube Q4 is connected to the power supply VCC, the base is connected to the output end of the first voltage regulator tube M1 and the drain end of the first PMOS tube P1, the input end of the first voltage regulator tube M1 is connected to the ground line, the gate terminal of the first PMOS tube P1 is connected to the bias voltage BISE, and the source terminal of the first PMOS tube is connected to the power supply VCC.

[0032] In this example, when the first PMOS tube P1 is connected to the external bias voltage BISE, it is normally turned on and is in a saturated state. A saturated current flows through it to provide a bias for the fourth NPN tube Q4. The fourth NPN tube Q4 is normally turned on, and the current flows through the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, the first NPN tube Q1, the second NPN tube Q2, and the third NPN tube Q3, and each is biased to achieve voltage control, and then the required voltage is output through each resistor.

[0033] like Figure 2 As shown, the error amplifier module includes a fifth NPN tube Q5, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a ninth resistor R9, a tenth resistor R10, and a first capacitor C1.

[0034] The emitter of the fifth NPN tube Q5 of the error amplifier module is grounded, connected to the emitter of the sixth NPN tube Q6, the emitter of the seventh NPN tube Q7, and the emitter of the ninth NPN tube Q9, the base of the fifth NPN tube Q5 is connected to the collector and the base of the sixth NPN tube, the drain of the second PMOS tube P2 is connected to the collector of the fifth NPN tube Q5, the gate of the second PMOS tube P2 is connected to the bias voltage VBF, the source of the second PMOS tube P2 is connected to the source P3 of the third PMOS tube and the drain of the fourth PMOS tube P4, the source of the fourth PMOS tube P4 is connected to the source of the fifth PMOS tube and the collector of the eighth NPN tube Q8, and connected to the power supply VCC, the The gate of the fourth PMOS tube P4 is connected to the gate of the fifth PMOS tube, the gate of the third PMOS tube is connected to the reference voltage VREF, the drain is connected to the collector of the sixth NPN tube Q6 and the base of the seventh NPN tube Q7, the collector of the seventh NPN tube is connected to the drain of the fifth PMOS tube P5 and the base of the eighth NPN tube Q8, the two ends of the first capacitor C1 are connected between the base and the collector of the seventh NPN tube Q7, the emitter of the eighth NPN tube Q8 is connected to the ninth resistor R9, the ninth resistor R9 is connected to the tenth resistor R10 and the collector of the ninth NPN tube Q9, the other end of the tenth resistor R10 is connected to the COMP output, and the base of the ninth NPN tube is connected to the bias voltage VBN.

[0035] In this example, the gate of the third PMOS tube P3 is connected to the voltage VREF provided by the reference, and the gate of the second PMOS tube P2 is connected to the feedback voltage VBF introduced externally, and the two voltages are compared. The signal is output through the seventh NPN tube Q7, and the first capacitor C1 is introduced between the base and the collector of the seventh NPN tube Q7 to perform Miller compensation on the circuit. The signal is further transmitted to the eighth NPN tube Q8 to construct an emitter follower structure.

[0036] like Figure 3 As shown, the current mode comparator includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a tenth NPN tube Q10, an eleventh resistor R11, and a twelfth resistor R12.

[0037] The source of the first NMOS tube N1 of the current mode comparator module is connected to the source of the second NMOS tube, and is externally connected to an external current source. The gate of the first NMOS tube N1 is connected to COMP, and the drain is connected to the drain of the sixth PMOS tube P6. The source of the sixth PMOS tube P6 is connected to the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube, and is connected to the power supply VCC. The gate of the sixth PMOS tube P6 is connected to the gate of the seventh PMOS tube P7 and the gate of the eighth PMOS tube. The drain of the seventh PMOS tube P7 is connected to The drain of the second NMOS tube N2 is connected, the gate of the second NMOS tube N2 is connected to the gate of the third NMOS tube N3, the drain of the eighth PMOS tube P8 is connected to the drain of the third NMOS tube N3, the gate and the drain of the third NMOS tube N3 are connected, the source of the third NMOS tube N3 is connected to the collector of the tenth NPN tube Q10, the base and the collector are connected, the emitter of the tenth NPN tube Q10 is connected to the eleventh resistor R11, the eleventh resistor R11 is connected to the twelfth resistor R12, and the twelfth resistor R12 is grounded.

[0038] In this example, the gate of the first NMOS tube N1 is connected to the COMP signal introduced by the error amplifier, the source of the first NMOS tube N1 is connected to the source of the second NMOS tube N2, and the external SENSE signal is connected to provide a tail current for the circuit, and the output of the comparison signals COMPA and COMPB is achieved by affecting the saturation current of the first NMOS tube N1 and the second NMOS tube N2. The sixth PMOS tube P6, the seventh PMOS tube P7, and the eighth PMOS tube P8 together form a current mirror structure. When the current passes through, the gate voltage of the second NMOS tube is biased through the voltage division and the conduction voltage drop of the twelfth resistor R12, the eleventh resistor R11, the tenth NPN tube Q10, and the third NMOS tube N3.

[0039] like Figure 4 As shown, the power module includes a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, an eleventh NPN tube Q11, and a thirteenth resistor R13.

[0040] One end of the thirteenth resistor R13 of the power module is connected to the bias voltage BIAS, and the other end is connected to the drain of the ninth PMOS tube P9. The source of the ninth PMOS tube P9 is connected to the source of the tenth PMOS tube P10 and the source of the eleventh PMOS tube P11, and is externally connected to VCC. The gate and drain of the ninth PMOS tube P9 are connected, and the gate is connected to the gate of the tenth PMOS tube P10, and the output voltage VBP is output. The gate of the tenth PMOS tube P10 is connected to the gate of the eleventh PMOS tube P11, the drain of the tenth PMOS tube is connected to the collector of the eleventh NPN tube Q11, the base of the eleventh NPN tube Q11 is connected to the collector, and the output voltage VBN is output. The emitter of the eleventh NPN tube Q11 is connected to the drain of the eleventh PMOS tube P11, and is externally grounded.

[0041] In this example, the gates of the ninth PMOS tube P9, the first PMOS tube P10, and the eleventh PMOS tube P11 are connected to each other to form a current mirror structure. The thirteenth resistor R13 is connected to the external bias voltage BIAS to provide voltage for the circuit. The eleventh NPN tube Q11 is normally turned on to achieve a VBN bias of about 0.7V to provide voltage for the internal circuit. When the circuit works normally, the bias voltage VBP of the internal circuit is provided at the gate of the ninth PMOS tube P9.

[0042] like Figure 5 As shown, the clock module includes a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a second capacitor C2, a third capacitor C3, a fourteenth resistor R14, and a fifteenth resistor R15.

[0043] One end of the second capacitor C2 of the clock module is connected to the fourteenth resistor R14, the third capacitor C3, the gate of the sixth NMOS tube N6, the gate of the twelfth PMOS tube, and the gate of the fifth NMOS tube N5, and the other end is connected to GND!, the fourteenth resistor R14 is connected to the drain of the fourth NMOS tube N4, the source of the fourth NMOS tube N4 is connected to the fifteenth resistor R15, the fifteenth resistor R15 is connected to the discharge port DISCHARGE, the gate of the fourth NMOS tube is connected to the third capacitor C3, the drain of the thirteenth PMOS tube P13, the drain of the seventh NMOS tube N7, the drain of the eighth NMOS tube N8, the gate of the fourteenth PMOS tube P14, the gate of the eighth NMOS tube N8, the source of the fifth NMOS tube N5 is connected to the source of the seventh NMOS tube N7, and the external GND! The drain of the fifth NMOS tube N5 is connected to the source of the sixth NMOS tube N6, the drain of the sixth NMOS tube N6 is connected to the drain of the twelfth PMOS tube P12, the gate of the seventh NMOS tube N7, and the gate of the thirteenth PMOS tube P13, the source of the twelfth PMOS tube P12 is connected to the source of the thirteenth PMOS tube P13, and is externally connected to the power supply VCC, the drain of the eighth NMOS tube N8 is connected to the drain of the fourteenth PMOS tube P14, and is connected to the output OSCOUT, the source of the eighth NMOS tube N8 is connected to GND!, and the source of the fourteenth PMOS tube P14 is connected to the power supply VCC.

[0044] In this example, the twelfth PMOS tube P12, the sixth NMOS tube N6, and the fifth NMOS tube N5 form a first-stage inverter structure, the thirteenth PMOS tube P13 and the seventh NMOS tube N7 form a second-stage inverter structure, and the fourth NMOS tube N4 forms a third-stage inverter. The three-stage inverter structure forms a ring oscillator structure to realize the control of the charge and discharge of the third capacitor C3. The output of a 2MHz clock signal is realized here.

[0045] like Figure 6 As shown, the protection module 1 includes a twelfth NPN tube Q12, a thirteenth NPN tube Q13, a fourteenth NPN tube Q14, a fifteenth NPN tube Q15, a sixteenth NPN tube Q16, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, and a second voltage regulator tube M2.

[0046] The emitter of the twelfth NPN tube Q12 of the protection module 1 is connected to the emitter of the thirteenth NPN tube Q13 and is externally grounded, the base of the twelfth NPN tube Q12 is connected to the base of the thirteenth NPN tube Q13, the collector of the twelfth NPN tube Q12 is connected to the drain of the fifteenth PMOS tube P15, the gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube P16, the source of the fifteenth PMOS tube P15 is connected to the source of the sixteenth PMOS tube P16 and is externally connected to VCC, the drain of the sixteenth PMOS tube is connected to the output end of the second voltage regulator tube M2, and the second The output end of the Zener tube M2 is connected to the collector of the sixteenth NPN tube Q16, the base of the sixteenth NPN tube Q16 is connected to the collector, the emitter of the sixteenth NPN tube Q16 is connected to the collector of the fifteenth NPN tube Q15, the base of the fifteenth NPN tube Q15 is connected to the collector, the emitter of the fifteenth NPN tube Q15 is connected to the collector of the fourteenth NPN tube Q14, the base of the fourteenth NPN tube Q14 is connected to the collector, the emitter of the fourteenth NPN tube Q14 is connected to the collector of the thirteenth NPN tube Q13, and the base of the thirteenth NPN tube Q13 is connected to the collector.

[0047] In this example, the gates of the fifteenth PMOS tube P15 and the sixteenth PMOS tube are connected to the voltage VBP to ensure the normal conduction of the fifteenth PMOS tube P15 and the sixteenth PMOS tube. The twelfth NPN tube Q12 and the thirteenth NPN tube Q13 form a current mirror structure. The fourteenth NPN tube Q14, the fifteenth NPN tube Q15, and the sixteenth NPN tube Q16 clamp the voltage of the circuit to about 2.1V through the connection between the base and the collector. The second voltage regulator tube M2 is a voltage regulator tube with a 6V to on-state voltage. When the input voltage exceeds 8.1V, the circuit will work to ensure the stability of the overall circuit.

[0048] like Figure 7 As shown, the protection module 2 includes a seventeenth NPN tube Q17, an eighteenth NPN tube Q18, a nineteenth NPN tube Q19, a twentieth NPN tube Q20, a third voltage regulator tube M3, a seventeenth PMOS tube P17, and an eighteenth PMOS tube P18.

[0049] The emitter of the seventeenth NPN tube Q17 of the protection module 2 is connected to the emitter of the eighteenth NPN tube Q18 and to the ground, the base of the seventeenth NPN tube Q17 is connected to the base of the eighteenth NPN tube Q18, the base of the seventeenth NPN tube Q17 is connected to the collector, the collector is connected to the emitter of the nineteenth NPN tube Q19, the base of the nineteenth NPN tube Q19 is connected to the collector, the collector of the nineteenth NPN tube Q19 is connected to the emitter of the twentieth NPN tube Q20, and the twentieth NPN The base of the tube Q20 is connected to the collector, the collector of the twentieth NPN tube Q20 is connected to the input electrode of the third voltage regulator tube M3, the output stage of the third voltage regulator tube M3 is connected to the drain of the seventeenth PMOS tube P17, the gate P17 of the seventeenth PMOS tube P17 is connected to the gate of the eighteenth PMOS tube P18, the bias voltage VBP is connected, the source is connected to the source of the eighteenth PMOS tube P18 and connected to VCC, and the drain of the eighteenth PMOS tube P18 is connected to the collector of the eighteenth NPN tube Q18.

[0050] In this example, the gate of the seventeenth PMOS tube P17 and the gate of the eighteenth PMOS tube P18 are connected to the voltage VBP to ensure the normal conduction of the two PMOS tubes and provide saturation current. The seventeenth NPN tube Q17 and the eighteenth NPN tube Q18 form a current mirror structure. The base and collector of the nineteenth NPN tube Q19 and the twentieth NPN tube Q20 are connected to achieve voltage bias. Together with the third voltage regulator tube M3, a voltage bias of 8.6V is achieved.

[0051] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection of the present invention.

Claims

1. A circuit of a PWM controller with wide input range and low power consumption, characterized in that: It includes a reference module, an error amplifier module, a current analog comparator module, a power supply module, a clock circuit module, a protection circuit, and a digital logic module.

2. The PWM controller circuit with wide input range and low power consumption as claimed in claim 1, characterized in that: The reference module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, and a first voltage regulator M1; The emitter of the first NPN tube Q1 of the reference module is grounded, and the base is connected to the collector. The emitter of the second NPN tube Q2 is connected to the collector of the first NPN tube Q1, and the base is connected to the collector. The emitter of the third NPN tube Q3 is connected to the collector of the second NPN tube Q2, and the base is connected to the collector. One end of the first resistor R1 is connected to the third NPN tube Q3. The second resistor R2 is connected to the first resistor R1. The third resistor R3 is connected to the second resistor R2. The fourth resistor R4 is connected to the third resistor R3. The fifth resistor R5 is connected to the sixth resistor R6, the seventh resistor R7 is connected to the sixth resistor R6, the eighth resistor R8 is connected to the seventh resistor R7, the emitter of the fourth NPN tube Q4 is connected to the first resistor R8, the collector of the fourth NPN tube Q4 is connected to the power supply VCC, the base is connected to the output end of the first voltage regulator tube M1 and the drain end of the first PMOS tube P1, the input end of the first voltage regulator tube M1 is connected to the ground line, the gate terminal of the first PMOS tube P1 is connected to the bias voltage BISE, and the source terminal of the first PMOS tube is connected to the power supply VCC.

3. The PWM controller circuit with wide input range and low power consumption as claimed in claim 1, characterized in that: The error amplifier module includes a fifth NPN tube Q5, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a ninth NPN tube Q9, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a ninth resistor R9, a tenth resistor R10, and a first capacitor C1; The emitter of the fifth NPN tube Q5 of the error amplifier module is grounded, connected to the emitter of the sixth NPN tube Q6, the emitter of the seventh NPN tube Q7, and the emitter of the ninth NPN tube Q9, the base of the fifth NPN tube Q5 is connected to the collector and the base of the sixth NPN tube, the drain of the second PMOS tube P2 is connected to the collector of the fifth NPN tube Q5, the gate of the second PMOS tube P2 is connected to the bias voltage VBF, the source of the second PMOS tube P2 is connected to the source P3 of the third PMOS tube and the drain of the fourth PMOS tube P4, the source of the fourth PMOS tube P4 is connected to the source of the fifth PMOS tube and the collector of the eighth NPN tube Q8, and connected to the power supply VCC, the The gate of the fourth PMOS tube P4 is connected to the gate of the fifth PMOS tube, the gate of the third PMOS tube is connected to the reference voltage VREF, the drain is connected to the collector of the sixth NPN tube Q6 and the base of the seventh NPN tube Q7, the collector of the seventh NPN tube is connected to the drain of the fifth PMOS tube P5 and the base of the eighth NPN tube Q8, the two ends of the first capacitor C1 are connected between the base and the collector of the seventh NPN tube Q7, the emitter of the eighth NPN tube Q8 is connected to the ninth resistor R9, the ninth resistor R9 is connected to the tenth resistor R10 and the collector of the ninth NPN tube Q9, the other end of the tenth resistor R10 is connected to the COMP output, and the base of the ninth NPN tube is connected to the bias voltage VBN.

4. A PWM controller circuit with wide input range and low power consumption as claimed in claim 1, characterized in that: The current mode comparator includes a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a tenth NPN tube Q10, an eleventh resistor R11, and a twelfth resistor R12; The source of the first NMOS tube N1 of the current mode comparator module is connected to the source of the second NMOS tube, and is externally connected to an external current source. The gate of the first NMOS tube N1 is connected to COMP, and the drain is connected to the drain of the sixth PMOS tube P6. The source of the sixth PMOS tube P6 is connected to the source of the seventh PMOS tube P7 and the source of the eighth PMOS tube, and is connected to the power supply VCC. The gate of the sixth PMOS tube P6 is connected to the gate of the seventh PMOS tube P7 and the gate of the eighth PMOS tube. The drain of the seventh PMOS tube P7 is connected to The drain of the second NMOS tube N2 is connected, the gate of the second NMOS tube N2 is connected to the gate of the third NMOS tube N3, the drain of the eighth PMOS tube P8 is connected to the drain of the third NMOS tube N3, the gate and the drain of the third NMOS tube N3 are connected, the source of the third NMOS tube N3 is connected to the collector of the tenth NPN tube Q10, the base and the collector are connected, the emitter of the tenth NPN tube Q10 is connected to the eleventh resistor R11, the eleventh resistor R11 is connected to the twelfth resistor R12, and the twelfth resistor R12 is grounded.

5. The PWM controller circuit with wide input range and low power consumption as claimed in claim 1, wherein the power module comprises a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, an eleventh NPN tube Q11, and a thirteenth resistor R13; One end of the thirteenth resistor R13 of the power module is connected to the bias voltage BIAS, and the other end is connected to the drain of the ninth PMOS tube P9. The source of the ninth PMOS tube P9 is connected to the source of the tenth PMOS tube P10 and the source of the eleventh PMOS tube P11, and is externally connected to VCC. The gate and drain of the ninth PMOS tube P9 are connected, and the gate is connected to the gate of the tenth PMOS tube P10, and the output voltage VBP is output. The gate of the tenth PMOS tube P10 is connected to the gate of the eleventh PMOS tube P11, the drain of the tenth PMOS tube is connected to the collector of the eleventh NPN tube Q11, the base of the eleventh NPN tube Q11 is connected to the collector, and the output voltage VBN is output. The emitter of the eleventh NPN tube Q11 is connected to the drain of the eleventh PMOS tube P11, and is externally grounded.

6. A PWM controller circuit with wide input range and low power consumption as claimed in claim 1, wherein the clock module comprises a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a second capacitor C2, a third capacitor C3, a fourteenth resistor R14, and a fifteenth resistor R15; One end of the second capacitor C2 of the clock module is connected to the fourteenth resistor R14, the third capacitor C3, the gate of the sixth NMOS tube N6, the gate of the twelfth PMOS tube, and the gate of the fifth NMOS tube N5, and the other end is connected to GND!, the fourteenth resistor R14 is connected to the drain of the fourth NMOS tube N4, the source of the fourth NMOS tube N4 is connected to the fifteenth resistor R15, the fifteenth resistor R15 is connected to the discharge port DISCHARGE, the gate of the fourth NMOS tube is connected to the third capacitor C3, the drain of the thirteenth PMOS tube P13, the drain of the seventh NMOS tube N7, the drain of the eighth NMOS tube N8, the gate of the fourteenth PMOS tube P14, the gate of the eighth NMOS tube N8, the source of the fifth NMOS tube N5 is connected to the source of the seventh NMOS tube N7, and the external GND! The drain of the fifth NMOS tube N5 is connected to the source of the sixth NMOS tube N6, the drain of the sixth NMOS tube N6 is connected to the drain of the twelfth PMOS tube P12, the gate of the seventh NMOS tube N7, and the gate of the thirteenth PMOS tube P13, the source of the twelfth PMOS tube P12 is connected to the source of the thirteenth PMOS tube P13, and is externally connected to the power supply VCC, the drain of the eighth NMOS tube N8 is connected to the drain of the fourteenth PMOS tube P14, and is connected to the output OSCOUT, the source of the eighth NMOS tube N8 is connected to GND!, and the source of the fourteenth PMOS tube P14 is connected to the power supply VCC.

7. A PWM controller circuit with wide input range and low power consumption as claimed in claim 1, wherein the protection module 1 comprises a twelfth NPN tube Q12, a thirteenth NPN tube Q13, a fourteenth NPN tube Q14, a fifteenth NPN tube Q15, a sixteenth NPN tube Q16, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, and a second voltage regulator tube M2; The emitter of the twelfth NPN tube Q12 of the protection module 1 is connected to the emitter of the thirteenth NPN tube Q13 and is externally grounded, the base of the twelfth NPN tube Q12 is connected to the base of the thirteenth NPN tube Q13, the collector of the twelfth NPN tube Q12 is connected to the drain of the fifteenth PMOS tube P15, the gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube P16, the source of the fifteenth PMOS tube P15 is connected to the source of the sixteenth PMOS tube P16 and is externally connected to VCC, the drain of the sixteenth PMOS tube is connected to the output end of the second voltage regulator tube M2, and the second The output end of the Zener tube M2 is connected to the collector of the sixteenth NPN tube Q16, the base of the sixteenth NPN tube Q16 is connected to the collector, the emitter of the sixteenth NPN tube Q16 is connected to the collector of the fifteenth NPN tube Q15, the base of the fifteenth NPN tube Q15 is connected to the collector, the emitter of the fifteenth NPN tube Q15 is connected to the collector of the fourteenth NPN tube Q14, the base of the fourteenth NPN tube Q14 is connected to the collector, the emitter of the fourteenth NPN tube Q14 is connected to the collector of the thirteenth NPN tube Q13, and the base of the thirteenth NPN tube Q13 is connected to the collector.

8. The PWM controller circuit with wide input range and low power consumption as claimed in claim 1, wherein the protection module 2 comprises a seventeenth NPN transistor Q17, an eighteenth NPN transistor Q18, a nineteenth NPN transistor Q19, a twentieth NPN transistor Q20, a third voltage regulator transistor M3, a seventeenth PMOS transistor P17, and an eighteenth PMOS transistor P18; The emitter of the seventeenth NPN tube Q17 of the protection module 2 is connected to the emitter of the eighteenth NPN tube Q18 and to the ground, the base of the seventeenth NPN tube Q17 is connected to the base of the eighteenth NPN tube Q18, the base of the seventeenth NPN tube Q17 is connected to the collector, the collector is connected to the emitter of the nineteenth NPN tube Q19, the base of the nineteenth NPN tube Q19 is connected to the collector, the collector of the nineteenth NPN tube Q19 is connected to the emitter of the twentieth NPN tube Q20, and the twentieth NPN The base of the tube Q20 is connected to the collector, the collector of the twentieth NPN tube Q20 is connected to the input electrode of the third voltage regulator tube M3, the output stage of the third voltage regulator tube M3 is connected to the drain of the seventeenth PMOS tube P17, the gate P17 of the seventeenth PMOS tube P17 is connected to the gate of the eighteenth PMOS tube P18, the bias voltage VBP is connected, the source is connected to the source of the eighteenth PMOS tube P18 and connected to VCC, and the drain of the eighteenth PMOS tube P18 is connected to the collector of the eighteenth NPN tube Q18.

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