Low-dropout linear voltage regulator, ferroelectric memory, and electronic device

Abstract

The application discloses a low-dropout linear voltage regulator, a ferroelectric memory and electronic equipment, which can be applied to the technical field of electronic circuits. The application sets the current boundary module, the first error amplifier module, the buffer module, the feedback module, the second error amplifier module and the discharge module in the low-dropout linear voltage regulator, so that after the bias voltage is provided through the current boundary module, the first error amplifier module performs error amplification processing according to the input reference voltage and the feedback voltage, the first amplified voltage is cached through the buffer module, the feedback module provides the working voltage for the ferroelectric chip according to the first amplified voltage and generates the feedback voltage at the same time, then the second error amplifier module performs voltage amplification processing according to the input reference voltage and the feedback voltage to obtain the second amplified voltage, and finally the discharge module adjusts the output voltage of the feedback module according to the second amplified voltage, so that the working frequency of the ferroelectric memory chip is improved, and the size of the overall circuit is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a low voltage difference linear regulator, a ferroelectric memory and an electronic device. Background Art

[0002] In related technologies, a low-dropout regulator (LDO) is a common basic circuit module in analog circuits, used to achieve level conversion and provide a stable, low-interference power supply for other circuits. Due to the particularity of large-capacity ferroelectric memory chip storage arrays, the output load requirement of the LDO is above 100mA. However, current ferroelectric chips typically use two LDOs to handle high and low load conditions respectively. This approach often causes severe voltage fluctuations and slow recovery time when switching between high and low loads, thereby limiting the operating frequency of the ferroelectric chip. At the same time, the use of two LDOs also increases the size of the overall circuit.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a low voltage difference linear regulator, a ferroelectric memory and an electronic device, which can increase the operating frequency of the ferroelectric memory chip and reduce the size of the overall circuit.

[0005] To achieve the above objectives, an embodiment of the present application provides a low voltage dropout linear regulator, comprising:

[0006] A current environment module, wherein the current environment module is used to provide a bias voltage;

[0007] a first error amplifier module, the first error amplifier module being connected to the current control module and performing error amplification processing according to an input reference voltage and a feedback voltage to obtain a first amplified voltage;

[0008] a buffer module, the buffer module being connected to the current control module and the first error amplifier module respectively, and being used to buffer the first amplified voltage;

[0009] a feedback module, the feedback module being connected to the current controller and the buffer module respectively, and being configured to provide an operating voltage to the ferroelectric chip according to the first amplified voltage, and to generate the feedback voltage;

[0010] a second error amplifier module, connected to the feedback module, configured to obtain a second amplified voltage after performing voltage amplification processing based on an input reference voltage and the feedback voltage;

[0011] A power leakage module is respectively connected to the feedback module and the second error amplifier module, and is used to adjust the output voltage of the feedback module according to the second amplified voltage.

[0012] In some embodiments, the current control module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a first resistor;

[0013] The source stage of the first MOS transistor, the source stage of the second MOS transistor, and the source stage of the fifth MOS transistor are all connected to an input power supply;

[0014] The drain of the first MOS transistor, the gate of the first MOS transistor, and the drain of the third MOS transistor are all connected to the gate of the second MOS transistor;

[0015] The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor;

[0016] The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor;

[0017] The source of the fourth MOS transistor is connected to the first end of the first resistor;

[0018] The drain of the sixth MOS transistor and the gate of the sixth MOS transistor are both connected to the drain of the fifth MOS transistor;

[0019] The drain of the seventh MOS tube and the gate of the seventh MOS tube are both connected to the source of the sixth MOS tube;

[0020] The gate of the sixth MOS tube is externally connected to an input bias current;

[0021] The source of the third MOS transistor, the second end of the first resistor, and the source of the seventh MOS transistor are all grounded.

[0022] In some embodiments, the first error amplifier module includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor;

[0023] The gate of the eighth MOS transistor is connected to the feedback module;

[0024] The source stage of the eighth MOS transistor, the source stage of the fifteenth MOS transistor, and the source stage of the sixteenth MOS transistor are all connected to an input power supply;

[0025] The drain of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the source of the tenth MOS transistor respectively;

[0026] The drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the source of the thirteenth MOS transistor respectively;

[0027] The drain of the tenth MOS transistor is connected to the drain of the twelfth MOS transistor and the source of the fourteenth MOS transistor respectively;

[0028] The gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor;

[0029] The drain of the thirteenth MOS transistor is respectively connected to the drain of the fifteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor;

[0030] The drain of the sixteenth MOS transistor and the drain of the fourteenth MOS transistor are both connected to the buffer module;

[0031] The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor;

[0032] The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are both grounded.

[0033] In some embodiments, the buffer module includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0034] The first end of the second resistor, the source of the eighteenth MOS transistor and the source of the nineteenth MOS transistor are all connected to an input power supply;

[0035] The second end of the second resistor is connected to the first end of the first capacitor;

[0036] The second end of the first capacitor, the gate of the seventeenth MOS transistor and the drain of the sixteenth MOS transistor are connected;

[0037] The drain of the eighteenth MOS tube, the drain of the nineteenth MOS tube, and the gate of the nineteenth MOS tube are all connected to the source of the seventeenth MOS tube;

[0038] The drain of the seventeenth MOS tube is grounded;

[0039] The first end of the second capacitor is connected to the source of the fourteenth MOS transistor;

[0040] The second end of the second capacitor is connected to the first end of the second resistor;

[0041] The second end of the second resistor is connected to the feedback module.

[0042] In some embodiments, the feedback module includes a twentieth MOS transistor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0043] The source of the 20th MOS tube is connected to the input power supply;

[0044] The gate of the 20th MOS transistor is connected to the gate of the 19th MOS transistor;

[0045] The drain of the 20th MOS transistor is connected to the second end of the third resistor and the first end of the fourth resistor respectively;

[0046] The second end of the fourth resistor and the first end of the fifth resistor are both connected to the gate of the ninth MOS transistor;

[0047] The second end of the fifth resistor and the first end of the sixth resistor are both connected to the second error amplifier module;

[0048] A second end of the sixth resistor is grounded.

[0049] In some embodiments, the second error amplifier module includes a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, and a twenty-fifth MOS transistor;

[0050] The source stage of the twenty-first MOS transistor and the source stage of the twenty-second MOS transistor are both connected to an input power supply;

[0051] The gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor;

[0052] The drain of the twenty-first MOS transistor is connected to the drain of the twenty-third MOS transistor;

[0053] The gate of the twenty-third MOS transistor is connected to the first end of the sixth resistor;

[0054] The source of the twenty-third MOS transistor is connected to the source of the twenty-fourth MOS transistor and the drain of the twenty-fifth MOS transistor respectively;

[0055] The source of the twenty-fifth MOS transistor is grounded;

[0056] The drain of the twenty-second MOS transistor and the drain of the twenty-fourth MOS transistor are both connected to the power discharge module;

[0057] The gate of the twenty-fourth MOS transistor is connected to a bias current.

[0058] In some embodiments, the power dissipation module includes a twenty-sixth MOS transistor and a twenty-seventh MOS transistor;

[0059] The drain of the twenty-sixth MOS transistor is connected to the output end of the feedback module;

[0060] The gate of the twenty-sixth MOS transistor is connected to the drain of the twenty-fourth MOS transistor;

[0061] The gate electrode and the drain electrode of the twenty-seventh MOS transistor are both connected to the source electrode of the twenty-sixth MOS transistor;

[0062] The source of the twenty-seventh MOS transistor is grounded.

[0063] In some embodiments, the voltage regulator further includes a third capacitor;

[0064] The first end of the third capacitor is connected to the input power supply;

[0065] The second end of the third capacitor is connected to the gate of the fifteenth MOS transistor.

[0066] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides a ferroelectric memory, comprising the above-mentioned low voltage dropout linear regulator.

[0067] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides an electronic device, comprising the above-mentioned ferroelectric memory.

[0068] The embodiments of the present application include at least the following beneficial effects: The present application provides a low-voltage difference linear regulator, a ferroelectric memory and an electronic device. The solution is achieved by setting a current amplifier module, a first error amplifier module, a buffer module, a feedback module, a second error amplifier module and a discharge module in the low-voltage difference linear regulator, so that after the current amplifier module provides a bias voltage, the first error amplifier module performs error amplification processing according to the input reference voltage and feedback voltage, and then caches the first amplified voltage through the cache module, and provides the ferroelectric chip with an operating voltage and generates a feedback voltage through the feedback module according to the first amplified voltage, and then the second error amplifier module performs voltage amplification processing according to the input reference voltage and feedback voltage to obtain a second amplified voltage, and then the discharge module adjusts the output voltage of the feedback module according to the second amplified voltage, so that the ferroelectric memory chip can maintain stability even when the output load of the regulator fluctuates rapidly under high-frequency working conditions, thereby improving the operating frequency of the ferroelectric memory chip and reducing the size of the overall circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 This is a module block diagram of a low-dropout linear regulator provided in an embodiment of the present application;

[0070] Figure 2 1 is a circuit diagram of a low voltage dropout linear regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application.

[0072] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0073] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" in the context of the present invention, and "at least one" or "at least one" includes one, two or more, "plurality" or "any one" includes two or more, "each" or "each one" in the context of the present invention, and "any" or "any one

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0075] Reference Figure 1The present application provides a low voltage difference linear regulator, which includes a current environment module, a first error amplifier module, a buffer module, a feedback module, a second error amplifier module and a discharge module. The current environment module is used to provide a bias voltage; the first error amplifier module is connected to the current environment module, and obtains a first amplified voltage after error amplification according to the input reference voltage and feedback voltage; the buffer module is respectively connected to the current environment module and the first error amplifier module, and is used to cache the first amplified voltage; the feedback module is respectively connected to the current environment and the buffer module, and is used to provide an operating voltage to the ferroelectric chip and generate a feedback voltage according to the first amplified voltage; the second error amplifier module is connected to the feedback module, and is used to obtain a second amplified voltage after voltage amplification according to the input reference voltage and feedback voltage; the discharge module is respectively connected to the feedback module and the second error amplifier module, and is used to adjust the output voltage of the feedback module according to the second amplified voltage. Specifically, the regulator provided by this embodiment can effectively increase the operating frequency of the ferroelectric memory chip and reduce the size of the overall circuit.

[0076] In the embodiments of this application, Figure 2 As shown, the current environment module includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and a first resistor R1; the source of the first MOS transistor M1, the source of the second MOS transistor M2 and the source of the fifth MOS transistor M5 are all connected to the input power supply; the drain of the first MOS transistor M1, the gate of the first MOS transistor M1 and the drain of the third MOS transistor M3 are all connected to the gate of the second MOS transistor M2; the drain of the second MOS transistor M2 is connected to the gate of the fourth MOS transistor M5. The drain of the third MOS transistor M4 is connected; the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4; the source of the fourth MOS transistor M4 is connected to the first end of the first resistor; the drain and gate of the sixth MOS transistor M6 are both connected to the drain of the fifth MOS transistor M5; the drain and gate of the seventh MOS transistor M7 are both connected to the source of the sixth MOS transistor M6; the gate of the sixth MOS transistor M6 is externally connected to the input bias current; the source of the third MOS transistor M3, the second end of the first resistor R1, and the source of the seventh MOS transistor M7 are all grounded. Specifically, in this embodiment, the first, second, and fifth MOS transistors can be PMOS transistors, and the third, fourth, sixth, and seventh MOS transistors can be NMOS transistors. In this embodiment, a stable mirrored current is obtained by mirroring the input current to provide a tail current to the first error amplifier module and the cache module, and a bias current to the first error amplifier, the cache module, and the feedback module.

[0077] In the embodiments of this application, Figure 2As shown, the first error amplifier module includes an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16; the gate of the eighth MOS transistor M8 is connected to the feedback module; the source of the eighth MOS transistor M8, the source of the fifteenth MOS transistor M15, and the source of the sixteenth MOS transistor M16 are all connected to the input power supply; the drain of the eighth MOS transistor M8 is respectively connected to the source of the ninth MOS transistor M9 and the source of the tenth MOS transistor M10; the drain of the ninth MOS transistor M9 is respectively connected to the drain of the eleventh MOS transistor M11 and the drain of the thirteenth MOS transistor M16. The source of the MOS transistor M13 is connected; the drain of the tenth MOS transistor M10 is respectively connected to the drain of the twelfth MOS transistor M12 and the source of the fourteenth MOS transistor M14; the gate of the thirteenth MOS transistor M13 is respectively connected to the gate of the fourteenth MOS transistor M14; the drain of the thirteenth MOS transistor M13 is respectively connected to the drain of the fifteenth MOS transistor M15, the gate of the fifteenth MOS transistor M15, and the gate of the sixteenth MOS transistor M16; the drain of the sixteenth MOS transistor M16 and the drain of the fourteenth MOS transistor M14 are both connected to the buffer module; the gate of the eleventh MOS transistor M11 is connected to the gate of the twelfth MOS transistor M12; the source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12 are both grounded. Specifically, the eighth MOS transistor is a tail current transistor, the ninth and tenth MOS transistors are input pair transistors, and the fourteenth and sixteenth MOS transistors form the output end. This embodiment performs error amplification processing based on the feedback module return voltage FB_U and the input reference voltage VREF, thereby achieving a voltage regulation process.

[0078] In the embodiments of this application, Figure 2As shown, the buffer module includes a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a second resistor R2, a third resistor R2, a first capacitor C1, and a second capacitor C2; a first end of the second resistor R2, a source of the eighteenth MOS transistor M18, and a source of the nineteenth MOS transistor M19 are all connected to the input power supply; a second end of the second resistor R2 is connected to the first end of the first capacitor; a second end of the first capacitor and the gate of the seventeenth MOS transistor M17 are connected to the drain of the sixteenth MOS transistor M16; the drain of the eighteenth MOS transistor M18, the drain of the nineteenth MOS transistor M19, and the gate of the nineteenth MOS transistor M19 are all connected to the source of the seventeenth MOS transistor M17; the drain of the seventeenth MOS transistor M17 is grounded; a first end of the second capacitor C2 is connected to the source of the fourteenth MOS transistor M14; a second end of the second capacitor C2 is connected to the first end of the second resistor R2; and a second end of the second resistor R2 is connected to the feedback module. In this embodiment, a buffer module is provided between the first error amplifier module and the feedback module, so that the output voltage of the first error amplifier module can be buffered, thereby improving circuit stability.

[0079] In this embodiment of the present application, the feedback module includes a 20th MOS transistor M20, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The source of the 20th MOS transistor M20 is connected to the input power supply; the gate of the 20th MOS transistor M20 is connected to the gate of the 19th MOS transistor M19; the drain of the 20th MOS transistor M20 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4, respectively; the second end of the fourth resistor R4 and the first end of the fifth resistor R5 are both connected to the gate of the ninth MOS transistor M9; the second end of the fifth resistor R5 and the first end of the sixth resistor R6 are both connected to the second error amplifier module; and the second end of the sixth resistor R6 is grounded. Specifically, the 20th MOS transistor in this embodiment can be a PMOS transistor. This embodiment effectively adjusts the stability of the output voltage by providing feedback on the output voltage.

[0080] In the embodiment of the present application, the second error amplifier module includes a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24, and a twenty-fifth MOS transistor M25; the source of the twenty-first MOS transistor M21 and the source of the twenty-second MOS transistor M22 are both connected to the input power supply; the gate of the twenty-first MOS transistor M21 is connected to the gate of the twenty-second MOS transistor M22; the drain of the twenty-first MOS transistor M21 is connected to the drain of the twenty-third MOS transistor M23; the gate of the twenty-third MOS transistor M23 is connected to the first end of the sixth resistor; the source of the twenty-third MOS transistor M23 is respectively connected to the source of the twenty-fourth MOS transistor M24 and the drain of the twenty-fifth MOS transistor M25; the source of the twenty-fifth MOS transistor M25 is grounded; the drain of the twenty-second MOS transistor M22 and the drain of the twenty-fourth MOS transistor M24 are both connected to the power dissipation module; and the gate of the twenty-fourth MOS transistor M24 is connected to the bias current. Specifically, in this embodiment, the twenty-fifth MOS transistor is a tail current transistor, and the twenty-third and twenty-fourth MOS transistors are input pair transistors. In this embodiment, the output voltage error can be amplified so that the power dissipation module can adjust the output voltage of the voltage regulator.

[0081] In the embodiments of this application, Figure 2 As shown, the power leakage module includes a twenty-sixth MOS transistor 26 and a twenty-seventh MOS transistor M27; the drain of the twenty-sixth MOS transistor M26 is connected to the output terminal of the feedback module; the gate of the twenty-sixth MOS transistor M26 is connected to the drain of the twenty-fourth MOS transistor M24; the gate and drain of the twenty-seventh MOS transistor M27 are both connected to the source of the twenty-sixth MOS transistor M26; and the source of the twenty-seventh MOS transistor M27 is grounded. In this embodiment, power is discharged to ground through the power leakage module, thereby adjusting the output voltage of the voltage regulator.

[0082] In the embodiments of this application, Figure 2 As shown, the voltage regulator further includes a third capacitor C3; a first end of the third capacitor C3 is connected to the input power supply; and a second end of the third capacitor C3 is connected to the gate of the fifteenth MOS transistor M25. This embodiment uses the third capacitor for isolation, thereby improving circuit operating stability.

[0083] It is understood that this embodiment utilizes the principle of a virtual short circuit in the first error amplifier module to force the resistor string feedback point FB_U to equal the reference voltage, and then generates the output voltage VOUT through the resistor string voltage divider. The seventeenth MOS transistor in the buffer module is a source-follower structure, and the output of the first error amplifier module controls the conduction level of the seventeenth MOS transistor. The nineteenth MOS transistor in the buffer module and the twentieth MOS transistor in the feedback module form a current mirror. The load current can be tolerated within the current mirror ratio range, and the feedback resistor string voltage divider point FB_L is always lower than FB_. When the output jitters upward, FB_L exceeds the reference voltage, the leakage path opens, and VOUT discharges directly to ground through the twenty-sixth and twenty-seventh MOS transistors.

[0084] Comparing this application with the existing voltage regulator tube, the results shown in Table 1 are obtained:

[0085] Table 1

[0086] Existing ferroelectric internal LDO This application Load capacity 20mA 100mA Setup time >10us <5us

[0087] It can be seen from this that the voltage regulator tube provided by this application has the following effects:

[0088] First, it can adapt to load current variations over a span of 100mA or more, to accommodate the specific layout and current requirements of ferroelectric memory chip arrays.

[0089] Second, when the chip state changes and the load switches, the LDO output can quickly follow the load and adjust the output, solving the problem of slow switching of existing ferroelectric chips.

[0090] Third, the output establishment problem when the existing ferroelectric memory chip uses two LDOs with large and small loads to switch can be solved, and it can adapt to the faster operating frequency of the chip.

[0091] In addition, an embodiment of the present application further provides a ferroelectric memory and an electronic device, wherein the ferroelectric memory includes the above-mentioned low voltage difference linear regulator, and the electronic device includes the ferroelectric memory.

[0092] It can be understood that the contents of the above-mentioned low-voltage difference linear regulator embodiment are applicable to the present ferroelectric memory and electronic device embodiment, and the beneficial effects achieved by the present ferroelectric memory and electronic device embodiment are the same as the beneficial effects achieved by the above-mentioned bandgap reference circuit embodiment.

[0093] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0094] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0096] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0097] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0098] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0100] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0103] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A low voltage dropout linear regulator, characterized in that: The voltage regulator comprises: A current environment module, wherein the current environment module is used to provide a bias voltage; a first error amplifier module, the first error amplifier module being connected to the current control module and performing error amplification processing according to an input reference voltage and a feedback voltage to obtain a first amplified voltage; a buffer module, the buffer module being connected to the current control module and the first error amplifier module respectively, and being used to buffer the first amplified voltage; a feedback module, the feedback module being connected to the current controller and the buffer module respectively, and being configured to provide an operating voltage to the ferroelectric chip according to the first amplified voltage, and to generate the feedback voltage; a second error amplifier module, connected to the feedback module, configured to obtain a second amplified voltage after performing voltage amplification processing based on an input reference voltage and the feedback voltage; a power leakage module, the power leakage module being respectively connected to the feedback module and the second error amplifier module, and being configured to adjust the output voltage of the feedback module according to the second amplified voltage; Wherein, the feedback module includes a twentieth MOS transistor, a fourth resistor, a fifth resistor and a sixth resistor; The source of the 20th MOS tube is connected to the input power supply; The gate of the 20th MOS tube is connected to the buffer module; The drain of the 20th MOS transistor is connected to the buffer module and the first end of the fourth resistor respectively; The second end of the fourth resistor and the first end of the fifth resistor are both connected to the first error amplifier; The second end of the fifth resistor and the first end of the sixth resistor are both connected to the second error amplifier module; The second end of the sixth resistor is grounded; The second error amplifier module includes a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor and a twenty-fifth MOS transistor; The source stage of the twenty-first MOS transistor and the source stage of the twenty-second MOS transistor are both connected to an input power supply; The gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor; The drain of the twenty-first MOS transistor is connected to the drain of the twenty-third MOS transistor; The gate of the twenty-third MOS transistor is connected to the first end of the sixth resistor; The source of the twenty-third MOS transistor is connected to the source of the twenty-fourth MOS transistor and the drain of the twenty-fifth MOS transistor respectively; The source of the twenty-fifth MOS transistor is grounded; The drain of the twenty-second MOS transistor and the drain of the twenty-fourth MOS transistor are both connected to the power discharge module; The gate of the twenty-fourth MOS transistor is connected to a bias current; The power discharge module includes a twenty-sixth MOS tube and a twenty-seventh MOS tube; The drain of the twenty-sixth MOS transistor is connected to the output end of the feedback module; The gate of the twenty-sixth MOS transistor is connected to the drain of the twenty-fourth MOS transistor; The gate electrode and the drain electrode of the twenty-seventh MOS transistor are both connected to the source electrode of the twenty-sixth MOS transistor; The source of the twenty-seventh MOS transistor is grounded.

2. The voltage stabilizer according to claim 1, wherein: The current environment module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a first resistor; The source stage of the first MOS transistor, the source stage of the second MOS transistor, and the source stage of the fifth MOS transistor are all connected to an input power supply; The drain of the first MOS transistor, the gate of the first MOS transistor, and the drain of the third MOS transistor are all connected to the gate of the second MOS transistor; The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor; The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor; The source of the fourth MOS transistor is connected to the first end of the first resistor; The drain of the sixth MOS transistor and the gate of the sixth MOS transistor are both connected to the drain of the fifth MOS transistor; The drain of the seventh MOS tube and the gate of the seventh MOS tube are both connected to the source of the sixth MOS tube; The gate of the fifth MOS tube is externally connected to an input bias current; The source of the third MOS transistor, the second end of the first resistor, and the source of the seventh MOS transistor are all grounded.

3. The voltage stabilizer according to claim 2, wherein: The first error amplifier module includes an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor; The gate of the eighth MOS transistor is connected to the feedback module; The source stage of the eighth MOS transistor, the source stage of the fifteenth MOS transistor, and the source stage of the sixteenth MOS transistor are all connected to an input power supply; The drain of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the source of the tenth MOS transistor respectively; The drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the source of the thirteenth MOS transistor respectively; the gate of the ninth MOS transistor is connected to the second end of the fourth resistor and the first end of the fifth resistor respectively; The drain of the tenth MOS transistor is connected to the drain of the twelfth MOS transistor and the source of the fourteenth MOS transistor respectively; The gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor; The drain of the thirteenth MOS transistor is respectively connected to the drain of the fifteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor; The drain of the sixteenth MOS transistor is connected to the drain of the fourteenth MOS transistor and is connected to the buffer module; The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor; The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are both grounded.

4. The voltage stabilizer according to claim 3, wherein: The buffer module includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a second resistor, a third resistor, a first capacitor and a second capacitor; The first end of the second resistor, the source of the eighteenth MOS transistor and the source of the nineteenth MOS transistor are all connected to an input power supply; The second end of the second resistor is connected to the first end of the first capacitor; The second end of the first capacitor, the gate of the seventeenth MOS transistor and the drain of the sixteenth MOS transistor are connected; The drain of the eighteenth MOS tube, the drain of the nineteenth MOS tube, and the gate of the nineteenth MOS tube are all connected to the source of the seventeenth MOS tube; the gate of the nineteenth MOS tube is connected to the gate of the twentieth MOS tube; The drain of the seventeenth MOS tube is grounded; The first end of the second capacitor is connected to the source of the fourteenth MOS transistor; The second end of the second capacitor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the drain of the twentieth MOS transistor.

5. The voltage stabilizer according to any one of claims 3 to 4, characterized in that: The voltage stabilizer further includes a third capacitor; The first end of the third capacitor is connected to the input power supply; The second end of the third capacitor is connected to the gate of the fifteenth MOS transistor.

6. A ferroelectric memory, characterized in that: The invention comprises the low voltage drop linear regulator according to any one of claims 1 to 5.

7. An electronic device, characterized in that: The ferroelectric memory device according to claim 6 is included.

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