System and method for checking asynchronous first-in first-out equipment

Abstract

The invention discloses a system and method for checking asynchronous first-in first-out equipment, and belongs to the technical field of communication. The system for checking the asynchronous first-in first-out equipment comprises a clock generation device, a first detection device and a second detection device, wherein the clock generation device is used for generating a first clock signal and a second clock signal of each asynchronous first-in first-out equipment; the first clock signal is a clock signal used by asynchronous first-in first-out equipment for receiving data; the second clock signal is a clock signal used by the asynchronous first-in first-out device to send data; the monitor is used for acquiring output data of the asynchronous first-in first-out equipment connected with the monitor; the detector is used for checking whether the time interval between two adjacent output data of the asynchronous first-in first-out equipment connected with the detector is correct or not; and the comparator is used for checking whether the data acquired by the monitor connected with the comparator is correct or not. According to the system and the method for checking the asynchronous first-in first-out equipment provided by the invention, each cascaded asynchronous first-in first-out equipment can be checked.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and in particular, relates to a system and method for checking an asynchronous first-in-first-out device. Background Art

[0002] At present, when checking the output of a single asynchronous First Input First Output (FIFO) device, a limited clock frequency deviation or a limit frequency deviation can be provided. However, for multiple cascaded asynchronous FIFO devices, currently only a clock signal with a frequency deviation can be applied to both sides of the multiple cascaded asynchronous FIFO devices to detect whether the overall output of the multiple cascaded asynchronous FIFO devices is correct, but it is impossible to detect whether the output of each asynchronous FIFO device in the multiple cascaded asynchronous FIFO devices is correct. Therefore, how to check each asynchronous FIFO device in the multiple cascaded asynchronous FIFO devices has become a technical issue that needs to be solved urgently in this field. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a system and method for checking an asynchronous first-in-first-out device, which can realize the checking of each asynchronous first-in-first-out device in a plurality of cascaded asynchronous first-in-first-out devices.

[0004] In a first aspect, the present application provides a system for checking an asynchronous first-in-first-out device, the system comprising: a clock generating device, m monitors, m detectors and m comparators; m is the number of asynchronous first-in-first-out devices to be checked; m of the asynchronous first-in-first-out devices are cascaded; m is a positive integer;

[0005] The clock generating device is used to generate a first clock signal and a second clock signal for each of the asynchronous first-in-first-out devices; the first clock signal is a clock signal used by the asynchronous first-in-first-out device to receive data; the second clock signal is a clock signal used by the asynchronous first-in-first-out device to send data;

[0006] The monitor is used to obtain output data of the asynchronous first-in-first-out device connected to the monitor;

[0007] The detector is used to check whether the time interval between two adjacent output data of the asynchronous first-in-first-out device connected to the detector is correct;

[0008] The comparator is used to check whether the data acquired by the monitor connected to the comparator is correct.

[0009] According to the system for checking asynchronous FIFO devices of the present application, it is possible to provide frequency deviations of various frequencies within a critical range for the asynchronous clocks on both sides of the asynchronous FIFO devices, and to check the outputs of the asynchronous FIFO devices in real time. Moreover, in the case of cascading multiple stages of asynchronous FIFO devices, it is still possible to provide frequency deviations of various frequencies within a critical range for each stage of asynchronous FIFO devices, and to check the outputs of each stage of asynchronous FIFO devices in real time. By giving a reference frequency, multiple target frequency deviations, a target offset direction, and the number of target clock signals, a frequency deviation of any frequency and any degree can be applied to a single asynchronous FIFO device and multiple cascaded asynchronous FIFO devices, and the output effect of each asynchronous FIFO device under different frequency deviations can be checked in real time.

[0010] According to one embodiment of the present application, the clock generating device includes:

[0011] An acquisition module, used for acquiring a reference frequency, m target frequency deviations, target offset directions, and a number m of target clock signal groups; each group of the target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each group of the target clock signals is the target frequency deviation; the m groups of the target clock signals correspond one to one with the m asynchronous first-in-first-out devices;

[0012] A signal generating module is used to generate an initial signal for each target frequency deviation based on the reference frequency and the target frequency deviation, and to invert the initial signal based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals.

[0013] In a second aspect, the present application provides a method for checking an asynchronous first-in-first-out device, which is used to detect m cascaded asynchronous first-in-first-out devices; m is a positive integer; the method comprises:

[0014] Generate a first clock signal and a second clock signal for each of the asynchronous FIFO devices; the first clock signal is a clock signal used by the asynchronous FIFO device to receive data; the second clock signal is a clock signal used by the asynchronous FIFO device to send data;

[0015] Obtaining output data of each of the asynchronous first-in-first-out devices;

[0016] Check respectively whether the time interval between two adjacent output data of each asynchronous first-in-first-out device is correct, and check respectively whether the output data of each asynchronous first-in-first-out device is correct.

[0017] According to the method for checking asynchronous FIFO devices of the present application, various frequency deviations within a critical range can be provided for asynchronous clocks on both sides of the asynchronous FIFO devices, and the output of the asynchronous FIFO devices can be checked in real time. Moreover, in the case of cascading multiple stages of asynchronous FIFO devices, various frequency deviations within a critical range can still be provided for each stage of asynchronous FIFO devices, and the output of each stage of asynchronous FIFO devices can be checked in real time. By giving a reference frequency, multiple target frequency deviations, target offset directions, and the number of target clock signals, a frequency deviation of any frequency and any degree can be applied to a single asynchronous FIFO device and multiple cascaded asynchronous FIFO devices, and the output effect of each asynchronous FIFO device under different frequency deviations can be checked in real time.

[0018] According to one embodiment of the present application, generating the first clock signal and the second clock signal of each of the asynchronous first-in-first-out devices includes:

[0019] Obtain a reference frequency, m target frequency deviations, target offset directions, and a number m of target clock signal groups; each group of the target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each of the target clock signals is the target frequency deviation; the m groups of the target clock signals correspond one-to-one to the m asynchronous first-in-first-out devices;

[0020] For each target frequency deviation, an initial signal is generated based on the reference frequency and the target frequency deviation, and the initial signal is inverted based on its polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals.

[0021] According to an embodiment of the present application, for each of the target frequency deviations, an initial signal is generated based on the reference frequency and the target frequency deviation, and the initial signal is inverted based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals, including:

[0022] For the x-th target frequency deviation, an initial signal is generated based on the reference frequency and the x-th target frequency deviation, and is reversed based on the polarity of the initial signal to obtain the first sub-signal and the second sub-signal corresponding to the x-th target frequency deviation, thereby obtaining the m-th group of target clock signals; wherein, 1≤x≤m.

[0023] According to an embodiment of the present application, for the x-th target frequency deviation, based on the reference frequency and the x-th target frequency deviation, an initial signal is generated, and the initial signal is inverted based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the x-th target frequency deviation, thereby obtaining the x-th target clock signal, including:

[0024] Generate the initial signal with random polarity and lasting for a target duration, and randomly generate a first offset and a second offset; the target duration is half of the period corresponding to the reference frequency plus the unit time of the initial offset; the initial offset is a random value between 0 and one-quarter of the x-th target frequency deviation; the sum of the first offset and the second offset is equal to half of the x-th target frequency deviation;

[0025] The initial signal is used as the first sub-signal corresponding to the xth target frequency deviation of the first upper half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first upper half cycle, and the polarity of the initial signal is reversed to generate the first sub-signal corresponding to the xth target frequency deviation of the first lower half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first lower half cycle; the duration of the first lower half cycle of the first sub-signal and the second sub-signal corresponding to the xth target frequency deviation are both the target duration;

[0026] Based on the target offset direction, determine the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle;

[0027] The polarity of the first sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the first sub-signal corresponding to the x-th target frequency deviation; and the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the second sub-signal corresponding to the x-th target frequency deviation.

[0028] According to an embodiment of the present application, based on the target offset direction, determining the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and the duration of the second half cycle, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, includes:

[0029] When the target offset direction is the first direction, the target parameter is determined as the first value; when the target offset direction is the second direction, the target parameter is determined as the second value; when the target offset direction is the third direction, the target parameter is determined as the first value or the second value;

[0030] Based on the target parameters, the period corresponding to the reference frequency, the first offset and the second offset, determine the duration of the first half period and the duration of the second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, as well as the duration of the first half period and the duration of the second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period.

[0031] According to an embodiment of the present application, the determining, based on the target parameter, the period corresponding to the reference frequency, the first offset, and the second offset, of the first half-period duration and the second half-period duration of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, and the first half-period duration and the second half-period duration of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period, includes:

[0032] When the target parameter is the first value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset quantity; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset quantity; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset quantity;

[0033] When the target parameter is the second numerical value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset number; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset number; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset number; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset number.

[0034] According to an embodiment of the present application, the polarity of the first sub-signal corresponding to the x-th target frequency deviation is reversed in units of half a cycle, and the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle are respectively continued to generate the first sub-signal corresponding to the x-th target frequency deviation, including:

[0035] In the case where the polarity of the first sub-signal is reversed to the first polarity, the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation is continued except the first cycle, and the y-th upper half cycle of the first sub-signal corresponding to the x-th target frequency deviation is obtained. In the case where the polarity of the first sub-signal is reversed to the second polarity, the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation is continued except the first cycle, and the y-th lower half cycle of the first sub-signal corresponding to the x-th target frequency deviation is obtained, thereby generating the first sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0036] According to an embodiment of the present application, the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle are respectively continued to generate the second sub-signal corresponding to the x-th target frequency deviation, including:

[0037] When the polarity of the second sub-signal is reversed to the first polarity, the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th upper half cycle of the second sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the second sub-signal is reversed to the second polarity, the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th lower half cycle of the second sub-signal corresponding to the x-th target frequency deviation, thereby generating the second sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0038] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0040] Figure 1 is a structural diagram of a system for checking an asynchronous first-in-first-out device provided in an embodiment of the present application;

[0041] Figure 2 is a schematic diagram of the structure of a clock generating device provided in an embodiment of the present application;

[0042] Figure 3 It is a flowchart of a method for checking an asynchronous first-in-first-out device provided in an embodiment of the present application;

[0043] Figure 4 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0045] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0046] In conjunction with the accompanying drawings, the system for checking asynchronous first-in-first-out devices, the system method for checking asynchronous first-in-first-out devices, the electronic device and the readable storage medium provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0047] like Figure 1 As shown, the system for checking asynchronous FIFO devices may include: a clock generating device 300, m monitors, m detectors and m comparators; m is the number of asynchronous FIFO devices to be checked; m asynchronous FIFO devices are cascaded; and m is a positive integer.

[0048] In actual implementation, a system for checking asynchronous FIFO devices may include a clock generating device 300, m monitors, m detectors and m comparators. The m asynchronous FIFO devices are cascaded, that is, in two adjacent levels of asynchronous FIFO devices, the output of the previous level of asynchronous FIFO devices is the input of the next level of asynchronous FIFO devices, and the clock signal used by the previous level of asynchronous FIFO devices to send data is the same as the clock signal used by the next level of asynchronous FIFO devices to receive data, thereby ensuring the transmission of data between asynchronous FIFO devices. It can be understood that the clock signal used by the asynchronous FIFO devices to receive data is different from the clock signal used to send data (specifically, the period may be different), thereby forming an asynchronous mode.

[0049] The clock generating device 300 is used to generate a first clock signal and a second clock signal for each asynchronous FIFO device; the first clock signal is the clock signal used by the asynchronous FIFO device to receive data; the second clock signal is the clock signal used by the asynchronous FIFO device to send data.

[0050] In actual implementation, the clock generating device 300 may provide each asynchronous FIFO device with a clock signal used by the asynchronous FIFO device to send data and a clock signal used by the asynchronous FIFO device to receive data.

[0051] The clock generating device 300 can generate m groups of target clock signals based on the reference frequency, m target frequency deviations and target offset directions. The above m groups of target clock signals correspond to the m asynchronous first-in-first-out devices one by one. Based on the above m groups of target clock signals, the first clock signal and the second clock signal of the m asynchronous first-in-first-out devices can be obtained and input into the m asynchronous first-in-first-out devices respectively.

[0052] The monitor is used to obtain output data of an asynchronous first-in-first-out device connected to the monitor.

[0053] The detector is used to check whether the time interval between two adjacent output data of an asynchronous first-in-first-out device connected to the detector is correct.

[0054] The comparator is used to check whether the data obtained by the monitor connected to the comparator is correct.

[0055] In actual implementation, the monitors, detectors, and comparators can correspond one to one with the asynchronous FIFO devices to be inspected. That is, the m monitors, m detectors, and m comparators mentioned above can be divided into m groups of devices, each group of devices can include a monitor, a detector, and a comparator, and any two groups of devices do not include the same type of devices. Each group of devices is connected to an asynchronous FIFO device, and any two groups of devices are connected to different asynchronous FIFO devices.

[0056] For each group of devices, the monitor in the group of devices can be connected to the output end of the asynchronous first-in-first-out device to obtain the output data of the asynchronous first-in-first-out device; the detector in the group of devices can also be connected to the output end of the asynchronous first-in-first-out device to obtain the time when the asynchronous first-in-first-out device outputs data each time, thereby obtaining the time interval between two adjacent output data, and based on the first clock signal and the second clock signal of the asynchronous first-in-first-out device, determine whether the time interval between two adjacent output data is correct (for example, it can be checked by comparing with a preset or pre-obtained target time interval); the comparator in the group of devices can be connected to the monitor in the group of devices to check whether the output data of the asynchronous first-in-first-out device connected to the monitor is correct (for example, it can be checked by comparing with the input data of the first-level asynchronous first-in-first-out device).

[0057] Figure 3The invention shows a system for checking asynchronous FIFO devices in the case of m=3, and the connection relationship between the system for checking asynchronous FIFO devices and three cascaded asynchronous FIFO devices. The system includes a clock generating device 300, which can be parameterized by a given reference frequency freq (which can be simplified as f), a target frequency offset offset (which can include three target frequency offset offset_input_x, i.e., m=3), a target offset direction dir, and the number of target clock signals n (N=n=3), three monitors (mon1, mon2, and mon3), three detectors (ipg_data_chk1, ipg_data_chk2, and ipg_data_chk3), and three comparators (fifo1_chk, fifo2_chk, and fifo3_chk). The system checks three cascaded asynchronous FIFO devices (fifo1, fifo2, and fifo3). Among them, sequence can represent a data queue used for checking, and the data in the queue can be transmitted through fifo1, fifo2, and fifo3 in sequence.

[0058] In some embodiments, the clock generation device 300 can call the clock generation function clk_gen_priv to generate clock signals such as rx1_clk, tx1_clk, tx2_clk, tx3_clk, etc. according to the input parameters (including reference frequency freq, target frequency offset offset and target offset direction dir).

[0059] In some embodiments, the above three asynchronous first-in-first-out devices may be asynchronous first-in-first-out devices with clock compensation.

[0060] The specific steps of the system checking fifo1, fifo2 and fifo3 may include:

[0061] The clock generation device 300 can call the clock generation function clk_gen_priv, and generate clock signals such as rx1_clk, tx1_clk, tx2_clk, and tx3_clk according to the input parameters (including the reference frequency freq, the target frequency offset offset, and the target offset direction dir); wherein the reference frequency freq is used to specify the frequency of the generated target clock signal; the target offset direction dir is used to indicate the magnitude relationship between the frequencies of the first sub-signal tx_clk and the second sub-signal rx_clk included in each target clock signal; the target frequency offset offset is used to specify the magnitude of the frequency offset of the target clock signal;

[0062] Among the above clock signals, rx1_clk can be input into the rx_clk port of fifo1 as the first clock signal of fifo1; tx1_clk can be input into the tx_clk port and the rx_clk port of fifo1 as the second clock signal of fifo1 and as the first clock signal of fifo2; tx2_clk can be input into the tx_clk port and the rx_clk port of fifo2 as the second clock signal of fifo2 and as the first clock signal of fifo3; tx3_clk can be input into the tx_clk port of fifo3 as the second clock signal of fifo3;

[0063] Among the above three monitors, mon1, mon2 and mon3 can collect the output data of fifo1, fifo2 and fifo3 respectively, and store them in queues act1_q, act2_q and act3_q respectively;

[0064] Among the above three detectors, ipg_data_chk1, ipg_data_chk2 and ipg_data_chk3 can respectively detect whether the time interval between the messages (output data is in the form of messages) output by fifo1, fifo2 and fifo3 is correct;

[0065] Among the above three comparators, fifo1_chk, fifo2_chk and fifo3_chk can respectively check whether the output data collected by the three monitors are correct.

[0066] It can be understood that the rx_data ports of fifo1, fifo2 and fifo3 are used to receive data, that is, receive external input data; and the tx_data ports of fifo1, fifo2 and fifo3 are used to send data, that is, output data to the outside.

[0067] In some embodiments, mon1, mon2 and mon3 may respectively collect output data of fifo1, fifo2 and fifo3 in real time according to instructions of valid signals vld of fifo1, fifo2 and fifo3.

[0068] In some embodiments, ipg_data_chk1, ipg_data_chk2 and ipg_data_chk3 can respectively detect whether the time intervals between the messages output by fifo1, fifo2 and fifo3 are correct according to the intervals between the valid signals vld of fifo1, fifo2 and fifo3.

[0069] It should be noted that for Figure 3The clock generation device 300 shown can generate three target clock signals, each of which includes a first sub-signal and a second sub-signal, so the clock signals generated by the clock generation device 300 include: a first sub-signal tx_clk_1 and a second sub-signal rx_clk_1 corresponding to the first target frequency deviation, a first sub-signal tx_clk_2 and a second sub-signal rx_clk_2 corresponding to the second target frequency deviation, and a first sub-signal tx_clk_3 and a second sub-signal rx_clk_3 corresponding to the third target frequency deviation. Considering the relationship between the first clock signal and the second clock signal of the cascaded asynchronous first-in-first-out device, rx_clk_1 can be used as rx1_clk, tx_clk_1 or rx_clk_2 can be used as tx1_clk, tx_clk_2 or rx_clk_3 can be used as tx2_clk, and tx_clk_3 can be used as tx3_clk. Although fifio2 may not use rx_clk_2 and fifio3 may not use rx_clk_3, since tx_clk_2 used by fifio2 and tx_clk_3 used by fifio3 meet the requirements of the target frequency offset, the requirement of using the clock signal of the target frequency offset to check each asynchronous first-in-first-out device in the cascade can be met.

[0070] According to the system for checking asynchronous first-in-first-out devices provided in the embodiments of the present application, it is possible to provide frequency deviations of various frequencies within a critical range for asynchronous clocks on both sides of the asynchronous first-in-first-out devices, and check the outputs of the asynchronous first-in-first-out devices in real time. In addition, in the case of cascading multiple stages of asynchronous first-in-first-out devices, it is still possible to provide frequency deviations of various frequencies within a critical range for each stage of asynchronous first-in-first-out devices, and check the outputs of each stage of asynchronous first-in-first-out devices in real time. By giving a reference frequency, multiple target frequency deviations, a target offset direction, and the number of target clock signals, a frequency deviation of any frequency and any degree is applied to a single asynchronous first-in-first-out device and multiple cascaded asynchronous first-in-first-out devices, and the output effect of each asynchronous first-in-first-out device under different frequency deviations can be checked in real time.

[0071] In some embodiments, Figure 2 As shown, the clock generating device 300 includes: an acquisition module 210 and a signal generating module 220 .

[0072] In actual implementation, the acquisition module 210 may be electrically connected to the sum signal generation module 220 .

[0073] The acquisition module 210 is used to obtain the reference frequency, m target frequency deviations, target offset directions and the number m of target clock signal groups; each group of target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each group of target clock signals is the target frequency deviation; the m groups of target clock signals correspond one-to-one to the m asynchronous first-in-first-out devices.

[0074] In actual execution, the acquisition module 210 may acquire the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction dir, and the number n of target clock signals based on the user's input. Alternatively, the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction dir, and the number n of target clock signals may be received from other devices, and the user has input the device or the device has acquired the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction, and the number m of groups of target clock signals.

[0075] The signal generating module 220 is used to generate an initial signal for each target frequency deviation based on the reference frequency and the target frequency deviation, and to invert the initial signal based on its polarity to obtain a first sub-signal and a second sub-signal corresponding to the target frequency deviation, thereby generating m groups of target clock signals.

[0076] In actual execution, the signal generating module 220 can generate an initial signal with a period corresponding to the target frequency deviation and the target offset direction based on the reference frequency and the target frequency deviation for any target frequency deviation, and reverse the polarity of the initial signal, determine the duration of each periodic signal according to the reversed polarity, and obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation. The only difference is that the period of the periodic signal is different from the period of the first sub-signal and the period of the second sub-signal, and the period of the first sub-signal and the period of the second sub-signal need to meet the requirements of the target frequency deviation and the target offset direction.

[0077] In some embodiments, the signal generating module 220 can be specifically used to: generate an initial signal for the xth target frequency deviation based on the reference frequency and the xth target frequency deviation, and reverse the initial signal based on the polarity to obtain a first sub-signal and a second sub-signal corresponding to the xth target frequency deviation, thereby obtaining the mth group of target clock signals; wherein 1≤x≤m.

[0078] In some embodiments, the signal generating module 220 may include:

[0079] An initialization unit is used to generate an initial signal with random polarity and a target duration, and randomly generate a first offset and a second offset; the target duration is half of the period corresponding to the reference frequency plus the unit time of the initial offset; the initial offset is a random value between 0 and one-quarter of the x-th target frequency deviation; the sum of the first offset and the second offset is equal to half of the x-th target frequency deviation;

[0080] A signal generating unit, used to use the initial signal as the first sub-signal corresponding to the xth target frequency deviation of the first upper half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first upper half cycle, and reverse the polarity of the initial signal to generate the first sub-signal corresponding to the xth target frequency deviation of the first lower half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first lower half cycle; the duration of the first lower half cycle of the first sub-signal and the second sub-signal corresponding to the xth target frequency deviation are both the target duration;

[0081] A determination unit, configured to determine, based on the target offset direction, a duration of a first half cycle of a first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and a duration of a second half cycle of a second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and a duration of a first half cycle and a duration of a second half cycle of a second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle;

[0082] The signal generating unit is also used to perform polarity inversion on the first sub-signal corresponding to the x-th target frequency deviation in units of half a cycle, and last for the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, respectively, to generate the first sub-signal corresponding to the x-th target frequency deviation; and to perform polarity inversion on the second sub-signal corresponding to the x-th target frequency deviation in units of half a cycle, and last for the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, respectively, to generate the second sub-signal corresponding to the x-th target frequency deviation.

[0083] In some embodiments, the determining unit may include:

[0084] a first determining subunit, configured to determine the target parameter as a first value when the target offset direction is a first direction; determine the target parameter as a second value when the target offset direction is a second direction; and determine the target parameter as the first value or the second value when the target offset direction is a third direction;

[0085] The second determination sub-unit is used to determine the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, as well as the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle based on the target parameters, the period corresponding to the reference frequency, the first offset and the second offset.

[0086] In some embodiments, the second determining subunit may be specifically configured to:

[0087] When the target parameter is the first numerical value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset quantity; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset quantity; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset quantity;

[0088] When the target parameter is the second numerical value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset number; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset number; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset number; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset number.

[0089] In some embodiments, the signal generating unit can be specifically used to, when the polarity of the first sub-signal is reversed to the first polarity, continue the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation except the first cycle, to obtain the y-th upper half cycle of the first sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the first sub-signal is reversed to the second polarity, continue the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation except the first cycle, to obtain the y-th lower half cycle of the first sub-signal corresponding to the x-th target frequency deviation, thereby generating a first sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0090] In some embodiments, the signal generating unit can be specifically used to, when the polarity of the second sub-signal is reversed to the first polarity, continue the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation except the first cycle, to obtain the y-th upper half cycle of the second sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the second sub-signal is reversed to the second polarity, continue the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation except the first cycle, to obtain the y-th lower half cycle of the second sub-signal corresponding to the x-th target frequency deviation, thereby generating the second sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0091] According to the system for checking asynchronous first-in-first-out devices provided in the embodiments of the present application, an initial signal is generated for each target frequency deviation based on a reference frequency, multiple target frequency deviations and a target offset direction, and the initial signal is inverted based on the polarity to obtain a first sub-signal and a second sub-signal corresponding to the target frequency deviation, thereby generating a specified number of target clock signals, which can generate a frequency deviation of any degree at any frequency, can apply a frequency deviation of any degree at any frequency to a single asynchronous first-in-first-out device and to a plurality of asynchronous first-in-first-out devices when they are cascaded, can provide frequency deviations of various frequencies within a critical range for the asynchronous clocks on both sides of each asynchronous first-in-first-out device in a single first-in-first-out device or in a plurality of cascaded first-in-first-out devices, and can generate a clock with a frequency deviation of any degree at any frequency for checking each asynchronous first-in-first-out device in a plurality of cascaded asynchronous first-in-first-out devices.

[0092] The embodiment of the present application also provides a method for checking an asynchronous first-in-first-out device, which is used to detect m cascaded asynchronous first-in-first-out devices; m is a positive integer. Figure 3 As shown, the method includes: step 310, step 320 and step 330.

[0093] In actual execution, the execution subject of the method for checking asynchronous first-in-first-out devices may be the aforementioned system for checking asynchronous first-in-first-out devices.

[0094] Step 310, generate a first clock signal and a second clock signal for each asynchronous FIFO device; the first clock signal is a clock signal used by the asynchronous FIFO device to receive data; the second clock signal is a clock signal used by the asynchronous FIFO device to send data.

[0095] In actual implementation, the clock generation device 300 can generate m groups of target clock signals based on the reference frequency, m target frequency deviations and target offset directions. The above m groups of target clock signals correspond to the m asynchronous first-in-first-out devices one by one. Based on the above m groups of target clock signals, the first clock signal and the second clock signal of the m asynchronous first-in-first-out devices can be obtained and input into the m asynchronous first-in-first-out devices respectively.

[0096] Step 320: Obtain output data of each asynchronous first-in-first-out device.

[0097] In actual implementation, each monitor can obtain the output data of the asynchronous first-in-first-out device connected to itself.

[0098] Step 330: Check whether the time interval between two adjacent output data of each asynchronous FIFO device is correct, and check whether the output data of each asynchronous FIFO device is correct.

[0099] In actual implementation, each detector can check whether the time interval between two adjacent output data of the asynchronous first-in-first-out device connected to itself is correct.

[0100] Each comparator can check whether the data obtained by the monitor connected to it is correct.

[0101] According to the method for checking asynchronous FIFO devices provided in the embodiment of the present application, various frequency deviations within a critical range can be provided for asynchronous clocks on both sides of the asynchronous FIFO devices, and the output of the asynchronous FIFO devices can be checked in real time. In addition, in the case of cascading multiple stages of asynchronous FIFO devices, various frequency deviations within a critical range can still be provided for each stage of asynchronous FIFO devices, and the output of each stage of asynchronous FIFO devices can be checked in real time. By giving a reference frequency, multiple target frequency deviations, a target offset direction, and the number of target clock signals, a frequency deviation of any frequency and any degree can be applied to a single asynchronous FIFO device and multiple cascaded asynchronous FIFO devices, and the output effect of each asynchronous FIFO device under different frequency deviations can be checked in real time.

[0102] In some embodiments, generating the first clock signal and the second clock signal of each asynchronous first-in-first-out device includes: obtaining a reference frequency, m target frequency deviations, a target offset direction, and a group number m of target clock signals; each group of target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each target clock signal is the target frequency deviation; and the m groups of target clock signals correspond one-to-one to the m asynchronous first-in-first-out devices.

[0103] In actual implementation, step 310 is a clock generation method. The clock generation method can be applied to a terminal, and can be specifically executed by hardware or software in the terminal. The terminal can be the aforementioned clock generation device 300.

[0104] The terminal includes, but is not limited to, a portable communication device such as a mobile phone or tablet computer with a touch-sensitive surface (e.g., a touch screen display and / or a touch pad). It should also be understood that in some embodiments, the terminal may not be a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., a touch screen display and / or a touch pad).

[0105] In the following various embodiments, a terminal including a display and a touch-sensitive surface is described. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, a mouse and a joystick.

[0106] The clock generation method provided in the embodiment of the present application may be executed by an electronic device or a functional module or functional entity in the electronic device that can implement the clock generation method. The electronic devices mentioned in the embodiment of the present application include but are not limited to mobile phones, tablet computers, computers, cameras, and wearable devices. The clock generation method provided in the embodiment of the present application is described below using an electronic device as an example of the execution subject.

[0107] In some embodiments, the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction dir, and the number n of target clock signals may be obtained based on the user's input. Alternatively, the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction dir, and the number n of target clock signals may be received from another device, and the user has input the device or the device has obtained the reference frequency f, m target frequency offsets offset_input_x (x=1, 2, ..., m), the target offset direction, and the number m of groups of target clock signals.

[0108] The clock generation method provided in the embodiment of the present application is used to generate 2m target clock signals based on the above-mentioned reference frequency, m target frequency deviations, target offset directions, and the number of groups m of target clock signals. Each group of target clock signals can be generated based on a target frequency deviation, and the group of target clock signals is the target clock signal corresponding to the target frequency deviation. The first sub-signal and the second sub-signal included in the group of target clock signals are respectively the first sub-signal and the second sub-signal corresponding to the target frequency deviation. Among them, the target offset direction dir is used to indicate the magnitude relationship between the frequency of the first sub-signal and the frequency of the second sub-signal in the first sub-signal and the second sub-signal included in each target clock signal.

[0109] For each target frequency deviation, an initial signal is generated based on the reference frequency and the target frequency deviation, and the initial signal is inverted based on its polarity to obtain a first sub-signal and a second sub-signal corresponding to the target frequency deviation, thereby generating m groups of target clock signals.

[0110] In actual implementation, for each target frequency deviation, the first sub-signal and the second sub-signal corresponding to the target frequency deviation can be generated respectively, so as to obtain the target clock signal corresponding to the target frequency deviation. Based on the target clock signals corresponding to the target frequency deviations, the required n target clock signals can be obtained.

[0111] For any target frequency deviation, the basic technical route for generating the first sub-signal and the second sub-signal corresponding to the target frequency deviation is: first, based on the reference frequency and the target frequency deviation, generate an initial signal with a period corresponding to the target frequency deviation and the target offset direction, and reverse the polarity of the initial signal, determine the duration of each periodic signal according to the reversed polarity, and obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation. The only difference is that the period of the periodic signal is different from the period of the first sub-signal and the period of the second sub-signal, and the period of the first sub-signal and the period of the second sub-signal need to meet the requirements of the target frequency deviation and the target offset direction.

[0112] It should be noted that both the reference frequency and the target frequency deviation can be set arbitrarily by the user. Accordingly, the period of the first sub-signal and the period of the second sub-signal can be any value within a certain range.

[0113] According to the method for checking asynchronous first-in-first-out devices provided in the embodiment of the present application, an initial signal is generated for each target frequency deviation based on a reference frequency, multiple target frequency deviations and a target offset direction, and the initial signal is inverted based on the polarity to obtain a first sub-signal and a second sub-signal corresponding to the target frequency deviation, thereby generating a specified number of target clock signals, which can generate a frequency deviation of any degree at any frequency, can apply a frequency deviation of any degree at any frequency to a single asynchronous first-in-first-out device and to a plurality of asynchronous first-in-first-out devices when they are cascaded, can provide frequency deviations of various frequencies within a critical range for the asynchronous clocks on both sides of a single first-in-first-out device or each asynchronous first-in-first-out device in a plurality of cascaded first-in-first-out devices, and can generate a clock with a frequency deviation of any degree at any frequency for checking each asynchronous first-in-first-out device in a plurality of cascaded asynchronous first-in-first-out devices.

[0114] In some embodiments, for each target frequency deviation, an initial signal is generated based on the reference frequency and the target frequency deviation, and the initial signal is reversed based on the polarity to obtain a first sub-signal and a second sub-signal corresponding to the target frequency deviation, thereby generating m groups of target clock signals, including: for the x-th target frequency deviation, an initial signal is generated based on the reference frequency and the x-th target frequency deviation, and the initial signal is reversed based on the polarity to obtain a first sub-signal and a second sub-signal corresponding to the x-th target frequency deviation, thereby obtaining an x-th group of target clock signals; wherein, 1≤x≤m.

[0115] In actual implementation, the target frequency deviation corresponds to each group of target clock signals one by one. Therefore, through the above basic technical route of generating a first sub-signal and a second sub-signal corresponding to a target frequency deviation, the first sub-signal and the second sub-signal corresponding to the target frequency deviation can be generated for each target frequency deviation, and the first sub-signal and the second sub-signal corresponding to m target frequency deviations can be obtained, thereby obtaining the target clock signals corresponding to m target frequency deviations. It can be understood that x is a positive integer.

[0116] According to the clock generation method provided in the embodiment of the present application, a target clock signal including a first sub-signal and a second sub-signal is generated for each target frequency deviation respectively, thereby generating m groups of target clock signals, which can generate a frequency deviation of any degree at any frequency, can apply a frequency deviation of any degree at any frequency to a single asynchronous first-in-first-out device and to a plurality of asynchronous first-in-first-out devices when they are cascaded, can provide frequency deviations of various frequencies within a critical range for the asynchronous clocks on both sides of a single first-in-first-out device or each asynchronous first-in-first-out device in a plurality of cascaded first-in-first-out devices, and can generate a clock with a frequency deviation of any degree at any frequency for checking each asynchronous first-in-first-out device in a plurality of cascaded asynchronous first-in-first-out devices.

[0117] In some embodiments, for the xth target frequency deviation, an initial signal is generated based on the reference frequency and the xth target frequency deviation, and the initial signal is reversed based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the xth target frequency deviation, thereby obtaining the xth group of target clock signals, including: generating an initial signal with random polarity and lasting for a target duration, and randomly generating a first offset and a second offset; the target duration is half of the period corresponding to the reference frequency plus the unit time of the initial offset number; the initial offset is a random value between 0 and one-quarter of the xth target frequency deviation; the sum of the first offset and the second offset is equal to half of the xth target frequency deviation.

[0118] In actual execution, the period p corresponding to the reference frequency can be obtained based on the reference frequency f.

[0119] In some embodiments, considering the conversion of time units and the accuracy of the target clock signal, the period p corresponding to the reference frequency can be calculated based on the following formula: p=(1000 / f)×1000000.

[0120] An initial signal clk_x corresponding to the xth target frequency deviation can be generated, and the polarity polar of the initial signal clk_x can be randomly determined. It can be understood that the polarity of a signal refers to the level state of the signal. Therefore, the initial signal of the first half cycle can be a high level or a low level. The initial signal can last for a target duration, and the target duration can be any value in the number of unit times from 0 to (offset_input_x / 4).

[0121] Based on the xth target frequency offset offset_input_x, the xth actually used frequency offset offset_x can be obtained. The xth actually used frequency offset offset_x can be calculated based on the following formula: offset_x=(offset_input_x) / 2.

[0122] Based on the x-th actually used frequency offset offset_x, a first offset offset_p_x corresponding to the x-th target frequency offset and a second offset offset_n_x corresponding to the x-th target frequency offset can be randomly generated. The sum of the first offset offset_p_x corresponding to the x-th target frequency offset and the second offset offset_n_x corresponding to the x-th target frequency offset is equal to the x-th actually used frequency offset offset_x, but the respective values ​​of the first offset offset_p_x corresponding to the x-th target frequency offset and the second offset offset_n_x corresponding to the x-th target frequency offset can be random.

[0123] The initial signal is used as the first sub-signal corresponding to the xth target frequency deviation of the first upper half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first upper half cycle, and the polarity of the initial signal is reversed to generate the first sub-signal corresponding to the xth target frequency deviation of the first lower half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first lower half cycle; the duration of the first lower half cycle of the first sub-signal corresponding to the xth target frequency deviation and the second sub-signal are both the target duration.

[0124] In actual implementation, the first sub-signal corresponding to the x-th target frequency deviation and the first upper half cycle of the second sub-signal corresponding to the x-th target frequency deviation can be the aforementioned initial signal. The initial signal is polarity reversed and still continues for the target duration to obtain the first sub-signal corresponding to the x-th target frequency deviation and the first lower half cycle of the second sub-signal corresponding to the x-th target frequency deviation.

[0125] Based on the target offset direction, determine the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, as well as the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle.

[0126] In actual execution, based on the target offset direction dir and on the basis of half of the period p corresponding to the reference frequency, the first offset offset_p_x corresponding to the x-th target frequency deviation and the second offset offset_n_x corresponding to the x-th target frequency deviation can be increased or decreased to obtain the first half-cycle duration (referring to the duration of each upper half-cycle after the first cycle) and the second half-cycle duration (referring to the duration of each lower half-cycle after the first cycle) of the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation, as well as the first half-cycle duration (referring to the duration of each upper half-cycle after the first cycle) and the second half-cycle duration (referring to the duration of each lower half-cycle after the first cycle) of the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation, so as to form a frequency deviation through the corresponding periodic offset.

[0127] The polarity of the first sub-signal corresponding to the x-th target frequency deviation is reversed in units of half a cycle, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the first sub-signal corresponding to the x-th target frequency deviation; and the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half a cycle, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the second sub-signal corresponding to the x-th target frequency deviation.

[0128] In actual implementation, the first sub-signal corresponding to the x-th target frequency deviation can be reversed every half cycle, and the duration of the new half-cycle signal can be based on the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, thereby generating the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation.

[0129] For the second sub-signal corresponding to the x-th target frequency deviation, it can be reversed every half cycle, and the duration of the new half-cycle signal can be based on the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, thereby generating the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation.

[0130] According to the clock generation method provided in an embodiment of the present application, an initial signal with random polarity and lasting for a target duration is generated, and a first offset and a second offset are randomly generated. The initial signal is used as the first sub-signal corresponding to the xth target frequency deviation of the first upper half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first upper half cycle, and the polarity of the initial signal is reversed to generate a first sub-signal corresponding to the xth target frequency deviation of the first lower half cycle and a second sub-signal corresponding to the xth target frequency deviation of the first lower half cycle. Based on the target offset direction, the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the xth target frequency deviation excluding the first cycle, as well as the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the xth target frequency deviation excluding the first cycle, are determined. The polarity of the first sub-signal corresponding to the xth target frequency deviation is reversed in units of half cycles, and the durations corresponding to the xth target frequency deviation are respectively lasting for the xth target frequency deviation. The first sub-signal corresponding to the x-th target frequency deviation is generated by taking the duration of the first half cycle and the second half cycle of the first sub-signal excluding the first cycle as the unit, and the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration of the first half cycle and the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation are respectively continued to generate the second sub-signal corresponding to the x-th target frequency deviation. The frequency deviation of any frequency and any degree can be generated, and any frequency deviation of any frequency and any degree can be applied to a single asynchronous first-in-first-out device and multiple asynchronous first-in-first-out devices when they are cascaded. Various frequency deviations within a critical range can be provided for the asynchronous clocks on both sides of each asynchronous first-in-first-out device in a single first-in-first-out device or multiple cascaded first-in-first-out devices. A clock with any frequency and any degree of frequency deviation can be generated for checking each asynchronous first-in-first-out device in multiple cascaded asynchronous first-in-first-out devices.

[0131] In some embodiments, based on the target offset direction, the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, as well as the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle are determined, including: when the target offset direction is a first direction, determining the target parameter as a first value; when the target offset direction is a second direction, determining the target parameter as a second value; when the target offset direction is a third direction, determining the target parameter as the first value or the second value.

[0132] In actual implementation, the target offset direction dir can be indicated by different values. In some embodiments, the values ​​of the target offset direction dir are 0, 1, and 2, respectively indicating that the frequency of the first sub-signal is pre-specified to be less than the frequency of the second sub-signal, the frequency of the first sub-signal is pre-specified to be greater than the frequency of the second sub-signal, and the magnitude relationship between the frequency of the first sub-signal and the frequency of the second sub-signal is randomly generated without pre-specification.

[0133] In some embodiments, when the value of the target offset direction dir is 0, the target parameter freq_offset_plus_minus can be determined as the first value 0; when the value of the target offset direction dir is 1, the target parameter freq_offset_plus_minus can be determined as the second value 1; when the value of the target offset direction dir is 2, the target parameter freq_offset_plus_minus can be determined as a random value between 0 and 1, that is, the value of the target parameter freq_offset_plus_minus is randomly selected from the first value 0 and the second value 1, and can be 0 or 1.

[0134] Based on the target parameters, the period corresponding to the reference frequency, the first offset and the second offset, determine the duration of the first half period and the duration of the second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, as well as the duration of the first half period and the duration of the second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period.

[0135] In actual execution, the period corresponding to the reference frequency can be increased or decreased based on different values ​​of the target parameters, and the amplitude of the increase or decrease can be determined based on the first offset or the second offset, so as to obtain the first half-period length and the second half-period length of the first sub-signal corresponding to the x-th target frequency deviation, as well as the first half-period length and the second half-period length of the second sub-signal corresponding to the x-th target frequency deviation (all are periods after the first period).

[0136] According to the clock generation method provided by the embodiment of the present application, when the target offset direction is the first direction, the target parameter is determined as the first value, when the target offset direction is the second direction, the target parameter is determined as the second value, and when the target offset direction is the third direction, the target parameter is determined as the first value or the second value. Based on the target parameter, the period corresponding to the reference frequency, the first offset and the second offset, the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the xth target frequency offset excluding the first cycle, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the xth target frequency offset excluding the first cycle are determined. A frequency offset of any degree at any frequency can be generated, and a frequency offset of any degree at any frequency can be applied to a single asynchronous first-in-first-out device and multiple asynchronous first-in-first-out devices when they are cascaded. Various frequency offsets within a critical range can be provided for asynchronous clocks on both sides of each asynchronous first-in-first-out device in a single first-in-first-out device or multiple cascaded first-in-first-out devices. A clock with a frequency offset of any degree at any frequency can be generated for checking each asynchronous first-in-first-out device in multiple cascaded asynchronous first-in-first-out devices.

[0137] In some embodiments, based on the target parameter, the period corresponding to the reference frequency, the first offset and the second offset, the duration of the first half period and the duration of the second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, as well as the duration of the first half period and the duration of the second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period are determined, including: when the target parameter is a first numerical value, the duration of the first half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period is determined as half of the period corresponding to the reference frequency minus the unit time of the first offset number, the duration of the second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period is determined as half of the period corresponding to the reference frequency minus the unit time of the second offset number, the duration of the first half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period is determined as half of the period corresponding to the reference frequency plus the unit time of the first offset number, and the duration of the second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period is determined as half of the period corresponding to the reference frequency plus the unit time of the second offset number.

[0138] In actual execution, when the target parameter freq_offset_plus_minus is the first value 0, the duration of the first half cycle of the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation is half_period_p_x=(p / 2)-offset_p_x (except the first upper half cycle), the duration of the second half cycle of the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation is half_period_n_x=(p / 2)-offset_n_x (except the first lower half cycle), the duration of the first half cycle of the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation is half_period_p_x=(p / 2)+offset_p_x (except the first upper half cycle), and the duration of the second half cycle of the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation is half_period_n_x=(p / 2)+offset_n_x (except the first lower half cycle).

[0139] When the target parameter is the second numerical value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset number; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset number; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset number; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset number.

[0140] In actual execution, when the target parameter freq_offset_plus_minus is the second value 1, the duration of the first half cycle of the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation is half_period_p_x=(p / 2)+offset_p_x (except the first upper half cycle), the duration of the second half cycle of the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation is half_period_n_x=(p / 2)+offset_n_x (except the first lower half cycle), the duration of the first half cycle of the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation is half_period_p_x=(p / 2)-offset_p_x (except the first upper half cycle), and the duration of the second half cycle of the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation is half_period_n_x=(p / 2)-offset_n_x (except the first lower half cycle).

[0141] According to the clock generation method provided by the embodiment of the present application, when the target parameter is a first value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset quantity, the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset quantity, the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity, and the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity, and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity, and the duration of the second half cycle of the first ... The duration of the second half cycle of the second sub-signal corresponding to the target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset number. It can generate a frequency deviation of any degree at any frequency, can apply a frequency deviation of any degree at any frequency to a single asynchronous first-in-first-out device and when multiple asynchronous first-in-first-out devices are cascaded, can provide frequency deviations of various frequencies within a critical range for the asynchronous clocks on both sides of a single first-in-first-out device or each asynchronous first-in-first-out device in multiple cascaded first-in-first-out devices, and can generate a clock with a frequency deviation of any degree at any frequency for checking each asynchronous first-in-first-out device in multiple cascaded asynchronous first-in-first-out devices.

[0142] In some embodiments, the polarity of the first sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle are respectively continued to generate the first sub-signal corresponding to the x-th target frequency deviation, including: when the polarity of the first sub-signal is reversed to the first polarity, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th upper half cycle of the first sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the first sub-signal is reversed to the second polarity, the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th lower half cycle of the first sub-signal corresponding to the x-th target frequency deviation, thereby generating the first sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0143] In actual implementation, polarity inversion may be performed every half cycle, so that the polarities of any two adjacent half cycles of the first sub-signal corresponding to the x-th target frequency deviation are opposite.

[0144] When the actual polarity of each polarity reversal is 1 (generally indicating a high level), the polarity of 1 is assigned to the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation, and continues for the length of the first half cycle, that is, it continues for half_period_p_x number of unit times, to obtain the signal of the upper half cycle in a cycle; and when the actual polarity after each polarity reversal is 0 (generally indicating a low level), the polarity of 0 is assigned to the first sub-signal tx_clk_x corresponding to the x-th target frequency deviation, and continues for the length of the second half cycle, that is, it continues for half_period_n_x number of unit times, to obtain the signal of the lower half cycle in a cycle.

[0145] By cyclically performing polarity inversion of the first sub-signal tx_clk_x, the first sub-signal tx_clk_x having a desired frequency offset of offset_x can be obtained.

[0146] It should be noted that the above embodiment takes the x-th target frequency deviation as an example to illustrate the generation process of the first sub-signal corresponding to the x-th target frequency deviation, but those skilled in the art can understand that the same method can be repeated m times to obtain the first sub-signals corresponding to m target frequency deviations.

[0147] According to the clock generation method provided in the embodiment of the present application, the polarity of the first sub-signal is reversed every half cycle, and the polarity is reversed for the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation respectively, so as to generate a first sub-signal corresponding to the x-th target frequency deviation. A frequency deviation of any degree at any frequency can be generated, and a frequency deviation of any degree at any frequency can be applied to a single asynchronous first-in-first-out device and multiple asynchronous first-in-first-out devices when they are cascaded. Frequency deviations of various frequencies within a critical range can be provided for asynchronous clocks on both sides of each asynchronous first-in-first-out device in a single first-in-first-out device or multiple cascaded first-in-first-out devices. A clock with a frequency deviation of any degree at any frequency can be generated for checking each asynchronous first-in-first-out device in multiple cascaded asynchronous first-in-first-out devices.

[0148] In some embodiments, the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle are respectively continued to generate the second sub-signal corresponding to the x-th target frequency deviation, including: when the polarity of the second sub-signal is reversed to the first polarity, the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th upper half cycle of the second sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the second sub-signal is reversed to the second polarity, the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th lower half cycle of the second sub-signal corresponding to the x-th target frequency deviation, thereby generating the second sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

[0149] In actual implementation, polarity inversion may be performed every half cycle, so that the polarities of any two adjacent half cycles of the second sub-signal corresponding to the x-th target frequency deviation are opposite.

[0150] When the actual polarity of each polarity reversal is 1 (generally indicating a high level), the polarity of 1 is assigned to the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation, and continues for the length of the first half cycle, that is, it continues for half_period_p_x number of unit times, to obtain the signal of the upper half cycle in one cycle; and when the actual polarity after each polarity reversal is 0 (generally indicating a low level), the polarity of 0 is assigned to the second sub-signal rx_clk_x corresponding to the x-th target frequency deviation, and continues for the length of the second half cycle, that is, it continues for half_period_n_x number of unit times, to obtain the signal of the lower half cycle in one cycle.

[0151] By cyclically performing polarity inversion of the second sub-signal rx_clk_x, the second sub-signal rx_clk_x with a desired frequency offset of offset_x can be obtained.

[0152] It should be noted that the above embodiment takes the x-th target frequency deviation as an example to illustrate the generation process of the second sub-signal corresponding to the x-th target frequency deviation, but those skilled in the art can understand that the same method can be repeated m times to obtain the second sub-signals corresponding to m target frequency deviations.

[0153] It can be understood that by obtaining the first sub-signals and the second sub-signals corresponding to m target frequency deviations, m groups of target clock signals can be obtained.

[0154] According to the clock generation method provided in the embodiment of the present application, the second sub-signal corresponding to the x-th target frequency deviation is generated by performing polarity inversion on the second sub-signal every half cycle, and the inversion lasts for the duration of the first half cycle and the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, respectively. A frequency deviation of any degree at any frequency can be generated, and a frequency deviation of any degree at any frequency can be applied to a single asynchronous first-in-first-out device and multiple asynchronous first-in-first-out devices when they are cascaded. Frequency deviations of various frequencies within a critical range can be provided for asynchronous clocks on both sides of each asynchronous first-in-first-out device in a single first-in-first-out device or multiple cascaded first-in-first-out devices. A clock with a frequency deviation of any degree at any frequency can be generated for checking each asynchronous first-in-first-out device in multiple cascaded asynchronous first-in-first-out devices.

[0155] The clock generating device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0156] The clock generating device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0157] The clock generation device provided in the embodiment of the present application can achieve Figure 3 The process of generating m groups of target clock signals in each process implemented by the method embodiment will not be described again here to avoid repetition.

[0158] In some embodiments, Figure 4 As shown, an embodiment of the present application also provides an electronic device 400, including a processor 401, a memory 402, and a computer program stored in the memory 402 and executable on the processor 401. When the program is executed by the processor 401, each process of the above-mentioned clock generation method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0159] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0160] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned clock generation method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0161] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0162] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned clock generation method when executed by a processor.

[0163] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0164] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned clock generation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0165] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0166] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0167] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0168] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0169] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0170] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A system for checking asynchronous first-in-first-out equipment, characterized in that: include: A clock generating device, m monitors, m detectors and m comparators; m is the number of asynchronous first-in-first-out devices to be checked; m asynchronous first-in-first-out devices are cascaded; m is a positive integer; The clock generating device is used to generate a first clock signal and a second clock signal for each of the asynchronous first-in-first-out devices; the first clock signal is a clock signal used by the asynchronous first-in-first-out device to receive data; the second clock signal is a clock signal used by the asynchronous first-in-first-out device to send data; The monitor is used to obtain output data of the asynchronous first-in-first-out device connected to the monitor; The detector is used to check whether the time interval between two adjacent output data of the asynchronous first-in-first-out device connected to the detector is correct; The comparator is used to check whether the data acquired by the monitor connected to the comparator is correct.

2. The system for checking asynchronous first-in-first-out equipment according to claim 1, characterized in that: The clock generating device comprises: An acquisition module, used for acquiring a reference frequency, m target frequency deviations, target offset directions, and a number m of target clock signal groups; each group of the target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each group of the target clock signals is the target frequency deviation; the m groups of the target clock signals correspond one to one with the m asynchronous first-in-first-out devices; A signal generating module is used to generate an initial signal for each target frequency deviation based on the reference frequency and the target frequency deviation, and to invert the initial signal based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals.

3. A method for checking an asynchronous first-in-first-out device, characterized in that: A method for detecting m cascaded asynchronous first-in-first-out devices; m is a positive integer; the method comprises: Generate a first clock signal and a second clock signal for each of the asynchronous FIFO devices; the first clock signal is a clock signal used by the asynchronous FIFO device to receive data; the second clock signal is a clock signal used by the asynchronous FIFO device to send data; Obtaining output data of each of the asynchronous first-in-first-out devices; Check respectively whether the time interval between two adjacent output data of each asynchronous first-in-first-out device is correct, and check respectively whether the output data of each asynchronous first-in-first-out device is correct.

4. The method for checking an asynchronous first-in-first-out device according to claim 3, characterized in that: Generating the first clock signal and the second clock signal of each of the asynchronous first-in-first-out devices comprises: Obtain a reference frequency, m target frequency deviations, target offset directions, and a number m of target clock signal groups; each group of the target clock signals includes a first sub-signal and a second sub-signal; the frequency difference between the first sub-signal and the second sub-signal included in each of the target clock signals is the target frequency deviation; the m groups of the target clock signals correspond one-to-one to the m asynchronous first-in-first-out devices; For each target frequency deviation, an initial signal is generated based on the reference frequency and the target frequency deviation, and the initial signal is inverted based on its polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals.

5. The method for checking an asynchronous first-in-first-out device according to claim 4, characterized in that: The generating an initial signal based on the reference frequency and the target frequency deviation for each target frequency deviation respectively, and inverting the initial signal based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the target frequency deviation, thereby generating m groups of the target clock signals, including: For the x-th target frequency deviation, an initial signal is generated based on the reference frequency and the x-th target frequency deviation, and is reversed based on the polarity of the initial signal to obtain the first sub-signal and the second sub-signal corresponding to the x-th target frequency deviation, thereby obtaining the x-th group of target clock signals; wherein, 1≤x≤m.

6. The method for checking an asynchronous first-in-first-out device according to claim 5, characterized in that: The generating an initial signal based on the reference frequency and the xth target frequency deviation for the xth target frequency deviation, and reversing the initial signal based on the polarity to obtain the first sub-signal and the second sub-signal corresponding to the xth target frequency deviation, thereby obtaining the xth group of target clock signals, includes: Generate the initial signal with random polarity and lasting for a target duration, and randomly generate a first offset and a second offset; the target duration is half of the period corresponding to the reference frequency plus the unit time of the initial offset; the initial offset is a random value between 0 and one-quarter of the x-th target frequency deviation; the sum of the first offset and the second offset is equal to half of the x-th target frequency deviation; The initial signal is used as the first sub-signal corresponding to the xth target frequency deviation of the first upper half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first upper half cycle, and the polarity of the initial signal is reversed to generate the first sub-signal corresponding to the xth target frequency deviation of the first lower half cycle and the second sub-signal corresponding to the xth target frequency deviation of the first lower half cycle; the duration of the first lower half cycle of the first sub-signal and the second sub-signal corresponding to the xth target frequency deviation are both the target duration; Based on the target offset direction, determine the duration of the first half cycle and the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, and the duration of the first half cycle and the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle; The polarity of the first sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the first sub-signal corresponding to the x-th target frequency deviation; and the polarity of the second sub-signal corresponding to the x-th target frequency deviation is reversed in units of half cycles, and the duration is respectively continued for the length of the first half cycle and the length of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle, to generate the second sub-signal corresponding to the x-th target frequency deviation.

7. The method for checking an asynchronous first-in-first-out device according to claim 6, characterized in that: The determining, based on the target offset direction, a duration of a first half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and a duration of a second half cycle of the first sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and a duration of a first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle and a duration of a second half cycle, including: When the target offset direction is the first direction, the target parameter is determined as the first value; when the target offset direction is the second direction, the target parameter is determined as the second value; when the target offset direction is the third direction, the target parameter is determined as the first value or the second value; Based on the target parameters, the period corresponding to the reference frequency, the first offset and the second offset, determine the duration of the first half period and the duration of the second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, as well as the duration of the first half period and the duration of the second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period.

8. The method for checking an asynchronous first-in-first-out device according to claim 7, characterized in that: The determining, based on the target parameter, the period corresponding to the reference frequency, the first offset, and the second offset, a duration of a first half period and a duration of a second half period of the first sub-signal corresponding to the x-th target frequency deviation excluding the first period, and a duration of a first half period and a duration of a second half period of the second sub-signal corresponding to the x-th target frequency deviation excluding the first period, comprising: When the target parameter is the first value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset quantity; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset quantity; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset quantity; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset quantity; When the target parameter is the second numerical value, the duration of the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the first offset number; the duration of the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency plus the unit time of the second offset number; the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the first offset number; the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation, excluding the first cycle, is determined as half of the cycle corresponding to the reference frequency minus the unit time of the second offset number.

9. The method for checking an asynchronous first-in-first-out device according to any one of claims 6 to 8, characterized in that: The step of performing polarity reversal on the first sub-signal corresponding to the x-th target frequency deviation in units of half a cycle, and lasting for a first half cycle duration and a second half cycle duration of the first sub-signal corresponding to the x-th target frequency deviation except for the first cycle, respectively, to generate the first sub-signal corresponding to the x-th target frequency deviation, comprising: In the case where the polarity of the first sub-signal is reversed to the first polarity, the first half cycle of the first sub-signal corresponding to the x-th target frequency deviation is continued except the first cycle, and the y-th upper half cycle of the first sub-signal corresponding to the x-th target frequency deviation is obtained. In the case where the polarity of the first sub-signal is reversed to the second polarity, the second half cycle of the first sub-signal corresponding to the x-th target frequency deviation is continued except the first cycle, and the y-th lower half cycle of the first sub-signal corresponding to the x-th target frequency deviation is obtained, thereby generating the first sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

10. The method for inspecting an asynchronous first-in-first-out device according to any one of claims 6 to 8, characterized in that: The step of performing polarity reversal on the second sub-signal corresponding to the x-th target frequency deviation in units of half a cycle, and lasting for a first half cycle duration and a second half cycle duration of the second sub-signal corresponding to the x-th target frequency deviation excluding a first cycle, respectively, to generate the second sub-signal corresponding to the x-th target frequency deviation, comprising: When the polarity of the second sub-signal is reversed to the first polarity, the duration of the first half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th upper half cycle of the second sub-signal corresponding to the x-th target frequency deviation, and when the polarity of the second sub-signal is reversed to the second polarity, the duration of the second half cycle of the second sub-signal corresponding to the x-th target frequency deviation excluding the first cycle is continued to obtain the y-th lower half cycle of the second sub-signal corresponding to the x-th target frequency deviation, thereby generating the second sub-signal corresponding to the x-th target frequency deviation; y is an integer greater than 1.

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