Computing resource configuration method and device of FPGA (Field Programmable Gate Array) equipment and FPGA equipment

Abstract

The embodiment of the invention provides a computing resource configuration method and device of FPGA equipment and the FPGA equipment. The method comprises the steps that a heterogeneous query execution plan is generated according to a query request of a user, and the heterogeneous query plan comprises heterogeneous operators and non-heterogeneous operators; and determining a first number of resource blocks required to be configured for executing the heterogeneous operator based on the calculation throughput for processing a non-heterogeneous operator adjacent to the heterogeneous operator and the calculation throughput which can be provided by a single resource block in a programmable array logic FPGA (Field Programmable Gate Array) device. Through the embodiment of the invention, the problems that the throughput of the FPGA equipment is not matched with the calculation throughput of the CPU and the resources of the FPGA equipment cannot be reasonably utilized in the current dynamic configuration scheme in the related technology are solved, and the effect of ensuring that the resources of the FPGA equipment are reasonably utilized in the query acceleration process of the database is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of heterogeneous computing technology, and in particular to a computing resource configuration method and apparatus for an FPGA device and an FPGA device. Background Art

[0002] In the related art, the database system will introduce heterogeneous computing devices represented by FPGA (Field Programmable Gate Arry) to process specific query operators or query pipelines. In order to enable the FPGA accelerator to better adapt to different query scenarios, some database systems adopt dynamic configuration strategies to manage single FPGA devices. However, the dynamic configuration scheme has the following problems: 1) The current dynamic configuration scheme only configures the fixed-scale computing logic of a specific operator to the FPGA accelerator in real time according to the query requirements, but ignores the computing throughput of other operators on the CPU (Central Processing Unit) side, resulting in the mismatch between the throughput of the FPGA device and the computing throughput of the CPU, and the FPGA device resources cannot be reasonably utilized; 2) In the current dynamic configuration, additional time overhead needs to be introduced during the configuration of the FPGA device and the use of the FPGA device. Therefore, the current dynamic configuration scheme is suitable for extremely complex query processing scenarios (i.e., minute level), but for some millisecond-level or even second-level queries, the configuration time overhead may cause the FPGA query accelerator to fail to perform the acceleration task in time, thereby offsetting the acceleration benefits of the FPGA device, and even causing negative benefits. Summary of the invention

[0003] The embodiments of the present invention provide a method and apparatus for configuring computing resources of a programmable array logic device, so as to at least solve the problem that in the current dynamic configuration scheme in the related art, the throughput of the FPGA device does not match the CPU computing throughput, and the FPGA device resources cannot be reasonably utilized.

[0004] According to one embodiment of the present invention, a computing resource configuration method for a programmable array logic device is provided, which is applied to the host side of a database, and includes: generating a heterogeneous query execution plan according to a user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators; based on the computing throughput of processing non-heterogeneous operators adjacent to the heterogeneous operators and the computing throughput that can be provided by a single resource block in a programmable array logic FPGA device, determining a first number of resource blocks required to be configured to execute the heterogeneous operators.

[0005] According to another embodiment of the present invention, a computing resource configuration method for a programmable array logic device is provided, which is applied to the programmable array logic FPGA side of a database, including: configuring a first number of idle resource blocks in a block resource pool according to the heterogeneous operators carried in the acceleration task and the first number; wherein the first number is determined by the computing throughput of the host side processing the non-heterogeneous operators adjacent to the heterogeneous operators and the computing throughput that can be provided by the single resource block.

[0006] According to another embodiment of the present invention, a computing resource configuration of a programmable array logic device is provided, including: a generation module, used to generate a heterogeneous query execution plan according to a user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators; a determination module, used to determine a first number of resource blocks required to be configured to execute the heterogeneous operator based on the computing throughput of processing non-heterogeneous operators adjacent to the heterogeneous operator and the computing throughput that can be provided by a single resource block in the programmable array logic FPGA device.

[0007] According to another embodiment of the present invention, a programmable array logic device is provided, comprising: a configuration module, used to configure a first number of idle resource blocks in a block resource pool according to heterogeneous operators carried in an acceleration task and a first number; wherein the first number is determined by the computing throughput of non-heterogeneous operators adjacent to the heterogeneous operators processed by the host side and the computing throughput that can be provided by the single resource block.

[0008] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0009] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0010] Through the above-mentioned embodiment of the present invention, the number of resource blocks required to be configured on the FPGA side to execute the heterogeneous operator takes into account the computational throughput of processing non-heterogeneous operators and the computational throughput that can be provided by a single resource block in the FPGA device, wherein the computational throughput of processing non-heterogeneous operators represents the resources required on the host side, so that the configuration of the host side of the database can be matched with that on the FPGA side, avoiding excessive or low use of FPGA onboard resources, and ensuring reasonable resource utilization; and according to the computational throughput that can be provided by a single resource block in the FPGA device, the computational logic scale of the heterogeneous operator can be flexibly adjusted based on demand, avoiding the problem of insufficient resource use or resource limitation. Therefore, the problem that the throughput of the FPGA device does not match the CPU computational throughput and the FPGA device resources cannot be reasonably utilized in the current dynamic configuration scheme in the related art can be solved, so as to achieve the effect of ensuring that the database reasonably utilizes the FPGA device resources during the query acceleration process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a hardware structure block diagram of a computer terminal for running a computing resource configuration method of a programmable array logic device according to an embodiment of the present invention;

[0012] Figure 2 is a structural block diagram of a heterogeneous database system according to an embodiment of the present invention;

[0013] Figure 3 is a flow chart of a method for configuring computing resources of a programmable array logic device according to an embodiment of the present invention;

[0014] Figure 4 is a flow chart of a method for configuring computing resources of a programmable array logic device according to an embodiment of the present invention;

[0015] Figure 5 is a structural block diagram of a computing resource configuration device according to an embodiment of the present invention;

[0016] Figure 6 is a block diagram of a programmable array logic device according to an embodiment of the present invention;

[0017] Figure 7 is a structural block diagram of a common heterogeneous database system according to an embodiment of the present invention;

[0018] Figure 8 is a flow chart of a method for configuring computing resources based on query load according to an embodiment of the present invention;

[0019] Fig. 9 It is a schematic diagram of a method for configuring computing resources based on query load according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0022] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal for running a computing resource configuration method for a programmable array logic device according to an embodiment of the present invention. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor or a programmable logic device) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 for communication functions and an input and output device 108. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0023] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the computing resource configuration method of the programmable array logic device in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0024] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0025] The embodiment of the present invention also provides a heterogeneous database system. Figure 2 is a structural block diagram of a heterogeneous database system according to an embodiment of the present invention. Figure 2 As shown, the heterogeneous database system includes two parts: a database host side (hereinafter referred to as the host side) and an FPGA query accelerator side (hereinafter referred to as the FPGA side), and the two parts communicate through a PCIe bus.

[0026] The database host contains five modules: query parsing module, execution plan generation module, plan processing module, configuration management module, and (configuration) cost analysis module. The query parsing module, execution plan generation module, and plan processing module all belong to the query processing engine in the original database, and are responsible for parsing the query requests input by users, generating the optimal query execution plan, and advancing query processing according to the query execution plan.

[0027] The execution plan generation module is also used to output a heterogeneous execution plan, which contains heterogeneous query operators that need to be processed by the FPGA query accelerator.

[0028] The plan processing module is used to process non-heterogeneous query operators, while heterogeneous query operators are handed over to the FPGA query accelerator.

[0029] The configuration management module is used to analyze the query processing throughput on the host side, that is, the number of working threads used for query processing on the host side, when implementing the block dynamic configuration mechanism based on query load, and provide the computing logic configuration scale on the FPGA query accelerator side. The computing logic configuration scale is the number of resource blocks required to execute heterogeneous operators, so that the computing throughput on the FPGA query accelerator side can match the query throughput on the database host side, thereby avoiding excessive or low usage of FPGA onboard resources, and then ensuring reasonable resource utilization.

[0030] The configuration cost analysis module is used to analyze whether the block dynamic configuration of the query load will cause additional query waiting, that is, additional time overhead; if the query waiting time for successful configuration is greater than the benefit of the FPGA acceleration operator, it is a negative benefit, and the configuration should be abandoned and the heterogeneous operator should be handed over to the CPU for processing. Otherwise, the block configuration task will be sent to the FPGA query accelerator side.

[0031] The FPGA device on the FPGA query accelerator side contains three modules: a block resource pool, a logic library, and a configuration control terminal.

[0032] The block resource pool is used to divide the reconfigurable onboard computing resources in the FPGA query accelerator into multiple resource blocks (Chunks), so that it has the ability to process the maximum data.

[0033] like Figure 2 As shown in the figure, an FPGA device contains multiple IO blocks (IO Blocks, IOBs) for implementing the interaction between the FPGA query accelerator and the host. Compared with the abundant computing resources, the IO resources in the FPGA are relatively limited, so its onboard computing resources are evenly divided into multiple Chunks according to the number of IOBs. Each Chunk and the adjacent IOBs form a configurable logic unit for implementing specific computing logic.

[0034] The logic library is used to store different types of logic configuration schemes in the onboard flash memory so that the computing logic can be quickly configured on the resource blocks.

[0035] The configuration control end is used to find the idle resource block (Chunk) when receiving the configuration request from the database host side, and complete the corresponding computing logic configuration so that it can process the corresponding heterogeneous query operator.

[0036] In an embodiment of the present invention, a method for configuring computing resources of a programmable array logic device running in the above-mentioned heterogeneous database system is also provided. Specifically, the method is applied to the host side of the database. Figure 3 is a flow chart of a method for configuring computing resources of a programmable array logic device according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0037] Step S302, generating a heterogeneous query execution plan according to the user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators;

[0038] In step S302 of this embodiment, a heterogeneous query execution plan is generated according to a user's query request, including: converting the query request into a corresponding query algebraic expression; and generating the query execution plan based on the query algebraic expression.

[0039] The query request includes a SQL (Structured Query Language) request.

[0040] In this embodiment, the query parsing module on the host side sends the converted query algebraic expression to the execution plan generation module to generate a heterogeneous query plan in the execution plan generation module, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators, wherein the heterogeneous operators will be processed by the FPGA side of the database, while the non-heterogeneous operators will be executed on the host side.

[0041] In one embodiment, a fixed number of threads are allocated on the host side to execute non-heterogeneous operators.

[0042] Step S304, determining a first number of resource blocks required to be configured to execute the heterogeneous operator based on the computing throughput of processing non-heterogeneous operators adjacent to the heterogeneous operator and the computing throughput that can be provided by a single resource block in a field programmable array logic (FPGA) device.

[0043] In this embodiment, the host side and the FPGA side are respectively configured with matching resources to ensure the same processing progress on both sides, avoid over- or under-utilization of FPGA onboard resources, and thus ensure reasonable resource utilization. Therefore, the number of resource blocks required to execute the heterogeneous operator needs to be determined based on the computational throughput of processing the above-mentioned non-heterogeneous operator, which is the resources required by the host side.

[0044] After step S304 of this embodiment, the method further includes: determining the configuration time for configuring all resource blocks required to execute the heterogeneous operators on the FPGA device based on the first quantity and the time for configuring a single resource block; and determining that the configuration time affects the timely execution of the heterogeneous operators when the configuration time is greater than the total execution time of all predecessor operators of the heterogeneous operators.

[0045] In one embodiment, when the configuration time affects the timely execution of the heterogeneous operator, the method further includes: determining a first time to execute the heterogeneous operator on the host side and a second time to execute the heterogeneous operator on the FPGA device; when the difference between the second time and the first time is greater than or equal to the difference between the configuration time and the total execution time, encapsulating the heterogeneous operator and the first number into an acceleration task and sending it to the FPGA device.

[0046] In step S304 of this embodiment, a first number of resource blocks required to be configured to execute the heterogeneous operator is determined, including: when a second number of resource blocks with the same computing logic as the heterogeneous operator has been configured on the FPGA side, it is only necessary to additionally configure a third number of the resource blocks on the FPGA device, wherein the value of the third number is the difference between the first number and the second number.

[0047] Through the above steps, the number of resource blocks required to be configured on the FPGA side to execute the heterogeneous operator takes into account the computational throughput of processing non-heterogeneous operators and the computational throughput that can be provided by a single resource block in the FPGA device, wherein the computational throughput of processing non-heterogeneous operators represents the resources required on the host side, so that the configuration of the host side of the database can be matched with that on the FPGA side, avoiding excessive or low use of FPGA onboard resources, and ensuring reasonable resource utilization; and according to the computational throughput that can be provided by a single resource block in the FPGA device, the computational logic scale of the heterogeneous operator can be flexibly adjusted based on demand, avoiding insufficient resource use or resource limitation. Therefore, the problem that the throughput of the FPGA device does not match the CPU computational throughput and the FPGA device resources cannot be reasonably utilized in the current dynamic configuration scheme in the related technology can be solved, so as to ensure that the database reasonably utilizes the FPGA device resources during the query acceleration process.

[0048] In this embodiment, a method for configuring computing resources of a programmable array logic device running in the above-mentioned heterogeneous database system is provided. Specifically, the method is applied to the FPGA side of the database.

[0049] In one embodiment, the FPGA side of the database has one and only one FPGA query accelerator connected to the host side of the database in the above embodiment through a PCIe bus.

[0050] Figure 4 is a flow chart of a method for configuring computing resources of a programmable array logic device according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0051] Step S402, according to the heterogeneous operators carried in the acceleration task and the first quantity, configure a first number of idle resource blocks in the block resource pool; wherein the first number is determined by the computing throughput of the non-heterogeneous operators adjacent to the heterogeneous operators processed by the host side and the computing throughput that the single resource block can provide.

[0052] Before step S402 of this embodiment, the method further includes: dividing the computing resources in the FPGA device into a plurality of resource blocks according to the number of input blocks or output blocks included in the FPGA device.

[0053] After step S402 of this embodiment, the method further includes: configuring the logic code corresponding to the heterogeneous operator in the logic library to the resource block to obtain a logic block for executing the heterogeneous operator.

[0054] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for a terminal device (which can be a computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0055] In this embodiment, a computing resource configuration device for a programmable array logic device is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0056] Figure 5 is a structural block diagram of a computing resource configuration device of a programmable array logic device according to an embodiment of the present invention. Figure 5 As shown, the device is located at the host side of the database, and includes: a generating module 51 and a determining module 52.

[0057] The generation module 51 is used to generate a heterogeneous query execution plan according to the user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators; the generation module 51 is functionally equivalent to the execution plan generation module of the above example.

[0058] The determining module 52 is used to determine the first number of resource blocks required to be configured to execute the heterogeneous operator based on the computing throughput of processing the non-heterogeneous operator adjacent to the heterogeneous operator and the computing throughput that can be provided by a single resource block in the field programmable array logic FPGA device. The determining module 52 is functionally equivalent to the configuration management module in the above embodiment.

[0059] Figure 6 is a block diagram of a programmable array logic device according to an embodiment of the present invention. Figure 6 As shown, the programmable logic device includes:

[0060] The configuration module 61 is used to configure a first number of idle resource blocks in the block resource pool according to the heterogeneous operators and the first number carried in the acceleration task; wherein the first number is determined by the computing throughput of the non-heterogeneous operators adjacent to the heterogeneous operators processed by the host side and the computing throughput that can be provided by the single resource block. The configuration module 61 is functionally equivalent to the configuration control end in the above embodiment.

[0061] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0062] To facilitate the understanding of the technical solution provided by the present invention, a detailed description will be given below in conjunction with embodiments of specific scenarios.

[0063] Introducing FPGA in the database can alleviate the computing pressure on the CPU to a certain extent and expand the computing power of the database system. FPGA is a field programmable gate array device, which is developed on the basis of programmable devices such as PAL. It has the programmability of CPU and GPU (Graphics Processing Unit) devices, and the high density, large capacity and low power consumption of ASIC (Application Specific Integrated Circuit) devices. Therefore, it is widely used in database systems as an efficient query accelerator.

[0064] However, in the existing database, the configuration management method of the FPGA query accelerator is relatively simple, which makes the onboard resources of the FPGA device under-utilized or over-utilized, and also ignores the time overhead of the accelerator management configuration. In this regard, the embodiment of the present invention expands the management configuration method of the FPGA query accelerator in the database, so that it has the ability to dynamically adjust according to the query load, thereby ensuring the reasonable use of FPGA device resources, and increasing the consideration of configuration time, thereby providing better query acceleration performance.

[0065] In order to enable the FPGA query accelerator to support specific computing tasks, the FPGA query accelerator also needs to be configured and managed according to a specific scheme, which can be roughly divided into a static configuration scheme and a dynamic configuration scheme. Figure 7 is a structural block diagram of a common heterogeneous database system according to an embodiment of the present invention. Figure 7As shown, the FPGA query accelerator of the database system includes one or more FPGA query accelerators, which are introduced into the database system through the PCIe bus and undertake the simple logic and high parallel computing tasks allocated by the CPU (for example, sorting and connection operators in the database). When the FPGA query accelerator completes the computing task, the result it generates needs to be returned to the CPU processor for unified processing.

[0066] In the static configuration scheme, the FPGA accelerator will be pre-written with a variety of computing logics to support several fixed query operators in the database (for example, aggregation operators and join operators). In other words, when the FPGA query accelerator is introduced into the database system, its internal computing logic will not be changed. Each computing logic on the FPGA device will occupy a fixed onboard resource (for example, CLB and registers, etc.). Therefore, if the relational database only uses one FPGA query accelerator, in order to adapt to different query scenarios, a large number of computing logics need to be implemented on one FPGA device, and each computing logic can only get lower onboard resources, making it difficult to provide better acceleration performance. When the database uses multiple FPGA accelerators, only one computing logic will be implemented on one FPGA device, so that different query computing scenarios or different heterogeneous query operators can be directly processed by different FPGA devices. In order to meet the ever-changing query scenarios, heterogeneous database systems need to introduce a large number of FPGA devices, which will increase system costs.

[0067] Dynamic configuration strategies are used to manage single FPGA devices, which can make FPGA accelerators better adapt to different query scenarios. Under the dynamic configuration strategy, the operators or pipelines that need to be accelerated in the query will be converted into specific calculation logic codes (for example, Verilog) and written to the FPGA query accelerator in real time. After the calculation logic is written, the corresponding query operator or pipeline can be handled by the FPGA query accelerator.

[0068] In an embodiment of the present invention, a dynamic configuration strategy of an FPGA query accelerator based on load perception is provided. Figure 2 In the heterogeneous database system, resources are dynamically configured based on the block dynamic configuration mechanism of query load and the dynamic configuration cost model of query load.

[0069] like Figure 2 As shown, in this dynamic configuration strategy, there is only one FPGA query accelerator in the heterogeneous database system, and it is connected to the database host through the PCIe bus, thus forming a CPU-FPGA heterogeneous database system.

[0070] At the same time, similar to the traditional database system, the query parsing module and the execution plan generation module are both running on the database host side, and the generated execution plan should include the execution cost estimate of each query operator (including the amount of data processed, execution time, and execution throughput). The difference is that in the query processing process of this embodiment, the database system will "push down" some query operators to the FPGA query accelerator side and hand them over to the corresponding computing logic for processing. As for the FPGA query accelerator side, it should have reconfigurable onboard resources inside, so as to support the dynamic reconfiguration of computing logic.

[0071] In this embodiment, the FPGA device also has a relatively large HBM space and flash memory space, which are used to store temporary data and logic codes respectively.

[0072] Specifically, the dynamic configuration strategy includes:

[0073] (1) Based on the block dynamic configuration mechanism of query load, the computing resources (Reconfigurable Resources) in a single FPGA device are divided into multiple blocks (Chunks) to ensure reasonable utilization of FPGA device resources. Among them, a Chunk can be used as a processing unit (Processing Unit) in the computing logic and has a fixed computing throughput. When the throughput of the CPU on the database host side to process the query load is known, the configuration mechanism can calculate the number of matching block processing units on the FPGA side, and then configure the computing logic that matches the throughput, thereby achieving reasonable utilization of FPGA device resources. At the block management granularity, the configuration strategy can also directly reuse existing idle and suitable block processing units (for example: if there is an idle Chunk, the Chunk has been configured with computing logic before, and the computing logic is the same as the computing logic to be processed, then the Chunk can be directly used for processing), reducing the scale of configuration and the time of configuration, thereby minimizing the impact of configuration time on query performance.

[0074] (2) Based on the dynamic configuration cost model of the query load, the configuration time of the FPGA query accelerator is analyzed, and it is determined whether the configuration time will affect the timely processing of the acceleration task, so as to avoid the time overhead of dynamic configuration bringing negative benefits to the query.

[0075] When the accelerated task cannot be processed in time due to configuration time, the dynamic configuration cost model further analyzes whether the benefits of task acceleration can offset the extra waiting time, and further decides whether the dynamic reconfiguration mechanism should be executed.

[0076] Figure 8 is a flow chart of a method for configuring computing resources based on query load according to an embodiment of the present invention. Figure 8As shown, the method comprises the following steps:

[0077] Step S802: Based on the received SQL request input by the user, the query parsing module on the database host side converts the SQL statement into a corresponding query algebraic expression, and sends the query algebraic expression to the plan generation module;

[0078] Step S804: the plan generation module generates a heterogeneous query execution plan according to the query algebraic expression, and the query execution plan includes heterogeneous query operators and non-heterogeneous query operators; wherein the heterogeneous query operators are functionally equivalent to the heterogeneous operators in the above embodiment, and the non-heterogeneous query operators are non-heterogeneous query operators;

[0079] Step S806, the plan processing module sends the heterogeneous query operator to the FPGA query accelerator for processing;

[0080] For example, Fig. 9 The aggregation operator Agg in is a heterogeneous query operator suitable for FPGA query accelerator processing, and Scan and Proj are non-heterogeneous query operators.

[0081] For non-heterogeneous query operators, the host side allocates a fixed number of threads to execute non-heterogeneous operators. For example, Scan and Proj are executed by 4 worker threads.

[0082] Step S808: After the heterogeneous execution plan is generated, the configuration management module on the database host side determines the number of resource blocks required to process the heterogeneous query operators.

[0083] Specifically, the number of resource blocks required by the heterogeneous query operator is obtained by dividing the computational throughput of adjacent non-heterogeneous operators (eg, scan or Proj) in the execution plan by the computational throughput that can be provided by a single resource block on the FPGA side.

[0084] At the same time, in order to ensure that the processing progress on the database host side and the FPGA query accelerator side is the same, both sides need to maintain equal resources, for example: Fig. 9 As shown, when the processing capacity of the database host side is known to be 4 threads, the query calculation logic on the FPGA side only needs to use 2 resource blocks to provide similar throughput, that is, the host side throughput is twice that of a single resource block (i.e., Chunk) of the FPGA.

[0085] In this embodiment, in order to avoid the time overhead of dynamic configuration from bringing negative benefits to the query, the database host side also analyzes the actual configuration scale of the FPGA query accelerator.

[0086] For example, Fig. 9In the FPGA query accelerator side, there is already one idle resource block configured with aggregation computing logic, so the accelerator actually only needs to configure aggregation computing logic for one more resource block.

[0087] Step S810: The configuration cost module on the database host side determines the actual configuration time of the logic block on the FPGA query accelerator side, and determines whether the actual configuration time affects the timely execution of the heterogeneous operators.

[0088] Specifically, in order to avoid the time overhead of dynamic configuration from bringing negative benefits to the query, the configuration cost module on the database host side will multiply the number of logic blocks (i.e., resource blocks with logic set) actually required to be configured by the configuration time of a single logic block to obtain the actual configuration time T_r. If the actual configuration time T_r is greater than the sum of the execution time T_s of all predecessor operators (such as scan) of the heterogeneous operator, it is considered that the configuration time affects the timely execution of the heterogeneous operator.

[0089] Step S812, when the configuration time affects the timely execution of heterogeneous operators, the configuration cost model determines whether the actual configuration time brings negative benefits to the entire query based on the actual configuration time, the time for executing heterogeneous operators on the database host side, and the time for executing heterogeneous operators on the FPGA side.

[0090] Specifically, the configuration cost model analyzes the time T_c for executing heterogeneous operators on the database host side and the time T_f for executing heterogeneous operators on the FPGA side. If the acceleration benefit T_f-T_c can be less than the additional waiting time T_r-T_s, it is considered that the configuration time brings negative benefits to the entire query and the configuration should be abandoned. On the contrary, the cost model believes that heterogeneous operators and their corresponding actual configuration scales should be encapsulated into acceleration tasks and sent to the FPGA query accelerator side.

[0091] Step S814, when the block configuration module on the FPGA query accelerator side receives the configuration task, it will select an idle resource block from the block resource pool and configure the corresponding logic code in the logic library to the resource block. After the configuration is completed, the configuration control end will feedback the configuration completion to the host side.

[0092] Through the above-mentioned embodiments of the present invention, the original FPGA-based query acceleration method is expanded, and a dynamic configuration solution based on query load is provided to ensure the rational use of FPGA device resources during the acceleration process, and to minimize the impact of configuration time on query time, thereby improving query performance.

[0093] With the continuous emergence of cloud-native databases and the continuous development of heterogeneous device virtualization technology, the load-aware dynamic configuration strategy in the embodiment of the present invention can also be further applied to the business scenarios of cloud databases.

[0094] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0095] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0096] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0097] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0098] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0099] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A computing resource configuration method for a programmable array logic (FPGA) device, applied to the host side of a database, characterized in that: include: Generate a heterogeneous query execution plan according to a user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators; Based on the computational throughput of processing non-heterogeneous operators adjacent to the heterogeneous operators and the computational throughput that can be provided by a single resource block in a field programmable array logic (FPGA) device, a first number of resource blocks required to be configured to execute the heterogeneous operators is determined.

2. The method according to claim 1, characterized in that Generate heterogeneous query execution plans based on user query requests, including: Converting the query request into a corresponding query algebraic expression; The query execution plan is generated based on the query algebraic expression.

3. The method according to claim 1, characterized in that After determining a first number of resource blocks required to be configured to execute the heterogeneous operator, the method further includes: Determine, based on the first quantity and the time to configure a single resource block, the configuration time of all resource blocks required to execute the heterogeneous operators on the FPGA device; In a case where the configuration time is greater than the total execution time of all predecessor operators of the heterogeneous operator, it is determined that the configuration time affects the timely execution of the heterogeneous operator.

4. The method according to claim 3, characterized in that In the case where the configuration time affects the timely execution of the heterogeneous operators, the method further includes: Determining a first time to execute the heterogeneous operator on the host side and a second time to execute the heterogeneous operator on the FPGA device; When the difference between the second time and the first time is greater than or equal to the difference between the configuration time and the total execution time, the heterogeneous operator and the first quantity are packaged into an acceleration task and sent to the FPGA device.

5. The method according to claim 1, characterized in that Determining a first number of resource blocks required to be configured to execute the heterogeneous operator includes: In the case where a second number of resource blocks with the same computing logic as the heterogeneous operator has been configured on the FPGA side, it is only necessary to additionally configure a third number of the resource blocks on the FPGA device, wherein the value of the third number is the difference between the first number and the second number.

6. A method for configuring computing resources of a programmable array logic device, applied to the programmable array logic FPGA side of a database, characterized in that: include: According to the heterogeneous operators and the first quantity carried in the acceleration task, a first number of idle resource blocks are configured in the block resource pool; wherein the first number is determined by the computing throughput of the non-heterogeneous operators adjacent to the heterogeneous operators processed by the host side and the computing throughput that can be provided by a single resource block.

7. The method according to claim 6, characterized in that According to the heterogeneous operators and the first quantity carried in the acceleration task, before configuring the first quantity of idle resource blocks in the block resource pool, the method further includes: According to the number of input blocks or output blocks contained in the FPGA device, the computing resources in the FPGA device are divided into a plurality of resource blocks.

8. The method according to claim 6, characterized in that After configuring a first number of idle resource blocks in the block resource pool, the method further includes: The logic code corresponding to the heterogeneous operator in the logic library is configured on the resource block to obtain a logic block for executing the heterogeneous operator.

9. A computing resource configuration device for a field programmable array logic (FPGA) device, located on the host side of a database, characterized in that: include: A generation module, used to generate a heterogeneous query execution plan according to a user's query request, wherein the heterogeneous query plan includes heterogeneous operators and non-heterogeneous operators; A determination module is used to determine a first number of resource blocks required to be configured to execute the heterogeneous operator based on a computing throughput of processing non-heterogeneous operators adjacent to the heterogeneous operator and a computing throughput that can be provided by a single resource block in a field programmable array logic (FPGA) device.

10. A programmable array logic device FPGA, characterized in that: include: A configuration module is used to configure a first number of idle resource blocks in a block resource pool according to the heterogeneous operators and the first number carried in the acceleration task; wherein the first number is determined by the computing throughput of the non-heterogeneous operators adjacent to the heterogeneous operators processed by the host side and the computing throughput that a single resource block can provide.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 5 are implemented, or the steps of the method described in any one of claims 6 to 8 are implemented.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the processor implements the steps of the method described in any one of claims 1 to 5, or implements the steps of the method described in any one of claims 6 to 8.

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