Chip assembly, communication method and computer program product

Abstract

The invention discloses a chip assembly, a communication method and a computer program product. The chip assembly comprises an interface bus; and at least two bare chips, each bare chip is provided with a corresponding address space segment, and the signal end of each bare chip is connected to the interface bus. According to the chip assembly, all bare chips are mounted on the same interface bus through design, and each bare chip is addressed into different address space segments, so that the purpose of distinguishing different bare chips through the address space segments can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip component, a communication method and a computer program product. Background Art

[0002] In the related art, in order to increase the capacity of the memory chip, the chip is re-invested or multiple small-capacity bare chips are sealed together, and different bare chips are operated through chip select signals. However, this design requires users to modify the circuit and code when upgrading the memory chip, and the compatibility between software and hardware is poor. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a chip assembly, which mounts all bare chips on the same interface bus by design and addresses each bare chip with a different address space segment, so as to achieve the purpose of distinguishing different bare chips by address space segments.

[0004] A second objective of the present invention is to provide a communication method.

[0005] A third object of the present invention is to provide a computer program product.

[0006] In order to solve the above problems, a first embodiment of the present invention proposes a chip component, including: an interface bus; at least two bare chips, each bare chip is provided with a corresponding address space segment, and the signal end of each bare chip is connected to the interface bus.

[0007] According to the chip component of the embodiment of the present invention, the signal end of each bare chip is connected to the interface bus, and each bare chip is provided with a corresponding address space segment, that is, all bare chips are mounted on the same interface bus, and each bare chip is addressed with a different address space segment, so as to achieve the purpose of distinguishing different bare chips by the address space segment. At the same time, based on the above design, when the chip component is upgraded, there is no need for the host side to modify the hardware interface or software code, and it is only necessary to mount the added bare chip signal end on the interface bus, thereby increasing the storage chip capacity without changing the original external interface and software protocol.

[0008] In some embodiments, each bare chip includes a memory unit and a register unit, and the address space segment of each bare chip includes a first address space segment and a second address space segment. The address code of the memory unit is the first address space segment, and the address code of the register unit is the second address space segment.

[0009] In some embodiments, each bare chip further includes a shared unit, the address space segment of each bare chip further includes a third address space segment, the address code of the shared unit is the third address space segment, and the shared unit can be mapped to the register unit based on the third address space segment.

[0010] In some embodiments, each bare chip is configured with a corresponding index value, and the index value is used to locate the position of each bare chip.

[0011] In some embodiments, the type of the interface bus is Standard SPI, QSPI, OPI or HexSPI.

[0012] A second aspect of the present invention proposes a communication method for the chip component of the above embodiment, the method comprising: receiving a first access operation instruction through the interface bus, the first access operation instruction comprising at least access address information and read / write operation information; determining a target bare chip to be accessed according to the access address information; and accessing the target bare chip according to the read / write operation information.

[0013] According to the communication method of an embodiment of the present invention, all bare chips are mounted on the same interface bus based on the design, and each bare chip is addressed with a different address space segment, so that each bare chip is accessed differently through the first access operation instruction received through the interface bus, thereby achieving the purpose of distinguishing different bare chips through address space segments.

[0014] In some embodiments, the method further includes: determining that the access address information is a shared unit of the target bare chip; and accessing the shared unit of the target bare chip according to the read / write operation information.

[0015] In some embodiments, accessing the shared unit of the target bare chip according to the read / write operation information includes: accessing the shared unit of the target bare chip according to the read operation information to perform a read operation on the register unit of the target bare chip; accessing the shared unit of the target bare chip according to the write operation information to perform a write operation on the register units of all bare chips.

[0016] In some embodiments, before accessing the shared unit of the target bare chip according to the read operation information, the method further includes: setting the access flag position of the target bare chip to 1 according to the access address information, and setting the access flag positions of other bare chips except the target bare chip to 0.

[0017] In some embodiments, the method further includes: receiving a second access operation instruction through the interface bus, the second access operation instruction at least including an index value to be accessed; and determining a target bare chip to be accessed according to the index value to be accessed.

[0018] A third aspect of the present invention provides a computer program product, including a computer program, which implements the communication method described in the above embodiment when executed by a processor.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic diagram of interface bus connection of a chip assembly according to an embodiment of the present invention; Figure 2 is a schematic diagram of a bare chip accessed by address space segments according to an embodiment of the present invention; Figure 3 is a schematic diagram of an access flag position of a target bare chip according to an embodiment of the present invention; Figure 4 is a schematic diagram of accessing a bare chip by an index value according to an embodiment of the present invention; Figure 5 is a flow chart of a communication method according to an embodiment of the present invention; Figure 6 is a flow chart of a communication method according to another embodiment of the present invention; Figure 7 is a flow chart of a communication method according to another embodiment of the present invention.

[0021] Reference numerals Chip assembly 100; Interface bus 10; bare chip 20; Memory unit 1; register unit 2; shared unit 3. DETAILED DESCRIPTION

[0022] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0023] In order to solve the above problems, a first embodiment of the present invention proposes a chip component, which is designed to mount all bare chips on the same interface bus and address each bare chip with a different address space segment, so as to achieve the purpose of distinguishing different bare chips through address space segments.

[0024] The following describes a chip assembly according to an embodiment of the present invention with reference to the accompanying drawings. Figure 1 As shown, the chip assembly 100 includes an interface bus 10 and at least two bare chips 20 .

[0025] Each bare chip 20 has a corresponding address space segment, and the signal end of each bare chip 20 is connected to the interface bus 10. It should be noted that the number of bare chips 20 can be two, three or more, which can be set according to actual conditions and is not specifically limited here.

[0026] Specifically, in the related art, when users upgrade chip components, they only want to increase their overall capacity without changing other parts, for example, without changing the hardware interface or software code of the chip components. In order to solve the above problem, in this application, multiple bare chips 20 are connected to the interface bus 10 at the same time, that is, in the chip design stage, all bare chips 20 are mounted on the same interface bus 10, such as Figure 1 As shown, the signal terminals of all bare chips 20, such as the chip select signal / Reset signal, are short-circuited and connected to the interface bus 10, and each bare chip 20 is accessed differently by addressing to different address space segments. With this design, when the chip assembly 100 is sealed later, the external interface can be kept unchanged. In addition, for the upgrade of memory chips, especially for increasing the overall capacity of the chip, multiple completely independent bare chips 20, namely memory dies, are sealed together without modifying the chip digital logic and memory part design. At the same time, the compatibility of the original chip external interface and software protocol is maintained. The solution is flexible, simple to implement, low cost, and good software and hardware compatibility. At the same time, when the host communicates with different bare chips, the address space segments are used to distinguish and access different bare chips 20, and there will be no problem of switching the communication interface when accessing different bare chips due to the use of chip select signals to operate different bare chips.

[0027] In some embodiments, for parts that do not want to be distinguished by address, they can be accessed in a mutually exclusive multiplexing manner.

[0028] According to the chip assembly 100 of the embodiment of the present invention, the signal end of each bare chip is connected to the interface bus, and each bare chip is provided with a corresponding address space segment, that is, all bare chips are mounted on the same interface bus, and each bare chip is addressed with a different address space segment, so as to achieve the purpose of distinguishing different bare chips by the address space segment. At the same time, based on the above design, when the chip assembly is upgraded, there is no need for the host to modify the hardware interface or software code, and only the added bare chip signal end needs to be mounted on the interface bus, thereby increasing the storage chip capacity without changing the original external interface and software protocol.

[0029] In some embodiments, Figure 2 As shown, each bare chip 20 includes a memory unit 1 and a register unit 2 .

[0030] The address space segment of each bare chip 20 includes a first address space segment and a second address space segment, the address code of the memory unit 1 is the first address space segment, and the address code of the register unit 2 is the second address space segment. In other words, the memory unit 1 and the register unit 2 inside the bare chip 20 are uniformly addressed, that is, the address space segment is used as the ID of the bare chip, and the address space segments allocated to different bare chips 20 are different. Each bare chip 20 has a unique ID, and its own address space segment is confirmed by the ID, and the address space segments allocated to the memory unit 1 and the register unit 2 inside each bare chip 20 are also different.

[0031] Specifically, the bare chip 20 accesses the memory unit 1 through the first address space segment, and accesses the register unit 2 through the second address space segment. Each bare chip 20 has its own unique first address space segment and second address space segment, so that multiple bare chips 20 can be distinguished by different first address space segments and second address space segments.

[0032] Exemplarily, the chip assembly 100 includes two bare chips 20, the two bare chips 20 are Die1 and Die2. Figure 2As shown, the first address space segment of Die1 is Space1, and the second address space segment is Space2; the first address space segment of Die1 is Space4, and the second address space segment is Space5, that is, Die1 and Die2 can access their respective memory units 1 through Space1 / Space4 respectively, and when receiving the access address Space information sent on the interface bus 10, only if the address Space falls within the corresponding Die, the corresponding Die will reply; and Die1 and Die2 can access their respective register units 2 through Space2 / Space5 respectively, and when receiving the access register address Space information sent on the interface bus 10, only if the address Space falls within the corresponding Die, the corresponding Die will reply. Among them, this Space interface can be used to test each Die individually. Specifically, when the host side needs to perform a read or write operation on the bare chip 20, it will send access address information such as Space to ensure that the corresponding bare chip 20 is selected. When the chip component 100 receives the access information sent by the host side, if its address falls in Space1 or Space2, then Die1 should access the address information and perform the corresponding operation; if its address falls in Space4 or Space5, then Die2 should access the address information. Only when its address falls in the first address space segment or the second address space segment of a bare chip 20, the bare chip 20 responds to its access address information and performs the corresponding operation; otherwise, it has nothing to do with the bare chip 20.

[0033] In some embodiments, Figure 2 As shown, each bare chip 20 further includes a shared unit 3 .

[0034] The address space segment of each bare chip 20 also includes a third address space segment, the address code of the shared unit 3 is the third address space segment, and the shared unit 3 can be mapped to the register unit 2 based on the third address space. In other words, each bare chip 20 can also access the content of the register unit 2 through the shared unit 3.

[0035] Specifically, take two bare chips as an example. Figure 2 As shown, Die1 and Die2 can also access the register content through the shared unit 3. Based on this, when the host performs a write operation, no matter which bare chip is accessed, all Dies perform the write operation; and, refer to Figure 3As shown, there is an access flag bit (Flag) inside each Die. When a Die is accessed, its access flag bit will be set to 1, and the access flag bits of other Dies will be cleared to 0. Therefore, no matter what the situation is, only one Die's flag will always be set to 1, that is, it is always guaranteed that only one Die communicates with the host side, thereby preventing multiple Dies from operating the bus at the same time and causing communication conflicts. Based on this, when the host side performs a read operation, it is necessary to determine whether the access flag bit (Flag) is set to 1. If so, the data is replied, otherwise the operation is ignored. Among them, the access to the shared unit 3 will not affect the access flag.

[0036] Among them, the shared unit 3 of all dies is the same, and multiple dies can be operated simultaneously through the third address space segment of the shared unit 3, so as to facilitate users to carry out product development. In addition, after the system is powered on or reset, the initial value of the access flag bit is determined by the ID.

[0037] In some embodiments, each bare chip 20 is configured with a corresponding index value, and the index value is used to locate the position of each bare chip. That is, on the basis of distinguishing different bare chips by address space segments, a method of indexing access to different bare chips is added, that is, the memory unit 1, register unit 2 and / or shared unit 3 inside different bare chips are addressed in the manner of index space. For example, only register unit 2 can be addressed, or memory unit 1 and register unit 2 can be addressed, or memory unit 1, register unit 2 and shared unit 3 can be addressed, so that memory unit 1, register unit 2 and / or shared unit 3 can be accessed through access instructions with index value information.

[0038] For example, Figure 4 As shown, the register unit distinction method can be changed to an index value, which is equivalent to addressing the register unit separately, thereby achieving the purpose of not occupying the memory unit space. Based on this, the register units of different bare chips are accessed by adding a register access instruction and attaching index information. Specifically, referring to Table 1, when performing read and write operations on the memory unit of the bare chip, it can be implemented by an access instruction with address space segment information, that is, "instruction + address", and when performing read and write operations on the register unit of the bare chip, it can be implemented by an access instruction with index value information, that is, "instruction + index".

[0039] Table 1

[0040] In some embodiments, the type of the interface bus 10 is Standard SPI, QSPI, OPI or HexSPI.

[0041] Specifically, the type of the interface bus 10 is selected according to the specific situation. Different interface types correspond to different connection modes of the bare chip 20. For example, Figure 1 As shown, the interface type of the interface bus 10 is a QSPI connection mode.

[0042] A second aspect of the present invention provides a communication method, which is used in the chip assembly 100 of the above embodiment. Figure 5 As shown, it includes steps S1 to S3, and the specific steps are as follows.

[0043] Step S1: receiving a first access operation instruction through an interface bus, wherein the first access operation instruction at least includes access address information and read / write operation information.

[0044] Specifically, since the signal end of each bare chip is connected to the interface bus, the host end sends a first access operation instruction through the interface bus to uniformly operate all the bare chips, determine the corresponding bare chip through the access address information, and determine the operation type of the bare chip through the read / write operation information.

[0045] Step S2, determining the target bare chip to be accessed according to the access address information.

[0046] Specifically, the access address information should include address space segment information. Since the bare chip has its corresponding address space segment, the target bare chip to be accessed can be determined through the access address information, and the memory unit, register unit or shared unit of the target bare chip to be accessed can be determined through the address space segment information.

[0047] Step S3, accessing the target bare chip according to the read / write operation information.

[0048] Specifically, if the read / write operation information is read, the memory unit, register unit or shared unit of the target bare chip performs a read operation; if the read / write operation information is write, the memory unit, register unit or shared unit of the target bare chip performs a write operation.

[0049] According to the communication method of an embodiment of the present invention, all bare chips are mounted on the same interface bus based on the design, and each bare chip is addressed with a different address space segment, so that each bare chip is accessed differently through the first access operation instruction received through the interface bus, thereby achieving the purpose of distinguishing different bare chips through address space segments.

[0050] In some embodiments, the method of the present application further includes: determining that the access address information is a shared unit of the target bare chip; and accessing the shared unit of the target bare chip according to the read / write operation information.

[0051] Specifically, if it is determined that the access address information is a shared unit of the target bare chip, and the read / write operation information is read, the target bare chip performs a read operation on its shared unit 3; if the read / write operation information is write, the target bare chip performs a write operation on its shared unit 3. Further, based on the third address space segment, the shared unit 3 is mapped to the register unit 2, so as to perform a corresponding read / write operation on the register unit 2.

[0052] In some embodiments, the shared units of the target bare chip are accessed according to the read / write operation information, including accessing the shared units of the target bare chip according to the read operation information to perform a read operation on the register units of the target bare chip, that is, when the host side performs a read operation, only the register units of the target bare chip are read, and other bare chips ignore this operation; accessing the shared units of the target bare chip according to the write operation information to perform a write operation on the register units of all bare chips.

[0053] Specifically, when the host performs a write operation, no matter which bare chip is accessed, all dies perform the write operation. The specific steps are as follows: Figure 6 shown.

[0054] Step S4: the host initiates a write register operation.

[0055] Step S5: Based on the third address space segment, access the shared unit, namely the COMMON space, through the interface bus.

[0056] Step S6: All Dies receive the address information and data and perform a write operation.

[0057] In some embodiments, before accessing the shared unit of the target bare chip according to the read operation information, the method further includes: setting the access flag position of the target bare chip to 1 according to the access address information, and setting the access flag positions of other bare chips except the target bare chip to 0.

[0058] Specifically, by setting the access flag of the target bare chip to 1 and the access flags of other bare chips except the target bare chip to 0, it is ensured that there is always only one bare chip 20 with the access flag set to 1, that is, only one bare chip communicates with the host side, to avoid communication conflicts caused by multiple bare chips 20 operating the interface bus at the same time. When the host side accesses the shared unit 3 of the bare chip 20, the target bare chip will not be changed, that is, the access to the shared unit 3 will not affect the access flag.

[0059] Exemplary, reference Figure 3As shown in the figure, there is an access flag bit (Flag) inside each Die. When a Die is accessed, its access flag bit will be set to 1, and the access flag bits of other Dies will be cleared to 0. Therefore, no matter what the situation is, only one Die's access flag bit will be set to 1, that is, it is always guaranteed that only one Die communicates with the host side, thereby preventing multiple Dies from operating the bus at the same time and causing communication conflicts. Based on this, when the host side performs a read operation, it is necessary to determine whether the access flag bit (Flag) is set to 1. If so, the data is replied, otherwise the operation is ignored. For details, please refer to Figure 7 Steps shown.

[0060] Step S7: the host initiates a register read operation.

[0061] Step S8: Based on the third address space segment, access the shared unit, namely the COMMON space, through the interface bus.

[0062] Step S9: All Dies receive address information and data.

[0063] Step S10, determining whether the access flag is 1.

[0064] Step S11: If yes, then execute the read operation.

[0065] Step S12: If not, ignore this operation.

[0066] In some embodiments, the method of the present application further includes: receiving a second access operation instruction through an interface bus, the second access operation instruction at least including an index value to be accessed; determining a target bare chip to be accessed according to the index value to be accessed. That is, on the basis of distinguishing different bare chips by address space segments, a method of indexing access to different bare chips is added, that is, addressing memory units 1, register units 2 and / or shared units 3 inside different bare chips in an index space manner, thereby accessing memory units 1, register units 2 and / or shared units 3 through access instructions with index value information.

[0067] A third aspect of the present invention provides a computer program product, including a computer program, which implements the communication method of the above embodiment when executed by a processor.

[0068] In the description of this specification, any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code including one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0069] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0070] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0071] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0072] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0073] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0075] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip assembly, characterized in that: include: Interface bus; At least two bare chips are provided, each bare chip is provided with a corresponding address space segment, and the signal end of each bare chip is connected to the interface bus.

2. The chip assembly according to claim 1, characterized in that: Each bare chip includes a memory unit and a register unit, and the address space segment of each bare chip includes a first address space segment and a second address space segment. The address code of the memory unit is the first address space segment, and the address code of the register unit is the second address space segment.

3. The chip assembly according to claim 2, characterized in that: Each bare chip further includes a shared unit, the address space segment of each bare chip further includes a third address space segment, the address code of the shared unit is the third address space segment, and the shared unit can be mapped to the register unit based on the third address space segment.

4. The chip assembly according to any one of claims 1 to 3, characterized in that: Each bare chip is configured with a corresponding index value, and the index value is used to locate the position of each bare chip.

5. The chip assembly according to claim 1, characterized in that: The type of the interface bus is StandardSPI, QSPI, OPI or HexSPI.

6. A communication method, characterized in that: For the chip assembly according to any one of claims 1 to 5, the method comprises: receiving a first access operation instruction through the interface bus, wherein the first access operation instruction at least includes access address information and read / write operation information; Determine the target bare chip to be accessed according to the access address information; The target bare chip is accessed according to the read / write operation information.

7. The communication method according to claim 6, characterized in that: The method further comprises: Determining that the access address information is a shared unit of the target bare chip; The shared unit of the target bare chip is accessed according to the read / write operation information.

8. The communication method according to claim 7, characterized in that: Accessing the shared unit of the target bare chip according to the read / write operation information includes: Accessing the shared unit of the target bare chip according to the read operation information to perform a read operation on the register unit of the target bare chip; The shared unit of the target bare chip is accessed according to the write operation information to perform a write operation on the register units of all bare chips.

9. The communication method according to claim 8, characterized in that: Before accessing the shared unit of the target bare chip according to the read operation information, the method further includes: The access flag position of the target bare chip is set to 1 according to the access address information, and the access flag positions of other bare chips except the target bare chip are set to 0.

10. The communication method according to any one of claims 6 to 9, characterized in that: The method further comprises: receiving a second access operation instruction through the interface bus, wherein the second access operation instruction at least includes an index value to be accessed; The target bare chip to be accessed is determined according to the index value to be accessed.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the communication method described in any one of claims 6 to 10 is implemented.

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