Address detection module and method and control system
By introducing timing control circuits, reference voltage generation circuits and comparison circuits into the address detection module, the traditional multi-bit address detection scheme has solved the problem of multiple pins and large power consumption, and efficient and low-power address detection is achieved.
Patent Information
- Application Number
- CN202411579644.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-02-25
AI Technical Summary
The traditional multi-bit address detection scheme occupies many pins, consumes a large power and has a large circuit area.
An address detection module is provided, including a timing control circuit, a reference voltage generation circuit and a comparison circuit. A plurality of reference voltages are generated by a timing control signal, and sequentially compared with the input voltage, and output a comparison result to obtain the address of the slave device.
The circuit structure is simplified, the chip pins and circuit area is saved, the circuit power consumption is reduced, and the address detection is achieved efficient.
Smart Images
Figure CN119513011A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to an address detection module, method and control system. Background Art
[0002] When a master device such as a microcontroller unit (MCU) controls multiple slave devices such as slave units (such as I / O devices), it is necessary to obtain the address of each slave device in order to communicate with each slave device based on the corresponding address. Therefore, the address detection circuit plays an important role in the communication process between the master device and the slave device, and it is a key module for communication between the master device and the slave device. The traditional multi-bit address detection scheme requires multiple pins to generate multiple reference voltages, which often sets a corresponding processing circuit for each reference voltage to obtain multiple processing results, and then decodes these processing results to obtain the address of the corresponding unit. It can be seen that the above-mentioned multi-bit address detection scheme occupies many pins, and the power consumption generated by the participation of multiple processing circuits in the detection work is large, and the circuit area is also large. Summary of the invention
[0003] In view of this, the present application provides an address detection module, method and control system to solve the problems of traditional multi-bit address detection schemes occupying many pins, high power consumption and large circuit area involved.
[0004] The present application provides an address detection module, comprising a timing control circuit, a reference voltage generating circuit and a comparison circuit; the first output end of the timing control circuit is connected to the control end of the reference voltage generating circuit, and the second output end is connected to the control end of the comparison circuit; the output end of the reference voltage generating circuit is connected to the first input end of the comparison circuit; the second input end of the comparison circuit is used to access the input voltage of the associated slave device;
[0005] The timing control circuit is used to output a timing control signal to the reference voltage generating circuit and the comparison circuit;
[0006] The reference voltage generating circuit is used to generate a plurality of reference voltages according to the timing control signal, and input each of the reference voltages to the comparison circuit;
[0007] The comparison circuit is used to compare each of the reference voltages with the input voltage in sequence according to the timing control signal, and output a comparison result; the comparison result is used to represent the slave device address represented by the input voltage.
[0008] Optionally, the comparison circuit includes a comparator; the first input terminal of the comparator is connected to each of the reference voltages in sequence, the second input terminal is connected to the input voltage, the control terminal is connected to the timing control signal, and the output terminal is used to output the comparison results of each of the reference voltages and the input voltage in sequence.
[0009] Optionally, the timing control signal includes a plurality of first control opportunities; and the reference voltage generating circuit is further configured to generate the corresponding reference voltage at each of the first control opportunities.
[0010] Optionally, the timing control signal includes 2 N A first control opportunity; the reference voltage generating circuit includes 2 N switches and 2 in series N +1 resistor; the first end of the first resistor is connected to the first preset voltage; the second end of the ith resistor is connected to the first end of the (i+1)th resistor, and is connected to the first input end of the comparison circuit through the ith switch ... N The second end of the +1 resistor is grounded; the i-th switch is turned on at the i-th first control timing, where 1≤i≤2 N +1, N is a natural number.
[0011] Optionally, the reference voltage generating circuit further includes a control unit; the control unit is respectively connected to the 2N switches for accessing the timing control signal and switching on the i-th switch at the i-th first control timing.
[0012] Optionally, the timing control signal also includes second control opportunities corresponding to each of the first control opportunities; the comparison circuit is further configured to compare the reference voltage generated at the corresponding first control opportunity with the input voltage in sequence at each of the second control opportunities.
[0013] Optionally, the timing control circuit includes any one of a clock signal generator, a PLL and an OSC.
[0014] Optionally, the timing control signal includes a clock signal; and / or the frequency of the timing control signal is greater than a preset frequency.
[0015] Optionally, the address detection module further includes an address decoding circuit; the address decoding circuit is arranged at the output end of the comparison circuit; the address decoding circuit is used to decode each of the comparison results to obtain the slave device address represented by the input voltage.
[0016] The present application also provides an address detection method, the address detection method comprising:
[0017] Generate timing control signals;
[0018] Generate multiple reference voltages in sequence according to the timing control signal;
[0019] According to the timing control signal, each of the reference voltages is compared with the input voltage of the associated slave device in sequence to obtain each comparison result; the comparison result is used to represent the slave device address represented by the input voltage.
[0020] The present application also provides a control system, which includes any one of the above-mentioned address detection modules.
[0021] Optionally, the control system further includes a master device and slave devices corresponding to each of the address detection modules, and the master device obtains the address of the slave device through the address detection module.
[0022] Optionally, a voltage generating circuit is provided in the slave device; the voltage generating circuit is used to generate an input voltage associated with the slave device.
[0023] Optionally, the voltage generating circuit includes an adjustable resistor; a first end of the adjustable resistor is used to access a second preset voltage, and a second end of the adjustable resistor is used to provide the input voltage.
[0024] In the above-mentioned address detection module, method and control system of the present application, the timing control circuit can output a timing control signal to the reference voltage generating circuit and the comparison circuit, so that the reference voltage generating circuit generates multiple reference voltages according to the timing control signal, and transmits each reference voltage to the comparison circuit in turn, so that the comparison circuit compares each reference voltage with the input voltage in turn according to the timing control signal, and outputs each comparison result to the address decoding circuit, so as to obtain the slave device address represented by the input voltage according to each comparison result. The above-mentioned address detection module can obtain the required address information by controlling a group of reference voltage generating circuits and comparison circuits through the timing control circuit, realize the address detection of the corresponding slave device, simplify the circuit structure, and do not need multiple processing circuits to participate in the address detection work, which can save the chip pins and circuit area occupied by the address detection scheme, and can also reduce the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1 is a schematic diagram of the structure of an address detection module according to an embodiment of the present application;
[0027] Figure 2 is a schematic diagram of a timing control signal according to an embodiment of the present application;
[0028] Figure 3is a schematic diagram of the structure of an address detection module according to another embodiment of the present application;
[0029] Figure 4 is a schematic diagram of the structure of an address detection module according to another embodiment of the present application;
[0030] Figure 5 is a schematic diagram of the structure of an address detection module according to another embodiment of the present application;
[0031] Figure 6 is a schematic diagram of the timing of related signals according to an embodiment of the present application;
[0032] Figure 7 is a flowchart of an address detection method according to an embodiment of the present application;
[0033] Figure 8 It is a schematic diagram of the control system structure of an embodiment of the present application;
[0034] Fig. 9 It is a partial structural diagram of a control system of another embodiment of the present application. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0036] In a first aspect, the present application provides an address detection module, which is used to detect the addresses of each slave device controlled by a master device; wherein the master device may include a main control chip such as a micro control unit, and the slave device may include each unit chip controlled by the micro control unit.
[0037] refer to Figure 1 As shown, the address detection module includes a timing control circuit 140, a reference voltage generating circuit 110 and a comparison circuit 120. The first output end of the timing control circuit 140 is respectively connected to the control end of the reference voltage generating circuit 110, and the second output end is connected to the control end of the comparison circuit 120; the output end of the reference voltage generating circuit 110 is connected to the first input end of the comparison circuit 120; the second input end of the comparison circuit 120 is used to access the input voltage of the associated slave device.
[0038] The timing control circuit 140 is used to output a timing control signal to the reference voltage generating circuit 110 and the comparison circuit 120 to control the operation of the reference voltage generating circuit 110 and the comparison circuit 120. Optionally, the timing control circuit 140 includes a circuit that generates a periodic signal, such as a pulse generator or a clock circuit. The timing control signal may include, for example Figure 2 Periodic signals such as the clock signal shown.
[0039] The reference voltage generating circuit 110 generates a plurality of reference voltages according to the timing control signal, and inputs each of the reference voltages to the comparison circuit 120. Optionally, the timing control signal includes a plurality of cycles, and the reference voltage generating circuit 110 may generate a reference voltage in each cycle in turn.
[0040] The comparison circuit 120 is used to compare each reference voltage with the input voltage in sequence according to the timing control signal, and output the corresponding comparison result to the address decoding circuit 130. The input voltage may include the voltage at the address pin of the slave device, which can be used to characterize the address of the corresponding slave device. Optionally, the input voltage can be generated by a voltage generating circuit corresponding to the slave device, and the voltage generating circuit can generate the corresponding input voltage by adjusting its internal adjustable resistance and / or the size of the connected voltage. The control end of the comparison circuit 120 is connected to the timing control signal so that the comparison circuit 120 performs the comparison work according to the timing control signal, so that the comparison work of the comparison circuit 120 is synchronized with the voltage generation work of the reference voltage generating circuit 110, so as to ensure the consistency of the working response of the reference voltage generating circuit 110 and the comparison unit.
[0041] In the above-mentioned address detection module, the timing control circuit 140 can output a timing control signal to the reference voltage generating circuit 110 and the comparison circuit 120, so that the reference voltage generating circuit 110 generates multiple reference voltages according to the timing control signal, and transmits each reference voltage to the comparison circuit 120 in turn, so that the comparison circuit 120 compares each reference voltage with the input voltage in turn according to the timing control signal, and outputs each comparison result to the address decoding circuit 130, so as to obtain the slave device address represented by the input voltage according to each comparison result. The above-mentioned address detection module can obtain the required address information by controlling a group of reference voltage generating circuits 110 and comparison circuits 120 through the timing control circuit 140, thereby realizing the address detection of the corresponding slave device, simplifying the circuit structure, and only one pin for obtaining the reference voltage needs to be set in the address detection module, and there is no need for multiple processing circuits to participate in the address detection work, which can save the chip pins and circuit area occupied by the address detection scheme, and can also reduce the circuit power consumption.
[0042] In some embodiments, reference Figure 3As shown, the address detection module further includes an address decoding circuit 130, which is arranged at the output end of the comparison circuit 120. The address decoding circuit 130 is used to decode each comparison result received continuously, and decode the comparison result into address information that can be recognized by the master device to obtain the slave device address represented by the input voltage; in addition, the address decoding circuit 130 can also upload the decoding result (i.e., the slave device address) to the master device, so that the master device obtains the address of the corresponding slave device.
[0043] The address decoding circuit 130 may be implemented by a decoder and / or a decoder, and its decoding rules may be set according to factors such as the length of the comparison result and / or the address information format that the master device can recognize. Optionally, the address decoding circuit 130 may continuously receive the comparison results corresponding to an input voltage, combine the comparison results into a sequence, and then decode the sequence to obtain the slave device address represented by the input voltage.
[0044] In some embodiments, the comparison circuit 120 can be implemented by a circuit with a comparison function such as a comparator; for example, the comparison circuit 120 can include a comparison unit for comparing the size of two input signals, the first input terminal of the comparison unit is connected to the reference voltage, the second input terminal is connected to the input voltage, and the output terminal is used to output the comparison result of the reference voltage and the input voltage, and the comparison result can be represented by a binary number, such as 0 or 1; specifically, when the reference voltage is greater than the input voltage, the comparison unit outputs 1 (or a high level), and when the reference voltage is less than or equal to the input voltage, the comparison unit outputs 0 (or a low level), so that the comparison unit can output a binary sequence after multiple comparisons for an input voltage, and the binary sequence includes corresponding multiple comparison results. The address decoding circuit 130 receives the binary sequence, decodes it, and can obtain the slave device address represented by the input voltage.
[0045] In some examples, reference Figure 4As shown, the comparison circuit 120 includes a comparator COMP. The first input terminal of the comparator COMP is used as the first input terminal of the comparison circuit 120, and is connected to each reference voltage in sequence; the second input terminal of the comparator COMP is used as the second input terminal of the comparison circuit 120, and is connected to the input voltage. The control terminal of the comparator COMP is used as the control terminal of the comparison circuit 120, and is connected to the timing control signal. The output terminal of the comparator COMP is used to output the comparison results of each reference voltage and the input voltage in sequence. Optionally, the first input terminal of the comparator COMP can be a positive input terminal (or a non-inverting input terminal), and the second input terminal can be a negative input terminal (or an inverting input terminal). When the reference voltage is greater than the input voltage, the comparison result is 1, and when the reference voltage is less than or equal to the input voltage, the comparison result is 0. The above comparator COMP compares the input voltage with multiple reference voltages respectively, and then obtains a binary sequence representing the corresponding slave device address. This example uses a comparator to perform multiple comparisons of the reference voltage and the corresponding input voltage to obtain a binary sequence representing the corresponding slave device address, which can further simplify the structure of the address detection module and reduce the corresponding circuit area.
[0046] In some embodiments, the timing control signal includes multiple first control opportunities. The first control opportunity can be a time period such as a clock cycle on the timing control signal; the first control opportunity can also be a specific time point in each clock cycle on the timing control signal, for example, the first control opportunity is the starting time point in each clock cycle on the timing control signal, etc.; in this way, the timing control signal includes multiple first control opportunities that appear successively, and the reference voltage generating circuit 110 can generate a reference voltage at each first control opportunity.
[0047] The reference voltage generating circuit 110 can be implemented by using a component such as a signal generator that can output multiple voltage signals in sequence; the signal generator can be connected to the timing control signal to generate a voltage signal at each first control opportunity, and the voltage signal is input to the comparison circuit 120 as a reference voltage. Optionally, the rule for the signal generator to generate a voltage signal according to the timing control signal can be pre-set according to the constraint characteristics of the relevant signal in the address detection process, for example, the voltage value corresponding to each first control opportunity on the timing control signal can be pre-set, and the signal generator can generate the corresponding voltage value at each first control opportunity, etc.
[0048] In some examples, the timing control signal includes 2 N At the first control time, the reference voltage generating circuit 110 generates 2 N A reference voltage. Figure 5 As shown, the reference voltage generating circuit 110 includes 2 N switches and 2 in series N+1 resistor; the first end of the first resistor R0 is connected to the first preset voltage VDD; the second end of the i-th resistor R(i-1) is connected to the first end of the i+1-th resistor Ri, and the second end of the i-th resistor R(i-1) is also connected to the first input end of the comparison circuit 120 through the i-th switch S(i-1); the second end of the i-th resistor R(i-1) is connected to the first input end of the comparison circuit 120 through the i-th switch S(i-1); N +1 resistor R2 N The second end of is grounded. The i-th switch is turned on at the i-th first control timing, so that the reference voltage generating circuit 110 can provide a reference voltage to the first input terminal of the comparison circuit 120 at each first control timing; 1≤i≤2 N +1, N is a natural number. The circuit structure and control logic of the reference voltage generating circuit 110 provided in this example are relatively simple, which can make the corresponding address detection process simpler.
[0049] Optionally, the reference voltage generating circuit 110 further includes a control unit (not shown in the figure); the control unit is connected to the two N A switch is used to access the timing control signal and turn on the i-th switch at the i-th first control timing, so that the working process of the reference voltage generating circuit 110 is more orderly.
[0050] Specifically, Figure 5 The working sequence of each component of the address detection module shown can be referred to Figure 6 As shown, the timing control signal is recorded as SEL<2 N -1:0>, SEL<2 during an address detection process N -1:0> can include 2 N clock cycles, and N-bit binary numbers are used to distinguish different clock cycles; each clock cycle can be a first control opportunity. The reference voltage generating circuit 110 generates 2 N Different reference voltages VREF<2 N -1:0>, the 2 N A reference voltage VREF<2 N -1:0> is used as the reference voltage connected to the comparison circuit 120. Under the control of the timing control signal, the comparison circuit 120 compares the input voltage VIN with VREF in sequence. <0> 、VREF <1> 、VREF <2> , ..., VREF < 2 N -1>This 2 N The reference voltage is compared and the output is 2 N The comparison result is that the address decoding circuit 130 is 2 N The binary sequence composed of the comparison results is decoded to obtain an N-bit binary address AD <n-1:0>, the N-bit binary address can represent the address of the corresponding slave device. Optionally, the input voltage VIN and the reference voltage VREF < 2 N -1:0> can be represented by N-bit binary numbers 2 N For example, 00…0 (N bits are 0) represents VREF <0> This reference voltage, 11…1 (N bit 1) means VREF<2 N -1> this reference voltage and so on.
[0051] In some examples, the timing control signal also includes a second control timing corresponding to each first control timing. The comparison circuit 120 is also used to compare the reference voltage generated at the corresponding first control timing with the input voltage at each second control timing to improve the consistency of the working response of the comparison circuit 120 and the reference voltage generating circuit 110.
[0052] Optionally, when the delay of the reference voltage generating circuit 110 transmitting the reference voltage to the comparison circuit 120 can be ignored, the second control timing and the first control timing can be the same time period or time point, so that when the reference voltage generating circuit 110 generates the reference voltage and inputs the reference voltage to the comparison circuit 120, the comparison circuit 120 can perform the comparison operation in time to ensure the working efficiency of the comparison circuit 120. Optionally, the second control timing and the first control timing are in the same clock cycle, and the second control timing is after the first control timing; for example, the first control timing is the rising edge of the clock signal, and the second control timing is the falling edge of the clock signal in the same clock cycle as the first control timing; or, the time difference between the second control timing and the first control timing can be the delay of the reference voltage generating circuit 110 transmitting the reference voltage to the comparison circuit 120; and so on.
[0053] In some embodiments, the timing control circuit 140 includes a clock circuit or a clock signal generator for generating a clock signal. Accordingly, the timing control signal includes a clock signal (e.g. Figure 2 The first control opportunity includes a high level period on the clock signal, that is, a high level period on each clock cycle is a first control opportunity; the first control opportunity may also be a time point such as a rising edge or a falling edge of the clock signal.
[0054] Optionally, the clock signal is a high frequency signal, and its frequency is greater than the preset frequency, so that the reference voltage generating circuit 110 generates the reference voltage more quickly, and the comparison circuit 120 performs the comparison operation more efficiently, which can improve the efficiency of the corresponding address detection work and avoid the delay problem when communicating according to the detected address. Among them, the preset frequency can be set according to the timeliness requirement of the address detection module.
[0055] In some examples, the timing control circuit 140 includes a clock signal generator, which stably generates a clock signal, thereby improving the stability of the timing control signal output to the reference voltage generating circuit 110 and the comparison circuit 120, thereby improving the stability of the reference voltage generating circuit 110 and the comparison circuit 120 during operation.
[0056] In some examples, the timing control circuit 140 includes a PLL (phase-locked loop), which can stably generate a frequency signal, ensure the reliability of the generated timing control signal, and has the advantage of low cost. On the basis of improving the corresponding address detection module, it can reduce the production cost of the address detection module.
[0057] In some examples, the timing control circuit 140 includes an OSC (oscillator). The OSC has the advantages of simple manufacturing process and low cost, and can simplify the manufacturing process of the address detection module to a certain extent and reduce the production cost of the address detection module.
[0058] In the above address detection module, the timing control circuit 140 can output a timing control signal to the reference voltage generating circuit 110 and the comparison circuit 120, so that the reference voltage generating circuit 110 generates multiple reference voltages according to the timing control signal, and transmits each reference voltage to the comparison circuit 120 in turn, so that the comparison circuit 120 compares each reference voltage with the input voltage in turn according to the timing control signal, obtains each comparison result, and performs decoding and other processing on each comparison result, so as to obtain the slave device address represented by the input voltage. It can be seen that the above address detection module can obtain the required address information by controlling a group of reference voltage generating circuits 110 and comparison circuits 120 through the timing control circuit 140, realize the address detection of the corresponding slave device, simplify the circuit structure, and only need to set a pin for obtaining the reference voltage in the address detection module, without multiple processing circuits participating in the address detection work, which can save the chip pins and circuit area occupied by the address detection scheme, and can also reduce the power consumption of the circuit.
[0059] A second aspect of the present application provides an address detection method, which is applied to the address detection module described in any of the above embodiments, referring to Figure 7 As shown, the above-mentioned address detection method includes steps S510 to S530.
[0060] S510, generating a timing control signal;
[0061] S520, sequentially generating a plurality of reference voltages according to the timing control signal;
[0062] S530, comparing each of the reference voltages with an input voltage of an associated slave device in sequence according to the timing control signal to obtain each comparison result; the comparison result is used to represent the slave device address represented by the input voltage.
[0063] Optionally, step S520 can generate multiple reference voltages in sequence according to a timing control signal. For example, the timing control signal may include multiple first control opportunities, which may be a control cycle or a control time point. Step S520 generates corresponding reference voltages in sequence at each first control opportunity of the timing control signal.
[0064] Optionally, the above-mentioned address detection method may include: S540, decoding each of the comparison results to obtain a slave device address represented by the input voltage.
[0065] Specifically, the address detection method is applied to Figure 3 The address detection module shown, that is, step S510 can be executed by the timing control circuit 140 , step S520 can be executed by the reference voltage generating circuit 110 , step S530 can be executed by the comparison circuit 120 , and step S540 can be executed by the address decoding circuit 130 .
[0066] Furthermore, the timing control signal includes 2 N After receiving the timing control signal, the reference voltage generating circuit 110 generates 2 N A reference voltage VREF<2 N -1:0> input to the comparison circuit 120. The input voltage VIN connected to the comparison circuit 120 is sequentially connected to VREF <0> 、VREF <1> 、VREF <2> , ..., VREF < 2 N -1>This 2 N The reference voltage is compared and the output is 2 N The comparison result is that the address decoding circuit 130 is 2 N The binary sequence composed of the comparison results is decoded to obtain an N-bit binary address AD <n-1:0>, the N-bit binary address can represent the address of the corresponding slave device.
[0067] The above-mentioned address detection method is applied to the address detection module described in any of the above-mentioned embodiments, and has all the beneficial effects of the address detection module described in any of the above-mentioned embodiments, which will not be described in detail here.
[0068] A third aspect of the present application provides a control system, which includes at least one address detection module described in any of the above embodiments.
[0069] Specifically, refer to Figure 8 As shown, the control system further includes a master device 200 and slave devices 300 corresponding to each address detection module 100; the master device 200 obtains the address of the corresponding slave device 300 through the address detection module 100. The second input end of the comparison circuit 120 in each address detection module 100 can be connected to the address pin (i.e., the pin for outputting address information) of the corresponding slave device 300, and the output end of the address decoding circuit 130 can be connected to the master device 200 through a communication line such as a bus. The master device 200 detects the address of the corresponding slave device 300 through each address detection module 100, and communicates with the corresponding slave device 300 according to the detected address to control the operation of the slave device 300.
[0070] Optionally, the master device 200 may include a main control chip such as a micro control unit; the slave device 200 may include various controlled units such as a motor and / or a camera that are controlled by the main control chip.
[0071] Optionally, the address detection module 100 can be arranged inside the corresponding slave device 300, so that the slave device 300 uses the address detection module 100 arranged inside it to implement address detection of its own device, which can reduce the communication between chips during the address detection process and save communication resources.
[0072] In some embodiments, a voltage generating circuit 310 is provided in the slave device 300 , and the voltage generating circuit 310 is used to generate an input voltage VIN of an associated slave device.
[0073] Specifically, refer to Fig. 9 As shown, the voltage generating circuit 310 includes an adjustable resistor R EXT ;Adjustable resistor R EXT The first end is used to connect to the second preset voltage V EXT , and the second end is connected to the address pin of the slave device 300 to provide the input voltage VIN. In the application process, the master device 200 can pre-set the corresponding device address for each slave device 300 connected to it. The device address can be represented by a voltage signal, that is, the voltage generating circuit 310 needs to generate a voltage signal corresponding to the slave device 300, and input the voltage signal as an input voltage to the address detection module 100, so that the address detection module 100 detects the device address represented by the input voltage. The above-mentioned voltage generating circuit 310 adjusts the adjustable resistor R EXT The resistance value of the corresponding circuit and / or the second preset voltage V EXT The size of the voltage signal provided by the voltage generating circuit 310 is adjusted so that the voltage signal provided by the voltage generating circuit 310 matches the device address set by the master device 200 for the slave device 300 to which the voltage generating circuit 310 is located. In this way, the input voltage provided by the voltage generating circuit 310 can more accurately represent the address of the slave device 300 to which the voltage generating circuit 310 is located.
[0074] In some examples, the inventors analyze the above address detection scheme, such as Fig. 9 In the address detection scheme shown, the timing control signal is recorded as SEL<2 N -1:0>, SEL<2 during an address detection process N -1:0> can include 2 N The reference voltage generating circuit 110 generates 2 clock cycles under the control of the timing control signal. N Different reference voltages VREF<2 N -1:0>, the 2 N A reference voltage VREF<2 N -1:0> is used as the reference voltage connected to the comparison circuit 120. Under the control of the timing control signal, the comparison circuit 120 compares the input voltage VIN with VREF in sequence. <0> 、VREF <1> 、VREF <2> , ..., VREF < 2 N -1>This 2 N The reference voltage is compared and the output is 2 N The comparison result is that the address decoding circuit 130 is 2 N The binary sequence composed of the comparison results is decoded to obtain an N-bit binary address AD <n-1:0>, the N-bit binary address can represent the address of the corresponding slave device. It can be seen that the address detection scheme provided by the present application can complete N-bit address detection with only one comparator; if an input voltage representing different addresses is to be generated at the address pin of the slave device 300, it is only necessary to adjust the adjustable resistor R EXT The resistance value of the corresponding circuit and / or the second preset voltage V EXT It can be seen that the address detection module 100 provided in the present application significantly optimizes the comparison circuit, and only one comparison circuit 120 is required to complete the previous need for 2 N The work of a comparison circuit is reduced, reducing the area and power consumption required for circuit implementation.
[0075] The above control system includes the address detection module described in any of the above embodiments, and has all the beneficial effects of the address detection module described in any of the above embodiments, which will not be repeated here.
[0076] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.
[0077] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0078] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "plurality" means two or more, unless otherwise clearly and specifically defined.
[0079] In this application, the word "exemplary" is used to mean "used as an example, illustration, or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as being more preferred or more advantageous than other embodiments. The above description is given in this application to enable any technician in the field to implement and use the present application. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.
Claims
1. An address detection module, characterized in that: The address detection module includes a timing control circuit, a reference voltage generating circuit and a comparison circuit; the first output end of the timing control circuit is connected to the control end of the reference voltage generating circuit, and the second output end is connected to the control end of the comparison circuit; the output end of the reference voltage generating circuit is connected to the first input end of the comparison circuit; the second input end of the comparison circuit is used to access the input voltage of the associated slave device; The timing control circuit is used to output a timing control signal to the reference voltage generating circuit and the comparison circuit; The reference voltage generating circuit is used to generate a plurality of reference voltages according to the timing control signal, and input each of the reference voltages to the comparison circuit; The comparison circuit is used to compare each of the reference voltages with the input voltage in sequence according to the timing control signal, and output a comparison result; the comparison result is used to represent the slave device address represented by the input voltage.
2. The address detection module according to claim 1, characterized in that: The comparison circuit comprises a comparator; The first input terminal of the comparator is connected to each of the reference voltages in sequence, the second input terminal is connected to the input voltage, the control terminal is connected to the timing control signal, and the output terminal is used to output the comparison results of each of the reference voltages and the input voltage in sequence.
3. The address detection module according to claim 1, characterized in that: The timing control signal includes a plurality of first control opportunities; The reference voltage generating circuit is further configured to generate the corresponding reference voltage at each of the first control timings.
4. The address detection module according to claim 1, characterized in that: The timing control signal includes 2 N The first control opportunity; The reference voltage generating circuit comprises 2 N switches and 2 in series N +1 resistor; the first end of the first resistor is connected to the first preset voltage; the second end of the ith resistor is connected to the first end of the (i+1)th resistor, and is connected to the first input end of the comparison circuit through the ith switch ... N The second end of the +1 resistor is grounded; the i-th switch is turned on at the i-th first control timing, where 1≤i≤2 N +1, N is a natural number.
5. The address detection module according to claim 4, characterized in that: The reference voltage generating circuit further includes a control unit; The control unit is respectively connected to 2 N The switch is used to access the timing control signal and turn on the i-th switch at the i-th first control opportunity.
6. The address detection module according to claim 4, characterized in that: The timing control signal also includes a second control opportunity corresponding to each of the first control opportunities; The comparison circuit is further configured to sequentially compare the reference voltage generated at the corresponding first control timing with the input voltage at each second control timing.
7. The address detection module according to claim 1, characterized in that: The timing control circuit includes any one of a clock signal generator, a PLL and an OSC.
8. The address detection module according to claim 1, characterized in that: The timing control signal includes a clock signal; and / or the frequency of the timing control signal is greater than a preset frequency.
9. The address detection module according to claim 1, characterized in that: The address detection module further includes an address decoding circuit; the address decoding circuit is arranged at the output end of the comparison circuit; The address decoding circuit is used to decode each of the comparison results to obtain the slave device address represented by the input voltage.
10. An address detection method, characterized in that: The address detection method comprises: Generate timing control signals; Generate multiple reference voltages in sequence according to the timing control signal; According to the timing control signal, each of the reference voltages is compared with the input voltage of the associated slave device in sequence to obtain each comparison result; the comparison result is used to represent the slave device address represented by the input voltage.
11. A control system, characterized in that: The control system comprises at least one address detection module according to any one of claims 1 to 9.
12. The control system according to claim 11, characterized in that: The control system further includes a master device and slave devices corresponding to each of the address detection modules, and the master device obtains the address of the slave device through the address detection module.
13. The control system according to claim 12, characterized in that: The slave device is provided with a voltage generating circuit; The voltage generating circuit is used to generate an input voltage associated with the slave device.
14. The control system according to claim 13, characterized in that: The voltage generating circuit includes an adjustable resistor; The first end of the adjustable resistor is used to access the second preset voltage, and the second end is used to provide the input voltage.