Two-dimensional field effect transistor model based on single-layer transition metal chalcogenide and construction method

Abstract

The invention relates to the field of design and simulation of semiconductor equipment, and discloses a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide and a construction method, and the construction method comprises the steps: setting the source end and the drain end of a two-dimensional field effect transistor to be in ohmic contact with a two-dimensional material, and constructing a charge model of the two-dimensional field effect transistor; according to the relationship between the charge and the capacitance, constructing a capacitance model comprising quantum capacitance and parasitic capacitance in the two-dimensional field effect transistor based on the charge determined by the charge model; determining stray capacitance between layers of the two-dimensional transistor, converting a circuit formed by the stray capacitance into a static capacitance network, and constructing a channel voltage model of the two-dimensional field effect transistor according to the relation between capacitance and voltage; and determining a general channel current model, and combining the relationship between the voltage, the capacitance and the charge determined by the channel voltage model with the general channel current model to obtain a final channel current model. The performance and the efficiency of the low-power-consumption electronic device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design and simulation, and in particular to a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide and a construction method thereof. Background Art

[0002] With the development of two-dimensional material technology, monolayer transition metal dichalcogenides (TMDs) have attracted widespread attention due to their excellent electronic and physical properties. The uniqueness of these materials is that they can significantly improve the performance of field-effect transistors (FETs), especially in low-power applications. However, two-dimensional material transistors will eventually work in large-scale circuits and are currently only used in simple circuits with a few tubes. With the continuous improvement of two-dimensional materials and the technology to generate transistors, the application of large-scale circuits will soon become feasible. In this process, it is essential to model the electrical properties of two-dimensional material transistors, including device design optimization, performance prediction, and the exploration of low-power switching circuits.

[0003] Existing two-dimensional transistor models usually have the following problems: 1. The quantum capacitance effect and abnormal transport mechanism of charge carriers unique to two-dimensional materials are not taken into account. 2. The characteristics of intrinsic devices are simply modeled based on the capacitance network, which means that such models are not scalable. 3. The concepts of drift and diffusion current, chemical or Fermi potential (or voltage) and electrostatic potential are not correctly defined and distinguished, making it impossible to characterize transistors as comprehensively as possible. 4. Only intrinsic characteristics are considered, making the model too idealized.

[0004] The existence of the above problems limits the application of TMD in the design of new two-dimensional semiconductor devices. Therefore, it is particularly important to design a model that can characterize the transistor effects and mechanisms of two-dimensional materials. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a two-dimensional field effect transistor model and construction method based on a single layer of transition metal chalcogenides, which can utilize single layer of transition metal chalcogenides to improve the performance and efficiency of low-power electronic devices, and lay the foundation for the subsequent support of complex circuit design and simulation.

[0006] To achieve the above-mentioned objectives, in the first aspect, the technical solution adopted by the present invention is: a method for constructing a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide compound, which includes: setting the source and drain ends of the two-dimensional field effect transistor to be in ohmic contact with the two-dimensional material to construct a charge model of the two-dimensional field effect transistor; according to the relationship between charge and capacitance, a capacitance model including quantum capacitance and parasitic capacitance inside the two-dimensional field effect transistor is constructed based on the charge determined by the charge model; the parasitic capacitance between each layer of the two-dimensional transistor is determined, and the circuit composed of the parasitic capacitance is converted into a static capacitance network, and a channel voltage model of the two-dimensional field effect transistor is constructed according to the relationship between capacitance and voltage; a general channel current model is determined, and the relationship between voltage, capacitance and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model.

[0007] Furthermore, a charge model of a two-dimensional field effect transistor is constructed, including: defining the voltage drop V on the surface of the two-dimensional material in the L interval C , and the Fermi-Dirac function f F (E), the middle energy band E0 and the effective mass D0 are simplified respectively; L is the length of the back gate oxide layer;

[0008] According to the simplified parameters, the charge model is determined as follows:

[0009]

[0010] In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the semiconductor middle band gap, E F is the Fermi level.

[0011] Further, a capacitance model including quantum capacitance and parasitic capacitance inside the two-dimensional field effect transistor is constructed based on the charge determined by the charge model, including: according to the relationship between charge and capacitance, the charge model is derived to obtain a capacitance model; the capacitance model is:

[0012]

[0013] In the formula, C q is the capacitor model, C q,p is the hole-dominated quantum capacitance, C q,n is the electron-dominated quantum capacitance, k is the Boltzmann constant, T is the room temperature, m * is the effective mass of the electron, is Planck's constant.

[0014] Furthermore, the parasitic capacitance between the layers of the two-dimensional transistor is determined, including: the top oxide capacitance is C t , the quantum capacitance of a single-layer MoS2 is C q , the bottom oxide capacitance is C b .

[0015] Furthermore, a channel voltage model of a two-dimensional field effect transistor is constructed based on the relationship between capacitance and voltage, including: converting a circuit composed of parasitic capacitances between materials of each layer of the two-dimensional transistor into a static capacitance network, and using Kirchhoff's voltage-current law to directly derive the relationship between voltage and capacitance; and obtaining a channel voltage model based on the relationship between voltage and capacitance, which is:

[0016]

[0017] Where V c (x) is the channel voltage model, V gs -V gs0 and V bs -V Bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, V gs is the gate-source voltage, V gs0 is the top gate flat band voltage, V Bs is the back gate voltage, V bs0 Back gate flat band voltage, Q n (V c ) is the contribution of electrons, and here it is emphasized that V c The function of Q n , V n (x) is the electron concentration, C t is the top oxide capacitance, C b is the bottom oxide capacitor.

[0018] Further, a general channel current model is determined, including: assuming that the drift-diffusion transport mechanism is inside the two-dimensional transistor channel, so as to determine the general channel current model as:

[0019]

[0020] In the formula, is a general channel current model, W is the gate width, μ is the effective hole mobility, V cd is the voltage drop at the drain end of the quantum capacitor, V cs is the voltage drop at the source of the quantum capacitor, Q n is the charge of the electron, V c is the channel voltage. V n (x) is the potential of the NMOS at channel x.

[0021] Further, the relationship between the voltage, capacitance and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model, including: by derivation of the channel voltage determined by the channel voltage model, and the capacitance-charge relationship, the final channel current model is obtained by combining the general channel current model:

[0022]

[0023] In the formula, I ds is the final channel current model, E g is the bandgap width.

[0024] In the second aspect, the technical solution adopted by the present invention is: a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide, the model is established based on the above-mentioned two-dimensional field effect transistor model construction method based on a single-layer transition metal chalcogenide, and the two-dimensional field effect transistor model includes: a charge model, a capacitance model, a channel voltage model and a channel current model;

[0025] The charge model is:

[0026]

[0027] The capacitor model is:

[0028]

[0029] The channel voltage model is:

[0030]

[0031] The channel current model is:

[0032]

[0033] In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F is the Fermi level, C q is the capacitor model, C q,p is the hole-dominated quantum capacitance, C q,n is the electron-dominated quantum capacitance, k is the Boltzmann constant, T is the room temperature, V c (x) is the channel voltage model, V gs -V gs0 and V bs -V bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, Vgs is the gate-source voltage, V gs0 is the top gate flat band voltage, V bs is the back gate voltage, V bs0 is the bottom gate flat band voltage, Q n (V c ) is the charge of the electron, and V c About V n (x) is the potential of NMOS at channel x, C t is the top oxide capacitance, C b is the bottom oxide capacitance, I ds is the final channel current model, E g is the bandgap width.

[0034] In a third aspect, the technical solution adopted by the present invention is: a computer-readable storage medium storing one or more programs, characterized in that the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device executes any one of the above methods.

[0035] In a fourth aspect, the technical solution adopted by the present invention is: a computing device, comprising: one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods.

[0036] The present invention adopts the above technical solution, which has the following advantages:

[0037] The physically based compact model provided by the present invention is applicable to field effect transistors containing a single layer of two-dimensional materials. This model integrates the unique properties of two-dimensional materials, such as their contribution to quantum capacitance, the influence of parasitic capacitance, and the electrical characteristics of the device affected thereby, and adopts the drift-diffusion mechanism to describe the transport behavior of carriers, thereby improving the performance and efficiency of low-power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of a method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenide in an embodiment of the present invention;

[0039] Figure 2 is a schematic diagram of a two-dimensional field effect transistor model in an embodiment of the present invention;

[0040] Figure 3 is a front structural diagram of a two-dimensional field effect transistor model in an embodiment of the present invention;

[0041] Figure 4is a main capacitance distribution diagram of a two-dimensional field effect transistor model in an embodiment of the present invention;

[0042] Figure 5 is a schematic diagram of a circuit composed of parasitic capacitors in an embodiment of the present invention being transformed into a static capacitor network;

[0043] Figure 6 4 is a current-voltage characteristic curve (IV curve) diagram of a two-dimensional transistor in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0045] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0046] In one embodiment of the present invention, a method for constructing a two-dimensional field effect transistor model based on a monolayer transition metal chalcogenide is provided, using a monolayer transition metal chalcogenide such as MoS2 and WSe2 to improve the performance and efficiency of low-power electronic devices. In this embodiment, Figure 1 , Figure 2 As shown, the model construction method includes the following steps:

[0047] 1) Set the source and drain of the two-dimensional field effect transistor to be in ohmic contact with the two-dimensional material, and construct the charge model Q of the two-dimensional field effect transistor c ;

[0048] 2) According to the relationship between charge and capacitance, the quantum capacitance and parasitic capacitance model C inside the two-dimensional field effect transistor is constructed based on the charge determined by the charge model q ;

[0049] 3) Determine the parasitic capacitance between the layers of the 2D transistor, and transform the circuit composed of the parasitic capacitance into a static capacitance network, and construct the channel voltage model V of the 2D field effect transistor based on the relationship between capacitance and voltage. c (x);

[0050] 4) Determine a universal channel current model, and combine the relationship between voltage, capacitance and charge determined by the channel voltage model with the universal channel current model to obtain the final channel current model I ds .

[0051] In the above step 1), constructing a charge model of a two-dimensional field effect transistor includes the following steps:

[0052] 1.1) Define the voltage drop V on the surface of a two-dimensional material in the L interval C , and the Fermi-Dirac function f F (E), the middle energy band E0 and the effective mass D0 are simplified respectively; L is the length of the back gate oxide layer;

[0053] 1.2) According to the simplified parameters, the charge model is determined as:

[0054]

[0055] In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F is the Fermi level.

[0056] in:

[0057]

[0058] In this embodiment, the core physical mathematical model of charge is used as a starting point to derive and calculate other models. For the charge model, first define the voltage drop V on the surface of the two-dimensional material in the L interval C , different from V ds ,as follows Figure 3 shown.

[0059] Next, define f F (E) is the Fermi-Dirac function, E F =qV c is the Fermi level, the reference energy level is the semiconductor middle band gap, E g is the band gap of monolayer MoS2. Parameter V c Represents C q The voltage drop or surface potential on the surface, D0 is the effective mass, q represents the electron charge, C q is a capacitor model. The following simplifications are made in the initial stage of modeling:

[0060] (1) Simplified to

[0061] (2) The intermediate energy band is simplified to

[0062] (3) The Fermi-Dirac function is simplified to f F (E)~1.

[0063] In step 2) above, the capacitance model refers to the quantum capacitance C dominated by the two-dimensional material. q Since the above charge model is also based on quantum states and Fermi-Dirac functions, the relationship between capacitance, charge, and potential still holds true. In this embodiment, the capacitance model and the voltage model proposed next use a different capacitance equivalent network. This capacitance model is a theoretical representation of the quantum capacitance and parasitic capacitance inside a two-dimensional transistor, while the following capacitance equivalent network is only based on the macroscopic parasitic capacitance between the various layers of transistor materials.

[0064] Among them, a capacitance model including quantum capacitance and parasitic capacitance inside the two-dimensional field effect transistor is constructed based on the charge determined by the charge model. Specifically, according to the relationship between charge and capacitance, the charge model is derived with respect to the potential to obtain the capacitance model.

[0065] The relationship between charge and capacitance:

[0066]

[0067] Directly derive the potential of the above charge model and obtain the capacitance model as follows:

[0068]

[0069] In the formula, C q is the capacitor model, C q,p is the hole-dominated quantum capacitance, C q,n is the electron-dominated quantum capacitance, k is the Boltzmann constant, and T is the room temperature.

[0070] In the above step 3), the parasitic capacitance between the layers of the two-dimensional transistor is determined, including: the top oxide capacitance is C t , the quantum capacitance of monolayer MoS2 is C q , the bottom oxide capacitance is C b ,like Figure 4 shown.

[0071] In the above step 3), a channel voltage model of a two-dimensional field effect transistor is constructed according to the relationship between capacitance and voltage, including the following steps:

[0072] 3.1) Transform the circuit composed of parasitic capacitance between the layers of materials in the two-dimensional transistor into a static capacitance network (such as Figure 5 As shown), using Kirchhoff's voltage-current law, the relationship between voltage and capacitance can be directly obtained;

[0073] 3.2) According to the relationship between voltage and capacitance, the channel voltage model is obtained as follows:

[0074]

[0075] Where V c (x) is the channel voltage model, V gs -V gs0 and V bs -V bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, V gs is the gate-source voltage, V gs0 is the top gate flat band voltage, V bs is the back gate voltage, V bs0 is the bottom gate flat band voltage, Q n (V c ) is the charge of the electron, and V c About V n (x) is the potential of NMOS at channel x, C t is the top oxide capacitance, C b is the bottom oxide capacitor.

[0076] The model includes the work function difference between the gate terminal and the MoS2 monolayer, the resulting charged interface states at the interface between the MoS2 monolayer and the oxide, and the intentional or unintentional doping of the MoS2 monolayer.

[0077] In the above step 4), a general channel current model is determined, specifically:

[0078] According to the modeling method adopted by ordinary silicon field effect transistors, it is assumed that the drift-diffusion transport mechanism is used inside the two-dimensional transistor channel. Then:

[0079]

[0080] v=μF

[0081]

[0082] Where W is the gate width, v(x) is the hole drift velocity, F is the electric field, and μ is the hole effective mobility.

[0083] Assume no dependence on field, carrier density or temperature. This model is applicable when the channel length is much longer than the mean free path of holes. The above combination gives a general channel current model:

[0084]

[0085] To obtain an explicit expression for the drain current, use V c Solve the integral by using Q as the integral variable. n Also denoted as V c After redefining the boundary conditions of the surface potential, the general channel current model is obtained as follows:

[0086]

[0087] In the formula, is a general channel current model, W is the gate width, μ is the effective hole mobility, V cd is the voltage drop at the drain end of the quantum capacitor, V cs is the voltage drop at the source of the quantum capacitor, Q n is the electron charge, V n (x) is the potential of NMOS at channel x, V c is the channel voltage.

[0088] In this embodiment, the relationship between voltage, capacitance and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model, which is specifically:

[0089] By differentiating the channel voltage determined by the channel voltage model:

[0090]

[0091] And the capacitance-charge relationship, combined with the general channel current model, the final channel current model is:

[0092]

[0093] In the formula, I ds is the final channel current model.

[0094] in:

[0095]

[0096] In summary, taking the simulation of the current-voltage curve of the model of the present invention as an example, first generate the .sp file of the model, in which the complete code is called (the model code is the .va file), and generate the simulation environment of the model: the gate terminal (Gate) of the transistor is connected to a 1V voltage, the drain terminal (Drain) is connected to a 1V voltage, and the source terminal (Source) is grounded (0V). Perform a direct current simulation (DC). Get the current-voltage characteristic curve (IV curve) of the two-dimensional transistor, such as Figure 6The simulation results match the curves of conventional field-effect transistors very well, and the model is calibrated by comparing with experimental data. This model can be used to optimize the design of two-dimensional transistors in the future, especially for low-power and high-performance applications, and ultimately enable designers to predict and optimize performance before design, including using the model to analyze and design low-power switching circuits and other high-performance electronic devices.

[0097] The present invention includes quantum effects and unique characteristic models of two-dimensional transistors, which can be applied to future EDA (Electronic design automation) applications. Compared with other models, it can more comprehensively characterize the electrical characteristics and quantum effects of two-dimensional material transistors. The model includes a charge model Q c , Capacitor Model C q , channel voltage model V c (x) and channel current model I ds .

[0098] Furthermore, the model of the present invention is scalable and can predict the working conditions of transistors under other parameters by modifying the parameters. The parameters of the model can be reversely adjusted according to various results appearing in the simulation, or the formula expression of the model can be refined to achieve a current-voltage curve similar to that of a conventional silicon field-effect transistor. In this way, there is no need to manually change the material or size to modify the parameters, and the design and production process is close to that of a conventional silicon transistor circuit.

[0099] Furthermore, compared with other two-dimensional transistor models, the present invention can fully reflect the relevant electrical characteristics of the model.

[0100] In one embodiment of the present invention, a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenides is provided, and the model is established based on the method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenides in the above embodiments. In this embodiment, the two-dimensional field effect transistor model includes: a charge model, a capacitance model, a channel voltage model, and a channel current model. Among them:

[0101] The charge model is:

[0102]

[0103] The capacitor model is:

[0104]

[0105] The channel voltage model is:

[0106]

[0107] The channel current model is:

[0108]

[0109] In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F is the Fermi level, C q is the capacitor model, C q,p is the electron-dominated quantum capacitance, C q,n is the hole-dominated quantum capacitance, k is the Boltzmann constant, T is the room temperature, V c (x) is the channel voltage model, V gs -V gs0 and V bs -V bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, V gs is the gate-source voltage, V gs0 is the top gate flat band voltage, V bs is the back gate voltage, V bs0 is the bottom gate flat band voltage, V n (x) is the potential of NMOS at channel x, C t is the top oxide capacitance, C b is the bottom oxide capacitance, E g is the bandgap width, I ds is the final channel current model.

[0110] The model provided in this embodiment is used to execute the above-mentioned method embodiments. Please refer to the above-mentioned embodiments for specific processes and detailed contents, which will not be repeated here.

[0111] A computing device provided in one embodiment of the present invention may be a terminal, which may include: a processor, a communication interface, a memory, a display screen and an input device. The processor, the communication interface and the memory communicate with each other through a communication bus. The processor is used to provide computing and control capabilities. The memory includes a non-volatile storage medium and an internal memory, wherein the non-volatile storage medium stores an operating system and a computer program, and the computer program is executed by the processor to implement the methods in the above embodiments; the internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner may be implemented through WIFI, a management network, NFC (near field communication) or other technologies. The display screen may be a liquid crystal display screen or an electronic ink display screen, and the input device may be a touch layer covered on the display screen, or a key, a trackball or a touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse, etc. The processor may call the logic instructions in the memory.

[0112] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0113] In one embodiment of the present invention, a computer program product is provided, wherein the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the methods provided by the above-mentioned method embodiments.

[0114] In one embodiment of the present invention, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores server instructions, and the computer instructions enable a computer to execute the methods provided in the above embodiments.

[0115] The above embodiment provides a computer-readable storage medium, whose implementation principle and technical effect are similar to those of the above method embodiment, and will not be repeated here.

[0116] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0117] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for constructing a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide, characterized in that: include: The source and drain of the two-dimensional field effect transistor are set to be in ohmic contact with the two-dimensional material, and a charge model of the two-dimensional field effect transistor is constructed; According to the relationship between charge and capacitance, a capacitance model including quantum capacitance and parasitic capacitance inside the two-dimensional field effect transistor is constructed based on the charge determined by the charge model; Determine the parasitic capacitance between the layers of the two-dimensional transistor, transform the circuit composed of the parasitic capacitance into a static capacitance network, and construct the channel voltage model of the two-dimensional field effect transistor based on the relationship between capacitance and voltage; A general channel current model is determined, and the relationship between voltage, capacitance and charge determined by the channel voltage model is combined with the general channel current model to obtain a final channel current model.

2. The method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenide as claimed in claim 1, characterized in that: Construct a charge model of a 2D field effect transistor, including: Define the voltage drop V on the surface of a two-dimensional material in the L interval C , and simplify the Fermi-Dirac function fF(E), the intermediate energy band E0 and the effective mass D0 respectively; L is the length of the back gate oxide layer; According to the simplified parameters, the charge model is determined as follows: In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the semiconductor middle band gap, E F is the Fermi level.

3. The method for constructing a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide as claimed in claim 1, characterized in that: A capacitance model including quantum capacitance and parasitic capacitance inside a two-dimensional field effect transistor is constructed based on the charges determined by the charge model, including: According to the relationship between charge and capacitance, the charge model is derived from the potential to obtain the capacitance model; The capacitor model is: In the formula, C q is the capacitor model, C q，p is the hole-dominated quantum capacitance, C q，n is the electron-dominated quantum capacitance, k is the Boltzmann constant, T is the room temperature, m * is the effective mass of the electron, is Planck's constant.

4. The method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenide as claimed in claim 1, characterized in that: Determine the parasitic capacitance between the layers of the 2D transistor, including: the top oxide capacitance is C t , the quantum capacitance of a single-layer MoS2 is C q , the bottom oxide capacitance is C b .

5. The method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenide as claimed in claim 1, characterized in that: A channel voltage model of a two-dimensional field effect transistor is constructed based on the relationship between capacitance and voltage, including: The circuit composed of parasitic capacitance between the layers of materials in the two-dimensional transistor is transformed into a static capacitance network, and the relationship between voltage and capacitance is directly obtained using Kirchhoff's voltage-current law. According to the relationship between voltage and capacitance, the channel voltage model is obtained as follows: Where V c (x) is the channel voltage model, V gs -V gs0 and V bs -V bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, V gs is the gate-source voltage, V gs0 is the top gate flat band voltage, V bs is the back gate voltage, V bs0 Back gate flat band voltage, Q n (Vc) is the contribution of electrons, and here it is emphasized that it is a function of Vc, the same as Q n , Vn(x) is the electron concentration, C t is the top oxide capacitance, C b is the bottom oxide capacitor.

6. The method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenide as claimed in claim 1, characterized in that: Determine the general channel current model, including: Assuming that the drift-diffusion transport mechanism is used inside the two-dimensional transistor channel, the general channel current model is determined as: In the formula, is a general channel current model, W is the gate width, μ is the effective hole mobility, Vcd is the quantum capacitor drain voltage drop, V cs is the voltage drop at the source of the quantum capacitor, Q n is the charge of the electron, V c is the channel voltage, V n (x) is the potential of the NMOS at channel x.

7. The method for constructing a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide as claimed in claim 6, characterized in that: The relationship between voltage, capacitance and charge determined by the channel voltage model is combined with the general channel current model to obtain the final channel current model, including: By taking the derivative of the channel voltage determined by the channel voltage model and the capacitance-charge relationship, the final channel current model is obtained by combining the general channel current model: In the formula, I ds is the final channel current model, E g is the bandgap width.

8. A two-dimensional field effect transistor model based on a single layer of transition metal chalcogenides, the model being established based on the method for constructing a two-dimensional field effect transistor model based on a single layer of transition metal chalcogenides as claimed in any one of claims 1 to 7, characterized in that: The two-dimensional field effect transistor model includes: a charge model, a capacitance model, a channel voltage model and a channel current model; The charge model is: The capacitor model is: The channel voltage model is: The channel current model is: In the formula, Q c is the charge model, q is the electron charge, DOS 2D (E) is the two-dimensional state density function, f(E F -E) is the Fermi-Dirac distribution function, E is the band gap energy, E F is the Fermi level, C q is the capacitor model, C q，p is the hole-dominated quantum capacitance, C q，n is the electron-dominated quantum capacitance, k is the Boltzmann constant, T is the room temperature, V c (x) is the channel voltage model, V gs -V gs0 and V bs -V bs0 are the overdrive voltages of the top gate-source voltage and the back gate-source voltage, V gs is the gate-source voltage, V gs0 is the top gate flat band voltage, V bs is the back gate voltage, V bs0 is the bottom gate flat band voltage, Q n (V c ) is the charge of the electron, and V c About V n (x) is the potential of NMOS at channel x, C t is the top oxide capacitance, C b is the bottom oxide capacitance, I ds is the final channel current model, E g is the bandgap width.

9. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform any one of the methods of claims 1 to 7.

10. A computing device, characterized in that: include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any one of the methods described in claims 1 to 7.

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