A method for macro cell layout in integrated circuit design

By optimizing macrocell placement using DBSCAN clustering, genetic algorithms, and simulated annealing algorithms, the problem of time-consuming manual placement is solved, thus improving the efficiency and reliability of integrated circuit design.

CN119514467BActive Publication Date: 2025-11-25TONGJI UNIV
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Patent Information

Application Number
CN202411488008.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-10-23
Publication Date
2025-11-25
Estimated Expiration
2044-10-23

AI Technical Summary

Technical Problem

Existing macrocell placement methods rely on manual experience, are time-consuming and ineffective, and are difficult to complete integrated circuit design efficiently.

Method used

The DBSCAN clustering algorithm is used to cluster macrocells, and the cluster results are optimized by combining the genetic algorithm. The layout is optimized by using the simulated annealing algorithm and the greedy algorithm. The layout is updated by area evaluation and line length evaluation models, and finally the congestion problem in macrocell layout is solved.

Benefits of technology

It achieves efficient and reliable macrocell layout, shortens the design cycle, and improves the efficiency and reliability of integrated circuit design.

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Abstract

The application discloses a macro cell layout method for integrated circuit design, comprising: obtaining circuit netlist information and macro cell structure characteristics to be laid out; clustering all macro cells according to the circuit netlist information based on a DBSCAN clustering algorithm to obtain multiple clusters; updating the multiple clusters based on a genetic algorithm; creating multiple macro cell arrays in the multiple clusters according to the macro cell structure characteristics; laying out the macro cell arrays in each cluster respectively; laying out each cluster respectively to obtain a preliminary layout result; updating the preliminary layout result using an area evaluation model and a line length evaluation model in a target function of a simulated annealing algorithm to obtain an updated layout result; updating the updated layout result again using a greedy algorithm to solve a congestion problem; and updating overlapping parts of the macro cells globally to obtain a final layout result.
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Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a macrocell layout method for integrated circuit design. Background Technology

[0002] With the continuous development of integrated circuit technology, its complexity is constantly increasing. To improve the efficiency of integrated circuit design, shorten the design cycle, and enhance the reliability of functions, modern large-scale integrated circuit design often employs a large number of macrocells. Macrocell placement is performed in the early stages of integrated circuit design, and its quality directly affects the subsequent standard cell placement, significantly impacting the performance, power consumption, and area of ​​the integrated circuit. In actual integrated circuit design, macrocell placement is typically completed first, followed by standard cell placement under the condition that the macrocell positions are fixed.

[0003] Current macrocell placement methods primarily rely on manual processes and are highly dependent on engineers' experience. The macrocell placement process involves considering numerous design constraints, such as placing macrocells as close as possible to module boundaries, placing macrocells with similar design hierarchies closer together, and maintaining sufficient spacing between macrocells. Manual macrocell placement methods require multiple trials and are time-consuming; therefore, designing an efficient and reliable automated macrocell placement method is crucial. Summary of the Invention

[0004] The main purpose of this application is to provide a macrocell layout method, which aims to solve the technical problems of poor results and long time consumption in manual macrocell layout.

[0005] To achieve the above objectives, this application provides a macro cell layout method, which includes the following steps:

[0006] S1. Obtain the netlist information and macrocell structure characteristics of the circuit to be laid out;

[0007] S2. Based on the DBSCAN clustering algorithm, all macrocells are clustered according to the circuit netlist information to obtain multiple clusters;

[0008] S3. Update multiple clusters based on genetic algorithms;

[0009] S4. Create multiple macrocell arrays in multiple clusters based on macrocell structural characteristics;

[0010] S5. Lay out the macrocell array in each cluster respectively;

[0011] S6. Lay out each cluster separately to obtain the preliminary layout results;

[0012] S7. In the objective function of the simulated annealing algorithm, the area evaluation model and the line length evaluation model are used to update the initial layout results to obtain the updated layout results.

[0013] S8. Use a greedy algorithm to update the updated layout result again to solve the congestion problem;

[0014] S9. Update the overlapping parts of the macro cells globally to obtain the final layout result.

[0015] In one embodiment, in S1, the circuit netlist information and macrocell structure features include:

[0016] Information on all design levels in the circuit, the number of standard cells in different design levels, the design level information of all macrocells, and the size and pin location information of all macrocells.

[0017] In one embodiment, S2 includes the following steps:

[0018] S21. The distance metric between two macrocells is calculated as follows:

[0019]

[0020] Where p represents two macrounits m i and m j The number of standard cells in the common design hierarchy between areas, where n represents the total number of standard cells in the circuit netlist, Area k Represents the area of ​​a standard unit;

[0021] S22. Using adaptive DBSCAN clustering algorithm parameters, generate a list of eps parameters ranging from 0 to 1 with a step size of 0.01, and a list of MinPts parameters ranging from 1 to N, where N represents the number of all macrocells.

[0022] S23. For all parameter lists of eps and MinPts, combine them in pairs to generate a parameter pair list. Generate a DBSCAN clustering result based on each parameter pair list, and only retain the results with 4 clusters.

[0023] S24. Assign macrocells that have not been assigned to a cluster to the cluster with the nearest average distance metric.

[0024] S25. Calculate the silhouette coefficient of each DBSCAN clustering result and sort them from high to low according to the silhouette coefficient. The silhouette coefficient is defined as:

[0025]

[0026] Where a(i) is the average distance metric from the i-th macrocell to other macrocells in the same cluster, and b(i) is the minimum of the average distance metric from the i-th macrocell to all macrocells in all other clusters.

[0027] In one embodiment, S3 includes the following steps:

[0028] S31. Gene encoding is performed on the DBSCAN clustering results to generate chromosomes;

[0029] S32. Each chromosome is considered an individual, and multiple individuals constitute a population.

[0030] S33. Expand the population size;

[0031] S34. Use a fitness function to evaluate the population. The fitness function is defined as:

[0032]

[0033]

[0034] Among them, V σ The coefficient of variation is σ, where σ represents the standard deviation between areas. The area represents the average value, and S represents the population silhouette coefficient. V represents the average of the standard deviation coefficients of the macrocell areas within all clusters. σB The area represents the standard deviation coefficient among all clusters, α, β, γ, and λ are coefficients, W represents the penalty term, and Area represents the area. cluster This represents the sum of the areas of all macrocells within a cluster, where n is the number of macrocells.

[0035] S35. Using the roulette wheel algorithm, select several individuals with high fitness function values ​​in each generation of the population. The probability of each individual being selected is proportional to its fitness function value, defined as:

[0036]

[0037] Where N represents the population size;

[0038] S36. Use crossover and mutation methods to update the genes of the selected individuals with high fitness function values;

[0039] S37. When the maximum number of iterations is reached, terminate the genetic algorithm and select the individual with the highest fitness function value from the last generation population as the final macrocell clustering result.

[0040] In one embodiment, in S33, the number of expansions is 100, and the expansion methods include crossover and mutation.

[0041] In one embodiment, S36 includes the following steps:

[0042] S361. Randomly select gene segments from the chromosomes of the selected parent individuals;

[0043] S362. Exchange randomly selected gene segments between two parent individuals to obtain an updated chromosome;

[0044] S363. Perform conflict detection on the updated chromosome, update duplicate genes, and obtain a second-updated chromosome;

[0045] S364. In the chromosome after the second update, randomly select a gene corresponding to a macrounit and move it to another cluster to obtain the chromosome after the third update.

[0046] S365. In the chromosomes after the three updates, randomly select a gene corresponding to a macrounit in each of the two clusters, and then swap their positions.

[0047] In one embodiment, in S7, the objective function of the simulated annealing algorithm is defined as follows:

[0048]

[0049] Among them, Area dead The area of ​​the invalid region is represented by WL, the bus length is represented by α and β, the weight coefficients are represented by max(), and the maximum value that appears during multiple iterations is represented by max().

[0050] In one embodiment, in S7, the area assessment model is defined as follows:

[0051]

[0052] Among them, Area total Represents the total area. Area represents the area of ​​a macrocell. std Area represents the rectangular area that can be used in a standard cell layout. pena This indicates the area of ​​the penalty region.

[0053] In one embodiment, in S7, the calculation steps of the line length evaluation model are as follows:

[0054] Calculate the equivalent pin information for all macrocells, including their location and bit width;

[0055] Create a polygon for standard cell layout;

[0056] Calculate the Manhattan distance from the equivalent pins of all macrocells to the polygon;

[0057] Calculate the sum of all Manhattan distances.

[0058] In one embodiment, S8 includes the following steps:

[0059] S81. Traverse all macro cells in the updated layout result;

[0060] S82. Determine whether the equivalent pin distance between the traversed macrocell and other macrocells is less than a threshold.

[0061] S83. Determine whether macrounits belong to the same group of connection relationships;

[0062] S84. If the equivalent pin distance of a macrocell is less than the threshold and they do not belong to the same group of connections, then the traversed macrocell is updated by rotation or flipping.

[0063] In one embodiment, S9 includes: introducing a penalty term into the objective function of the simulated annealing algorithm, first recording the overlapping regions, overlapping macrocells, and their clusters, and then defining the penalty term as follows:

[0064]

[0065] Area overlap It is the common area between the new layout result and the recorded overlapping area. macro It records the area of ​​overlapping macrocells. Based on the updated objective function, the macrocell layout is redone. If the overlap problem occurs again, this process needs to be repeated until a macrocell layout result without overlap is achieved. Attached Figure Description

[0066] Figure 1 This is a flowchart illustrating a macrocell placement method for integrated circuit design, as described in an embodiment of this application.

[0067] Figure 2 This is a schematic diagram of the macrocell structure features in the embodiments of this application.

[0068] Figure 3 This is a schematic diagram illustrating the process of updating multiple clusters based on a genetic algorithm in an embodiment of this application.

[0069] Figure 4 This is a schematic diagram of the preliminary layout result of macrocells in the embodiments of this application.

[0070] Figure 5 This is a schematic diagram of the area assessment model in the embodiments of this application.

[0071] Figure 6 This is a schematic diagram of the line length evaluation model in the embodiments of this application.

[0072] Figure 7 This is a schematic diagram illustrating the repair of overlapping macrocell portions in an embodiment of this application. Detailed Implementation

[0073] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0074] It should be noted that the embodiments of this application are preferred for implementation and are not intended to limit the application in any way. The technical features or combinations of technical features described in the embodiments of this application should not be considered isolated; they can be combined with each other to achieve better technical effects. The scope of the preferred embodiments of this application may also include other implementations, and this should be understood by those skilled in the art to which the embodiments of this application pertain.

[0075] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of exemplary embodiments may have different values.

[0076] To better describe the technical solution of this application, the macrocell layout method of this application is explained below in conjunction with some existing technologies:

[0077] Modern integrated circuit design relies heavily on EDA tools, and chip design is becoming increasingly automated. However, the task of macrocell placement still heavily depends on the experience of engineers. Macrocell placement requires considering multiple factors and undergoing multiple design iterations to achieve an ideal result, typically taking a long time.

[0078] Macrocells are significantly larger than standard cells, sometimes reaching thousands of times their size. Because large macrocells have a substantial impact on the overall layout of integrated circuits, the design process typically involves placing the macrocells first, followed by the standard cells. Then, routing is performed to connect the macrocells and standard cells.

[0079] Macro-unit placement requires a series of constraints. For example, macro-units should be placed as close as possible to module boundaries, macro-units with similar design levels should be placed closer together, macro-units should have a certain distance between them, and macro-units should not overlap. Current macro-unit placement methods mainly focus on how to use appropriate data structures to describe the macro-unit placement and how to use appropriate optimization algorithms to optimize the macro-unit placement results.

[0080] A common approach to describing macrocell layout is based on a binary tree data structure, where each node corresponds to a macrocell. This can be used to describe the macrocell layout of a LB Compact structure, a compact layout where no macrocells can move further to the left or down. This approach allows macrocells to be placed in the bottom left corner of the module. To fully utilize the module's space, typically four binary trees are created, with the macrocell layout corresponding to each tree placed in a corner of the module by rotation or flipping.

[0081] Embodiments of this application provide a macrocell placement method for integrated circuit design. This method clusters macrocells into multiple clusters based on standard cell information at the design level where the macrocells reside. A genetic algorithm is used to optimize the clustering results, and multiple macrocell arrays are created within each cluster based on the characteristics of the macrocells. Simulated annealing is used to optimize the macrocell placement results, a greedy algorithm is used to address congestion issues in the macrocell placement results, and finally, overlapping macrocells are updated globally.

[0082] See Figure 1 , Figure 1 This is a flowchart illustrating a macrocell placement method for integrated circuit design, as described in an embodiment of this application.

[0083] like Figure 1 As shown in the embodiments of this application, a macrocell placement method for integrated circuit design is provided, the macrocell placement method including the following steps:

[0084] Step S1: Obtain the netlist information and macrocell structure features of the circuit to be laid out.

[0085] In this embodiment, it should be noted that the netlist information of the circuit to be laid out includes the connection information of the macrocell, the design level information of the macrocell, and the standard cell information contained in each design level; the macrocell structural features include the size of the macrocell, the pin information of the macrocell, see [link to documentation]. Figure 2 , Figure 2 This is a schematic diagram of the macrocell structure features in the embodiments of this application.

[0086] Step S2: Based on the DBSCAN clustering algorithm, cluster all macrocells according to the circuit netlist information to obtain multiple clusters. Specifically, S2 may include the following steps:

[0087] S21. The distance metric between two macrocells is calculated as follows:

[0088]

[0089] Where p represents two macrounits m i and m j The number of standard cells in the common design hierarchy between areas, where n represents the total number of standard cells in the circuit netlist, Area k This represents the area of ​​a standard unit.

[0090] In this embodiment, it should be noted that, in order to make the clustering results as reasonable as possible, the method adopted is to use the ratio of the sum of the areas of all standard cells in the common design hierarchy among macrocells to the sum of the areas of all standard cells in the circuit netlist as the distance metric between macrocells.

[0091] S22. Using adaptive DBSCAN clustering algorithm parameters, generate a list of eps parameters from 0 to 1 with a step size of 0.01, and generate a list of MinPts parameters from 1 to N, where N represents the number of all macrocells.

[0092] In this embodiment, it should be noted that in order to implement the adaptive DBSCAN clustering algorithm without manually specifying parameters, an improved parameter acquisition method is adopted. By generating parameter lists for eps and MinPts respectively, the parameters are automatically acquired.

[0093] S23. For all the parameter lists of eps and MinPts, combine them in pairs to generate a parameter pair list. Generate a DBSCAN clustering result based on each parameter pair list, and retain only the results with 4 clusters.

[0094] In this embodiment, it should be noted that, in order to obtain reasonable clustering results, the generated parameter lists of eps and MinPts are combined in pairs to generate several parameter pair lists of eps and MinPts. A DBSCAN clustering is performed on each parameter pair list. In order to make full use of the space of the macrocell layout, four clusters are required. Therefore, in all DBSCAN clustering results, only the results with four clusters are retained, which can improve the rationality of the macrocell layout.

[0095] S24. Assign macrocells that have not been assigned to a cluster to the cluster with the nearest average distance metric.

[0096] In this embodiment, it should be noted that outliers may occur in the DBSCAN clustering results, and the macrocell layout scheme requires all macrocells to belong to a single cluster. Therefore, macrocells that do not belong to any cluster after DBSCAN clustering need to be assigned to a single cluster. The specific steps are as follows: calculate the average distance metric from the outlier macrocell to the macrocells in each cluster, and assign the macrocell to the cluster with the smallest average distance metric; if there are multiple clusters with the smallest average distance metric, select the cluster with the fewest macrocells.

[0097] S25. Calculate the silhouette coefficient of each DBSCAN clustering result and sort them from highest to lowest silhouette coefficient. The silhouette coefficient is defined as:

[0098]

[0099] Where a(i) is the average distance metric from the i-th macrocell to other macrocells in the same cluster, and b(i) is the minimum of the average distance metric from the i-th macrocell to all macrocells in all other clusters.

[0100] In this embodiment, it should be noted that since DBSCAN clustering may produce multiple results that meet the requirements, it is necessary to evaluate the quality of different results and rank them. A common method for evaluating the quality of clustering results is to use the silhouette coefficient, which does not depend on the true value but evaluates the degree of intra-cluster clustering and inter-cluster dispersion of the clustering results.

[0101] Step S3: Update the multiple clusters based on a genetic algorithm. Specifically, as follows... Figure 3 As shown, S3 may include the following steps:

[0102] S31. Gene encoding is performed on the DBSCAN clustering results to generate chromosomes.

[0103] In this embodiment, it should be noted that, based on the clustering results of DBSCAN, each cluster is first sorted, and then each macrounit is sorted within the cluster, finally obtaining an ordered macrounit sequence, which is used as the gene encoding for clustering.

[0104] S32. Each chromosome is considered an individual, and multiple individuals constitute a population.

[0105] S33. Expand the population to meet the algorithm requirements.

[0106] In this embodiment, it should be noted that the clustering results from DBSCAN are often too small to meet the requirements for initializing the population, which can cause the genetic algorithm to get stuck in a local optimum. Crossover and mutation methods can be used to expand the clustering results until the required population size is met. For example, if the expansion quantity is 100, the expansion method can include crossover and mutation.

[0107] S34. Use a fitness function to evaluate the population. The fitness function is defined as:

[0108]

[0109] Among them, V σ The coefficient of variation is σ, where σ represents the standard deviation between areas. The area represents the average value, and S represents the population silhouette coefficient. V represents the average of the standard deviation coefficients of the macrocell areas within all clusters. σB The coefficients of variation of the area among all clusters are α, β, γ, and λ, where W represents the penalty term. luster This represents the sum of the areas of all macrocells within a cluster, where n is the number of macrocells.

[0110] In this embodiment, it should be noted that the fitness function is designed to fully consider multiple factors in the macrocell layout: the sum of the macrocell areas of different clusters should be as close as possible, which is beneficial for making full use of space; macrocells of the same type should be given priority to be placed in the same cluster, which is beneficial for reducing the area of ​​invalid regions; and a cluster with an excessively large area should be avoided.

[0111] S35. Using the roulette wheel algorithm, select several individuals with high fitness function values ​​in each generation of the population. The probability of each individual being selected is proportional to its fitness function value, defined as:

[0112]

[0113] Where N represents the population size;

[0114] In this embodiment, it should be noted that, in order to ensure that the best genes in each generation are preserved, the probability of selecting the individual with the highest fitness is set to 1.

[0115] S36. Genetic updates are performed on selected individuals with high fitness function values ​​using crossover and mutation methods. Specifically, this includes the following steps:

[0116] S361. Randomly select gene segments from the chromosomes of the selected parent individuals;

[0117] S362. Exchange the randomly selected gene segments between the two parent individuals to obtain an updated chromosome;

[0118] S363. Perform conflict detection on the updated chromosome, update duplicated genes, and obtain a secondary chromosome.

[0119] Updated chromosomes;

[0120] S364. In the chromosome after the second update, randomly select a gene corresponding to a macrounit and move it.

[0121] Move to another cluster to obtain chromosomes updated three times;

[0122] S365. In the chromosomes after the three updates, randomly select a gene corresponding to a macrounit in each of the two clusters, and then swap their positions.

[0123] In this embodiment, it should be noted that crossover and mutation are methods used in genetic algorithms to increase population diversity and prevent chromosomes in the population from being too similar, which would lead to slow evolution.

[0124] S37. When the maximum number of iterations is reached, terminate the genetic algorithm and select the individual with the highest fitness function value from the last generation population as the final macrocell clustering result.

[0125] In this embodiment, it should be noted that after the genetic algorithm is completed, an optimized macrocell clustering result is obtained, and then the macrocells in each cluster are laid out separately.

[0126] Step S4: Create multiple macrocell arrays in the multiple clusters according to the macrocell structure characteristics.

[0127] In this embodiment, it should be noted that when creating the macrocell array, macrocells are grouped according to their characteristics to ensure that macrocells of the same type are grouped together. If a group contains too many macrocells, it can be split, with each split group containing an appropriate number of macrocells. The macrocells within each group are laid out using a binary tree data structure. After the layout is complete, the macrocells of a group are packaged to generate a macrocell array.

[0128] Step S5: Lay out the macrocell array in each of the clusters.

[0129] In this embodiment, it should be noted that after packaging to generate the macrocell array, the arrays within each cluster are re-laid out. If the arrays are moved or rotated at this time, the positions of the macrocells within the arrays will also change accordingly. After the array layout is completed, it is unpacked to determine the position of each macrocell.

[0130] Step S6: Lay out each cluster separately to obtain a preliminary layout result.

[0131] See Figure 4 , Figure 4 This is a schematic diagram of the preliminary layout result of macrocells in the embodiments of this application.

[0132] In this embodiment, it should be noted that after the macrocell layout of the four clusters is completed, the layout results of the different clusters are placed sequentially at the four corners of the module according to the distance metric between them, to obtain the preliminary layout result. Clusters with closer distance metrics should also be positioned closer together. The distance metric between clusters is as follows:

[0133]

[0134] Where C1 and C2 represent two clusters, m i and m j These represent macrounits located in C1 and C2, respectively, dist(m i ,m j ) represents the distance metric between two macrocells.

[0135] Step S7: Use a novel area evaluation model and line length evaluation model in the objective function of the simulated annealing algorithm to update the preliminary layout results and obtain the updated layout results.

[0136] The objective function of the simulated annealing algorithm is defined as follows:

[0137]

[0138] Where α and β represent weighting coefficients, which are usually 0.5, but can be set as needed. Area dead WL represents the area of ​​the invalid region, WL represents the bus length, and max() represents the maximum value that occurs during multiple iterations.

[0139] In this embodiment, it should be noted that area and line length are important optimization objectives in the macrocell placement problem. Therefore, the influence of both area and line length needs to be considered when designing the objective function, and the choice of objective function directly affects the optimization effect of the algorithm. Since area and line length belong to different units of measurement, normalization is required.

[0140] The area assessment model is defined as follows:

[0141]

[0142] Among them, Area total Represents the total area. Area represents the area of ​​a macrocell that is not connected to other regions. std Area represents the rectangular area that can be used in a standard cell layout. pena To represent the area of ​​the penalty region, see [link / reference]. Figure 5 , Figure 5 This is a schematic diagram of the area assessment model in the embodiments of this application.

[0143] In this embodiment, it should be noted that the area evaluation model fully considers the common macro-cell layout structure in map planning, which is closer to the real situation. It adds a penalty area, which is defined as the sum of the areas of the macro-cells that are not connected to other regions, which helps the algorithm escape local optima.

[0144] The calculation steps for the line length evaluation model are as follows:

[0145] Calculate the equivalent pin information for all macrocells, including their location and bit width;

[0146] Create a polygon for standard cell layout;

[0147] Calculate the Manhattan distance from the equivalent pins of all macrocells to the polygon;

[0148] Calculate the sum of all Manhattan distances.

[0149] In this embodiment, it should be noted that a macrocell typically contains many pins. To simplify calculations, equivalent input / output pins are created on each side of the macrocell, with their positions representing the average coordinates of all input / output pins on that side. These equivalent pins also contain net width information. A polygon is created outside the envelope rectangle containing all macrocells to simulate the area for subsequent standard cell layout. The Manhattan distance from all equivalent pins in each macrocell to the nearest edge of the polygon is calculated. If there are interconnections between macrocells, the Manhattan distance between equivalent pins is also calculated. The distances are adjusted according to the net width of the equivalent pins. The sum of all distances is calculated and used as the bus length for the macrocell layout problem. See [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the line length evaluation model in the embodiments of this application.

[0150] Step S8: Update the updated layout result again using a greedy algorithm to solve the congestion problem, specifically including:

[0151] S81. Traverse all macro cells in the updated layout result;

[0152] S82. Determine whether the equivalent pin distance between the traversed macrocell and other macrocells is less than a threshold, i.e., determine whether the equivalent pin distance of the macrocells is too close, wherein the threshold is defined as:

[0153]

[0154] Width pins Num represents the equivalent pin width of a macrocell, pitch represents the minimum line spacing of the metal layer containing the pin, and Num represents the number of pins. routing_layer This indicates the total number of available cabling resources;

[0155] S83. Determine whether macrounits belong to the same group of connection relationships;

[0156] S84. If the equivalent pin distance of a macrocell is less than the threshold and they do not belong to the same group of connections, then the traversed macrocell is updated by rotation or flipping.

[0157] In this embodiment, it should be noted that when the pins of two macrocells are too close together and these two macrocells do not belong to the same connection group, it will lead to a shortage of routing resources in that area during the later routing stage. Adjusting the direction of each macrocell based on a greedy algorithm can effectively solve the congestion problem in macrocell layout.

[0158] Step S9: Update the overlapping parts of the macro cells globally to obtain the final layout result.

[0159] See Figure 7 , Figure 7 This is a schematic diagram illustrating the repair of overlapping macrocell portions in an embodiment of this application.

[0160] In this embodiment, it should be noted that in the global macrocell layout, the layout results of each cluster are independent of each other. Therefore, the layout results of different clusters may overlap, especially when the number of macrocells is large or the size of the macrocells is large. To solve the problem of macrocell overlap, a penalty term is introduced into the objective function of the simulated annealing algorithm. First, the overlapping regions, overlapping macrocells, and their respective clusters are recorded. Then, the penalty term is defined as follows:

[0161]

[0162] Area overlap It is the common area between the new layout result and the recorded overlapping area. macro It records the area of ​​overlapping macrocells. Based on the updated objective function, the macrocell layout is redone. If the overlap problem occurs again, this process needs to be repeated until a macrocell layout result without overlap is achieved.

[0163] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above-disclosed technical content should be considered as equivalent and valid embodiments and fall within the scope of protection of the technical solution of this application.

Claims

1. A method for macro cell placement in integrated circuit design, characterized by, Comprise: S1, obtaining circuit netlist information and macro cell structure characteristics to be laid out; S2, based on DBSCAN clustering algorithm, clustering all macro cells according to circuit netlist information, obtaining a plurality of clusters; S3, updating a plurality of clusters based on genetic algorithm; S4, creating a plurality of macro cell arrays in a plurality of clusters according to macro cell structure characteristics; S5, respectively laying out macro cell arrays in each cluster; S6, respectively laying out each cluster to obtain a preliminary layout result; S7, updating the preliminary layout result in the objective function of the simulated annealing algorithm using an area evaluation model and a line length evaluation model to obtain an updated layout result; S8, using a greedy algorithm to update the updated layout result again to solve the congestion problem; S9, updating the overlapping part of the macro cell globally to obtain the final layout result, specifically including: introducing a penalty term in the objective function of the simulated annealing algorithm, first recording the overlapping area, the overlapping macro cell and the cluster they belong to, and then defining the penalty term as follows: Area overlap is the common area between the new layout result and the recorded overlapping area, Area macro is the area of the recorded overlapping macro cell, and the macro cell layout is re-performed based on the updated target function. If the overlapping problem occurs again, this process needs to be repeated until the macro cell layout result without overlapping is achieved.

2. The method as claimed in claim 1, characterized in that, In S1, the circuit netlist information and macro cell structure characteristics include: All design hierarchy information in the circuit netlist, standard cell quantity information in different design hierarchies, design hierarchy information of all macro cells, and size and pin position information of all macro cells.

3. The method as claimed in claim 1, wherein, The S2 includes the following steps: S21, the distance metric between two macro cells is calculated as: where p represents the number of standard cells in the common design hierarchy between two macro cells m i and m j ; n represents the number of all standard cells in the circuit netlist; Area k represents the area of a standard cell. S22, using adaptive DBSCAN clustering algorithm parameters, generating all eps parameters from 0 to 1 with a step of 0.01, generating MinPts parameters from 1 to N, where N represents the number of all macro cells; S23, combining all eps and MinPts parameter lists in pairs to generate a parameter pair list, and generating a DBSCAN clustering result according to each parameter pair list, only keeping the result with 4 clusters; S24, assigning the macro cells not assigned to the cluster to the cluster with the closest average distance metric; S25, calculating the silhouette coefficient of each DBSCAN clustering result, and sorting according to the silhouette coefficient from high to low, the silhouette coefficient is defined as: Where a(i) is the average distance metric of the ith macro cell to other macro cells in the same cluster, and b(i) is the minimum value of the average distance metric of the ith macro cell to all macro cells in other clusters.

4. The method as claimed in claim 1, wherein, The S3 includes the following steps: S31, gene coding is performed on the DBSCAN clustering result to generate a chromosome; S32, each chromosome is used as an individual, and a plurality of individuals form a population; S33, the number of individuals in the population is expanded; S34, the population is evaluated using a fitness function, and the fitness function is defined as: where V σ denotes the standard deviation coefficient, σ denotes the standard deviation between areas, denotes the average value of areas, S denotes the contour coefficient of the population, denotes the average value of the standard deviation coefficient of macrocell areas within all clusters, V σB denotes the standard deviation coefficient of areas between all clusters, α, β, γ and λ are coefficients, W denotes a penalty term, Area cluster denotes the sum of areas of all macrocells within a cluster, n is the number of macrocells; S35, using a roulette algorithm to select a number of individuals with high fitness function values in each generation of population, and the probability of selection of each individual is proportional to its fitness function value, and the probability is defined as: Where N represents the size of the population; S36, using the methods of crossover and mutation to update the genes of the selected individuals with high fitness function values; S37, terminate the genetic algorithm when the maximum number of iterations is reached, and select the individual with the highest fitness function value in the last generation population as the final macro cell clustering result.

5. The method as claimed in claim 4, characterized in that, The S36 includes the following steps: S361, randomly select the gene fragments in the chromosomes of the selected parent individuals; S362, exchange the randomly selected gene fragments of the two parent individuals to obtain updated chromosomes; S363, perform conflict detection on the updated chromosomes, update the repeated genes, and obtain secondarily updated chromosomes; S364, randomly select a gene corresponding to a macro cell in the secondarily updated chromosomes and move it to another cluster to obtain thirdly updated chromosomes; S365, randomly select a gene corresponding to a macro cell in each of the two clusters in the thirdly updated chromosomes, and then exchange their positions.

6. The method as claimed in claim 1, wherein, In S7, the objective function of the simulated annealing algorithm is defined as follows: Area dead represents the area of the invalid region, WL represents the bus length, a and β represent the weight coefficients, and max() represents the maximum value in the multiple iteration process.

7. The method as claimed in claim 6, characterized in that, In S7, the area evaluation model is defined as follows: where Area total represents the total area, represents the area of the macrocell, Area std represents the rectangular area available for standard cell placement, Area pena represents the area of the penalty region.

8. The method as claimed in claim 6, wherein, In S7, the line length evaluation model calculation steps are as follows: Calculate the equivalent pin information of all macro cells, including position and bit width; Create a polygon for the standard cell layout; Calculate the Manhattan distance from the equivalent pins of all macro cells to the polygon; Calculate the sum of all Manhattan distances.

9. The method as claimed in claim 1, wherein, The S8 includes the following steps: S81, traverse all macro cells in the updated layout result; S82, judge whether the equivalent pin distance of the traversed macro cell and other macro cells is less than a threshold value; S83, judge whether the macro cells belong to the same connection relationship group; S84, if the equivalent pin distance of the macro cells is less than the threshold value and they do not belong to the same connection relationship group, update the traversed macro cell in the form of rotation or flipping.

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