A method, system and storage medium for inserting a level conversion device

Abstract

The present invention provides a method, system and storage medium for inserting a level conversion device, the method comprising: obtaining all signal pin information of a level conversion device to be inserted in an IP core (Intelligent Property core) to form a pin set; dividing the pin set into an upper pin set, a lower pin set, a left pin set and a right pin set according to the coordinate relationship between the signal pin and the IP core; determining the coordinates of the level conversion device corresponding to the signal pins in the upper pin set, the lower pin set, the left pin set and the right pin set in combination with the height and width of the level conversion device; inserting the level conversion device according to the coordinates of the level conversion device. The present invention can efficiently and accurately add a level conversion device to an IP core, significantly reduce the workload of back-end designers, and improve the work quality. In particular, it has a significant improvement for projects with advanced processes, multiple IP cores and a large number of level conversion devices that need to be inserted.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a level conversion device insertion method, system and storage medium. Background Art

[0002] As chips enter deep submicron and nanometer process nodes, the difficulty of chip design has reached a new height, and higher requirements have been put forward for design methods, production tools, and chip performance. In the current SOC (System on Chip) design, different modules have different performance requirements. Under such requirements, low-voltage logic came into being, that is, a design is divided into different voltage domains, and modules with high speed and performance requirements use high voltage domains; modules with low speed and performance requirements use low voltage domains. On a larger digital IC chip, such as CPU and PGU, there may be several different voltage domains. Lower voltage means lower power consumption, so the design of multiple voltage domains will only play an increasingly important role in future development. However, different voltage domains mean different level signals, and there is a mismatch in signal levels in the communication between them. If two modules in different voltage domains communicate, level conversion is required.

[0003] The conversion between different levels requires the use of level conversion devices, which are divided into two categories: high-level to low-level devices and low-level to high-level devices. The height of the level conversion device is twice the height of the ordinary standard unit, and it contains a total of 5 pins (Pin): VDD, VSS, VDDL (VDDH), I, Z. Among them, VDD and VSS connect the power supply and ground of the normal voltage domain, the VDDL (VDDH) pin connects the power supply of the high or low voltage domain, I connects the input signal, and Z connects the output signal. For SOC design with advanced technology, if there are multiple voltage domains, a large number of level conversion devices need to be inserted between different voltage domains, and these level conversion devices need to be manually inserted, and power supply planning is done separately. For digital back-end engineers, it is a very large and complex task.

[0004] At present, the method of inserting level conversion devices is basically to manually insert level conversion devices for different IP cores (Intelligent Property cores) one by one. When there are a large number of signals that need level conversion, the manual insertion method is particularly time-consuming, and the insertion position needs to be moved manually, and each version needs to be reinserted during the chip design iteration process. Since the existing method consumes a lot of time and cannot guarantee whether the inserted level conversion device is connected correctly, there is an urgent need for a method that can automatically insert and reasonably place level conversion devices for different IP cores. Summary of the invention

[0005] In view of the problems existing in the prior art, a method, system and storage medium for inserting a level conversion device are provided, which can automatically insert and reasonably place level conversion devices for various IP cores (Intelligent Property cores) during the digital back-end design and development of advanced process multi-voltage domain chips, shorten chip development time and improve chip performance.

[0006] A first aspect of the present invention provides a method for inserting a level conversion device, comprising:

[0007] Obtain all signal pin information of the level conversion device to be inserted into the IP core to form a pin set;

[0008] According to the coordinate relationship between the signal pins and the IP core, the pin set is divided into an upper pin set, a lower pin set, a left pin set and a right pin set;

[0009] Determine the coordinates of the level conversion devices corresponding to the signal pins in the upper pin set, the lower pin set, the left pin set, and the right pin set, respectively, based on the height and width of the level conversion device;

[0010] The insertion of the level conversion device is completed according to the coordinates of the level conversion device.

[0011] As a preferred solution, the pin set is divided into an upper pin set, a lower pin set, a left pin set and a right pin set according to the coordinate relationship between the signal pin and the IP core, specifically including:

[0012] Assign the signal pins whose horizontal coordinates are smaller than the horizontal coordinates of the IP core to the left pin set;

[0013] Assign the signal pins whose horizontal coordinates are larger than the horizontal coordinates of the IP core to the right pin set;

[0014] Assign the signal pins whose ordinate is smaller than the ordinate of the IP core to the lower pin set;

[0015] Assign signal pins whose ordinates are greater than the ordinates of the IP core to the upper pin set.

[0016] As a preferred solution, the coordinates of the level conversion devices corresponding to the signal pins in the upper pin set, the lower pin set, the left pin set and the right pin set are determined in combination with the height and width of the level conversion device, specifically including:

[0017] For the upper pin set and the lower pin set: according to the coordinates and quantity of the signal pins in the set and the width of the level conversion device, obtain the horizontal coordinates of the level conversion devices corresponding to all the signal pins in the set, and according to the second preset distance and the vertical coordinates of the signal pins, determine the vertical coordinates of all the level conversion devices;

[0018] For the left pin set and the right pin set: according to the coordinates and quantity of the signal pins in the set and the height of the level conversion device, obtain the ordinates of the level conversion devices corresponding to all the signal pins in the set, and according to the first preset distance and the abscissa of the signal pins, determine the abscissa of all the level conversion devices;

[0019] The first preset distance and the second preset distance are used to characterize the distance between the signal pin and the connected level conversion device.

[0020] As a preferred solution, obtaining the horizontal coordinates of the level conversion devices corresponding to all the signal pins in the set according to the coordinates, quantity and width of the level conversion devices of the signal pins in the set specifically includes:

[0021] The abscissa of the center position is determined according to the maximum abscissa and the minimum abscissa of the signal pins in the set, and the abscissas of the level conversion devices on both sides of the center position are obtained in turn according to the number of signal pins and the width of the level conversion device.

[0022] As a preferred solution, according to the coordinates, quantity and height of the level conversion device of the signal pins in the set, the vertical coordinates of the level conversion device corresponding to all the signal pins in the set are obtained, which specifically includes:

[0023] The center position ordinate is determined according to the maximum ordinate and the minimum ordinate of the signal pins in the set, and the ordinates of the level conversion devices on both sides of the center position are obtained in sequence according to the number of signal pins and the height of the level conversion device.

[0024] As a preferred solution, the inserting of the level conversion device according to the coordinates of the level conversion device specifically includes:

[0025] Determine the type of level conversion device to be inserted based on the signal pin and the voltage domain to which it is connected;

[0026] According to the coordinates of the level conversion device, the corresponding type of level conversion device is inserted between the corresponding signal pin and the signal line to complete the logical connection.

[0027] As a preferred solution, determining the type of the level conversion device to be inserted according to the signal pin and the voltage domain connected thereto specifically includes:

[0028] If the output signal pin of the IP core is connected to the low voltage domain, a high-to-low level conversion device is inserted; if the output signal pin is connected to the high voltage domain, a low-to-high level conversion device is inserted; if the input signal pin of the IP core is connected to the low voltage domain, a low-to-high level conversion device is inserted; if the input signal pin is connected to the high voltage domain, a high-to-low level conversion device is inserted.

[0029] As a preferred solution, it also includes adding a power supply network of the level conversion device according to the coordinates of the level conversion device, specifically including:

[0030] According to the coordinates of each level conversion device, a rectangular frame centered on the level conversion device is determined;

[0031] confining the second power supply terminal of the level conversion device within the rectangular frame;

[0032] A power network is added on the upper layer of the level conversion device. The power lines distributed in the power network fall vertically into the rectangular frame of each level conversion device and are connected to the second power terminals of all the level conversion devices in the lower layer through punching. The power network is powered by the power lines on the top layer of the chip.

[0033] A second aspect of the present invention provides a system, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executes the method for inserting a level conversion device as described in the first aspect.

[0034] A third aspect of the present invention provides a computer-readable storage medium having computer program instructions stored thereon, wherein the program instructions are used to implement a process corresponding to the level conversion device insertion method described in the first aspect when executed by a processor.

[0035] Compared with the prior art, the beneficial effects of adopting the above technical solution are:

[0036] 1) The present invention can efficiently and accurately add level conversion devices to IP cores, significantly reducing the workload of back-end designers and significantly improving the quality of work. This is especially true for projects with advanced processes and multiple IP cores that require a large number of level conversion devices to be inserted.

[0037] 2) The present invention saves IP core-related winding resources and avoids timing problems caused by unreasonable placement of level conversion devices.

[0038] 3) The present invention improves the design efficiency of the back-end, reduces the time of design iterations, and reduces the cost of chip development. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a flow chart of the level conversion device insertion method proposed by the present invention.

[0040] Figure 2 FIG. 1 is a schematic diagram of a power supply network in an embodiment of the present invention.

[0041] Figure 3 Insert schematic for a conventional level-translation device.

[0042] Figure 4 FIG. 1 is a schematic diagram of inserting a level conversion device in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar modules or modules with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limitations on the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0044] In large digital SOC chips with advanced technology and multiple voltage domains, the number of IP cores ranges from dozens to hundreds, and each IP core has dozens or hundreds of pins; if these IP cores are in different voltage domains, the number of level conversion devices that need to be inserted is counted in thousands. If the existing insertion method is used, the workload is very large, and errors are easily made when making logical connections, which will also make the power supply planning of the entire design quite complicated. In addition, level conversion devices that are not placed according to a rule may cause serious routing congestion problems around the IP core, further causing the timing related to the IP core to be difficult to converge. Based on this, an embodiment of the present invention proposes a method for inserting a level conversion device, which can efficiently and accurately determine the insertion coordinates of the level conversion device and realize the automatic addition of the level conversion device.

[0045] Traditionally, the work before layout and routing is called digital front-end (Front End) design, and the work after layout and routing is called digital back-end (Back End) design. The purpose of layout is to generate the layout data file required for making the mask. At the same time, the netlist file (Netlist) and standard delay file (Signed Distance Field, SDF) after layout are also generated. The level conversion device insertion method proposed in this embodiment is implemented based on the files generated in this process. Specifically, after completing the digital back-end design, for communication between different voltage domains, it is necessary to add level conversion devices to ensure that there is no abnormal leakage current when the signal goes from the low voltage domain to the high voltage domain and from the low voltage domain to the high voltage domain, thereby ensuring the normal operation of the chip. This embodiment proposes a method for inserting a level conversion device, please refer to Figure 1 , the specific plan is as follows:

[0046] Step 100: Obtain information of all signal pins of the IP core to be inserted into the level conversion device to form a pin set.

[0047] Obtain the gate-level netlist, timing constraint file, unmodifiable unit constraint file, unified power format file, and IP core data file in the design process, import the corresponding files into the automation tool, and generate the database of the initial design. In this embodiment, the automation tool can use the PR tool, and other tools can be selected as needed in other embodiments.

[0048] Complete the automatic layout planning of IP core and the arrangement of signal ports in the automation tool according to the relevant documents. It should be noted that when arranging, the hard cores in the design need to be placed in the core area according to the data flow and the position of the power pin pads to meet the requirements of voltage drop and data flow.

[0049] After completing the IP core planning, obtain the instantiation name of the IP core that needs to be inserted into the level conversion device, and then further determine the instantiation name of the signal pin corresponding to the IP core that needs to be inserted into the level conversion device to form a pin set. In this embodiment, the pin set of an IP core is used for illustration. When there are multiple IP cores, a corresponding pin set is established for each IP core, and then the subsequent level conversion device insertion process is performed on the pin sets.

[0050] Step 200: According to the coordinate relationship between the signal pins and the IP core, the pin set is divided into an upper pin set, a lower pin set, a left pin set and a right pin set.

[0051] The pin set obtained in step 100 is traversed, and the signal line connected to the signal pin can be determined through the instantiation name of the signal pin, and the connection relationship of the level conversion device can be determined later. At the same time, the horizontal and vertical coordinates (X, Y) of each signal pin can be obtained, and the horizontal and vertical coordinates (X, Y) of the signal pin are compared with the horizontal and vertical coordinates (X', Y') of the IP core, and the pin set can be divided into an upper pin set, a lower pin set, a left pin set, and a right pin set located above, below, left, and right of the IP core. In this embodiment, the horizontal and vertical coordinates of the IP core refer to the horizontal and vertical coordinates of its center point.

[0052] Specifically, the signal pins whose horizontal coordinates X are less than the horizontal coordinate X' of the IP core are divided into the left pin set; the signal pins whose horizontal coordinates X are greater than the horizontal coordinate X' of the IP core are divided into the right pin set; the signal pins whose vertical coordinates Y are less than the vertical coordinate Y' of the IP core are divided into the lower pin set; the signal pins whose vertical coordinates Y are greater than the vertical coordinate Y' of the IP core are divided into the upper pin set, and finally the upper pin set, the lower pin set, the left pin set and the right pin set are obtained.

[0053] Step 300 , combining the height and width of the level conversion device, respectively determining the coordinates of the level conversion devices correspondingly connected to the signal pins in the upper pin set, the lower pin set, the left pin set, and the right pin set.

[0054] In this embodiment, for the upper pin set and the lower pin set, the horizontal coordinates of the level conversion devices corresponding to all the signal pins in the set are obtained according to the coordinates, quantity and width of the signal pins in the set, and the vertical coordinates of all the level conversion devices are determined according to the second preset distance and the vertical coordinates of the signal pins. For the left pin set and the right pin set, the vertical coordinates of the level conversion devices corresponding to all the signal pins in the set are obtained according to the coordinates, quantity and height of the signal pins in the set, and the horizontal coordinates of all the level conversion devices are determined according to the first preset distance and the horizontal coordinates of the signal pins. The first preset distance and the second preset distance are used to characterize the distance between the signal pin and the connected level conversion device.

[0055] The following is an explanation of the coordinate determination process of the level conversion device corresponding to the signal pin in each pin set.

[0056] For the right pin set, obtain the maximum and minimum ordinates of the signal pins in the right pin set, add the maximum ordinate to the minimum ordinate and divide by 2 to get the center position ordinate Y1, and divide the number of signal pins in the upper pin set by 2 to get the number of level conversion devices N that need to be inserted from the center position to the upper and lower sides. At this time, the height H of the level conversion device is connected, and 1 to N H are added and 1 to N H are subtracted from the center position ordinate Y1, respectively, to obtain the ordinates of the level conversion devices in the upper part of the center position (Y1+1H), (Y1+2H), ..., (Y1+NH) and the ordinates of the level conversion devices in the lower part of the center position are (Y1-1H), (Y1-2H), ..., (Y1-NH). Since all signal pins in the right pin set have the same horizontal coordinate, i.e., X1, the horizontal coordinates of all level conversion devices can be obtained by adding the first preset distance ΔX to the signal pin horizontal coordinate X1, so that the horizontal and vertical coordinates of the level conversion devices corresponding to the signal pins of all right pin sets can be determined as (X1+ΔX, Y1+1H), (X1+ΔX, Y1+2H)...(X1+ΔX, Y1+NH), (X1+ΔX, Y1-1H), (X1+ΔX, Y1-2H),..., (X1+ΔX, Y1-NH). Among them, the first preset distance ΔX can be selected according to the project, preferably 20u or 30u.

[0057] It should be noted that, in the process of determining the ordinate of the above-mentioned level conversion device, adjacent level conversion devices can be designed adjacent to each other, that is, the difference between the ordinates is a height H, or the spacing between adjacent level conversion devices can be adjusted as needed, for example, the difference between the ordinates is designed to be 2H, and it is only necessary to ensure that the inserted level conversion device is near the corresponding pin.

[0058] For the left pin set, the ordinate of the pin set inserted into the level conversion device is the same as that of the right pin set, and the abscissa is obtained by subtracting the first preset distance ΔX from the abscissa of the signal pin.

[0059] For the upper pin set, the maximum horizontal coordinate and the minimum horizontal coordinate of the signal pin in the upper pin set are obtained, and the maximum horizontal coordinate and the minimum horizontal coordinate are added and divided by 2 to obtain the horizontal coordinate X3 of the center position. The number of signal pins in the upper pin set is divided by 2 to obtain the number of level conversion devices N that need to be inserted to the left and right sides of the horizontal coordinate X3 of the center position. At this time, combined with the width M of the level conversion device, 1 to N M are added and 1 to N M are subtracted from the horizontal coordinate X3 of the center position, respectively, to obtain the vertical coordinates (X3+1M), (X3+2M), ..., (X3+NM) of the level conversion device to the right of the center position and the vertical coordinates (X3-1M), (X3-2M), ..., (X3-NM) of the level conversion device to the left of the center position. For the signal pins in the upper pin set, all the signal pins have the same ordinate, i.e., Y3. At this time, the ordinate of all the level conversion devices can be obtained by adding the ordinate Y3 of the signal pin to the second preset distance ΔY. In this way, the horizontal and vertical coordinates of the level conversion devices corresponding to the signal pins of all the upper pin sets can be determined as (X3+1M, Y3+ΔY), (X3+2M, Y3+ΔY), ..., (X3+NM, Y3+ΔY), (X3-1M, Y3+ΔY), (X3-2M, Y3+ΔY), ..., (X3-NM, Y3+ΔY). Among them, the second preset distance ΔY can be selected according to the project, preferably 20u or 30u.

[0060] Similarly, in the process of determining the horizontal coordinates of the above-mentioned level conversion devices, adjacent level conversion devices can be designed adjacent to each other, that is, the difference between the horizontal coordinates is the width, and the spacing between adjacent level conversion devices can also be adjusted as needed. For example, the difference between the vertical coordinates is designed to be 2M, and it is only necessary to ensure that the inserted level conversion device is near the corresponding pin.

[0061] For the lower pin set, the horizontal coordinate of the insertion level conversion device is the same as that of the upper pin set, and the vertical coordinate is obtained by subtracting the second preset distance ΔY from the vertical coordinate of the signal pin.

[0062] Through this step, the coordinates of the level conversion device to be inserted can be obtained, as shown in Table 1.

[0063] Table 1 Coordinate table of level conversion devices

[0064]

[0065] The method can change the inserted level conversion device along with the IP core regardless of how the position of the IP core changes, and can ensure that the insertion position is near the signal pin of the IP core, thereby avoiding problems such as timing violations caused by unreasonable insertion position of the level conversion device and too long wiring. Step 400: Complete the insertion of the level conversion device according to the coordinates of the level conversion device.

[0066] After determining the coordinates of the level conversion device, the insertion process of the level conversion device needs to be performed. Before inserting the level conversion device, it is necessary to determine the type of level conversion device required for each signal pin. In this embodiment, by traversing the pin set, the input and output properties of all signal pins are determined, and the type of level conversion device that needs to be inserted for the core area is determined according to the direction of the signal pin, and the level conversion device is inserted into the corresponding coordinate according to the determined type.

[0067] For output signal pins, if connected to a low voltage domain, the IP core is in a high voltage domain at this time, and a high-to-low level conversion device needs to be inserted; if connected to a high voltage domain, the IP core is in a low voltage domain at this time, and a low-to-high level conversion device needs to be inserted.

[0068] For input signal pins, if connected to a low voltage domain, the IP core is in a high voltage domain, and a low-to-high level conversion device is required; if connected to a high voltage domain, the IP core is in a low voltage domain, and a high-to-low level conversion device needs to be inserted.

[0069] Among them, the low-to-high level conversion device is used to convert the low-level signal into a high-level signal. When the signal in the low-voltage domain drives the unit in the high-voltage domain, due to insufficient driving capability, the input flip time of the device in the high-voltage domain will be increased, which will lead to increased delay and timing violation. Therefore, it is necessary to insert a low-to-high level conversion device to reduce unit delay and internal power consumption. The high-to-low level conversion device is used to convert the high-level signal into a low-level signal, which can be achieved by connecting two inverters in series.

[0070] In order to prevent the position of the inserted level conversion device from being changed during the placement stage in a later process, after the level conversion device is inserted, its state is changed to an immovable fixed state in the automation tool.

[0071] After completing the insertion of the level conversion device, the logical connection needs to be completed. For any signal pin, disconnect the signal line connected to the signal pin, and add a new signal line to complete the connection between the level conversion device and the signal pin. Specifically, for the input signal pin, connect the input end of the level conversion device to the original signal line, connect the output end of the level conversion device to the input end of the new signal line, and connect the output end of the new signal line to the input signal pin. For the output signal pin, connect the input end of the level conversion device to the output end of the new signal line, connect the input end of the new signal line to the input signal pin, and connect the output end of the level conversion device to the original signal line.

[0072] Through the above process, the insertion and logical connection of the level conversion device are completed. In order to ensure the power supply of the level conversion device, this embodiment provides a power network design method to supply power to the high voltage power supply terminal or low voltage driving bias terminal of all level conversion devices.

[0073] In order to ensure that the second power supply terminal VDDH (VDDL) pins of all level conversion devices can be covered, in this embodiment, the rectangular frame centered on the coordinates of each level conversion device is determined. Assuming that the coordinates of a level conversion device are (X5, Y5), add ΔL to the horizontal coordinate X5 (ΔL is recommended to be 20u or 30u according to the project) to obtain X6, and add ΔL to the vertical coordinate Y5 to obtain Y6; subtract ΔL from the horizontal coordinate X5 to obtain X7; subtract ΔL from the vertical coordinate Y5 to obtain Y7, so that according to the coordinates (X5, Y5) of the level conversion device, the diagonal coordinates (X6, Y6) and (X7, Y7) of a rectangle are obtained respectively. The diagonal coordinates can be used to obtain a rectangular frame with a length and width of 2ΔL with the level conversion device as the center point. At this time, the power supply planning of the VDDH (VDDL) pin of the level conversion device is carried out in the rectangular frame. This can save winding resources and accurately connect the power supply to each level conversion device to avoid the situation where the power supply is not connected.

[0074] At this time, add a power network on the upper layer of the level conversion device, and ensure that the power lines distributed in the power network fall vertically into the rectangular frame of each level conversion device, and connect to the high voltage power supply end or low voltage drive bias end of all the level conversion devices in the lower layer through drilling holes to complete the power supply. Among them, the power network is powered by the power lines on the top layer of the chip.

[0075] For general chips, they usually include multi-layer designs. Taking a chip including M1~M9 layers as an example, the VDDH (VDDL) pin of the level conversion device is in the M2 layer, but since there are many devices and pins in this layer, directly designing the power supply network is likely to cause interference. Therefore, in this embodiment, the power supply network is designed in the upper layer of M2, that is, the M3 layer, so that the power supply network can cover the rectangular frame range of all level conversion devices in the vertical direction, and is connected to the VDDH (VDDL) pin in the rectangular frame by punching. At the same time, the power supply network of the M3 layer is connected to the M9 layer through the horizontal and vertical crisscrossing power lines, and the M9 layer provides power. When designing the power lines in the M3 layer power supply network, it is necessary to accurately calculate the pitch and offset between the power lines, so as to ensure that the power lines in the M3 layer can fall on the VDDH (VDDL) pins of the level conversion device, and the width of the power line should be able to completely cover the VDDH (VDDL) pins. Since the present embodiment focuses on designing the power network of the level conversion device, after completing the design of the power line of the M3 layer, the M4 to M9 layers can be designed according to the needs without making too many requirements. The following is a reference for the power line settings of the M3~M9 layers: M3: width 0.038u, offset 0.702u, pitch 4.32u, vertical direction; M4: width 0.08u, offset 0.288u, pitch 1.728u, horizontal direction; M5: width 0.08u, offset 0.996u, pitch 4.32u, vertical direction; M6: width 0.08u, offset 0.288u, pitch1.728u, horizontal direction; M7: width 0.12u, offset 0.996u, pitch 4.32u vertical direction; M8: width 0.63u, offset 2.3u, pitch 3.78u, horizontal direction M9: width 0.63u, offset 2.131u, pitch 3.78u, vertical direction. Through the above settings, draw power lines in the rectangular frame with automated tools, and then punch holes from the M9 layer to the M2 layer to complete the power planning of the VDDH (VDDL) pins of the level conversion device. Conventional VDD and VSS are the same as the ordinary standard power supply in the core area, and can be connected through the power supply line of the M1 layer, which will not be described here.

[0076] Please refer to Figure 2 In the figure, 23_new~40_new are the instantiation names of the level conversion devices, the blue lines are the logical connection diagrams between the level conversion devices and the IP core, and the green lines and yellow lines represent the power lines of different layers, where the green lines are the power lines of the M3 layer, and the yellow lines are the power lines of the M4 layer. Figure 2It can be seen that the power lines from M3 to M9 are accurately marked within the rectangular range where the level conversion device is located, and the power line of M3 is accurately placed on the VDDH (VDDL) pin. Similarly, when the IP core is moved, there is no need to manually re-plan the power supply. The power line will automatically re-plan the power line within the rectangular range set around the level conversion device.

[0077] In order to more intuitively demonstrate the effect of the solution of the present invention, Figure 3 The figure shows the traditional level conversion device insertion method. In the figure, ① is the level conversion device, ② is the logic connection diagram, and ③ is the IP core. The placement is random, resulting in a disorderly logic connection. In advanced processes, it is very likely to cause winding problems near the IP core, which will affect the timing and make power planning very complicated. Figure 4 , in the figure, ① is a level conversion device, ② is a schematic diagram of the logical connection, and ③ is an IP core. After adopting the level conversion device insertion method proposed in the present invention, the level conversion device is accurately placed near the signal pin of the IP core, and the logical connection is also one-to-one correspondence between the signal pin and the level conversion device. In the early stage of the project, the IP core may be moved frequently and the position is not fixed. If the level conversion device is added manually and separately every time, it will not only take a lot of time, but also easily lead to errors in the logical connection. The solution proposed by the present invention can realize the automatic placement and logical connection of the level conversion device. No matter how the IP core moves, the level conversion device will be accurately placed near the signal pin of the IP core, achieving the purpose of automatic placement and logical connection.

[0078] This embodiment provides a comparison of the timing margin (slack), congestion (congestion), and voltage drop (IR drop) related to the IP core obtained before and after the method of the present invention is used, as shown in Table 2.

[0079] Table 2 Performance comparison table

[0080]

[0081] (1) It can be clearly seen from the timing margin that among the five timing paths compared, the important paths with tight timing have an improvement of 4.8% to 15.2% after using the solution of the present invention. This is also a very considerable benefit for designs with advanced processes and difficult to converge IP core timing. The congestion problem is also solved to a certain extent. (2) From the congestion comparison, it can be seen that the congestion level has basically decreased after using the present invention. This is due to the reasonable placement of the level conversion device and the one-to-one correspondence of the logical connection, which avoids the situation of winding in circles during the winding process, and the benefit to congestion is also positive. (3) From the voltage drop comparison, it can be seen that the voltage drop of the inserted level conversion device is also significantly reduced. This is because we have planned the power supply of the level conversion device in advance before planning the power supply of the entire chip, avoiding the power supply of the level conversion device being weak due to the power line in the core area affecting the power supply routing of the level conversion device, and then causing the voltage drop problem.

[0082] The present invention determines the type of the corresponding inserted level conversion device by the direction of the IP core signal pin; determines the coordinates of the inserted level conversion device in turn according to the coordinates of the signal pins in the four directions of the IP core, so as to realize the reasonable planning of the position of the level conversion device according to different positions; and determines the scope of power supply planning according to the position of the level conversion device, so as to avoid the problems of leak holes, voltage drop and waste of winding resources caused by unreasonable power supply planning. The purpose of automatically adding power conversion devices, logical connection and power supply planning is achieved, and the level conversion devices can be automatically placed after the IP core position is determined, shortening the development time for the advanced process multi-IP core multi-voltage domain design, ensuring the accuracy of the logical connection, and avoiding the winding problems caused by the unreasonable placement of the level conversion device, and then the timing and voltage drop problems.

[0083] An embodiment of the present invention further provides a system, including a memory and a processor, wherein the memory stores a computer program corresponding to the aforementioned level conversion device insertion method that can be loaded and executed by the processor.

[0084] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation method of the present application.

[0085] For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Those of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for inserting a level conversion device, characterized in that: include: Obtain all signal pin information of the level conversion device to be inserted into the IP core to form a pin set; According to the coordinate relationship between the signal pins and the IP core, the pin set is divided into an upper pin set, a lower pin set, a left pin set and a right pin set; Determine the coordinates of the level conversion devices corresponding to the signal pins in the upper pin set, the lower pin set, the left pin set, and the right pin set, respectively, based on the height and width of the level conversion device; According to the coordinates of the level conversion device, the level conversion device is inserted; The step of combining the height and width of the level conversion device to determine the coordinates of the level conversion device correspondingly connected to the signal pins in the upper pin set, the lower pin set, the left pin set, and the right pin set includes: For the upper pin set and the lower pin set: determine the abscissa of the center position according to the maximum abscissa and the minimum abscissa of the signal pins in the set, then obtain the abscissas of the level conversion devices on both sides of the center position in turn according to the number of signal pins and the width of the level conversion device, and determine the ordinates of all the level conversion devices according to the second preset distance and the ordinates of the signal pins; For the left pin set and the right pin set: determine the ordinate of the center position according to the maximum ordinate and the minimum ordinate of the signal pins in the set, obtain the ordinates of the level conversion devices on both sides of the center position in sequence according to the number of signal pins and the height of the level conversion device, and determine the abscissa of all the level conversion devices according to the first preset distance and the abscissa of the signal pin; The first preset distance and the second preset distance are used to characterize the distance between the signal pin and the connected level conversion device.

2. The level conversion device insertion method according to claim 1, characterized in that: According to the coordinate relationship between the signal pin and the IP core, the pin set is divided into an upper pin set, a lower pin set, a left pin set and a right pin set, specifically including: Assign the signal pins whose horizontal coordinates are smaller than the horizontal coordinates of the IP core to the left pin set; Assign the signal pins whose horizontal coordinates are larger than the horizontal coordinates of the IP core to the right pin set; Assign the signal pins whose ordinate is smaller than the ordinate of the IP core to the lower pin set; Assign signal pins whose ordinates are greater than the ordinates of the IP core to the upper pin set.

3. The level conversion device insertion method according to claim 1 or 2, characterized in that: The step of inserting the level conversion device according to the coordinates of the level conversion device specifically includes: Determine the type of level conversion device to be inserted based on the signal pin and the voltage domain to which it is connected; According to the coordinates of the level conversion device, the corresponding type of level conversion device is inserted between the corresponding signal pin and the signal line to complete the logical connection.

4. The level conversion device insertion method according to claim 3, characterized in that: The step of determining the type of the level conversion device to be inserted according to the signal pin and the voltage domain connected thereto specifically includes: If the output signal pin of the IP core is connected to the low voltage domain, a high-to-low level conversion device is inserted; if the output signal pin is connected to the high voltage domain, a low-to-high level conversion device is inserted; if the input signal pin of the IP core is connected to the low voltage domain, a low-to-high level conversion device is inserted; if the input signal pin is connected to the high voltage domain, a high-to-low level conversion device is inserted.

5. The level conversion device insertion method according to claim 1, characterized in that: It also includes adding a power supply network of the level conversion device according to the coordinates of the level conversion device, specifically including: According to the coordinates of each level conversion device, a rectangular frame centered on the level conversion device is determined; The second power supply terminal of the level conversion device is confined within the rectangular frame; the second power supply terminal is used to connect the power supply of the high-low voltage domain or the low voltage domain; A power network is added on the upper layer of the level conversion device. The power lines distributed in the power network fall vertically into the rectangular frame of each level conversion device and are connected to the second power terminals of all the level conversion devices in the lower layer through punching. The power network is powered by the power lines on the top layer of the chip.

6. A system, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program corresponding to the level conversion device insertion method according to any one of claims 1 to 5 that can be loaded and executed by the processor.

7. A computer-readable storage medium, characterized in that: Computer program instructions are stored thereon, and when the program instructions are executed by a processor, they are used to implement a process corresponding to the level conversion device insertion method according to any one of claims 1 to 5.

Images